17th week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140110782 | Source Tip Optimization For High Voltage Transistor Devices - The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region. | 2014-04-24 |
20140110783 | HIGH GAIN DEVICE - A method of forming a device is disclosed. A substrate having a high gain (HG) device region for a HG transistor is provided. A HG gate is formed on the substrate in the HG device region. The HG gate includes sidewall spacers on its sidewalls. Heavily doped regions are formed adjacent to the HG gate. Inner edges of the heavily doped regions are aligned with about outer edges of the sidewall spacers of the HG gate. The heavily doped regions serve as HG source/drain (S/D) regions of the HG gate. The HG S/D regions do not include lightly doped drain (LDD) regions or halo regions. | 2014-04-24 |
20140110784 | REPLACEMENT METAL GATE FINFET - A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin. | 2014-04-24 |
20140110785 | REPLACEMENT METAL GATE FINFET - A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer. | 2014-04-24 |
20140110786 | SEMICONDUCTOR DEVICE HAVING BURIED CHANNEL ARRAY - A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes. | 2014-04-24 |
20140110787 | Layout Schemes for Cascade MOS Transistors - A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected. | 2014-04-24 |
20140110788 | Power Converter Package Including Top-Drain Configured Power FET - In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET. | 2014-04-24 |
20140110789 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P | 2014-04-24 |
20140110790 | STRUCTURE AND METHOD FOR FORMING A LOW GATE RESISTANCE HIGH-K METAL GATE TRANSISTOR DEVICE - A low gate resistance high-k metal gate transistor device is formed by providing a set of gate stacks (e.g., replacement metal gate (RMG) stacks) in a trench on a silicon substrate. The gate stacks in the trench may have various layers such as: a high-k layer formed over the substrate; a barrier layer (formed over the high-k layer; a p-type work function (pWF) layer formed over the barrier layer; and an n-type work function (nWF) layer formed over the pWF layer. The nWF layer will be subjected to a nitrogen containing plasma treatment to form a nitridized nWF layer on the top surface, and an Al containing layer will then be applied over the gas plasma treated layer. By utilizing a gas plasma treatment, the gap within the trench may remain wider, and thus allow for improved Al fill and reflow at high temperature (400° C.-480° C.) subsequently applied thereto. | 2014-04-24 |
20140110791 | HYBRID GATE LAST INTEGRATION SCHEME FOR MULTI-LAYER HIGH-k GATE STACKS - A method for manufacturing a dual workfunction semiconductor device using a hybrid gate last integration scheme is described. According to one embodiment, the method includes heat-treating a first high-k film at a first heat-treating temperature to diffuse a first chemical element from a first cap layer into the first high-k film in a device region to form a first modified high-k film. The method further includes a gate-last processing scheme to form recessed features defined by sidewall spacers in the device regions and depositing a second high-k film in the recessed features. Some embodiments include forming an oxygen scavenging layer on the first high-k film, where the heat-treating the first high-k film scavenges oxygen from an interface layer to eliminate or reduce the thickness of an interface layer. | 2014-04-24 |
20140110792 | PFET POLYSILICON LAYER WITH N-TYPE END CAP FOR ELECTRICAL SHUNT - A semiconductor device includes a PFET transistor (a PMOS FET) having a poly(silicon) layer with a p-type doped portion and an n-type doped portion. The p-type doped portion is located above a channel region of the transistor and the n-type doped portion is located in an end portion of the poly layer outside the channel region. The poly layer may be formed by doping portions of an amorphous silicon layer with either the p-type dopant or the n-type dopant and then annealing the amorphous silicon layer to diffuse the dopants and crystallize the amorphous silicon to form polysilicon. The n-type doped portion of the poly layer may provide an electrical shunt in the end portion of the poly layer to reduce any effects of insufficient diffusion of the p-type dopant in the poly layer. | 2014-04-24 |
20140110793 | CMOS TRANSISTOR AND FABRICATION METHOD - Exemplary embodiments provide transistors and methods for forming the transistors. An exemplary CMOS transistor can be formed by epitaxially forming a first stress layer in/on a semiconductor substrate having a first region including a first gate structure and a second region including a second gate structure. A barrier layer can be formed to cover the second region and to expose the first region. The barrier layer can be used as a mask to remove a portion of the first stress layer from the first region. A second stress layer can be formed in a groove formed in the semiconductor substrate on sides of the first gate structure in the first region. The fabrication method can be simplified and the formed CMOS transistors can have high carrier mobility. | 2014-04-24 |
20140110794 | FACILITATING GATE HEIGHT UNIFORMITY AND INTER-LAYER DIELECTRIC PROTECTION - Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process. | 2014-04-24 |
20140110795 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate where a cell region and a contact region are defined, an isolation region and an active region disposed alternately in the contact region, transistors configured to include a gate formed over the substrate and a source and a drain formed in the active region at both sides of the gate, in the contact region, memory blocks configured to include conductive lines stacked over the substrate and formed over the transistors, the conductive lines being extended from the cell region to the contact region in the direction crossing over the isolation region and the active region, and contact plugs formed between the memory blocks in the contact region. | 2014-04-24 |
20140110796 | Semiconductor Package with Conductive Carrier Integrated Heat Spreader - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier. | 2014-04-24 |
20140110797 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOS semiconductor device has a MOS structure, including a p | 2014-04-24 |
20140110798 | METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH LOW-K SPACERS AND THE RESULTING DEVICE - One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer. | 2014-04-24 |
20140110799 | ELECTRONIC DEVICE AND ITS MANUFACTURING METHOD - An electronic device includes a substrate, a sidewall that is disposed on the substrate and forms a cavity, a first layer that is disposed on the sidewall and covers the cavity, a second layer that is formed on the first layer and has a region disposed outside an outline of the first layer in a plan view, a dielectric layer disposed below the region of the second layer disposed outside the outline of the first layer in a plan view, and a functional element disposed inside the cavity. | 2014-04-24 |
20140110800 | Method for manufacturing a cap for a mems component, and hybrid integrated component having such a cap - A manufacturing method for a cap, for a hybrid vertically integrated component having a MEMS component a relatively large cavern volume having a low cavern internal pressure, and a reliable overload protection for the micromechanical structure of the MEMS component. A cap structure is produced in a flat cap substrate in a multistep anisotropic etching, and includes at least one mounting frame having at least one mounting surface and a stop structure, on the cap inner side, having at least one stop surface, the surface of the cap substrate being masked for the multistep anisotropic etching with at least two masking layers made of different materials, and the layouts of the masking layers and the number and duration of the etching steps being selected so that the mounting surface, the stop surface, and the cap inner side are situated at different surface levels of the cap structure. | 2014-04-24 |
20140110801 | PACKAGING FOR SEMICONDUCTOR SENSOR DEVICES AND METHODS - A pressure sensor includes a first housing having a cavity. The pressure sensor further includes a pressure sensing device attached to a bottom of the cavity. The pressure sensor further includes a layer of gel over the pressure sensing device. The pressure sensor further includes a baffle in contact with the gel to reduce movement of the gel. | 2014-04-24 |
20140110802 | Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for connecting the MRAM Cells - A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap. | 2014-04-24 |
20140110803 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING AN EASY CONE ANISOTROPY - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2014-04-24 |
20140110804 | MAGNETORESISTIVE DEVICE AND METHOD FOR FORMING THE SAME - According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes a free magnetic layer structure having a variable magnetization orientation, and a synthetic antiferromagnetic layer structure including at least three ferromagnetic layers arranged one over the other and antiferromagnetically coupled, each ferromagnetic layer having a fixed magnetization orientation, wherein the free magnetic layer structure and the synthetic antiferromagnetic layer structure are arranged one over the other. According to further embodiments of the present invention, a method for forming a magnetoresistive device is also provided. | 2014-04-24 |
20140110805 | SILICON LIGHT TRAP DEVICES, SYSTEMS AND METHODS - Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art. | 2014-04-24 |
20140110806 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes a photoelectric conversion element, a fixed charge layer, a silicon nitride film, and a silicon oxide film. The photoelectric conversion element performs photoelectric conversion of converting incident light into the amount of charges corresponding to the amount of received light, and accumulates the charges. The fixed charge layer is formed on a light receiving surface side of the photoelectric conversion element, and holds negative fixed charges. The silicon nitride film is formed on a light receiving surface side of the fixed charge layer. The silicon oxide film is formed between the fixed charge layer and the silicon nitride film. | 2014-04-24 |
20140110807 | CAMERA MODULE - A camera module has a sensor chip including a sensor unit formed on a main surface around which sides are disposed. A lens chip is fixed to the sensor chip with a spacer unit and includes a lens unit corresponding to the sensor unit. A light shieldable layer covers a first side of the sensor chip and a side of the spacer unit. A first cutting surface includes a second side of the sensor chip and a side of the light shieldable layer on a same plane. | 2014-04-24 |
20140110808 | PHOTODIODE AND PHOTODIODE ARRAY - A photodiode array PDA | 2014-04-24 |
20140110809 | METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE - According to one embodiment, a method of manufacturing a solid-state imaging device includes a trench forming process, a concave portion forming process, a coating process, and a burying process. In the trench forming process, a trench is formed at the position to isolate a plurality of photoelectric conversion elements. In the concave portion forming process, a concave portion is formed at the position to form a light shielding film of shielding at least part of subject light incident on an adjustment photoelectric conversion element used for an image quality adjustment of an imaged image. In the coating process, inner circumferential surfaces of the trench and the concave portion are coated with an insulating film. In the burying process, a light shielding member is buried inside the trench and the concave portion whose inner circumferential surface are coated with the insulating film. | 2014-04-24 |
20140110810 | PHOTODIODE ARRAY - A light receiving region includes a plurality of light detecting sections | 2014-04-24 |
20140110811 | SEMICONDUCTOR DEVICE, IMAGING DEVICE, METHOD OF INSPECTING SEMICONDUCTOR SUBSTRATE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are electrically connected to each other in a state in which a first connection surface of the first semiconductor substrate and a second connection surface of the second semiconductor substrate face each other. A concave portion is formed in at least one of the first connection surface and the second connection surface. An electrode, which is electrically connected to a portion of wirings included in a wiring layer provided in the first semiconductor substrate or the second semiconductor substrate in which the concave portion is formed and is capable of being electrically connected to an outside, is formed in an inside of the concave portion. | 2014-04-24 |
20140110812 | BACKSIDE ILLUMINATION IMAGE SENSOR, MANUFACTURING METHOD THEREOF AND IMAGE-CAPTURING DEVICE - A backside illumination image sensor equipped with a plurality of pixels disposed in a two-dimensional pattern, includes: image-capturing pixels; and focus detection pixels. | 2014-04-24 |
20140110813 | Absorbers for High Efficiency Thin-Film PV - Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing at least one of Na, Mg, K, or Ca to increase the band gap at the front surface of the absorber layer. | 2014-04-24 |
20140110814 | Resurf High Voltage Diode - A trench-isolated RESURF diode structure ( | 2014-04-24 |
20140110815 | High Voltage Diode - A trench-isolated RESURF diode structure ( | 2014-04-24 |
20140110816 | SEMICONDUCTOR DEVICES - Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed. | 2014-04-24 |
20140110817 | SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH - Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process. | 2014-04-24 |
20140110818 | RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHOD FOR NODES THEREOF - A manufacturing method for the nodes of the RAM device, includes the steps as follows: forming a STI layer on a substrate to divide the substrate into several active areas; sequentially forming a first insulating layer and a hard mask layer on the substrate; etching the first insulating layer to form a first hole for exposing the STI layer and partial of the active areas; filling a conductive material in the first hole to form a conductor; forming a protective layer on the top surface of the conductor, wherein each protective layer has an opening aligning the STI layer; etching the conductor from the opening until the STI layer to form a second hole for exposing the STI layer, wherein each conductor is divided into two nodes by the second hole arranged therebetween; and forming a second insulating layer in the second hole for electrically isolating the nodes. | 2014-04-24 |
20140110819 | BALLASTED POLYCRYSTALLINE FUSE - A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse. | 2014-04-24 |
20140110820 | PASSIVE COMPONENT AS THERMAL CAPACITANCE AND HEAT SINK - Representative implementations of devices and techniques provide improved thermal performance of a chip die disposed within a layered printed circuit board (PCB). Passive components may be strategically located on one or more surfaces of the PCB. The passive components may be arranged to conduct heat generated by the chip die away from the chip die. | 2014-04-24 |
20140110821 | FOLDED CONICAL INDUCTOR - A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track. | 2014-04-24 |
20140110822 | Semiconductor Device Including Magnetically Coupled Monolithic Integrated Coils - A semiconductor device includes a first coil that is monolithically integrated in a first portion of a semiconductor body and that includes a first winding wrapping around a first core structure. A second coil is monolithically integrated in a second portion of the semiconductor body and includes a second winding wrapping around the second core structure. The first and second coils are magnetically coupled with each other. An insulator frame in the semiconductor body surrounds the first portion and excludes the second portion. High dielectric strength between the first and the second coils is achieved without patterning a backside metallization for connecting the turns of the windings and without being restricted to thin substrates. | 2014-04-24 |
20140110823 | CONTACT STRUCTURE - One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example. | 2014-04-24 |
20140110824 | SEMICONDUCTOR DEVICES HAVING HYBRID CAPACITORS AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes. | 2014-04-24 |
20140110825 | Compound Semiconductor Lateral PNP Bipolar Transistors - Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes. | 2014-04-24 |
20140110826 | BACKSIDE PROTECTION FOR A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) - Consistent with an example embodiment, there is a semiconductor device, having a topside surface and an underside surface, the semiconductor device comprises an active device of an area defined on the topside surface, the topside surface having a first area. A protective material is on to the underside surface of the semiconductor device, the protective material has an area greater than the first area. A laminating film attaches the protective material to the underside surface. The protective material serves to protect the semiconductor device from mechanical damage during handling and assembly onto a product's printed circuit board. | 2014-04-24 |
20140110827 | PRESSED-CONTACT TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A pressed-contact type semiconductor device includes a power semiconductor element, on an upper surface of which at least a first electrode is formed and on a lower surface of which at least a second electrode is formed, lead frames which face the first electrode and the second electrode of the power semiconductor element respectively, and a clip which applies a pressure to the lead frames while the power semiconductor element is sandwiched by the lead frames, wherein a metallic porous plating part is formed on a surface which faces the first electrode or the second electrode, the surface being a surface of at least one of the lead frames. | 2014-04-24 |
20140110828 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink. | 2014-04-24 |
20140110829 | Module Comprising a Semiconductor Chip - A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element. | 2014-04-24 |
20140110830 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package, including: a first heat radiating plate; a second heat radiating plate formed below the first heat radiating plate; a heat radiating lead formed above the first heat radiating plate and having both ends contacted with the second heat radiating plate; an insulating layer formed above the heat radiating lead; at least one power device formed above the insulating layer; and at least one control device formed above the insulating layer. | 2014-04-24 |
20140110831 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line. | 2014-04-24 |
20140110832 | CO-SUPPORT CIRCUIT PANEL AND MICROELECTRONIC PACKAGES - A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package. | 2014-04-24 |
20140110833 | POWER MODULE PACKAGE - Disclosed herein is a power module package. The power module package includes a substrate having one surface formed with a circuit pattern including a chip mounting pad and an external connection pad and the other surface; a semiconductor chip mounted on the chip mounting pad; and an external connection terminal having one terminal and the other terminal, the one terminal being connected to the external connection pad and the other terminal protruding to the outside, in which the external connection pad and the external connection terminal are bonded to each other by welding. | 2014-04-24 |
20140110834 | SEMICONDUCTOR ELEMENT COOLING STRUCTURE - A semiconductor element cooling structure includes a side wall provided on a downstream side of flow of cooling air in a cooling air passage, a plurality of cooling fins forming cooling air branch passages, and a plurality of cooling fins forming cooling air branch passages. The cooling fins each have an end portion at a tip extending toward the cooling air passage. A virtual line obtained by connecting the end portions of the plurality of cooling fins and a virtual line obtained by connecting the end portions of the plurality of cooling fins each have a gradient with respect to a direction of the flow of the cooling air in the cooling air passage which is greater on an upstream side of the flow of the cooling air in the cooling air passage than on the downstream side thereof. | 2014-04-24 |
20140110835 | Bump Package and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump. | 2014-04-24 |
20140110836 | Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods - Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region. | 2014-04-24 |
20140110837 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 2014-04-24 |
20140110838 | SEMICONDUCTOR DEVICES AND PROCESSING METHODS - Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness. | 2014-04-24 |
20140110839 | Metal Bump Joint Structure - A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension. | 2014-04-24 |
20140110840 | Semiconductor Packages with Integrated Antenna and Method of Forming Thereof - In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface. | 2014-04-24 |
20140110841 | Semiconductor Packages with Integrated Antenna and Methods of Forming Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar. | 2014-04-24 |
20140110842 | USING A DOUBLE-CUT FOR MECHANICAL PROTECTION OF A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) - Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device. | 2014-04-24 |
20140110843 | Semiconductor Unit with Submount for Semiconductor Device - A semiconductor unit includes a submount and a chip coupled to the submount. The submount is configured with a base and a plurality of layers between the base and the chip. One of the layers, a heat-spreading electro-conducting sliver (“Ag”) layer, is deposited atop the base. The thickness of the Ag layer is selected so that a cumulative coefficient of thermal expansion of the submount substantially matches that one of the chip. Coupled to the active zone of the chip is a stress-dumping layer made from elastic malleable materials. | 2014-04-24 |
20140110844 | WIRE BONDABLE SURFACE FOR MICROELECTRONIC DEVICES - The present invention concerns thin diffusion barriers in metal and metal alloy layer sequences of contact area/barrier layer/first bonding layer type for metal wire bonding applications. The diffusion barrier is selected from Co-M-P. Co-M-B and Co-M-B—P alloys wherein M is selected from Mn, Zr, Re, Mo, Ta and W having a thickness in the range 0.03 to 0.3 μm. The first bonding layer is selected from palladium and palladium alloys. | 2014-04-24 |
20140110845 | DAMASCENE GAP STRUCTURE - One or more techniques or systems for forming a damascene gap structure are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region. In this manner, a damascene gap structure associated with a cleaner gap is provided, for example. | 2014-04-24 |
20140110846 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 2014-04-24 |
20140110847 | BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES - A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width W | 2014-04-24 |
20140110848 | STRONG, HEAT STABLE JUNCTION - Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device. | 2014-04-24 |
20140110849 | Copper-Titanium Alloy Sputtering Target, Semiconductor Wiring Line Formed Using the Sputtering Target, and Semiconductor Element and Device Each Equipped with the Semiconductor Wiring Line - A copper-titanium alloy sputtering target comprising 3 at % or more and less than 15 at % of Ti and a remainder made up of Cu and unavoidable impurities, wherein a variation (standard deviation) in hardness is within 5.0 and a variation (standard deviation) in electric resistance is within 1.0 in an in-plane direction of the target. Provided are: a sputtering target for forming a copper-titanium alloy wiring line for semiconductors capable of causing the copper alloy wiring line for semiconductors to be equipped with a self-diffusion suppressive function, effectively preventing contamination around the wiring line caused by diffusion of active Cu, improving electromigration (EM) resistance, corrosion resistance and the like, enabling the arbitrary formation of a barrier layer in a simple manner, and uniformizing film properties; a copper-titanium alloy wiring line for semiconductors; and a semiconductor element and a device each equipped with the semiconductor wiring line. | 2014-04-24 |
20140110850 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film. | 2014-04-24 |
20140110851 | Semiconductor Device - A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers. | 2014-04-24 |
20140110852 | ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE - An active matrix substrate ( | 2014-04-24 |
20140110853 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. | 2014-04-24 |
20140110854 | SEMICONDUCTOR DIES WITH REDUCED AREA CONSUMPTION - The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process. | 2014-04-24 |
20140110855 | CD CONTROL - A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CD | 2014-04-24 |
20140110856 | Fan-Out Wafer Level Package Structure - A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips | 2014-04-24 |
20140110857 | REDUCTION CHEMISTRY FOR ETCHING - An etching is performed with reduction chemistry to prevent erosion of a hard mask. Embodiments include forming a hard mask over one or more layers above a substrate, patterning the hard mask to form openings in the hard mask, and etching the one or more layers with an etchant including hydrogen (H | 2014-04-24 |
20140110858 | EMBEDDED CHIP PACKAGES AND METHODS FOR MANUFACTURING AN EMBEDDED CHIP PACKAGE - A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad. | 2014-04-24 |
20140110859 | EMBEDDING THIN CHIPS IN POLYMER - Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region. | 2014-04-24 |
20140110860 | Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable. | 2014-04-24 |
20140110861 | Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer. | 2014-04-24 |
20140110862 | TSV Formation - A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material. | 2014-04-24 |
20140110863 | Power Converter Package Including Vertically Stacked Driver IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 2014-04-24 |
20140110864 | CHIP ARRANGEMENT AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side. | 2014-04-24 |
20140110865 | OPTOELECTRONIC DEVICE AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic component includes a first substrate on which are arranged an active region and a first contact region, and a first contact layer arranged in the first contact region. The second component includes a second substrate on which is arranged at least one second contact layer arranged in a second contact region. The first contact layer connects electrically conductively with the active region and additionally is bonded to the second contact layer by an adhesive layer. The adhesive layer includes an electrically conductive adhesive. The first contact layer and/or the second contact layer are patterned at least in part. | 2014-04-24 |
20140110866 | SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP - A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die. | 2014-04-24 |
20140110867 | Substrate and Method for Cutting the Substrate - The present invention discloses a method for cutting a substrate. The method includes the steps of 1) creating a etching groove in the first surface of the first sheet and the third surface of the second sheet; 2) laminating the first and second sheets with the etching grooves aligned with each other; and 3) using a cutter to cut through the second surface of first sheet and the fourth surface of the second sheet along a preset set cutting line such that a crack extending vertically to the etching grooves so as to sever the first and second sheets. The present invention further discloses a substrate. By way of the foregoing, the taper and gradient along the cutting edge can be reduced. | 2014-04-24 |
20140110868 | METHOD OF MANUFACTURING DISPLAY DEVICE - A method for forming a display device includes forming a liquid crystal layer between a first substrate and a second substrate spaced apart from the first substrate, in which the liquid crystal layer includes a liquid crystal composition including a reactive mesogen, applying an electric field to the liquid crystal layer, firstly curing the liquid crystal layer at a temperature from about −20° C. to about 60° C., and secondly curing the liquid crystal layer without applying the electric field. The liquid crystal composition includes the reactive mesogen in an amount exceeding 0 percent by weight and equal to or smaller than about 30 percent by weight relative to a total weight of the liquid crystal composition. | 2014-04-24 |
20140110869 | METHOD FOR PRODUCING CARBONACEOUS FILM, METHOD FOR PRODUCING GRAPHITE FILM, ROLL OF POLYMER FILM, AND ROLL OF CARBONACEOUS FILM - Disclosed herein is a method for producing an elongated (rolled) carbonaceous film by polymer pyrolysis while suppressing the fusion bonding of the carbonaceous film. The method for producing a carbonaceous film includes the step of heat-treating a polymer film wound into a roll, wherein the heat treatment is performed after the polymer film is wound into a roll to have a gap between adjacent layers of the polymer film at a temperature lower than a pyrolysis onset temperature of the polymer film so that the roll of polymer film as a whole satisfies a relationship that a value obtained by dividing a thickness of a gap between adjacent layers of the polymer film (Ts) by a thickness of the polymer film (Tf) (Ts/Tf) is 0.16 or higher but 1.50 or lower. As a method for forming gaps between the layers of the polymer film, a method in which the polymer film is wound into a roll together with a slip sheet and then the slip sheet is removed can be used, which is effective at suppressing the fusion bonding of a carbonaceous film. | 2014-04-24 |
20140110870 | Process For Utilising Waste Drill Cuttings In Plastics - An environmentally beneficial process for utilising waste drill cuttings from oil and gas exploration. The waste drill cuttings ( | 2014-04-24 |
20140110871 | Concept to Separate Wet End and Dry End Paper Machine Control Through Estimation of Physical Properties at the Wire - Partitioning control of the wet end and dry end, by introducing estimates of physical properties such as dry weight: and percent ash at the wire, allows for machine direction (MD) controls to continue during loss of scanner measurements. A mathematical model estimates the controlled, variables, such as dry weight, basis weight, and ash percent at the wire, and these estimated values are then controlled. When scanner measurements resume, parameters in the model are recursively updated to compensate for any model errors and ensure an accurate model. MD controls consist of a cascade set-up where the estimated wire-dry weight or wire basis weight and estimated wire ash percent are controlled by manipulating stock flow and addition of filler to stock. When scanner measurements are available, they become the downstream variables in the cascade control and are controlled by manipulation of the setpoints for the estimated wire weight and ash. | 2014-04-24 |
20140110872 | SYSTEM AND METHOD FOR ADDITIVE MANUFACTURING OF AN OBJECT - The method comprises sequentially forming a plurality of layers in a configured pattern corresponding to the shape of the object, thereby forming the object. The formation of each layer comprises dispensing at least one uncured building material, and at least partially curing the uncured building material, wherein for at least one layer, the curing is initiated at least t seconds after commencement of curing of a layer immediately preceding that layer. The t parameter is longer than the number of seconds required for the formation of the layer. | 2014-04-24 |
20140110873 | BLOW MOULDING MACHINE WITH VARIABLE INTERMEDIATE PRESSURE LEVEL - A method for the shaping of plastics material pre-forms into plastics material containers, wherein the plastics material pre-forms are introduced into a blow mould and are expanded to form the plastic bottles by being acted upon with a gaseous medium in the blow mould, includes the steps of:
| 2014-04-24 |
20140110874 | Apparatus and method for expanding preforms into containers - The invention relates to an apparatus as well as to a method for expanding preforms into containers within a blow mold by means of a pressurised pneumatic medium, wherein a compressor piston unit for compressing the pneumatic medium is in flow communication with the blow mold, in order to introduce a volume flow of the pneumatic medium into an inner region of the blow mold, and wherein an actuator unit that can be activated by a hydraulic medium interacts with at least one element of the compressor piston unit, in order to drive the compressor piston unit during an expansion process of the container for compressing the pneumatic medium, and in order to be driven itself, during a relaxation process that temporally follows the expansion process, due to the returning volume flow of the pneumatic medium into the compressor piston unit. | 2014-04-24 |
20140110875 | COMPOSITE PRODUCT MANUFACTURING SYSTEM AND METHOD - A method of manufacture of a composite material is provided. The method includes providing a deformable body having substrate and matrix materials on a surface of a first tool. The substrate material is loosely bound by the matrix material and may include a composite pre-form. The relative movement between the first tool and a second tool is controlled so as to apply pressure to the body between opposing surfaces of the first and second tools and thereby debulk and/or consolidate said body. The first or second tool includes a plurality of individually controllable tool elements, the temperature and/or displacement of said elements being controlled to generate a desired profile in said body. An adaptive debulking system and tool are also disclosed. | 2014-04-24 |
20140110876 | BLOW MOULDING MACHINE WITH A CLEAN ROOM AND A DRYING UNIT FOR SUPPLYING AIR - An apparatus is provided for moulding plastic preforms into plastic containers, including a transport unit, on which a plurality of moulding stations is provided and which moves the moulding stations along a predefined transport path, wherein the moulding stations respectively have blow mould parts that are movable relative to each other, the parts are movable relative to each other for opening and closing blow moulds; and including a clean room that surrounds a transport path, along which the moulding stations are transported, and which is separated from an environment by at least one wall; wherein the apparatus includes a cooling system for cooling at least one element of the respective moulding stations; and wherein the apparatus includes a supply unit that supplies a gaseous medium to the clean room. The apparatus also includes a drying unit for drying the gaseous medium supplied to the clean room via the supply unit. | 2014-04-24 |
20140110877 | THERMOPLASTIC TOUGHENING MATERIAL AND RELATED METHOD - A non-fibrous, apertured membrane comprises at least one thermoplastic polymeric material and has a discrete porous structure. The membrane is soluble in the thermoset matrix polymer of a composite material. | 2014-04-24 |
20140110878 | Dough Cutting and Stamping Apparatus and Method - An apparatus is provided for forming, cutting and stamping a dough sheet into a plurality of uniformly stamped, imprinted dough pieces. The apparatus engages a leading portion of a dough sheet as it travels along a conveyor. The apparatus includes a drum rotatably disposed relative to the conveyor, a plurality of cutter molds disposed on the rotatable drum and a plurality of pattern imprinters formed within internal cavities defined by the plurality of cutter molds. Each of the cutter molds simultaneously cuts a dough piece received in the internal cavity and imprints on the dough piece to form a rounded edge roll. The pattern imprinter preferably has a star configuration for stamping the dough to form Kaiser-type rolls. | 2014-04-24 |
20140110879 | METHOD FOR MAKING, INKING, AND MOUNTING STAMPS FOR MICRO-CONTACT PRINTING - A method of preparing a patterned micro-contact printing stamp for micro contact printing including the making of a submaster of e.g. epoxy, against which a micro-contact printing stamp from polydimethylsiloxane or other stamp forming material can be formed. The micro-contact printing stamp can then be exposed to an inking material while the micro-contact printing stamp is still against the submaster, resulting in a micro-contact printing stamp capable of making numerous impressions before the inking material is exhausted. | 2014-04-24 |
20140110880 | THERMOPLASTIC ELASTOMER COMPOUNDS EXHIBITING SHAPE MEMORY VIA THERMO-MECHANICAL ACTION - A thermoplastic elastomer compound is disclosed having a high strain recovery rate and a high strain fixity rate to provide shape memory, preferably manageable shape memory. One type of thermoplastic elastomer compound is comprises a maleated styrenic block copolymer and polycaprolactone to achieve the shape memory. A second type of thermoplastic elastomer compound comprises styrene-ethylene/butylene-styrene and a paraffin wax having less than about 0.5% oil content. Shape modes of articles made from the thermoplastic elastomer compound can be altered by at least one thermo-mechanical event to cause deformation of the compound from a first shape to a second shape with retention of the compound in the second shape for any reasonable time interval. | 2014-04-24 |
20140110881 | CONTROLLED-RELEASE AMINE-CATALYZED, SULFUR-CONTAINING POLYMER AND EPOXY COMPOSITIONS - Compositions comprising sulfur-containing polymers such as polythioethers and polysulfides, polyepoxides, and controlled-release amine catalysts useful in aerospace sealant applications are disclosed. The compositions exhibit extended pot life and the rate of curing can be tailored for specific applications. | 2014-04-24 |