17th week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130099259 | HIGH-VOLTAGE LIGHT-EMITTING DEVICE - The present invention relates to a high-voltage light-emitting device suitable for light-emitting diode chip array module. The device comprises a set of light emitting diode chips, about 18-25 chips, deposited on a substrate by using a non-matrix arrangement. Through the adjustments, the high-voltage light-emitting device of the present invention has optimized luminous efficiency. | 2013-04-25 |
20130099260 | RESIST STRIPPING COMPOSITION AND METHOD OF STRIPPING RESIST USING THE SAME - Disclosed herein is a resist stripping composition, which has an excellent ability of stripping a residual resist remaining after dry or wet etching at the tune of forming patterns in a process of manufacturing a flat panel display substrate. | 2013-04-25 |
20130099261 | LIGHT EMITTING MODULE - In a light emitting module, a semiconductor light emitting element is mounted on a mounting board. A plated layer is provided on the surface of the mounting board so as to be electrically connected to the semiconductor light emitting element mounted on the mounting board. The plated layer has a power feeding portion and an element connection portion. The power feeding portion extends, of the surfaces of the mounting board, from the upper surface on which the semiconductor light emitting element is to be mounted to a stepped surface located below the upper surface, so that power can be fed, on the stepped surface, to the semiconductor light emitting element. The element connection portions are provided on the upper surface such that a plurality of the semiconductor light emitting elements mounted on the upper surface are connected together in series. | 2013-04-25 |
20130099262 | LIQUID CRYSTAL DISPLAY - A liquid crystal display according to an exemplary embodiment of the present invention includes a substrate, a plurality of pixels arranged in a matrix on the substrate where each pixel includes a switching element, a plurality of gate lines that are connected to the switching elements and extend in a row direction, and a gate driver that is connected to the gate lines and is formed on the substrate as an integrated circuit. In the liquid crystal display, the gate driver includes a first region and a second region that is not aligned with the first region. | 2013-04-25 |
20130099263 | FULL SPECTRUM LED LIGHT SOURCE - A LED light source has a red, blue and green LED triad for generating a full spectrum of colored light that appears to be emanating from a point source. The LED triad is mounted in a CPC that is surrounded by a cylindrical reflector. | 2013-04-25 |
20130099264 | SOLID STATE LIGHT SOURCES BASED ON THERMALLY CONDUCTIVE LUMINESCENT ELEMENTS CONTAINING INTERCONNECTS - Solid state light sources based on LEDs mounted on or within thermally conductive luminescent elements provide both convective and radiative cooling. Low cost self-cooling solid state light sources can integrate the electrical interconnect of the LEDs and other semiconductor devices. The thermally conductive luminescent element can completely or partially eliminate the need for any additional heatsinking means by efficiently transferring and spreading out the heat generated in LED and luminescent element itself over an area sufficiently large enough such that convective and radiative means can be used to cool the device. | 2013-04-25 |
20130099265 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device includes a light emitting structure comprising a first area comprising a first semiconductor layer doped with a first dopant, a second semiconductor layer doped with a second dopant and a first active layer, and a second area comprising a third semiconductor layer doped with the first dopant and comprising an exposed region, a fourth semiconductor layer arranged on the third semiconductor layer except for the exposed region and doped with the second dopant and a second active layer, and provided with first and second trenche formed from the fourth semiconductor layer to the first semiconductor layer and separated from each other, a first electrode comprising first and second electrode pad, a second electrode, and a third electrode arranged on the fourth semiconductor layer and comprising a third electrode pad, a fourth electrode pad and a fifth electrode pad. | 2013-04-25 |
20130099266 | RADIATION-EMITTING SEMICONDUCTOR DEVICE - A radiation-emitting semiconductor device includes a chip connection region, a radiation-emitting semiconductor chip, and a light-absorbing material, wherein the radiation-emitting semiconductor chip is fixed to the chip connection region, the chip connection region is covered with the light-absorbing material at selected locations at which said chip connection region is not covered by the radiation-emitting semiconductor chip, and the radiation-emitting semiconductor chip is free of the light-absorbing material in locations. | 2013-04-25 |
20130099267 | LIGHT EMITTING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - A light emitting device (LED) package and a manufacturing method thereof are provided. The LED package may include a package body including a cavity, a first lead frame and a second lead frame that are disposed in the cavity of the package body, and an LED mounted on a bottom surface of the cavity of the package body, the LED including a transparent substrate, a first semiconductor layer, an active layer, and a second semiconductor layer that are laminated sequentially in one of a first direction that is parallel to the bottom surface of the cavity and a second direction that is inclined with respect to the bottom surface of the cavity. | 2013-04-25 |
20130099268 | WAFER-SCALED LIGHT-EMITTING STRUCTURE - This invention discloses a wafer-scaled light-emitting structure comprising a supportive substrate; an anti-deforming layer; a bonding layer; and a light-emitting stacked layer, wherein the anti-deforming layer reduces or removes the deformation like warp caused by thinning of the substrate. | 2013-04-25 |
20130099269 | ELECTRONIC ASSEMBLY - An electronic assembly includes a first substrate and a second substrate, a hole through the first substrate, the second substrate having a trace with an indentation, an electronic device mounted over the indentation in the trace, and the first substrate is attached to the second substrate such that the electronic device is positioned within the hole through the first substrate. | 2013-04-25 |
20130099270 | LEAD FRAME FOR OPTICAL SEMICONDUCTOR DEVICE, METHOD OF PRODUCING THE SAME, AND OPTICAL SEMICONDUCTOR DEVICE - A lead frame for an optical semiconductor device, having a reflection layer at least on one side or each side of the outermost surface of a substrate, partially or entirely, in which the reflection layer has, on the outermost surface at least in a region where light emitted by an optical semiconductor element is reflected, a microstructure with at least the surface thereof having been mechanically deformed, which is converted from a plating microstructure formed of a metal or an alloy thereof; a method of producing the same, and an optical semiconductor device having the same. | 2013-04-25 |
20130099271 | LIGHT-EMITTING DEVICE AND LIGHTING APPARATUS INCORPORATIONG SAME - A light-emitting device is provided that can extract light in all directions and that has wide directivity. This light-emitting device includes: an elongated bar-shaped package extending sideways, the package being formed such that a plurality of leads are formed integrally with a first resin with part of the leads exposed; a light-emitting element that is fixed onto at least one of the leads and that is electrically connected to at least one of the leads; and a second resin sealing the light-emitting element. In the light-emitting device, the first resin and the second resin are formed of optically transparent resin, and the leads have outer lead portions used for external connection and protruding sideways from both left and right ends of the package. | 2013-04-25 |
20130099272 | OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip includes a semiconductor body, having an n-conducting region and a p-conducting region, and a single n-type contact element, via which the n-conducting region can be electrically contact-connected through the p-conducting region. | 2013-04-25 |
20130099273 | WIRING SUBSTRATE, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate. | 2013-04-25 |
20130099274 | LIGHT EMITTING ELEMENT - A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect. | 2013-04-25 |
20130099275 | LED PACKAGE AND METHOD OF MAKING THE SAME - LED packages and their fabrication techniques are disclosed to provide LED package with improved thermal dissipation based on one or more thermally conductive channels or studs. In one implementation, a LED package includes a plastic body structured to have a hole that penetrates through the plastic body; a metal contact formed on the plastic body at one side of the hole to cover the hole; a LED mounted to the metal contact at a location that spatially overlaps with the hole; and a stud formed in the hole in contact with the metal contact at a first end of the stud and extending to an opening of the hole at a second end of the stud, the stud being formed of a thermally conductive material to transfer heat from the LED through the metal contact and the stud to dissipate the heat at the opening of the hole via the second end of the stud. | 2013-04-25 |
20130099276 | LED LIGHT SOURCE DEVICE AND MANUFACTURING METHOD FOR THE SAME - An object of the invention is to provide an LED light source device and a manufacturing method for the same that can maintain high reflectance over an extended period of time notwithstanding the interaction between light and heat. More specifically, the invention provides an LED light source device that includes a substrate, an electrode formed on the substrate, a white inorganic resist layer deposited over the substrate so as to cover a surface thereof everywhere except where the electrode is formed, and an LED element connected to the electrode, wherein the white inorganic resist layer contains fine white inorganic particles dispersed or mixed into an inorganic binder, and a method for manufacturing such an LED light source device. | 2013-04-25 |
20130099277 | SELECTIVE DRY ETCHING OF N-FACE (Al,In,Ga)N HETEROSTRUCTURES - A method of selective dry etching of N-face (Al,In,Ga)N heterostructures through the incorporation of an etch-stop layer into the structure, and a controlled, highly selective, etch process. Specifically, the method includes: (1) the incorporation of an easily formed, compatible etch-stop layer in the growth of the device structure, (2) the use of a laser-lift off or similar process to decouple the active layer from the original growth substrate, and (3) the achievement of etch selectivity higher than 14:1 on N-face (Al,In,Ga)N. | 2013-04-25 |
20130099278 | SCR APPARATUS AND METHOD FOR ADJUSTING THE SUSTAINING VOLTAGE - An SCR apparatus includes an SCR structure and a first N injection region. The SCR structure includes a P+ injection region, a P well, an N well and a first N+ injection region, the first N injection region is located under an anode terminal of the P+ injection region of the SCR structure. A method for adjusting a sustaining voltage therefor is provided as well. | 2013-04-25 |
20130099279 | POWER SEMICONDUCTOR DEVICE - An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer. | 2013-04-25 |
20130099280 | OVERVOLTAGE AND/OR ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An overvoltage protection devices operable to provide protection against overvoltage events of positive and negative polarity, comprising: an N P N semiconductor structure defining: a first N-type region; a first P-type region; and a second N-type region; wherein one of the first or second N-type regions is connected to a terminal, conductor or node that is to be protected against an overvoltage event, and the other one of the first or second N-type regions is connected to a reference, and wherein a field plate is in electrical contact with the first P-type region, and the field plate overlaps with but is isolated from portions of the first and second N type regions. | 2013-04-25 |
20130099281 | POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION - Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches. | 2013-04-25 |
20130099282 | FinFET Device And Method Of Manufacturing Same - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first dielectric layer disposed over the substrate. The semiconductor device further includes a buffer layer disposed over the substrate and between first and second walls of a trench of the dielectric layer. The semiconductor device further includes an insulator layer disposed over the buffer layer and between the first and second wall of the trench of the dielectric layer. The semiconductor device also includes a second dielectric layer disposed over the first dielectric layer and the insulator layer. Further, the semiconductor device includes a fin structure disposed over the insulator layer and between first and second walls of a trench of the second dielectric layer. | 2013-04-25 |
20130099283 | III-V Multi-Channel FinFETs - A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric. | 2013-04-25 |
20130099284 | GROUP III-NITRIDE METAL-INSULATOR-SEMICONDUCTOR HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed. | 2013-04-25 |
20130099285 | HIGH ELECTRON MOBILITY TRANSISTOR HAVING REDUCED THRESHOLD VOLTAGE VARIATION AND METHOD OF MANUFACTURING THE SAME - According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area. | 2013-04-25 |
20130099286 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A first GaN layer, a first AlGaN layer, a second GaN layer and a third GaN layer are formed in layers on a substrate. A second AlGaN layer is formed on the sidewall of an opening formed in the multilayer structure. A gate electrode is formed to fill an electrode trench in an insulating film. A portion of the insulating film between the gate electrode and the second AlGaN layer functions as a gate insulating film. A source electrode is formed above the gate electrode and a drain electrode is formed below the gate electrode. This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor. | 2013-04-25 |
20130099287 | GALLIUM ARSENIDE HETEROJUNCTION SEMICONDUCTOR STRUCTURE - Embodiments of semiconductor structure are disclosed along with methods of forming the semiconductor structure. In one embodiment, the semiconductor structure includes a semiconductor substrate, a collector layer formed over the semiconductor substrate, a base layer formed over the semiconductor substrate, and an emitter layer formed over the semiconductor substrate. The semiconductor substrate is formed from Gallium Arsenide (GaAs), while the base layer is formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound. The base layer formed from the GaInNAsSb compound has a low bandgap, but a lattice that substantially matches a lattice constant of the underlying semiconductor substrate formed from GaAs. In this manner, semiconductor devices with lower base resistances, turn-on voltages, and/or offset voltages can be formed using the semiconductor structure. | 2013-04-25 |
20130099288 | SiGe HBT and Manufacturing Method Thereof - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which a shallow trench is formed of a first shallow trench and a second shallow trench vertically joined together in the active region, the second shallow trench being located directly under the first shallow trench and having a width less than that of the first shallow trench; a pseudo buried layer is formed surrounding the bottom and side walls of the second shallow trench and is in contact with the collector region to serve as a connection layer of a collector; a deep hole contact is formed in the shallow trench and is in contact with the pseudo buried layer to pick up the collector. A SiGe HBT manufacturing method is also disclosed. The present invention is capable of improving the cut-off frequency of a SiGe HBT. | 2013-04-25 |
20130099289 | Compact Memory Arrays - Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels. | 2013-04-25 |
20130099290 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is a method for manufacturing a semiconductor device that can improve the performance of a photodiode that is formed on a same substrate as a thin film transistor without greatly deteriorating the productivity of the semiconductor device. On a glass substrate | 2013-04-25 |
20130099291 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREFOR - A solid-state imaging device includes a first and second pixel regions. In the first pixel region, a photoelectric conversion unit, a floating diffusion region (FD), and a transferring transistor are provided. In the second pixel region, an amplifying transistor, and a resetting transistor are provided. A first element isolation portion is provided in the first pixel region, while a second element isolation portion is provided in the second pixel region. An amount of protrusion of an insulating film into a semiconductor substrate in the first element isolation portion is smaller, than that in the second element isolation portion. | 2013-04-25 |
20130099292 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor substrate of a semiconductor device has a sensor region and an integrated circuit region, and a cavity is formed immediately under a surface layer portion of the sensor region. A capacitive acceleration sensor is formed on the sensor region by working a surface layer portion of the semiconductor substrate opposed to the cavity. The capacitive acceleration sensor includes an interdigital fixed electrode and an interdigital movable electrode. A CMIS transistor is formed on the integrated circuit region. The CMIS transistor includes a P-type well region and an N-type well region formed on the surface layer portion of the semiconductor substrate. A gate electrode is opposed to the respective ones of the P-type well region and the N-type well region through a gate insulating film formed on a surface of the semiconductor substrate. | 2013-04-25 |
20130099293 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region. | 2013-04-25 |
20130099294 | MOSFETs with Multiple Dislocation Planes - A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes forming a first dislocation plane adjacent to a gate electrode of the MOSFET, and forming a second dislocation plane adjacent to the gate electrode of the MOSFET. The first and the second dislocation planes are on a same side of the gate electrode, and extend into source/drain regions of the MOSFET. | 2013-04-25 |
20130099295 | REPLACEMENT GATE FABRICATION METHODS - Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region. | 2013-04-25 |
20130099296 | TRANSISTOR WITH SELF-ALIGNED CHANNEL WIDTH - A device includes a transistor including a source and a drain disposed in a substrate and a gate disposed above the substrate. The gate includes a first longitudinal member disposed above the source and the drain and running substantially parallel to a channel of the transistor. The first longitudinal member is disposed over a first junction isolation area. The gate also includes a second longitudinal member disposed above the source and the drain and running substantially parallel to the channel of the transistor. The second longitudinal member is disposed over a second junction isolation region. The gate also includes a cross member running substantially perpendicular to the channel of the transistor and connecting the first longitudinal member to the second longitudinal member. The cross member is disposed above and between the source and the drain. | 2013-04-25 |
20130099297 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device electrically connected between a pad and an internal circuit is provided and includes a capacitor, a first resistor, a voltage-drop element and an NMOS transistor. A first end of the capacitor is electrically connected to the pad. A first end of the first resistor is electrically connected to a second end of the capacitor, and a second end of the first resistor is electrically connected to ground. The NMOS transistor and the voltage-drop element are connected in series between the pad and the ground, a gate of the NMOS transistor is electrically connected to the second end of the capacitor, and a bulk of the NMOS transistor is electrically connected to the ground. | 2013-04-25 |
20130099298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a buried gate formed in a mat and in an adjacent dummy region. A space larger than is conventional is formed in a dummy region of a mat edge where the buried gate is to be created. This larger space inhibits shortening of an end of a buried gate and reduction in pattern size attributable to lithographic distortion arising between patterned (mat) and unpatterned (dummy) regions. Device reliability is thereby improved by avoiding gap-fill defects of a gate material. | 2013-04-25 |
20130099299 | Semiconductor Device - An object is to provide a semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of times of writing operations. A semiconductor device includes a source-bit line, a first signal line, a second signal line, a word line, and a memory cell connected between the source-bit lines. The memory cell includes a first transistor, a second transistor, and a capacitor. The second transistor is formed including an oxide semiconductor material. A gate electrode of the first transistor, one of a source and drain electrodes, and one of electrodes of the capacitor are electrically connected to one another. The source-bit line and a source electrode of the first transistor are electrically connected to each other. Another source-bit line adjacent to the above source-bit line and a drain electrode of the first transistor are electrically connected to each other. | 2013-04-25 |
20130099300 | Floating Gate Structure of Flash Memory Device and Method for Fabricating the Same - The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an I-shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability. | 2013-04-25 |
20130099301 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THEREOF - A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern. | 2013-04-25 |
20130099302 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device according to embodiment of the present invention includes a tunnel insulating layer formed over a semiconductor substrate, a floating gate formed over the tunnel insulating layer, a dielectric layer formed over the floating gate, and a control gate including a third silicon layer formed over the dielectric layer, a fourth silicon layer formed over the third silicon layer, and a conductive layer formed over the fourth silicon layer, wherein the fourth silicon layer has a greater width than the third silicon layer. | 2013-04-25 |
20130099303 | MEMORY AND MANUFACTURING METHOD THEREOF - A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures. | 2013-04-25 |
20130099304 | 3-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another. | 2013-04-25 |
20130099305 | SEMICONDUCTOR DEVICES INCLUDING A VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - Semiconductor devices having vertical channel transistors are provided. The semiconductor device includes an insulation layer on a substrate and a buried bit line on the insulation layer. The buried bit line extends in a first direction. An active pillar is disposed on the buried bit line. The active pillar includes a lower dopant region, a channel region having a first sidewall and an upper dopant region vertically stacked on the buried bit line. A contact gate electrode is disposed to be adjacent to the first sidewall of the channel region. A word line is electrically connected to the contact gate electrode. The word line extends in a second direction intersecting the first direction. A string body connector is electrically connected to the channel region. Related methods are also provided. | 2013-04-25 |
20130099306 | 3-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines. | 2013-04-25 |
20130099307 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer. | 2013-04-25 |
20130099308 | Semiconductor Device Having a Through Contact and a Manufacturing Method Therefor - According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material. | 2013-04-25 |
20130099309 | VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE - A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions. | 2013-04-25 |
20130099310 | Trench MOS Device with Schottky Diode and Method for Manufacturing Same - In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction. | 2013-04-25 |
20130099311 | INTEGRATED GATE RUNNER AND FIELD IMPLANT TERMINATION FOR TRENCH DEVICES - In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench. | 2013-04-25 |
20130099312 | SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING - A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type. | 2013-04-25 |
20130099313 | FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE - FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide. | 2013-04-25 |
20130099314 | Semiconductor Device With Multiple Stress Structures And Method Of Forming The Same - A method of fabricating and a semiconductor device with multiple dislocation structures is disclosed. The exemplary semiconductor device includes gate structure overlying a top surface of a semiconductor substrate and a first gate spacer disposed on a sidewall of the gate structure and overlying the top surface of the substrate. The semiconductor device further includes a crystallized semiconductor material overlying the top surface of the semiconductor substrate and adjacent to a sidewall of the first gate spacer. The semiconductor device further includes a second gate spacer disposed on the sidewall of the first gate spacer and overlying the crystallized semiconductor material. The semiconductor device further includes a first stressor region disposed in the semiconductor substrate and a second stressor region disposed in the semiconductor substrate and in the crystallized semiconductor material. | 2013-04-25 |
20130099315 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region. | 2013-04-25 |
20130099316 | SELECTIVE FLOATING BODY SRAM CELL - A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. | 2013-04-25 |
20130099317 | Fin-Based Adjustable Resistor - According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel. | 2013-04-25 |
20130099318 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 2013-04-25 |
20130099319 | THIN SEMICONDUCTOR-ON-INSULATOR MOSFET WITH CO-INTEGRATED SILICON, SILICON GERMANIUM AND SILICON DOPED WITH CARBON CHANNELS - A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate. | 2013-04-25 |
20130099320 | SEMICONDUCTOR DEVING HAVING METAL GATE ELECTRODE AND METHOD OF FABRICATION THEREOF - The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer. | 2013-04-25 |
20130099321 | METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRATED CIRCUIT DIE USING THERMAL PROXIMITY CORRECTION - A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal. | 2013-04-25 |
20130099322 | METHOD FOR MANUFACTURING INSULATED-GATE TRANSISTORS - A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate. | 2013-04-25 |
20130099323 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region. | 2013-04-25 |
20130099324 | GAN-ON-SI SWITCH DEVICES - A low leakage current switch device ( | 2013-04-25 |
20130099325 | SEMICONDUCTOR DEVICE - A semiconductor device is implementated that includes a source region, multiple elongated drain regions, a channel region, a source electrode, a drain electrode, and a gate electrode. The source region is a flat planar region formed on a compound semiconductor layer. The multiple elongated drain regions are formed so that they are each electrically isolated from each other on the compound semiconductor layer. The channel region is formed so that it contacts one side of the source region and is electrically isolated from the source region and the multiple elongated drain regions. The source electrode is formed at least in a portion on top of the source region. The drain electrode is formed so that it is connected electrically to the multiple elongated drain regions. The gate electrode is formed so that it is connected electrically to the multiple channel regions. | 2013-04-25 |
20130099326 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures. | 2013-04-25 |
20130099327 | CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate, a well region formed in the substrate, and a gate formed on the substrate. The CMOS device also includes a first region and a second region formed in the well region and arranged at two sides of the gate. Further, the CMOS device includes a first light-doped drain (LDD) region and a second LDD region formed in the well region and extending the first region and the second region, respectively, towards the gate. The CMOS device also includes a first doped layer formed in the first LDD region, and a conduction type of an ion doped in the first doped layer is opposite to a conduction type of an ion doped in the first LDD region. | 2013-04-25 |
20130099328 | P-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET. | 2013-04-25 |
20130099329 | METHOD FOR MANUFACTURING INSULATED-GATE MOS TRANSISTORS - A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate. | 2013-04-25 |
20130099330 | Controllable Undercut Etching of Tin Metal Gate Using DSP+ - A wet process utilizing a dilute acid oxidant solution, for example, a dilute sulfuric acid with hydrogen peroxide is used in the fabrication of a metal gate electrode of a semiconductor device, offering high etch selectivity and high controllability to achieve a desired profile for the metal gate electrode. In some embodiments, the dilute acid oxidant solution is a dilute sulfuric peroxide solution, comprising at least 50% or 80% by weight of water, less than 30% or 15% by weight of sulfuric acid, and less than 20% or 20% of hydrogen peroxide with optionally less than 100 ppm or 30 ppm ozone. In some embodiments, the dilute sulfuric peroxide solution further comprises less than 100 ppm of hydrofluoric acid. The dilute acid oxidant solution can be used effectively to clean the metal gate electrode or to form an undercut on a metal gate layer of the metal gate electrode. | 2013-04-25 |
20130099331 | STRUCTURE AND PROCESS FOR MICROELECTROMECHANICAL SYSTEM-BASED SENSOR - A structure and a process for a microelectromechanical system (MEMS)-based sensor are provided. The structure for a MEMS-based sensor includes a substrate chip. A first insulating layer covers a top surface of the substrate chip. A device layer is disposed on a top surface of the first insulating layer. The device layer includes a periphery region and a sensor component region. The periphery region and a sensor component region have an air trench therebetween. The component region includes an anchor component and a moveable component. A second insulating layer is disposed on a top surface of the device layer, bridging the periphery region and a portion of the anchor component. A conductive pattern is disposed on the second insulating layer, electrically connecting to the anchor component. | 2013-04-25 |
20130099332 | WAFER LEVEL PACKAGING - A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer. | 2013-04-25 |
20130099333 | MICRO-ELECTRO-MECHANICAL SYSTEM HAVING MOVABLE ELEMENT INTEGRATED INTO LEADFRAME-BASED PACKAGE - A MEMS may integrate movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, leaving the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package may be a leadframe-based plastic molded body having an opening through the thickness of the body. The movable part may be anchored in the body and extend at least partially across the opening. The chip may be flip-assembled to the leads to span across the foil, and may be separated from the foil by a gap. The leadframe may be a prefabricated piece part, or may be fabricated in a process flow with metal deposition on a sacrificial carrier and patterning of the metal layer. The resulting leadframe may be flat or may have an offset structure useful for stacked package-on-package devices. | 2013-04-25 |
20130099334 | Z-Axis Semiconductor Fluxgate Magnetometer - A z-axis fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence forms a vertical magnetic core structure, a first wire structure wound around the magnetic core structure, and a second wire structure wound around the magnetic core structure. | 2013-04-25 |
20130099335 | Novel Magnetic Tunnel Junction Device And Its Fabricating Method - Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes. | 2013-04-25 |
20130099336 | MAGNETIC TUNNEL JUNCTION DEVICE AND ITS FABRICATING METHOD - The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention. | 2013-04-25 |
20130099337 | MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetic memory element includes a memory layer, a first nonmagnetic layer, a reference layer, a second nonmagnetic layer, and an adjustment layer which are stacked. The adjustment layer is configured to reduce a leakage magnetic field from the reference layer. The adjustment layer is formed by stacking an interface layer provided on the second nonmagnetic layer, and a magnetic layer having magnetic anisotropy perpendicular to a film surface. Saturation magnetization of the interface layer is larger than that of the magnetic layer. | 2013-04-25 |
20130099338 | MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetic memory element includes a memory layer having magnetic anisotropy perpendicular to a film surface and having a variable magnetization direction, a first nonmagnetic layer provided on the memory layer, and a reference layer provided on the first nonmagnetic layer, having magnetic anisotropy perpendicular to a film surface, and having an invariable magnetization direction. An area of the memory layer is larger than that of the reference layer. Magnetization in an end portion of the memory layer is smaller than that in a central portion of the memory layer. | 2013-04-25 |
20130099339 | Spintronic Electronic Device and Circuits - A spintronic electronic apparatus having a multilayer structure. The apparatus includes a substrate, having disposed in succession upon the substrate; a bottom interface layer; a pinned layer; a tunneling barrier; a free layer; and a top interface layer, wherein the apparatus operates as a non-resonant magnetic tunnel junction in a large amplitude, out-of-plane magnetization precession regime having weakly current dependent, large diode volt-watt sensitivity when external microwave signals that exceed a predetermined threshold current and have a frequency that is lower than a predetermined level excite the magnetization precession. | 2013-04-25 |
20130099340 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, SIGNAL TRANSMISSION/RECEPTION METHOD USING SUCH SEMICONDUCTOR DEVICE, AND TESTER APPARATUS - A semiconductor device includes a substrate, a bonding pad provided above the substrate, a first signal transmitting/receiving portion provided above the substrate and below the bonding pad, and a transistor provided over the substrate. The transistor is connected to the first signal transmitting/receiving portion. | 2013-04-25 |
20130099341 | IMAGE SENSOR FOR STABILIZING A BLACK LEVEL - An image sensor includes first pixels, second pixels and a deep trench. The first pixels are formed in an active region of a semiconductor substrate, and configured to measure photo-charges corresponding to incident light. The second pixels are formed in an optical-black region of the semiconductor substrate, and are configured to measure black levels. The deep trench is formed vertically in a boundary region of the optical-black region, where the boundary region is adjacent to the active region, and configured to block leakage light and diffusion carriers from the active region. | 2013-04-25 |
20130099342 | LATERAL COLLECTION PHOTOVOLTAICS - A nanostructured or microstructured array of elements on a conductor layer together form a device electrode of a photovoltaic or detector structure. The array on the conductor layer has a high surface area to volume ratio configuration defining a void matrix between elements. An active layer or active layer precursors is disposed into the void matrix as a liquid to form a thickness coverage giving an interface on which a counter-electrode is positioned parallel to the conduction layer or as a vapor to form a conformal thickness coverage of the array and conduction layer. The thickness coverage is controlled to enhance collection of at least one of electrons and holes arising from photogeneration, or excitons arising from photogeneration, to the device electrode or a device counter-electrode as well as light absorption in said active layer via reflection and light trapping of said device electrode. | 2013-04-25 |
20130099343 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: a plurality of pixel cells; and column signal lines. Each of the pixel cells includes: a photoelectric conversion film, a pixel electrode, a transparent electrode, an amplifier transistor, a reset transistor, and an address transistor. The solid-state imaging device further includes: a lower-refractive-index transparent layer formed above the transparent electrode; and higher-refractive-index transparent parts embedded in the lower-refractive-index transparent layer and each having a refractive index higher than a refractive index of the lower-refractive-index transparent layer. Each of the higher-refractive-index transparent parts separates light passing through the higher-refractive-index transparent part into zero-order diffracted light, first-order diffracted light, and negative-first-order diffracted light which exit the higher-refractive-index transparent part and travel toward the photoelectric conversion film. | 2013-04-25 |
20130099344 | RADIATION IMAGE PICKUP APPARATUS, RADIATION IMAGE PICKUP SYSTEM, AND METHOD FOR MANUFACTURING RADIATION IMAGE PICKUP APPARATUS - The present invention provides a radiation image pickup apparatus in which one or more image pickup elements are easily exchanged. | 2013-04-25 |
20130099345 | ELECTRICAL CONTACTS TO NANOSTRUCTURED AREAS - A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed. | 2013-04-25 |
20130099346 | Back-Side Readout Semiconductor Photomultiplier - This disclosure provides systems, methods, and apparatus related to semiconductor photomultipliers. In one aspect, a device includes a p-type semiconductor substrate, the p-type semiconductor substrate having a first side and a second side, the first side of the p-type semiconductor substrate defining a recess, and the second side of the p-type semiconductor substrate being doped with n-type ions. A conductive material is disposed in the recess. A p-type epitaxial layer is disposed on the second side of the p-type semiconductor substrate. The p-type epitaxial layer includes a first region proximate the p-type semiconductor substrate, the first region being implanted with p-type ions at a higher doping level than the p-type epitaxial layer, and a second region disposed on the first region, the second region being doped with p-type ions at a higher doping level than the first region. | 2013-04-25 |
20130099347 | SUPERJUNCTION SEMICONDUCTOR DEVICE - A superjunction semiconductor device is disclosed in which the trade-off relationship between breakdown voltage characteristics and voltage drop characteristics is considerably improved, and it is possible to greatly improve the charge resistance of an element peripheral portion and long-term breakdown voltage reliability. It includes parallel pn layers of n-type drift regions and p-type partition regions in superjunction structure. PN layers are depleted when off-state voltage is applied. Repeating pitch of the second parallel pn layer in a ring-like element peripheral portion encircling the element active portion is smaller than repeating pitch of the first parallel pn layer in the element active portion. Element peripheral portion includes low concentration n-type region on the surface of the second parallel pn layer. The depth of p-type partition region of an outer peripheral portion in the element peripheral portion is smaller than the depth of p-type partition region of an inner peripheral portion. | 2013-04-25 |
20130099348 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction. | 2013-04-25 |
20130099349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening. | 2013-04-25 |
20130099350 | Semiconductor Device and Method of Manufacture - A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material. | 2013-04-25 |
20130099351 | BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A bipolar transistor is disclosed, which includes a collector region, a base region, an emitter region and field plates. Each field plate is present in a structure of a flat sidewall covering one side face of the active region so that it also covers the collector region from one side. The field plate has its surface parallel to the side face of the active region and is isolated from the side face of the active region by a pad oxide layer. The field plate has its top lower than the surface of the active region. The bipolar transistor is capable of improving the breakdown voltage of the device without increasing the collector resistance or deteriorating the frequency characteristic. A method of manufacturing bipolar transistor is also disclosed. | 2013-04-25 |
20130099352 | STRUCTURE AND METHOD FOR A HIGH-K TRANSFORMER WITH CAPACITIVE COUPLING - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 2013-04-25 |
20130099353 | ESD PROTECTION DEVICE - An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer provided on a surface of the semiconductor substrate. An ESD protection circuit is provided on or in an outer layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post electrodes. First ends of the interlayer wiring lines disposed in the thickness direction are connected to the input/output electrodes disposed on the surface of the semiconductor substrate, and second ends of the interlayer wiring lines are connected to first ends of the in-plane wiring lines routed in plan view. Prismatic post electrodes are provided between second ends of the in-plane wiring lines and terminal electrodes. | 2013-04-25 |
20130099354 | CAPACITOR WITH DEEP TRENCH ION IMPLANTATION - An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance. | 2013-04-25 |
20130099355 | MEMS Structures and Methods for Forming the Same - A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer | 2013-04-25 |
20130099356 | Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing - A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property. | 2013-04-25 |
20130099357 | STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON - A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer. | 2013-04-25 |
20130099358 | ELECTRONIC, OPTICAL AND/OR MECHANICAL APPARATUS AND SYSTEMS AND METHODS FOR FABRICATING SAME - Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate. | 2013-04-25 |