17th week of 2022 patent applcation highlights part 58 |
Patent application number | Title | Published |
20220130671 | METHOD AND STRUCTURE FOR CUTTING DENSE LINE PATTERNS USING SELF-ALIGNED DOUBLE PATTERNING - A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer. | 2022-04-28 |
20220130672 | SEMICONDUCTOR STRUCTURE FORMATION METHOD AND MASK - A semiconductor structure formation method and a mask are provided. One form of the formation method includes: providing a base, including a target layer; forming a mandrel material layer on the base, the mandrel material layer including a first region and a second region encircling the first region; performing ion doping on the mandrel material layer in the second region, the ion doping being suitable for increasing the etching resistance of the mandrel material layer, where the mandrel material layer in the second region serves as an anti-etching layer, and the mandrel material layer in the first region serves as a mandrel layer; forming a first trench that runs through, along a first direction, at least part of the mandrel material layer in the first region, where part of the mandrel material layer in the first region remains at two sides of the first trench along a second direction; forming spacers on side walls of the first trench, so that the spacers form a first groove by encircling; removing the mandrel layer to form second grooves; and etching, using the anti-etching layer and the spacers as masks, the target layer below the first groove and the second grooves, to form the target pattern. In embodiments and implementations of the present disclosure, a pitch between target patterns is further compressed. | 2022-04-28 |
20220130673 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR - A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×10 | 2022-04-28 |
20220130674 | DEVICE AND METHOD FOR BONDING OF SUBSTRATES - A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force F | 2022-04-28 |
20220130675 | PROCESSED WAFER AND METHOD OF MANUFACTURING CHIP FORMATION WAFER - A method of manufacturing a chip formation wafer includes: forming an epitaxial film on a first main surface of a silicon carbide wafer to provide a processed wafer having one side adjacent to the epitaxial film and the other side; irradiating a laser beam into the processed wafer from the other side of the processed wafer so as to form an altered layer along a surface direction of the processed wafer; and separating the processed wafer with the altered layer as a boundary into a chip formation wafer having the one side of the processed wafer and a recycle wafer having the other side of the processed wafer. The processed wafer has a beveling portion at an outer edge portion of the processed wafer, and an area of the other side is larger than an area of the one side in the beveling portion. | 2022-04-28 |
20220130676 | METHODS AND DEVICES FOR SUBTRACTIVE SELF-ALIGNMENT - A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes. | 2022-04-28 |
20220130677 | Semiconductor Device and Manufacturing Method Thereof - The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure. | 2022-04-28 |
20220130678 | BARRIER LAYER FOR CONTACT STRUCTURES OF SEMICONDUCTOR DEVICES - The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure. | 2022-04-28 |
20220130679 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure in provided. The method includes providing a substrate, forming a gate electrode layer on the substrate, and performing a defluorination treatment on the gate electrode layer. The method also includes, after performing the defluorination treatment, forming a barrier layer on a portion of a surface of the gate electrode layer. The barrier layer is made of a material including titanium element. | 2022-04-28 |
20220130680 | METHOD FOR STRUCTURING A SUBSTRATE - A method for structuring a substrate is specified, in particular structuring by means of selective etching in the semiconductor and IC substrate industry, in which the following steps are carried out: providing a substrate, applying a titanium seed layer, full-area coating with a photoresist layer, lithographic structuring of the photoresist layer, in order to expose regions of the titanium seed layer, selectively depositing copper as conductor tracks in those areas in which the titanium seed layer is exposed, removing the structured photoresist, and etching the titanium seed layer in the areas previously covered by the structured photoresist, wherein phosphoric acid is used to etch the titanium seed layer and, in addition, exposure to UV light is carried out during the etching of the titanium. | 2022-04-28 |
20220130681 | METHOD OF ETCHING AN INDIUM GALLIUM ZINC OXIDE (IGZO) STRUCTURE - A method of etching an indium gallium zinc oxide (IGZO) structure is provided. In one aspect, the method includes exposing the IGZO structure to a reactant flow including a hydrocarbon-based reactant. Thereby, a reactant layer is formed on the IGZO structure. The method also includes exposing the reactant layer formed on the IGZO structure to an argon flow. Thereby, one or more reactant molecules are removed from the reactant layer. The one or more reactant molecules, which are removed from the reactant layer formed on the IGZO structure, are removed together with one or more IGZO molecules, thus leading to an etching of the IGZO structure. | 2022-04-28 |
20220130682 | STIFFENER PACKAGE AND METHOD OF FABRICATING STIFFENER PACKAGE - A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns. | 2022-04-28 |
20220130683 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; providing a supporting platform having a plurality of vacuum valves; disposing a substrate on the supporting platform; applying vacuum attraction to a portion of the substrate through a portion of the plurality of vacuum valves, wherein the portion of the substrate corresponding to the vacuum attraction is defined as an attracted region; and performing an exposure on a portion of the attracted region, wherein an area of the attracted region is larger than the basic working area and smaller than an area of the supporting platform. | 2022-04-28 |
20220130684 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH BONDING - A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the device includes a plurality of capacitors. | 2022-04-28 |
20220130685 | SEMICONDUCTOR PACKAGES - Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line. | 2022-04-28 |
20220130686 | CONTROL OF UNDER-FILL USING AN ENCAPSULANT AND A TRENCH OR DAM FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE - Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls in combination with a dam or a trench to control the distribution of an under-fill material between one or more components and a packaging substrate. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant reduces the tendency of the under-fill material to wick around the solder balls by capillary action which can prevent or limit the capillary under-fill material from flowing onto or contacting other components. The dam or trench aids in retaining the under-fill material within a keep out zone to prevent or limit the under-fill material from contacting other components. | 2022-04-28 |
20220130687 | GASBOX FOR SEMICONDUCTOR PROCESSING CHAMBER - Exemplary semiconductor processing chambers may include a gasbox including a first plate having a first surface and a second surface opposite to the first surface. The first plate of the gasbox may define a central aperture that extends from the first surface to the second surface. The first plate may define an annular recess in the second surface. The first plate may define a plurality of apertures extending from the first surface to the annular recess in the second surface. The gasbox may include a second plate characterized by an annular shape. The second plate may be coupled with the first plate at the annular recess to define a first plenum within the first plate. | 2022-04-28 |
20220130688 | SEMICONDUCTOR CHAMBER COMPONENTS WITH HIGH-PERFORMANCE COATING - Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a showerhead. The chambers may include a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled with the platen along a second surface of the platen opposite the first surface of the platen. The shaft may extend at least partially through the chamber body. A coating may extend conformally about the first surface of the platen, the second surface of the platen, and about the shaft. | 2022-04-28 |
20220130689 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus configured to process a combined substrate in which a first substrate having thereon a device layer and a second substrate are bonded to each other includes a holder configured to hold a rear surface of the second substrate; a processing unit configured to process the first substrate held by the holder; a first processing liquid supply configured to etch a front surface of the first substrate by supplying a first processing liquid to the front surface of the first substrate opposite to a surface thereof where the device layer is provided; and a second processing liquid supply configured to remove a metal contaminant on the rear surface of the second substrate by supplying a second processing liquid to the rear surface of the second substrate. | 2022-04-28 |
20220130690 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus configured to dry a substrate with a processing fluid in a supercritical state includes: a processing vessel; a substrate holder configured to hold the substrate horizontally within the processing vessel; a first supply line connected to a first fluid supply provided at the processing vessel and configured to supply the processing fluid into the processing vessel; a drain line connected to a drain unit provided at the processing vessel and configured to drain the processing fluid from the processing vessel; a bypass line branched off from the first supply line and connected to the drain line, the bypass line being configured to allow at least a part of the processing fluid flowing in the first supply line to be drained into the drain line without passing through the processing vessel; and a bypass opening/closing valve configured to open or close the bypass line. | 2022-04-28 |
20220130691 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method of performing liquid processing on a substrate in a substrate processing apparatus, which includes a substrate table configured to suction the substrate, a heater configured to heat the substrate table, and a processing liquid nozzle configured to supply a processing liquid to the substrate suctioned to the substrate table, includes: a suctioning process of suctioning the substrate by the substrate table when there is no temperature difference between the substrate and the substrate table or when a temperature difference between the substrate and the substrate is within a predetermined range; and after the suctioning process, a processing liquid supply process of supplying the processing liquid from the processing liquid nozzle to the substrate suctioned to the substrate table heated by the heater. | 2022-04-28 |
20220130692 | SEMICONDUCTOR CHAMBER COMPONENT CLEANING SYSTEMS - Exemplary semiconductor chamber component cleaning systems may include a receptacle. The receptacle may include a bottom lid that may be an annulus. The annulus may be characterized by an inner annular wall and an outer annular wall. A plurality of recessed annular ledges may be defined between the inner annular wall and the outer annular wall. Each recessed annular ledge of the plurality of recessed annular ledges may be formed at a different radial position along the bottom lid. The cleaning systems may include a top lid removably coupled with the bottom lid about an exterior region of the top lid. The cleaning systems may include a tank defining a volume to receive the receptacle. | 2022-04-28 |
20220130693 | Semiconductor Fabrication System Embedded with Effective Baking Module - The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber. | 2022-04-28 |
20220130694 | DYNAMIC RELEASE TAPES FOR ASSEMBLY OF DISCRETE COMPONENTS - A method includes positioning a discrete component assembly on a support fixture of a component transfer system, the discrete component assembly including a dynamic release tape including a flexible support layer, and a dynamic release structure disposed on the flexible support layer, and a discrete component adhered to the dynamic release tape. The method includes irradiating the dynamic release structure to release the discrete component from the dynamic release tape. | 2022-04-28 |
20220130695 | PROCESSING SYSTEM AND TRANSFER METHOD - There is provided a processing system. The processing system comprises: a chamber in which a consumable member is installed; a storage module configured to store the consumable member; a position detection sensor configured to detect a position of the consumable member; a vacuum transfer module connected to the chamber and the storage module, the vacuum transfer module having a transfer robot configured to transfer the consumable member between the chamber and the storage module; and a controller. The controller is configured to perform processes of: (a) controlling the transfer robot to transfer the consumable member installed in the chamber to the storage module; (b) detecting the position of the consumable member transferred to the storage module by the position detection sensor; and (c) controlling the transfer robot to transfer a new consumable member different from the consumable member from the storage module to the chamber at a position adjusted based on the position of the consumable member detected in the process (b). | 2022-04-28 |
20220130696 | ROBOT EMBEDDED VISION APPARATUS - A substrate transport apparatus includes a transport chamber, a drive section, a robot arm, an imaging system with a camera mounted through a mounting interface of the drive section in a predetermined location with respect to the transport chamber and disposed to image part of the arm, and a controller connected to the imaging system and configured to image, with the camera, the arm moving to or in the predetermined location, the controller effecting capture of a first image of the arm on registry of the arm proximate to or in the predetermined location, the controller is configured to calculate a positional variance of the arm from comparison of the first image with a calibration image of the arm, and determine a motion compensation factor changing an extended position of the arm. Each camera effecting capture of the first image is disposed inside the perimeter of the mounting interface. | 2022-04-28 |
20220130697 | METHOD OF MONITORING TOOL - A method includes transferring a tool monitoring device to a load port of a tool. An environmental parameter of the load port is monitored by the tool monitoring device. The tool monitoring device is removed from the load port after the environmental parameter of the load port is monitored. A door of the tool in front of the load port is closed. The door of the tool is kept closed during a period from a time of transferring the tool monitoring device to the load port to a time of removing the tool monitoring device from the load port. | 2022-04-28 |
20220130698 | GAS PURGE DEVICE AND GAS PURGING METHOD - The present disclosure provides a gas purge device and a gas purge method for purging a wafer container to clean wafers. The gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration. | 2022-04-28 |
20220130699 | EQUIPMENT FRONT END MODULE - Proposed is an EFEM configured to perform wafer transfer between a wafer storage device and process equipment. More particularly, proposed is an EFEM that prevents harmful gases inside a transfer chamber in which wafer transfer is performed from escaping out of the EFEM. | 2022-04-28 |
20220130700 | TRANSPORT SYSTEM - Embodiments herein relate to a transport system and a substrate processing and transfer (SPT) system. The SPT system includes a transport system that connects two processing tools. The transport system includes a vacuum tunnel that is configured to transport substrates between the processing tools. The vacuum tunnel includes a substrate transport carriage to move the substrate through the vacuum tunnel. The SPT system has a variety of configurations that allow the user to add or remove processing chambers, depending on the process chambers required for a desired substrate processing procedure. | 2022-04-28 |
20220130701 | SUBSTRATE TRANSFER APPARATUS, SUBSTRATE TRANSFER METHOD, AND SUBSTRATE PROCESSING SYSTEM - A substrate transport apparatus which transports a substrate to a substrate transport position. The apparatus comprises: a transport unit including a substrate holder that holds the substrate, a base having magnets and configured to move the substrate holder, and a link member connecting the substrate holder to the base; and a planar motor having a main body, electromagnetic coils arranged in the main body, and a linear driver supplying power to the electromagnetic coils to magnetically levitate and linearly drive the base. The base includes a first member and a second member rotatably provided in the first member, and the magnets are provided inside the first member and the second member, the link member is rotatably connected to the second member, and the linear driver rotates the second member with respect to the first member and expands and contracts the substrate holder via the link member. | 2022-04-28 |
20220130702 | METHOD FOR ADJUSTING CONTACT POSITION OF LIFT PINS, METHOD FOR DETECTING CONTACT POSITION OF LIFT PINS, AND SUBSTRATE PLACEMENT MECHANISM - A method for adjusting a contact position of lift pins in a substrate placement mechanism is provided. The substrate placement mechanism includes a substrate placement table and a substrate lifting mechanism having lift pins and a driving mechanism, wherein the contact position of the lift pins is a height position where tip ends of the lift pins get in contact with the substrate. The method comprises creating torque waveforms, for a plurality of voltages, indicating temporal changes of a torque of the motor while moving the tip ends of the lift; obtaining from the plurality of torque waveforms a contact point when the lift pins get in contact with the substrate and calculating the contact position from the contact point and a speed of the motor; determining whether the contact position is within an appropriate range; and automatically adjusting the contact position when the contact position is not within the appropriate range. | 2022-04-28 |
20220130703 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - The inventive concept relates to a substrate treating method including measuring an alignment state of a substrate placed on a hand of a transfer unit that transfers the substrate, transferring the substrate to a substrate alignment unit by the transfer unit when the alignment state of the substrate is faulty, and aligning a location of the substrate by the substrate alignment unit, wherein the substrate treating method includes temporarily correcting the location of the substrate before the substrate is loaded on the substrate alignment unit when it is measured in the measuring of the alignment state that the alignment state of the substrate exceeds a sensor reading range. | 2022-04-28 |
20220130704 | BIPOLAR ELECTROSTATIC CHUCK TO LIMIT DC DISCHARGE - Exemplary support assemblies may include an electrostatic chuck body defining a support surface that defines a substrate seat. The assemblies may include a support stem coupled with the chuck body. The assemblies may include a heater embedded within the chuck body. The assemblies may include a first bipolar electrode embedded within the electrostatic chuck body between the heater and support surface. The assemblies may include a second bipolar electrode embedded within the chuck body between the heater and support surface. Peripheral edges of one or both of the first and second bipolar electrodes may extend beyond an outer periphery of the seat. The assemblies may include an RF power supply coupled with the first and second bipolar electrodes. The assemblies may include a first floating DC power supply coupled with the first bipolar electrode. The assemblies may include a second floating DC power supply coupled with the second bipolar electrode. | 2022-04-28 |
20220130705 | ELECTROSTATIC CHUCK WITH POWDER COATING - An electrostatic chuck (ESC) is provided. An ESC body is provided. An organic coating is disposed on at least a surface of the ESC body | 2022-04-28 |
20220130706 | ETCHING APPARATUS AND METHODS OF CLEANING THEREOF - A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus. | 2022-04-28 |
20220130707 | TRANSFER SUBSTRATE - A transfer substrate for an element includes a support and an elastic body. The support includes a first surface including a first opening portion and a second surface located on the opposite side of the first surface and having a groove portion. The elastic body includes a third surface closing an upper surface of the groove portion and a fourth surface located on the opposite side of the third surface and including a plurality of projection portions. Each of the plurality of projection portions includes a second opening portion. The first opening portion and the second opening portion are penetrated via the groove portion. | 2022-04-28 |
20220130708 | High Flow Vacuum Chuck - A vacuum chuck is provided, comprising: a vacuum buffer in fluid communication with a vacuum source, the vacuum buffer being an enclosed volume in the vacuum chuck; a top plate, defining surface features on a first side, and an internal network of distribution channels open to the first side via through holes; and a flow valve configured to control fluid communication between the network of distribution channels and the vacuum buffer. By opening the flow valve, negative pressure is applied from between a substrate disposed on the first side of the top plate through the through holes into the vacuum buffer, thereby flattening the substrate against at least part of the first side of the top plate. | 2022-04-28 |
20220130709 | STAGE STRUCTURE FOR SEMICONDUCTOR FABRICATION PROCESS, SYSTEM OF PICKING UP SEMICONDUCTOR CHIP, AND METHOD OF CONTROLLING TILTING ANGLE OF PICKUP HEAD - A stage structure for a semiconductor fabrication process is disclosed. The stage structure may include a stage and a pickup head tilting control device. The pickup head tilting control device may include a correction plate, a tilting driving device which is coupled to the correction plate and is configured to adjust an inclination angle of the correction plate, and a control circuitry configured to control the tilting driving device. The correction plate may include a correction surface which is selectively in contact with a suction surface of a pickup head. | 2022-04-28 |
20220130710 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - An apparatus for treating a substrate includes a transfer part, a first transfer robot and a second transfer robot disposed in a longitudinal direction of the transfer part, a liquid treating part disposed at one side of the transfer part to apply a liquid onto the substrate by supplying the liquid to the substrate, and a heat treating part disposed at an opposite side of the transfer part to face a first process treating part, to perform heat-treatment with respect to the substrate. The heat treating part includes a cooling transfer module to transfer the substrate between the first transfer robot and the second transfer robot and to cool the substrate. | 2022-04-28 |
20220130711 | Material Handling Robot - An apparatus including a controller; a robot drive; a robot arm connected to the robot drive, where the robot arm has links including an upper arm, a first forearm connected to a first end of the upper arm, a second forearm connected to a second opposite end of the upper arm, a first end effector connected to the first forearm and a second end effector connected to the second forearm; and a transmission connecting the robot drive to the first and second forearms and the first and second end effectors. The transmission is configured to rotate the first and second forearms relative to the upper arm and rotate the first and second end effectors on their respective first and second forearms. The upper arm is substantially rigid and movement of the upper arm by the robot drive moves both the first and second forearms in opposite directions. | 2022-04-28 |
20220130712 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes: a rotary table provided inside a processing container; a stage provided on an upper surface of the rotary table in order to mount a substrate thereon, and configured to revolve by a rotation of the rotary table; a heater configured to heat the substrate mounted on the stage; and a rotation shaft provided at a location that rotates together with the rotary table to freely rotate while supporting the stage, and including a low heat conductivity body formed of a material with a heat conductivity lower than that of the stage. | 2022-04-28 |
20220130713 | SEMICONDUCTOR PROCESSING CHAMBER TO ACCOMMODATE PARASITIC PLASMA FORMATION - Exemplary processing systems may include a chamber body. The systems may include a pedestal configured to support a semiconductor substrate. The systems may include a faceplate. The chamber body, the pedestal, and the faceplate may define a processing region. The faceplate may be coupled with an RF power source. The systems may include a remote plasma unit. The remote plasma unit may be coupled at electrical ground. The systems may include a discharge tube extending from the remote plasma unit towards the faceplate. The discharge tube may define a central aperture. The discharge tube may be electrically coupled with each of the faceplate and the remote plasma unit. The discharge tube may include ferrite extending about the central aperture of the discharge tube. | 2022-04-28 |
20220130714 | INTERCONNECT STRUCTURES AND METHODS FOR FORMING SAME - A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing. | 2022-04-28 |
20220130715 | METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE - The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; providing a supporting platform having a plurality of vacuum valves; disposing a substrate on the supporting platform; applying vacuum attraction to a portion of the substrate through a portion of the plurality of vacuum valves, wherein the portion of the substrate corresponding to the vacuum attraction is defined as an attracted region; and performing an exposure on a portion of the attracted region, wherein an area of the attracted region is larger than the basic working area and smaller than an area of the supporting platform. | 2022-04-28 |
20220130716 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate having a trench therein; a first layer covering the bottom and the sidewall of the trench; and a second layer covering the surface of the first layer, wherein the step coverage of the second layer is different from the step coverage of the first layer. The embodiment of the invention is conducive to obtaining a multi-layer structure with preset step coverage. | 2022-04-28 |
20220130717 | DEEP TRENCH ISOLATION WITH SEGMENTED DEEP TRENCH - A semiconductor device has a first trench and a second trench of a trench structure located in a substrate. The second trench is separated from the first trench by a trench space that is less than a first trench width of the first trench and less than a second trench width of the second trench. The trench structure includes a doped sheath having a first conductivity type, contacting and laterally surrounding the first trench and the second trench. The doped sheath extends from the top surface to an isolation layer and from the first trench to the second trench across the trench space. The semiconductor device includes a first region and a second region, both located in the semiconductor layer, having a second, opposite, conductivity type. The first region and the second region are separated by the first trench, the second trench, and the doped sheath. | 2022-04-28 |
20220130718 | STEPPED TOP VIA FOR VIA RESISTANCE REDUCTION - Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity. | 2022-04-28 |
20220130719 | DIFFERENTIAL HARDMASKS FOR MODULATION OF ELECTROBUCKET SENSITIVITY - Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations. | 2022-04-28 |
20220130720 | FORMATION METHOD OF SEMICONDUCTOR STRUCTURE - Provided is a formation method of a semiconductor structure, including: providing a substrate having a first region and a second region, a plurality of discrete through holes being formed in the substrate, an arrangement density of the through holes in the first region being greater than that in the second region; forming a sacrificial layer filling the through holes; etching some thickness of the substrate around the sacrificial layer to form openings, the openings surrounding the sacrificial layer, a depth of the opening being less than a depth of the through hole in a direction perpendicular to a surface of the substrate; and removing the sacrificial layer, the openings communicating with the corresponding through holes to form trenches. | 2022-04-28 |
20220130721 | APPLICATION OF SELF-ASSEMBLED MONOLAYERS FOR IMPROVED VIA INTEGRATION - Methods for fabricating an IC structure by applying self-assembled monolayers (SAMs) are disclosed. An example IC structure includes a stack of three metallization layers provided over a support structure, where the first metallization layer includes a bottom metal line, the third metallization layer includes a top metal line, and the second metallization layer includes a via coupled between the bottom metal line and the top metal line, where via's sidewalls are enclosed by a first dielectric material. Application of one or more SAMs results in at least a portion of the via's sidewalls being lined with a second dielectric material so that the second dielectric material is between the first dielectric material and an electrically conductive material of the via, where the dielectric constant of the second dielectric material is higher than that of the first dielectric material and lower than about 6. | 2022-04-28 |
20220130722 | MULTI COLOR STACK FOR SELF ALIGNED DUAL PATTERN FORMATION FOR MULTI PURPOSE DEVICE STRUCTURES - A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity. | 2022-04-28 |
20220130723 | METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH AIR GAPS FOR LOW CAPACITANCE INTERCONNECTS - A method of fabricating air gaps in advanced semiconductor devices for low capacitance interconnects. The method includes exposing a substrate to a gas pulse sequence to deposit a material that forms an air gap between raised features. | 2022-04-28 |
20220130724 | METHODS AND APPARATUS FOR LOW RESISTIVITY AND STRESS TUNGSTEN GAP FILL - Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr. | 2022-04-28 |
20220130725 | THROUGH SILICON VIA AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV. | 2022-04-28 |
20220130726 | SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR STRUCTURE - Embodiments of the present disclosure propose a semiconductor packaging method and a semiconductor structure. The semiconductor packaging method includes: providing a substrate; forming a metal pad on the substrate, where there is a gap between a sidewall of the metal pad and the substrate; and connecting multiple metal pads on substrates to each other. | 2022-04-28 |
20220130727 | SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT - A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first conductive feature and a second conductive feature surrounded by the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element having a first portion over the second dielectric layer and a second portion penetrating through the second dielectric layer to be electrically connected to the first conductive feature. In addition, the semiconductor device structure includes a conductive via penetrating through the second dielectric layer to be electrically connected to the second conductive feature. The second portion of the resistive element is wider than the conductive via. | 2022-04-28 |
20220130728 | METHOD FOR PRODUCING A DIODE - At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate. | 2022-04-28 |
20220130729 | Semiconductor Device and Method of Manufacture - A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices. | 2022-04-28 |
20220130730 | Semiconductor Device and Method - A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes. | 2022-04-28 |
20220130731 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a stack structure disposed on a lower structure; an insulating structure disposed on the stack structure; and a vertical structure extending in a direction perpendicular to an upper surface of the lower structure and having side surfaces opposing the stack structure and the insulating structure. The stack structure includes interlayer insulating layers and gate layers, alternately stacked, and the insulating structure includes a lower insulating layer, an intermediate insulating layer on the lower insulating layer, and an upper insulating layer on the intermediate insulating layer. | 2022-04-28 |
20220130732 | OXYGEN VACANCY PASSIVATION IN HIGH-K DIELECTRICS FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR - Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer. | 2022-04-28 |
20220130733 | SEMICONDUCTOR DEVICE INCLUDING A TEST DUMMY PATTERN, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ERROR USING THE TEST DUMMY PATTERN - In a method of inspecting an error, a lower wiring structure may be formed. A main dummy pattern and a test dummy pattern may be formed on the lower wiring structure, The main dummy pattern may include a via pattern and a wiring pattern having a width greater than a width of the via pattern. The test dummy pattern may be spaced apart from the main dummy pattern by no less than a critical distance. The test dummy pattern may have a width substantially the same as that of the via pattern. The test dummy pattern may have a height substantially the same as that of the main dummy pattern. The test dummy pattern may then be tested to predict an error of the main dummy pattern based on an error of the test dummy pattern. | 2022-04-28 |
20220130734 | LIDDED SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having a top surface and a bottom surface; a semiconductor die mounted on the top surface of the substrate; and a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die. The lid comprises an annular lid base and a cover plate removably installed on the annular lid base. The semiconductor package can be uncovered by removing the cover plate and a forced cooling module can be installed in place of the cover plate. | 2022-04-28 |
20220130735 | PACKAGE FOR POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A package for a power semiconductor device includes a housing, a power semiconductor module disposed within the housing, first and second fluidic channels extending through the housing on opposite sides of the power semiconductor module, and first and second arrays of heat transfer elements respectively disposed within the first and second fluidic channels. The first and second arrays of heat transfer elements are respectively physically bonded to first and second major surfaces of the power semiconductor module. A method of manufacturing a package for a power semiconductor device includes (i) respectively bonding first and second arrays of heat transfer elements to first and second major surfaces of a power semiconductor module, (ii) encapsulating the heat transfer elements within a sacrificial material, (iii) forming a housing around the sacrificial material and the heat transfer elements, and (iv) removing the sacrificial material from the housing to form first and second fluidic channels. | 2022-04-28 |
20220130736 | CONDUCTIVE FEATURE WITH NON-UNIFORM CRITICAL DIMENSION AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions. | 2022-04-28 |
20220130737 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate which comprises a first surface and a second surface opposing each other, a hard macro which is disposed on the first surface of the substrate, comprises a cell area and a halo area formed along the periphery of the cell area, and comprises a first connection wiring disposed at a first metal level and having at least a part extending from the cell area to the halo area, a first power rail which is disposed on the second surface of the substrate and receives a first voltage, and a first through via which penetrates the halo area and the substrate to connect the first power rail and the first connection wiring and is a single structure. | 2022-04-28 |
20220130738 | FLEXIBLE INTERPOSER - The present invention provides for an interposer subassembly that is suitable for an electronic system having at least one integrated circuit (1C) component. The interposer subassembly comprises a flexible base layer, having a first surface and an opposing second surface, at least one active electronic circuit component, operatively integrated within said flexible base layer, and at least one first patterned contact layer, provided on any one of said first surface and said second surface of said flexible base layer and which is configured to operably interface with said at least one active electronic circuit component and the at least one 1C component. | 2022-04-28 |
20220130739 | FLEXIBLE SUBSTRATE AND SEMICONDUCTOR APPARATUS - A flexible substrate includes a first area including a first circuit, the first circuit configured to be connectable to a first component, a second area including a second circuit, the second circuit configured to be connectable to a second component, a connecting area provided between the first area and the second area and including a third circuit, the third circuit connecting the first circuit and the second circuit, one or more first via conductors provided between the first area and the connecting area and electrically isolated from the first circuit, the second circuit, and the third circuit, and one or more second via conductors provided between the second area and the connecting area and electrically isolated from the first circuit, the second circuit, and the third circuit. | 2022-04-28 |
20220130740 | POWER MODULE - A power module can include a casing mounted to a baseplate that contains a substrate with circuitry. The circuitry can include pins for coupling signals to/from the circuitry. These pins can extend through a cover portion of the casing so that an electronic substrate, such as a printed circuit board (PCB) can be press-fit onto the pins. When press-fit, the electronic substrate is supported and positioned by support pillars that extend from the base plate to above the cover portion of the casing. If the pins and the support pillars have different coefficients of thermal expansion, damage to connection points between the pins and the circuitry may occur. Here, a power module is disclosed that has thermally matched pins and support pillars so that when the system is thermally cycled over a range of temperatures, the connection points are not damaged by forces induced by thermal expansion. | 2022-04-28 |
20220130741 | PACKAGE STRUCTURE FOR PASSIVE COMPONENT TO DIE CRITICAL DISTANCE REDUCTION - Disclosed is a package and methods for making same. A package includes: a substrate having a first region comprising N number of metallization layers and a second region comprising M number of metallization layers, where M is less than N; a passive component located within the second region on a first surface of the substrate; and a die located within the second region on a second surface of the substrate opposite the first surface of the substrate, the die being electrically coupled to the passive component by at least one of the M number of metallization layers within the second region. | 2022-04-28 |
20220130742 | GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION - Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed. | 2022-04-28 |
20220130743 | GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES - Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring. | 2022-04-28 |
20220130744 | REDISTRIBUTION STRUCTURE AND FORMING METHOD THEREOF - Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer. | 2022-04-28 |
20220130745 | VERTICAL INTERCONNECTS WITH VARIABLE PITCH FOR SCALABLE ESCAPE ROUTING - The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side. | 2022-04-28 |
20220130746 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a first insulation layer, a first through hole extending through the first insulation layer in a thickness-wise direction, a first via wiring formed in the first through hole, a second insulation layer formed on an upper surface of the first insulation layer, a first recess formed in a lower surface of the second insulation layer and connected to the first through hole, an opening formed in an upper surface of the second insulation layer and connected to the first recess, a second recess formed in an upper surface of the first via wiring and connected to the first recess, a second via wiring formed in the opening, the first recess, and the second recess, and a first wiring pattern formed on the upper surface of the second insulation layer and electrically connected to the first via wiring by the second via wiring. | 2022-04-28 |
20220130747 | LIGHT-EMITTING SUBSTRATE AND DISPLAY APPARATUS - A light-emitting substrate includes a base, a first conductive pattern layer disposed on the base and a second conductive pattern layer disposed on a side of the first conductive pattern layer away from the base. The first conductive pattern layer includes first signal lines. The second conductive pattern layer includes lamp bead pads. The lamp bead pads include first lamp bead pads and at least one second lamp bead pad. A vertical projection of each first lamp bead pad on the base at least partially overlaps with a vertical projection of a first signal line on the base. A vertical projection of each second lamp bead pad on the base is outside vertical projections of the first signal lines on the base. A distance between a first lamp bead pad and the base is substantially the same as a distance between a second lamp bead pad and the base. | 2022-04-28 |
20220130748 | METHODS OF EMBEDDING MAGNETIC STRUCTURES IN SUBSTRATES - Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material. | 2022-04-28 |
20220130749 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME - Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer. | 2022-04-28 |
20220130750 | SOLDER MASK FOR THERMAL PAD OF A PRINTED CIRCUIT BOARD TO PROVIDE RELIABLE SOLDER CONTACT TO AN INTEGRATED CIRCUIT - A method of forming a solder connection includes forming a solder mask on a thermal pad of a printed circuit board. The solder mask leaves unmasked portions of the thermal pad and forming the solder mask includes forming a plurality of mask stripes extending from edges of each unmasked portion towards a center of the unmasked portion. The method includes depositing solder paste on the unmasked portions of the thermal pad and placing an exposed thermal pad of an integrated circuit package on the solder paste deposited on the thermal pad of the printed circuit board. The method includes forming a solder connection by heating the solder paste between the unmasked portions of the thermal pad on the printed circuit board and the exposed thermal pad of the integrated circuit package. | 2022-04-28 |
20220130751 | COPPER PLATING STRUCTURE AND PACKAGE STRUCTURE INCLUDING THE SAME - A copper plating structure and a package structure including the same are provided, and the copper plating structure includes at least one first copper layer and at least one second copper layer. The first copper layer includes a (111) crystal plane, wherein a proportion of the (111) crystal plane in each of the first copper layers is 36% to 100%. The second copper layer is located on the first copper layer and includes a non-(111) crystal plane or includes a (111) crystal plane and a non-(111) crystal plane, wherein a proportion of the (111) crystal plane in each of the second copper layers is 0% to 57%. | 2022-04-28 |
20220130752 | SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability. | 2022-04-28 |
20220130753 | METAL-OXIDE-METAL (MOM) CAPACITORS FOR INTEGRATED CIRCUIT MONITORING - An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices. | 2022-04-28 |
20220130754 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged. | 2022-04-28 |
20220130755 | INTERCONNECT STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via. | 2022-04-28 |
20220130756 | INTERCONNECT STRUCTURE - An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line. | 2022-04-28 |
20220130757 | INTERCONNECT STRUCTURE AND METHODS THEREOF - A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed. | 2022-04-28 |
20220130758 | STITCHING TO ENABLE DENSE INTERCONNECT ARRANGEMENTS - Methods for fabricating interconnect arrangements of a metallization layer Mx by using stitching that is enabled by subtractive metallization are disclosed. An example method includes providing a metal layer and a collection layer over the metal layer. The method then includes forming openings for two sets of metal lines by performing a first lithographic process to provide, in the collection layer, first openings for a first set of lines, and then performing a second lithographic process to provide, in the collection layer, second openings for a second set of lines. The method further includes performing a third lithographic process to provide a further opening (a stitch opening) that overlaps with at least one of the first openings of a first track and at least one of the second openings of a second track, and, finally, transferring the pattern of the first, second, and stitch openings to the metal layer. | 2022-04-28 |
20220130759 | BACKSIDE SIGNAL INTERCONNECTION - A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate. | 2022-04-28 |
20220130760 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SAME - A semiconductor device includes one or more active semiconductor components, wherein a front side is defined over the semiconductor substrate and a back side is defined beneath the semiconductor substrate. A front side power rail is formed at the front side of the semiconductor device and is configured to receive a first reference power voltage. First and second back side power rails are formed on the back side of the semiconductor substrate and are configured to receive corresponding second and third reference power voltages. The first, second and third reference power voltages are different from each other. | 2022-04-28 |
20220130761 | INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE - An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers. | 2022-04-28 |
20220130762 | SEMICONDUCTOR STRUCTURE AND MANUFACTURE METHOD THEREOF - A method of making a semiconductor structure can include: (i) forming a plurality of oxide layers on a semiconductor substrate; (ii) forming a plurality of conductor layers on the plurality of oxide layers; (iii) forming plurality of thickening layers on the plurality of conductor layers; (iv) patterning the plurality of conductor layers and the plurality of thickening layers to form a hard mask; and (v) implanting ion using the hard mask to form a plurality of doped regions. | 2022-04-28 |
20220130763 | ENABLING LONG INTERCONNECT BRIDGES - A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown. | 2022-04-28 |
20220130764 | LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COMMODITY PROGRAMMABLE LOGIC IC CHIP AND MEMORY IC CHIP - A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar. | 2022-04-28 |
20220130765 | SUBSTRATE LOSS REDUCTION FOR SEMICONDUCTOR DEVICES - Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad. | 2022-04-28 |
20220130766 | SUBSTRATE HAVING ELECTRONIC COMPONENT EMBEDDED THEREIN - A substrate having an electronic component embedded therein includes a core structure including a first insulating body and core wiring layers and having a cavity penetrating through a portion of the first insulating body, an electronic component disposed in the cavity, an insulating material covering at least a portion of each of the core structure and the electronic component and disposed in at least a portion of the cavity, a wiring layer disposed on the insulating material, and a build-up structure disposed on the insulating material and including a second insulating body and a build-up wiring layer. A material of the first insulating body has a coefficient of thermal expansion (CTE) less than a CTE of the second insulating body, and the insulating material has a CTE less than a CTE of a material of the second insulating body. | 2022-04-28 |
20220130767 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip | 2022-04-28 |
20220130768 | LEADLESS POWER AMPLIFIER PACKAGES INCLUDING TOPSIDE TERMINATIONS AND METHODS FOR THE FABRICATION THEREOF - Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports. | 2022-04-28 |
20220130769 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF - An electronic package is provided, in which at least one first electronic component is arranged on one surface of a circuit structure with circuit layers and a plurality of second electronic components are arranged on the other surface. The first electronic component can electrically bridge two of the plurality of second electronic components via the circuit layers to replace part of the circuit layers of the circuit structure, so that the circuit layers of the circuit structure can maintain a larger wiring specification and reduce the number of circuit layers, thereby improving the process yield. | 2022-04-28 |
20220130770 | Copper Filled Recess Structure and Method for Making the Same - The present application discloses a copper filled recess structure, which comprises a recess formed in a first dielectric layer; a block layer is formed on the bottom surface and side surfaces of the recess; a cobalt layer and a ruthenium layer are formed on the surface of the block layer; a copper layer completely fills the recess; a supportive nucleation film layer of the copper layer is formed by superposing the cobalt layer and the ruthenium layer. The present application further discloses a method for making a copper filled recess structure. Since the copper layer in the present application does not contain a copper seed layer and completely consists of the electrochemically-plated copper film, the ability of filling copper in the recess can be improved, and it is especially suitable for use as a copper connection and a via at a process node of less than 14 nm. | 2022-04-28 |