17th week of 2022 patent applcation highlights part 60 |
Patent application number | Title | Published |
20220130871 | HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS - High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers. | 2022-04-28 |
20220130872 | ELECTRONIC DEVICE - An electronic device includes a panel. The panel has a working area, and the working area includes a unit circuit, at least two first repairing lines and at least one second repairing line. The at least two first repairing lines are disposed on the periphery of the unit circuit and extend in the first direction. The at least one second repairing line is disposed on the periphery of the unit circuit and extends in a second direction. The first direction is different from the second direction. | 2022-04-28 |
20220130873 | HIGH-K DIELECTRIC MATERIALS COMPRISING ZIRCONIUM OXIDE UTILIZED IN DISPLAY DEVICES - Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer. | 2022-04-28 |
20220130874 | LOW-LATENCY THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY PANEL - The present invention provides a low-latency thin film transistor, an array substrate, and a display panel. The low-latency thin film transistor includes a gate, an active layer disposed on a side of the gate, and a source and a drain disposed above the gate, and the source and the drain are respectively connected to the active layer, wherein in a direction perpendicular to the active layer, at least part of an orthographic projection of the drain is located outside an orthographic projection of the gate. | 2022-04-28 |
20220130875 | Photodetector - In a photodetector using GePDs, a photodetector having small change in light sensitivity due to temperature is provided. A photodetector includes a plurality of photodiodes formed on a silicon substrate and having germanium or a germanium compound in a light absorption layer, and two chips of integrated circuits arranged parallel to two sides connected to one corner of the silicon substrate, respectively, the two integrated circuits are connected to photodiodes formed on the silicon substrate, two or more of the photodiodes are arranged equidistantly from the integrated circuit that is parallel to one side connected to the one corner, and the numbers of equidistantly arranged photodiodes are equal, when viewed from the integrated circuits. | 2022-04-28 |
20220130876 | PIXEL ARRAY AND AN IMAGE SENSOR INCLUDING THE SAME - A pixel array including: a plurality of pixel groups, each pixel group including: a plurality of unit pixels respectively including photoelectric conversion elements disposed in a semiconductor substrate; trench structures disposed in the semiconductor substrate and extending in a vertical direction from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate to electrically and optically separate the photoelectric conversion elements from each other; and a microlens disposed above or below the semiconductor substrate, the microlens covering all of the photoelectric conversion elements in the plurality of unit pixels to focus an incident light to the photoelectric conversion elements. | 2022-04-28 |
20220130877 | PHOTOELECTRIC CONVERSION APPARATUS AND PHOTOELECTRIC CONVERSION SYSTEM - A photoelectric conversion apparatus includes a plurality of avalanche photodiodes. Each of the plurality of avalanche photodiodes includes an avalanche multiplication unit formed by a first semiconductor region of a first conductivity type that is arranged at a first depth, and a second semiconductor region of a second conductivity type different from the first conductivity type and which is arranged at a second depth deeper than the first depth. A fourth semiconductor region at least one of a conductivity type and an impurity concentration of which is different from those of a third semiconductor region of the second conductivity type is arranged at a position shallower than the third semiconductor region, and a depth of a boundary portion between the third semiconductor region and the fourth semiconductor region is deeper than that of the avalanche multiplication unit. | 2022-04-28 |
20220130878 | DIODE ARRAY, ARRANGEMENT, AND SYSTEM - A diode array with at least two image elements. The diode array includes a distribution transistor as well as a feed line for receiving a reference current and a first supply terminal coupled to the distribution transistor for supplying the distribution transistor. A diode and an input transistor are provided for each image element, each of which is coupled to the diode for supplying the diode. The distribution transistor forms a distribution current mirror with the respective input transistor of at least two image elements. | 2022-04-28 |
20220130879 | IMAGE SENSOR AND IMAGING APPARATUS - The purpose of the present disclosure is to improve the dynamic range of an image sensor including a polarization pixel. | 2022-04-28 |
20220130880 | CAMERA PACKAGE, METHOD FOR MANUFACTURING CAMERA PACKAGE, AND ELECTRONIC DEVICE - The present disclosure relates to a camera package, a method for manufacturing a camera package, and an electronic device with which it is possible to reduce manufacturing cost for lens formation. | 2022-04-28 |
20220130881 | IMAGE SENSOR DEVICE HAVING A FIRST LENS AND A SECOND LENS OVER THE FIRST LENS - An image sensor device is provided. The image sensor device includes a substrate. The image sensor device includes a light-sensing region in the substrate. The image sensor device includes an isolation structure in the substrate. The isolation structure surrounds the light-sensing region. The image sensor device includes a grid layer over the substrate. The grid layer is over the isolation structure. The image sensor device includes a first lens over the light-sensing region and surrounded by the grid layer. The image sensor device includes a color filter layer over and in direct contact with the first lens. The first lens is embedded in the color filter layer. The image sensor device includes a second lens over the color filter layer. | 2022-04-28 |
20220130882 | IMAGE SENSOR, CAMERA ASSEMBLY, AND MOBILE TERMINAL - An image sensor, a camera assembly, and a mobile terminal are provided. The image sensor includes multiple pixels, and each pixel includes an isolation layer, a light guide layer, and a photoelectric conversion element. The light guide layer is formed within the isolation layer, and the refractive index of the light guide layer is greater than the refractive index of the isolation layer. The photoelectric conversion element receives light that passes through the light guide layer. | 2022-04-28 |
20220130883 | CLOSE BUTTED COLLOCATED VARIABLE TECHNOLOGY IMAGING ARRAYS ON A SINGLE ROIC - A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization. | 2022-04-28 |
20220130884 | IMAGE SENSOR - An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures. | 2022-04-28 |
20220130885 | PIXEL-ARRAY SUBSTRATE AND ASSOCIATED METHOD - A pixel-array substrate includes a floating diffusion region and a first photodiode formed in a semiconductor substrate. A top surface of the semiconductor substrate defines a trench | 2022-04-28 |
20220130886 | POINTED-TRENCH PIXEL-ARRAY SUBSTRATE AND ASSOCIATED FABRICATION METHOD - A pointed-trench pixel-array substrate includes a floating diffusion region and a photodiode region formed in a semiconductor substrate. The semiconductor substrate includes, between a top surface and a back surface thereof, a sidewall surface and a bottom surface defining a trench extending into the semiconductor substrate away from a planar region of the top surface surrounding the trench. In a cross-sectional plane perpendicular to the top surface and intersecting the floating diffusion region, the photodiode region, and the trench, (i) the bottom surface is V-shaped and (ii) the trench is located between the floating diffusion region and the photodiode region | 2022-04-28 |
20220130887 | APPARATUS FOR INTEGRATED MICROWAVE PHOTONICS ON A SAPPHIRE PLATFORM, METHOD OF FORMING SAME, AND APPLICATIONS OF SAME - An integrated microwave photonics (IMWP) apparatus is provided using sapphire as a platform. The IMWP apparatus includes: a sapphire substrate having a step-terrace surface; and a III-V stack layer epitaxially grown on the sapphire substrate. The III-V stack layer includes: a first III-V layer disposed on the sapphire substrate; a low temperature (LT) III-V buffer layer disposed on the first III-V layer; multiple second III-V layers disposed and stacked on the LT III-V buffer layer; a third III-V layer disposed on the second III-V layers; a III-V quantum well layer disposed on the third III-V layers; and a fourth III-V layer disposed on the III-V quantum well layer. The second III-V layers are respectively annealed. A growth temperature of the LT III-V layer and a growth temperature of the III-V quantum well layer are lower than a growth temperature of each of the first, second, third and fourth III-V layers. | 2022-04-28 |
20220130888 | Deep Trench Isolations and Methods of Forming the Same - A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench. | 2022-04-28 |
20220130889 | METHOD FOR FORMING CONTACTS APPLIED TO CMOS IMAGE SENSOR - A method for forming contacts applied to a CMOS image sensor includes: forming a transmission gate structure; performing source and drain ion implantation processes to form source and drain; forming auxiliary sidewalls on the outer sides of the gate sidewalls, the material of the auxiliary sidewalls being the same as the material of the adjacent gate sidewalls; sequentially forming a silicide block layer, a contact etch stop layer and an interlayer dielectric layer; defining source and drain contact regions; performing etching processes to remove the interlayer dielectric layer and the contact etch stop layer corresponding to the source and drain contact regions sequentially; etching the silicide block layer by adopting a predetermined etching selection ratio to form source and drain contacts, wherein the etching rate of the silicide block layer is higher than the etching rate of the auxiliary sidewalls in the process of etching the silicide block layer. | 2022-04-28 |
20220130890 | MICRO LIGHT-EMITTING DIODE DISPLAY - A micro light-emitting diode display, including at least one first type semiconductor base layer, a plurality of semiconductor light-emitting mesas, and a conducting layer, is provided. The plurality of semiconductor light-emitting mesas are dispersedly disposed on the at least one first type semiconductor base layer. The at least one first type semiconductor base layer has a surface exposed by the semiconductor light-emitting mesas. The conducting layer is disposed on the surface of the at least one first type semiconductor base layer and is in an interlaced distribution configuration with the semiconductor light-emitting mesas. The ratio of the area of the conducting layer in contact with the surface to the area of the surface is greater than or equal to 0.2. | 2022-04-28 |
20220130891 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a substrate including a display area and a non-display area, and a first surface and a second surface; pixels disposed on the first surface; a signal line disposed on the first surface, and electrically connected to each pixel; a cushion layer disposed on the pixels and the signal line, and including at least one contact hole that exposes a portion of the signal line; a connector disposed in the at least one contact hole and electrically connected to the signal line; and a driver disposed on the cushion layer and electrically connected to the pixels through the connector. Each pixel includes a display element layer disposed on the first surface and including at least one light emitting element, and a pixel circuit layer disposed on the display element layer and including at least one transistor electrically connected to the at least one light emitting element. | 2022-04-28 |
20220130892 | LIGHT EMITTING MODULE AND DRIVING METHOD THEREOF, AND DISPLAYING DEVICE - A light emitting module and a driving method thereof, and a displaying device. The light emitting module includes: a light emitting base plate, wherein the light emitting base plate includes M rows and N columns of light emitting regions, and each of the light emitting regions includes a plurality of light emitting devices that are connected in series; and a driving assembly, wherein the driving assembly includes one or more driving chips, each of the driving chips includes a plurality of first leads and a plurality of second leads, each of the first leads is connected to the first terminal of a corresponding one instance of the light emitting regions, and each of the second leads is connected to the second terminal of a corresponding one instance of the light emitting regions; wherein a total quantity of the second leads in the driving assembly is integer multiples of N. | 2022-04-28 |
20220130893 | Radiation Emitting Semiconductor Chip and Radiation Emitting Semiconductor Device - In an embodiment a radiation emitting semiconductor chip includes a semiconductor layer sequence with a plurality of active regions and a main extension plane, wherein each active region has a main extension direction, wherein each active region is configured to emit electromagnetic radiation from an emitter region extending parallel to the main extension plane, wherein at least two active regions overlap in plan view, wherein the emitter regions are arranged at grid points of a regular grid connected by at least one grid line, and wherein the main extension direction of at least one active region encloses an angle of at least 10° and at most 80° with the grid lines of the regular grid. | 2022-04-28 |
20220130894 | OPTOELECTRONIC SEMICONDUCTOR DEVICE WITH A PLURALITY OF IMAGE ELEMENTS AND SEPARATING ELEMENTS, AND METHOD FOR PRODUCING THE OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device may include a plurality of picture elements, each of which include a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type arranged one above the other to form a semiconductor layer stack. The optoelectronic semiconductor device further includes separating elements arranged between adjacent picture elements and extend in a horizontal direction along a boundary of the adjacent picture element, adjoin the first and the second semiconductor layers, respectively, and extend in the vertical direction through the first and the second semiconductor layers, respectively. | 2022-04-28 |
20220130895 | UNIT OF LIGHT-EMITTING ELEMENTS AND DISPLAY DEVICE INCLUDING THE SAME - A unit of light-emitting elements is provided. The unit includes: a plurality of light-emitting elements having a shape extended in a first direction and arranged and spaced apart from one another in a second direction perpendicular to the first direction; and a binder extending around a periphery of the plurality of light-emitting elements and fixing the plurality of light-emitting elements. Each of the plurality of light-emitting elements includes: a first semiconductor layer; a second semiconductor layer; and an active layer between the first semiconductor layer and the second semiconductor layer. The plurality of light-emitting elements includes a first light-emitting element and a second light-emitting element. A first semiconductor layer of the first light-emitting element, an active layer of the first light-emitting element, and a second semiconductor layer of the first light-emitting element are arranged along the first direction in this order, and a second semiconductor layer of the second light-emitting element, an active layer of the second light-emitting element, and a first semiconductor layer of the second light-emitting element are arranged along the first direction in this order. | 2022-04-28 |
20220130896 | DISPLAY DEVICE AND METHOD OF FABRICATING THE DISPLAY DEVICE - A display device may include a substrate including a plurality of pixel regions, each including a first region and a second region; and a pixel in each of the pixel regions. The pixel may include a display element portion including a plurality of light emitting elements that emit a light of a first color. The display element portion may include a color filter on the first surface of the substrate and corresponding to the second region, a first electrode and a second electrode on the color filter and spaced apart from each other in a first direction, the plurality of light emitting elements, which are between the first electrode and the second electrode, a first contact electrode on the first electrode and a second contact electrode on the second electrode, and a color conversion layer on the first contact electrode and the second contact electrode and including color conversion particles. | 2022-04-28 |
20220130897 | CHIP-ON-BOARD TYPE PHOTOELECTRIC DEVICE - A chip-on-board type photoelectric device exemplarily includes: a package substrate, provided with a chip mounting region, a first electrode and a second electrode, the first and second electrodes being arranged spaced from each other at a periphery of the chip mounting region; first photoelectric chips, arranged in the chip mounting region to form inwardly concave strip-shaped patterns as mutually spaced first color temperature regions, and electrically connected between the first and second electrodes to form at least one first photoelectric chip string; and second photoelectric chips, arranged in the chip mounting region to form second color temperature regions. A light-emitting color temperature of each the second color temperature region is higher than that of each the first color temperature region. The second photoelectric chips are electrically connected between the first and second electrodes to form second photoelectric chip strings. A good uniformity of light mixing can be achieved. | 2022-04-28 |
20220130898 | LIGHT EMITTING DEVICE HAVING COMMONLY CONNECTED LED SUB-UNITS - A light emitting diode (LED) stack for a display including a first LED stack including a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, an intermediate bonding layer disposed between the first LED stack and the second LED stack to bond the second LED stack to the first LED stack, an upper bonding layer disposed between the second LED stack and the third LED stack to couple the third LED stack to the second LED stack, and a first hydrophilic material layer disposed between the first LED stack and the upper bonding layer. | 2022-04-28 |
20220130899 | INTEGRATED MEMS-CMOS ULTRASONIC SENSOR - Ultrasonic sensing approaches are described with integrated MEMS-CMOS implementations. Embodiments include ultrasonic sensor arrays for which PMUT structures of individual detector elements are at least partially integrated into the CMOS ASIC wafer. MEMS heating elements are integrated with the PMUT structures by integrating under the PMUT structures in the CMOS wafer and/or over the PMUT structures (e.g., in the protective layer). For example, embodiments can avoid wafer bonding and can reduce other post processing involved with conventional manufacturing of PMUT ultrasonic sensors, while also improving thermal response. | 2022-04-28 |
20220130900 | ARITHMETIC OPERATION CIRCUIT AND NEUROMORPHIC DEVICE - An arithmetic operation circuit including: a variable resistance element that includes three terminals that are a first terminal, a second terminal, and a third terminal and is configured to be able to change a resistance value; a first electrode connected to the first terminal; a second electrode; a third electrode; a first switching element connected between the second electrode and the second terminal; a second switching element connected between the third electrode and the third terminal; and a capacitor connected between a transmission line connecting the second terminal and the first switching element and the ground. | 2022-04-28 |
20220130901 | MAGNETIC TUNNEL JUNCTION ELEMENT AND MAGNETORESISTIVE MEMORY DEVICE - Provided is a magnetic tunnel junction element and a magnetoresistive memory device. The magnetic tunnel junction element includes a fixed layer maintaining a magnetization direction, an insulating layer, a free layer having a variable magnetization direction, and an antiferromagnetic oxide layer. The fixed layer, the free layer, and the antiferromagnetic oxide layer may be sequentially stacked. The free layer and the antiferromagnetic oxide layer may be in direct contact with each other. | 2022-04-28 |
20220130902 | CROSSBAR ARRAY CIRCUITS WITH 2T1R RRAM CELLS FOR LOW VOLTAGE OPERATIONS - Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal. | 2022-04-28 |
20220130903 | RRAM STRUCTURE WITH ONLY PART OF VARIABLE RESISTIVE LAYER COVERING BOTTOM ELECTRODE AND METHOD OF FABRICATING THE SAME - An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface. | 2022-04-28 |
20220130904 | BURIED TRACK - The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material. | 2022-04-28 |
20220130905 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH TRANSISTORS - A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions. | 2022-04-28 |
20220130906 | Display Substrate and Preparation Method Thereof, and Display Apparatus - A display substrate, a preparation method thereof and a display apparatus. The display substrate comprises a substrate, multiple pixel units arranged on the substrate and a color filter layer arranged on the pixel unit, wherein the color filter layer comprises color optical filters of different colors and a touch control structure layer arranged between the color optical filters of different colors; the touch control structure layer comprises a touch control connection electrode, a first coating protective layer covering the touch control connection electrode and a touch control electrode arranged on the first coating protective layer, the touch control electrodes comprise a first touch control electrode and a second touch control electrode, and at least one of the first touch control electrode and the second touch control electrode is connected with the touch control connection electrode through a via hole penetrating through the first coating protective layer. | 2022-04-28 |
20220130907 | DISPLAY DEVICE - A display device includes a first substrate, a pixel structure, a first optical filter, a first-color filter, a second optical filter, a second-color filter, and a second substrate. The pixel structure is disposed between the first substrate and each of the optical filters. The first-color filter is disposed on the first optical filter and has a first refractive index. The second optical filter is spaced from the first optical filter and includes a second-color pigment. The second-color filter is disposed on the second optical filter and has a second refractive index. The second substrate is disposed on the first color filter and the second color filter and has a third refractive index. A difference between the third refractive index and the second refractive index is less than a difference between the third refractive index and the first refractive index. | 2022-04-28 |
20220130908 | DISPLAY DEVICE - A display device includes a display unit. The display unit includes a light emitting unit and a light converting layer disposed on the light emitting unit. The display unit emits a green output light under an operation of a highest gray level. The green output light has an output spectrum, wherein an intensity integral of the output spectrum from 380 nm to 489 nm is defined as a first intensity integral, an intensity integral of the output spectrum from 490 nm to 780 nm is defined as a second intensity integral, a ratio of the first intensity integral over the second intensity integral is defined as a first ratio, and the first ratio is greater than 0% and less than or equal to 7.5%. | 2022-04-28 |
20220130909 | Organic Light Emitting Diode Device, Method for Manufacturing the Same and Display Device - A method for manufacturing the display substrate is provided, including providing a substrate, providing a green light emitting element on the substrate forming a green color resist film layer on a light exit side of the green light emitting element; forming a pattern including a green color film layer by adjusting a irradiation time of the exposure light irradiated to the green color resist film layer using a digital gray scale adjustment method. | 2022-04-28 |
20220130910 | TOUCH PANEL INTEGRATING BENDING SENSOR FOR FOLDABLE OLED DISPLAY - A flexible touch panel apparatus includes a series of first electrodes extending along a first direction, at least one second electrode extending along a second direction and defining a bending axis of the flexible touch panel. An elastomeric layer is located between the series of first electrodes at least second electrode. A series of third electrodes are extending along the second direction parallel to the bending axis, and an insulator layer is located between at least one second electrode and the series of third electrodes. At least one second electrode is capacitively coupled to at least one of the series of first electrodes for bend sensing in the flexible touch panel along the bending axis, and the third electrodes are capacitively coupled to the first electrodes for touch sensing on the flexible touch panel. | 2022-04-28 |
20220130911 | DISPLAY DEVICE - A display device includes a stretchable substrate that includes a plurality of unit regions. Each of the plurality of unit regions includes a plurality of island regions and at least one bridge region that connects adjacent island regions to each other. A display panel is on the stretchable substrate. The display panel includes a plurality of display parts and at least one wiring part. The plurality of display parts correspondingly overlap the plurality of island regions. The at least one wiring part correspondingly overlaps the at least one bridge region. An input sensor is on the display panel. The input sensor includes a plurality of sensing electrodes and at least one subsidiary electrode. The plurality of sensing electrodes correspondingly overlaps the plurality of unit regions. When viewed in a plan view the at least one subsidiary electrode is correspondingly disposed between adjacent sensing electrodes. | 2022-04-28 |
20220130912 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A bendable display device includes a display panel, a display circuit board having a first end thereof electrically connected to the display panel, a touch circuit board having a first end thereof electrically connected to the display panel, a support layer disposed on a surface of the display panel, and first and second heat dissipation layers. Each of the first heat dissipation layer and the second heat dissipation layer is disposed on a side of the support layer away from the display panel, and the first dissipation layer and the second dissipation layer are disposed on two sides of a bending area of the bendable display device. A second end of the display circuit board and a second end of the touch circuit board are respectively disposed on the first heat dissipation layer and the second heat dissipation layer. A connecting member for electrically connecting the first heat dissipation layer and the second heat dissipation layer is provided between the first heat dissipation layer and the second heat dissipation layer. | 2022-04-28 |
20220130913 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. The display panel includes: a base substrate; a plurality of pixel units arranged on the base substrate in an array, wherein each pixel unit comprises a pixel driving circuit and a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element; a plurality of signal lines, electrically connected to the pixel driving circuit, respectively; and a light shielding portion on the base substrate. orthographic projections of at least two of the signal lines on the base substrate are spaced apart by a gap, at least one of interference and diffraction is generated due to a plurality of gaps in response to that at least a part of light passes through the gaps, and an orthographic projection of the light shielding portion on the base substrate covers at least orthographic projections of the gaps on the base substrate. | 2022-04-28 |
20220130914 | DISPLAY DEVICE AND ELECTRONIC DEVICE - A display device ( | 2022-04-28 |
20220130915 | DISPLAY DEVICE - A display device according to an exemplary embodiment includes: a substrate including a display area and a transmission area; a metal blocking layer disposed in the display area of the substrate; an inorganic insulating layer disposed on the metal blocking film; a transistor disposed on the inorganic insulating layer; an emission layer connected to the transistor; and a light blocking layer and a color filter disposed on the emission layer of the display area, wherein the edge of the light blocking layer is protruded toward the transmission area more than the edge of the metal blocking layer. | 2022-04-28 |
20220130916 | OLED DISPLAY PANEL AND DISPLAY DEVICE - An organic light-emitting diode (OLED) display panel and a display device are provided. The OLED display panel includes first pixel units and second pixel units that are arranged symmetrically-mirrored to each other. A longitudinal direction of pixel electrode of each pixel unit is parallel to a longitudinal direction of the OLED display panel. Blue sub-pixels of each pixel unit are individually arranged in a row, and red sub-pixels and green sub-pixels are arranged together in another row, so as to alleviate technical problems where a pixel arrangement of traditional hybrid arrangement OLED panels restricts printing method. | 2022-04-28 |
20220130917 | DISPLAY PANEL - A display panel is provided and includes at least one cutting section and a functional section. A cross-sectional structure of the display panel includes a substrate, a blocking portion, and an encapsulating layer. The substrate includes a first sub-portion corresponding to a position of the cutting section. The blocking portion is disposed on the first sub-portion. The encapsulating layer is disposed on the blocking portion. A contact surface between the encapsulating layer and the blocking portion is a rugged surface. | 2022-04-28 |
20220130918 | DISPLAY DEVICE AND DRIVING METHOD OF DISPLAY DEVICE - A display device that can switch between normal display and see-through display is provided. Visibility in see-through display is improved. A liquid crystal element overlaps with a light-emitting element. The light-emitting element, a transistor, and the like overlapping with the liquid crystal element transmit visible light. When the liquid crystal element blocks external light, an image is displayed with the light-emitting element. When the liquid crystal element transmits external light, an image displayed with the light-emitting element is superimposed on a transmission image through the liquid crystal element. | 2022-04-28 |
20220130919 | DISPLAY PANEL, MANUFACTURING METHOD, DRIVING METHOD AND DISPLAY DEVICE - The present disclosure discloses a display panel, a manufacturing method, a driving method and a display device. When the display panel needs to display a normal image, a pixel driving circuit and a first control circuit drive an organic light emitting diode to emit light. When the display panel needs to perform fingerprint detection of a finger, the pixel driving circuit and a second control circuit drive a micro light emitting diode to emit light, so that the light emitted by the micro light emitting diode can be received by a photoelectric converter after being reflected by the finger, the photoelectric converter can output a detection signal, and furthermore, fingerprint information of the finger can be determined according to the detection signal. | 2022-04-28 |
20220130920 | Display panel - The present disclosure provides a display panel, the display panel includes a flexible substrate with a curve region, the curve region has a Gauss curvature K1, the Gauss curvature K1 is not equal to zero, a plurality of thin film transistors disposed on the flexible substrate, and a plurality of light emitting units disposed on the flexible substrate and driven by the thin film transistors, the flexible substrate at least has an opening in the curve region. | 2022-04-28 |
20220130921 | DISPLAY DEVICE - A display device according to an embodiment includes: a substrate including a display area, a dummy area, and a peripheral area; a passivation layer positioned in the display area, the dummy region, and the peripheral area of the substrate; a first adhesive auxiliary layer positioned on the passivation layer and positioned in the dummy region; a dummy pixel defining layer positioned on the first adhesive auxiliary layer and including a hydrophobic material; a second adhesive auxiliary layer positioned on the passivation layer, positioned in the peripheral area, and including a lateral side contacting the dummy pixel defining layer; a common voltage transmitter positioned in the peripheral area; and a common electrode connected to the common voltage transmitter, and positioned on the second adhesive auxiliary layer and the dummy pixel defining layer. | 2022-04-28 |
20220130922 | PIXEL AND DISPLAY DEVICE INCLUDING THE SAME - An embodiment provides a pixel including: a first bank pattern on a substrate; a first electrode and a second electrode on the first bank pattern and extending in a first direction; an insulating layer on the first electrode and the second electrode; a plurality of light emitting elements on the insulating layer between the first electrode and the second electrode; a first contact electrode electrically connecting the first electrode and the light emitting elements; and a second contact electrode electrically connecting the second electrode and the light emitting elements. The first electrode and the second electrode may be spaced from each other in a second direction different from the first direction on the first bank pattern. | 2022-04-28 |
20220130923 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - A display panel is provided. A pixel defining layer of the display panel includes a first defining layer and a second defining layer, wherein the first defining layer includes a first base body and first magnets dispersed in the first base body, and the second defining layer includes a second base body and second magnets dispersed in the second base body; both the first base body and the second base body are hydrophobic and elastic; and a side face of the first base body perpendicular to a bearing surface of the substrate and a side face of the second base body perpendicular to the bearing surface of the substrate being in contact with each other. | 2022-04-28 |
20220130924 | APPARATUS, DISPLAY APPARATUS, PHOTOELECTRIC CONVERSION APPARATUS, ELECTRONIC EQUIPMENT, ILLUMINATION APPARATUS, AND MOVING OBJECT - An apparatus including sub-pixels arranged on a substrate, the sub-pixels including a first, a second, and a third sub-pixels, each of the sub-pixels including a lower electrode, an insulating layer covering an end portion of the lower electrode, an organic layer, and an upper electrode in mentioned order starting from a side closer to the substrate, at least part of the organic layer being continuously arranged in at least two of regions between a position on a first lower electrode included in the first sub-pixel and a position on a second lower electrode included in the second sub-pixel, between the position on the second lower electrode and a position on a third lower electrode included in the third sub-pixel, and between the position on the third lower electrode and the position on the first lower electrode. | 2022-04-28 |
20220130925 | ELECTRONIC DEVICE, DISPLAY APPARATUS, PHOTOELECTRIC CONVERSION APPARATUS, ELECTRONIC EQUIPMENT, ILLUMINATION APPARATUS, AND MOVING OBJECT - An electronic device including elements arranged on a substrate, each of the elements including an insulating layer, a first electrode, a functional layer, and a second electrode in mentioned order starting from a side closer to the substrate. The insulating layer has an inclined portion that is inclined relative to the substrate. The first electrode has a first portion positioned on the inclined portion and a second portion in contact with the functional layer. The second portion has a smaller inclination angle relative to the substrate than the first portion. A thickness of the functional layer positioned on the first portion in a direction normal to a functional layer surface in contact with the first portion is smaller than a thickness of the functional layer positioned on the second portion in a direction normal to a functional layer surface in contact with the second portion. | 2022-04-28 |
20220130926 | DISPLAY PANEL AND METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE - Provided is a display panel, including: a backplane; a first electrode and an auxiliary layer, disposed on a same side of the backplane, wherein a distance between a surface of the first electrode distal from the backplane and the backplane is shorter than or equal to a distance between a surface of the auxiliary layer distal from the backplane and the backplane; a pixel defining layer, at least partially disposed on a side of the auxiliary layer distal from the backplane; a second electrode, disposed on a side of the pixel defining layer distal from the backplane; and an auxiliary electrode, disposed on a side of the second electrode distal from the backplane, wherein an orthographic projection of the auxiliary electrode onto the backplane is located within an orthographic projection of the pixel defining layer onto the backplane. | 2022-04-28 |
20220130927 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME, AND ELECTRONIC DEVICE - Provided is a method for manufacturing a display panel. First, the method includes sequentially preparing an anode layer and a first pixel define layer on a side of a substrate layer, then coating an organic light-induced material on a first surface, distal from the anode layer, of the first pixel define layer, and forming a polymer film layer by reacting the first pixel define layer with the organic light-induced material under a predetermined condition, and then preparing an organic functional layer and a cathode layer on a surface, distal from the first pixel define layer, of the organic light-induced material. The organic light-induced material at least contains a hydroxyl group and an unsaturated carbon-carbon double bond. | 2022-04-28 |
20220130928 | DISPLAY DEVICE - A display device includes: a substrate; a bank having a first main opening and sub-openings extending from the first main opening; a first electrode and a second electrode on the first substrate and being spaced apart from each other in a first direction and extending in a second direction; a plurality of light-emitting elements on the first electrode and the second electrode and being spaced apart from each other in the second direction; a first connection electrode on the first electrode and contacting first ends of the light-emitting elements; and a second connection electrode on the second electrode and contacting second ends of the light-emitting elements. The first connection electrode is connected to the first electrode through a first contact, and the second connection electrode is connected to the second electrode through a second contact on the second electrode. The first contact and the second contact overlap the sub-openings. | 2022-04-28 |
20220130929 | DISPLAY DEVICE - A separation wall is provided in a frame shape along a circumferential edge of a through-hole in a non-display region, in which the through-hole is formed, defined in an island shape inside a display region. The separation wall includes a wall base portion provided in a frame shape by a part of a second interlayer insulating film and a resin layer provided in an eave shape on the wall base portion to extend to a through-hole side and a display region side. Opening portions opening upward are provided on peripheries of the wall base portion on the through-hole side and the display region side in the second interlayer insulating film. | 2022-04-28 |
20220130930 | DISPLAY DEVICE - A display device including a display area, a peripheral area adjacent to the display area, light-emitting diodes disposed in the display area, transistors electrically connected to the light-emitting diodes, and a pad section including a pad electrode having a multi-layered structure, the pad electrode being disposed in the peripheral area. The pad electrode includes a main metal layer, a first conductive layer on an upper surface of the main metal layer, the first conductive layer including a conductive oxide, and an auxiliary layer on a lower surface of the main metal layer. | 2022-04-28 |
20220130931 | DISPLAY DEVICE - A display device according to an embodiment includes: a first conductive layer that is disposed on a substrate; a transistor that is disposed on the substrate; and a light emitting element that is electrically connected to the transistor, wherein the transistor includes a semiconductor layer that at least partially overlaps the first conductive layer and is disposed on the first conductive layer, and a gate electrode that is disposed on the semiconductor layer. The semiconductor layer includes a first region that does not overlap the first conductive layer, a third region that overlaps the first conductive layer, and a second region that is disposed between the first region and the third region and traverses an edge of the first conductive layer. The first width of the semiconductor layer in the first region is smaller than a second width of the semiconductor layer in the second region. | 2022-04-28 |
20220130932 | THIN FILM TRANSISTOR SUBSTRATE, DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes: a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, disposed on the inclined surface, and including a first conductive region and a second conductive region in which impurities are doped, and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. The inclined surface extends in a first direction in a plan view. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction that crosses the first direction. | 2022-04-28 |
20220130933 | DISPLAY PANEL AND DISPLAY DEVICE - The embodiments of the disclosure disclose a display panel and a display device. The display panel includes a base substrate including a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit, wherein the pixel circuit includes a storage capacitor; a first conductive layer located on a side, lacing away from the base substrate, of a first insulating layer, the first conductive layer including a plurality of scanning wires; a second insulating layer located on a side, facing away from the base substrate, of the first conductive layer; a second conductive layer located on a side, facing away from the base substrate, of the second insulating layer; a fourth insulating layer located on a side, facing away from the base substrate, of the second conductive layer; and a third conductive layer located on a side, facing away from the base substrate, of the fourth insulating layer, the third conductive layer including a plurality of data wires arranged at intervals; where the storage capacitor includes three stacked electrode plates, and the three stacked electrode plates are respectively arranged on the same layer together with the first conductive layer, the second conductive layer and the third conductive layer. | 2022-04-28 |
20220130934 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a display device and a method of manufacturing the display device. The display device includes a substrate including a display area and a peripheral area outside the display area, a plurality of data lines disposed in the display area, a plurality of lines disposed in the display area, respectively connected to the plurality of data lines, and configured to respectively transmit a data signal from a driving circuit disposed in the peripheral area to the plurality of data lines, an insulating layer covering the plurality of lines; and a light-emitting element disposed on the insulating layer, wherein each of the plurality of lines comprises a plurality of branches branched in a direction crossing an extending direction of the line, and a black layer is disposed on an insulating layer at a position corresponding to an interval between a plurality of adjacent branches in a vertical direction. | 2022-04-28 |
20220130935 | DISPLAY DEVICE - Discussed is a display device including a display panel that includes a substrate, a light shield layer disposed on the substrate, a light emitting element layer disposed on the light shield layer and including a plurality of subpixels, an encapsulation layer disposed on the light emitting element layer, and a polarizing layer disposed on the encapsulation layer, and a sensor disposed under the display panel. A display area of the display panel includes a main display area and a sensor area. The sensor is arranged to photoelectrically convert light received through the sensor area of the display panel, and the sensor area includes a radial pattern. | 2022-04-28 |
20220130936 | ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL, METHOD OF MANUFACTURING SAME, AND DISPLAY DEVICE - An organic light-emitting diode display panel, a method of manufacturing the same, and a display device are provided. The organic light-emitting diode display panel includes a flexible substrate defined with a test circuit region thereon. The test circuit region is provided with a test circuit and defined with a circuit trace region. The circuit trace region includes a plurality of traces, a plurality of transistors, a control line, and at least one pin. Each one of the traces is connected to one of the transistors. The control line is electrically connected to a control end of each of the transistors to turn on or turn off the transistors to avoid the circuit from short-circuiting. | 2022-04-28 |
20220130937 | DISPLAY PANEL AND PREPARATION METHOD THEREOF AND DISPLAY APPARATUS - Disclosed in embodiments of the present disclosure are a display panel, a preparation method thereof and a display apparatus. The display panel includes: a first blocking dam located in the blocking area and surrounding the hole area, a second blocking dam located on one side of the first blocking dam close to the hole area and surrounding the hole area, a heightening layer located between the first blocking dam and the second blocking dam, a crack detect wire located on one side of the second blocking dam close to the hole area, at least two connection leading wires leading the crack detect wire out to the display area through the blocking area; in a direction perpendicular to a plane where the display panel is located, an orthographic projection of an area between the connection leading wires has an overlap area with an orthographic projection of the heightening layer. | 2022-04-28 |
20220130938 | DISPLAY DEVICE - A display device may include a first scan connection line connecting a first scan line connected to a first pixel and a first scan output transistor, a first sensing connection line connecting a first sensing line connected to the first pixel and a first sensing output transistor, the first sensing connection line crossing and overlapping the first scan connection line, a second sensing connection line connecting a second sensing line connected to a second pixel adjacent to the first pixel in a first direction and a second sensing output transistor, and a second scan connection line connecting a second scan line connected to the second pixel and a second scan output transistor, the second scan connection line crossing and overlapping the second sensing connection line. | 2022-04-28 |
20220130939 | DISPLAY DEVICE - A display device includes: a substrate including a display area and a peripheral area positioned outside the display area; a first power supply line positioned in the peripheral area; a first insulating layer positioned on the first power supply line; and a second power supply line positioned on the first insulating layer in the peripheral area. The first power supply line includes a first main wire extending in a first direction and a first sub-wire diverging toward the display area from the first main wire, the second power supply line includes a second main wire extending in the first direction and a second sub-wire diverging toward the display area from the second main wire, the first main wire includes an internal edge positioned near the first sub-wire and an external edge facing the internal edge, and the second main wire does not overlap the internal edge in a plan view. | 2022-04-28 |
20220130940 | LIGHT EMITTING DISPLAY PANEL AND LIGHT EMITTING DISPLAY APPARATUS USING THE SAME - Disclosed is a light emitting display panel in which a portion overlapped with data lines is patterned in a cathode electrode, and a light emitting display apparatus using the same. The light emitting display panel comprises a substrate, a first signal line along a first direction of the substrate, a first insulating film covering the first signal line, a second insulating film covering the first insulating film, an anode electrode patterned by each pixel, a bank cocvering ends of the anode electrode, a first light emitting layer on the anode electrode disposed at a first side of the bank, a second light emitting layer on the anode electrode disposed at a second side of the bank, a first cathode electrode on the first light emitting layer, and a second cathode electrode on the second light emitting layer, wherein the first and second cathode electrodes are separated from each other on the upper surface of the bank. | 2022-04-28 |
20220130941 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device includes a substrate, a light emitting layer, a first power supply wire, a second power supply wire, a connection pattern, and an upper electrode. The substrate has a display region, a peripheral region surrounding the display region and including first, second, and third peripheral regions, and a pad region disposed on one side of the peripheral region. The light emitting layer is disposed in the display region on the substrate. The first power supply wire is disposed in the second and third peripheral regions and a part of the first peripheral region on the substrate. The second power supply wire is disposed in the display region, the first peripheral region, and the third peripheral region on the substrate without being disposed in the second peripheral region, and is located inward of the first power supply wire. | 2022-04-28 |
20220130942 | METHOD OF COMPENSATING FOR DEGRADATION OF DISPLAY DEVICE - A method of compensating for degradation of a display device includes sensing a first sensing current flowing through a sensing line connected to a pixel, which includes a programming period for writing a data voltage of a predetermined color to a storage capacitor of the pixel, sensing a sensing voltage of the sensing line, which includes a period for charging a line capacitor connected to the sensing line, estimating a voltage of an anode electrode of an organic light emitting diode using a second sensing current estimated from the first sensing current and the sensing voltage, and determining a degradation compensation value using the voltage of the anode electrode. | 2022-04-28 |
20220130943 | DISPLAY SUBSTRATE AND DISPLAY APPARATUS - A display substrate includes a base substrate, a first light-shielding layer, a plurality of first sub-pixels and a first power line. The first light-shielding layer is disposed on a side of the base substrate, the first light-shielding layer is located at least in a first display area, and has a plurality of openings arranged in an array. The first sub-pixels are disposed at a side of the first light-shielding layer away from the base substrate and are located in the first display area, and orthogonal projections of the first sub-pixels on the base substrate are non-overlapping with orthogonal projections of the openings on the base substrate. The first power line includes a first power bus and a plurality of first power sub-lines, and the first light-shielding layer is electrically connected to the first power line. | 2022-04-28 |
20220130944 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND ELECTRONIC DEVICE INCLUDING THE SAME - A thin film transistor array substrate comprises a panel including the thin film transistor array substrate, and an electronic device including the panel that includes a conductive auxiliary layer disposed on the substrate, a gate electrode and first and second electrodes that are disposed on the conductive auxiliary layer and spaced apart from one another, a gate insulating film disposed on the gate electrode, and an active layer disposed on or over the gate insulating film and the first and second electrodes, and including a first region, a second region spaced apart from the first region, a first auxiliary region surrounding the first region, and a second auxiliary region surrounding the second region, where an electrical resistance of each of the first auxiliary region and the second auxiliary region is lower than that of the channel region and higher than that of each of the first and second regions. | 2022-04-28 |
20220130945 | Display Panel and Display Apparatus Using the Same - A display panel in which a bridge portion is included in any one of two signal lines at its intersection area, and a display apparatus using the same. The display panel comprises a substrate, a first signal line along a first direction, a first insulating film covering the first signal line, a second signal line along a second direction different from the first direction, a second insulating film covering the first insulating film, and a first pixel electrode on the second insulating film, wherein the second signal line includes an extension line, a connection line, an overlapping line, and a bridge portion connected to the extension line, the connection line, and the overlapping line through contact holes disposed on the second insulating film. | 2022-04-28 |
20220130946 | OLED Display Design for Local Transparency - New and/or improved techniques and arrangements are provided to increase the overall transparency of a local region within the display itself based on arrangements of backplane and/or frontplane architectures. | 2022-04-28 |
20220130947 | CAPACITOR AND METHOD FOR FABRICATING THE SAME - Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same, wherein the capacitor may include a first conductive layer, a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer. | 2022-04-28 |
20220130948 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type. | 2022-04-28 |
20220130949 | TRENCH PATTERN FOR TRENCH CAPACITOR YIELD IMPROVEMENT - Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements. | 2022-04-28 |
20220130950 | SEMICONDUCTOR DEVICES INCLUDING SUPPORT PATTERN AND METHODS OF FABRICATING THE SAME - Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole. | 2022-04-28 |
20220130951 | POWER SEMICONDUCTOR DEVICE - An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n− type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films and. | 2022-04-28 |
20220130952 | SEMICONDUCTOR DEVICE - An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view. | 2022-04-28 |
20220130953 | SYSTEMS AND METHODS FOR JUNCTION TERMINATION OF WIDE BAND GAP SUPER-JUNCTION POWER DEVICES - A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device. | 2022-04-28 |
20220130954 | MICROELECTRONIC DEVICES INCLUDING ISOLATION STRUCTURES NEIGHBORING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS - A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described. | 2022-04-28 |
20220130955 | SEMICONDUCTOR DEVICE STRUCTURE - Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature. | 2022-04-28 |
20220130956 | SILICON ON INSULATOR (SOI) DEVICE AND FORMING METHOD THEREOF - A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device. | 2022-04-28 |
20220130957 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second active patterns, a field insulating film between the first and second active patterns, a first gate structure intersecting the first active pattern and including a first gate electrode and a first gate spacer, a second gate structure intersecting the second active pattern and including a second gate electrode and a second gate spacer, a gate separation structure on the field insulating film between the first and second gate structures, the gate separation structure including a gate separation filling film on a gate separation liner, and a connecting spacer between the gate separation structure and the field insulating film, the connecting spacer protruding from a top surface of the field insulating film, and the gate separation liner contacting the connecting spacer and extending along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film. | 2022-04-28 |
20220130958 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE - The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a. third section between the first section and the second section. | 2022-04-28 |
20220130959 | System And Technique For Creating Implanted Regions Using Multiple Tilt Angles - A system and method for creating various dopant concentration profiles using a single implant energy is disclosed. A plurality of implants are performed at the same implant energy but different tilt angles to implant ions at a variety of depths. The result of these implants may be a rectangular profile or a gradient profile. The resulting dopant concentration profile depends on the selection of tilt angles, doses and the number of implants. Varying tilt angle rather than varying implant energy to achieve implants of different depths may significantly improve efficiency and throughput, as the tilt angle can be changed faster than the implant energy can be changed. Additionally, this method may be performed by a number of different semiconductor processing apparatus. | 2022-04-28 |
20220130960 | HETEROJUCTION BIPOLAR TRANSISTOR - A heterojunction bipolar transistor, comprising: a substrate, having a first surface and an opposite second surface; a sub-emitter layer arranged on the first surface; a compound emitter layer arranged on the sub-emitter layer, making the sub-emitter layer and the compound emitter layer forms an emitter layer; a base layer arranged on the compound emitter layer; a collector ledge layer arranged on the base layer; a collector layer arranged on the collector ledge layer; a lateral oxidation region arranged on the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region, so that the inner region of the compound emitter layer forms a current aperture. | 2022-04-28 |
20220130961 | Epitaxial Source/Drain Structure and Method - A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature. | 2022-04-28 |
20220130962 | NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN REGION AND METHOD TO FABRICATE SAME - Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins. | 2022-04-28 |
20220130963 | Methods of Gate Contact Formation for Vertical Transistors - Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate. | 2022-04-28 |
20220130964 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A structure of a semiconductor device, including a substrate, is provided. A first gate insulating layer is disposed on the substrate. A second gate insulating layer is disposed on the substrate. The second gate insulating layer is thicker than the first gate insulating layer and abuts the first gate insulating layer. A gate layer has a first part gate on the first gate insulating layer and a second part gate on the second gate insulating layer. A dielectric layer has a top dielectric layer and a bottom dielectric layer. The top dielectric layer is in contact with the gate layer, and the bottom dielectric layer is in contact with the substrate. A field plate layer is disposed on the dielectric layer and includes a depleted region, and is at least disposed on the bottom dielectric layer. A method for fabricating the semiconductor device is provided too. | 2022-04-28 |
20220130965 | FIELD EFFECT TRANSISTOR WITH SOURCE-CONNECTED FIELD PLATE - A transistor device includes a semiconductor layer, source and drain contacts on the semiconductor layer, a gate contact on the semiconductor layer between the source and drain contacts, and a field plate over the semiconductor layer between the gate contact and the drain contact. The transistor device includes a first electrical connection between the field plate and the source contact that is outside an active region of the transistor device, and a second electrical connection between the field plate and the source contact. | 2022-04-28 |
20220130966 | FIELD EFFECT TRANSISTOR WITH AT LEAST PARTIALLY RECESSED FIELD PLATE - A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer. | 2022-04-28 |
20220130967 | LDMOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An LDMOS transistor can include: a field oxide layer structure adjacent to a drain region; and at least one drain oxide layer structure adjacent to the field oxide layer structure along a lateral direction, where a thickness of the drain oxide layer structure is less than a thickness of the field oxide layer, and at least one of a length of the field oxide layer structure and a length of the drain oxide layer structure is adjusted to improve a breakdown voltage performance of the LDMOS transistor. | 2022-04-28 |
20220130968 | INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING SAME - An integrated circuit includes a set of power rails, a set of active regions, a first set of conductive lines and a first and a second set of vias. The set of power rails is configured to supply a first or second supply voltage, and is on a first level of a back-side of a substrate. The set of active regions is a second level of a front-side of the substrate. The first set of conductive lines extend in a second direction and overlap the set of active regions. The first set of vias is between and electrically couples the set of active regions and the first set of conductive lines together. The second set of vias is between and electrically couples the first set of conductive lines and the set of power rails together. | 2022-04-28 |
20220130969 | POWER DEVICE WITH A CONTACT HOLE ON A SLOPED ILD REGION - A power semiconductor device includes a semiconductor layer having a first conductivity type. An active region has a plurality of gate trenches. An interlayer dielectric (ILD) has a sloped region and a planar region. A metal contact hole has a sidewall aligned to the sloped region of the ILD. A metal contact is provided in the metal contact hole and couples the active region. | 2022-04-28 |
20220130970 | SEMICONDUCTOR DEVICE - A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film. | 2022-04-28 |