17th week of 2022 patent applcation highlights part 61 |
Patent application number | Title | Published |
20220130971 | SEMICONDUCTOR DEVICE HAVING EMBEDDED CONDUCTIVE LINE AND METHOD OF FABRICATING THEREOF - Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure. | 2022-04-28 |
20220130972 | SEMICONDUCTOR DEVICE INCLUDING A GATE STRUCTURE - A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin. | 2022-04-28 |
20220130973 | Structures of Gate Contact Formation for Vertical Transistors - Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate. | 2022-04-28 |
20220130974 | Contact and Method for Making the Same - The present application discloses a contact, which comprises a contact opening, and a Ti layer, a glue layer and a tungsten layer which completely fill the contact opening; the Ti layer is subjected to annealing treatment; the tungsten layer comprises a tungsten seed layer and a tungsten body layer; the glue layer consists of a TiN layer which is divided into a plurality of TiN sub-layers, all or part of the TiN sub-layers are subjected to the annealing treatment, and the size of grains of the TiN sub-layer subjected to the annealing treatment is limited by the thickness of the corresponding TiN sub-layer. The present application further discloses a method for making a contact. The present application can prevent the annealing treatment of the TiSi layer from producing large lattice grains in the glue layer, thus can make the tungsten seed layer be a continuous structure. | 2022-04-28 |
20220130975 | INTEGRATED CHIP AND METHOD OF FORMING THEREOF - An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type. | 2022-04-28 |
20220130976 | Negative Capacitance Transistor With External Ferroelectric Structure - A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer. | 2022-04-28 |
20220130977 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers. | 2022-04-28 |
20220130978 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF - A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate. | 2022-04-28 |
20220130979 | Semiconductor Device and Method for Manufacture - A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals. | 2022-04-28 |
20220130980 | VERTICAL TRANSISTOR INCLUDING SYMMETRICAL SOURCE/DRAIN EXTENSION JUNCTIONS - A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness. | 2022-04-28 |
20220130981 | LDMOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - A LDMOS transistor and manufacturing method includes: forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, and at least exposes part of the source region; forming a first conductive channel by using a sidewall as a mask, the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer. | 2022-04-28 |
20220130982 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain. | 2022-04-28 |
20220130983 | BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME - A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view. | 2022-04-28 |
20220130984 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, a source, a drain, and a gate stack. The source, the drain, and the gate stack are disposed on the barrier layer. The gate stack includes a first epitaxial layer on the barrier layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The semiconductor device further includes a gate disposed on the gate stack. | 2022-04-28 |
20220130985 | FIELD EFFECT TRANSISTOR WITH ENHANCED RELIABILITY - A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance Γ | 2022-04-28 |
20220130986 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Al | 2022-04-28 |
20220130987 | High Voltage Blocking III-V Semiconductor Device - A semiconductor device includes type IV semiconductor base substrate, first and second device areas that are electrically isolated from one another, a first region of type III-V semiconductor material formed over the first device area, a second region of type III-V semiconductor material formed over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material, a first high-electron mobility transistor integrally formed in the first region, and a second high-electron mobility transistor integrally formed in the second region. The first and second high-electron mobility transistors are connected in series. A source terminal of the first high-electron mobility transistor is electrically connected to the first device area. The first device area is electrically isolated from a subjacent intrinsically doped region of the base substrate by a first two-way voltage blocking device. | 2022-04-28 |
20220130988 | ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME - Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and/or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is/are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse. | 2022-04-28 |
20220130989 | APPARATUS AND CIRCUITS INCLUDING TRANSISTORS WITH DIFFERENT POLARIZATIONS AND METHODS OF FABRICATING THE SAME - Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion. | 2022-04-28 |
20220130990 | NORMALLY-OFF TRANSISTOR WITH REDUCED ON-STATE RESISTANCE AND MANUFACTURING METHOD - A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region. | 2022-04-28 |
20220130991 | SEMICONDUCTOR DEVICE WITH BACKSIDE POWER RAIL AND METHODS OF FABRICATION THEREOF - A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer. | 2022-04-28 |
20220130992 | THREE-DIMENSIONAL FIELD EFFECT DEVICE - A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves. | 2022-04-28 |
20220130993 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction. | 2022-04-28 |
20220130994 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH RECESSED ACCESS TRANSISTOR - The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a patterned mask having a plurality of openings on a substrate; etching the substrate through the openings to form an etched substrate and a trench in the etched substrate, wherein the etched substrate comprises a protrusion; introducing dopants having a first conductivity type in the etched substrate and on either side of the trench to form a plurality of first impurity regions; forming an isolation film in the trench; and depositing a conductive material on the isolation film. | 2022-04-28 |
20220130995 | POWER SEMICONDUCTOR DEVICES INCLUDING A TRENCHED GATE AND METHODS OF FORMING SUCH DEVICES - Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer. | 2022-04-28 |
20220130996 | GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING IMPROVED DEEP SHIELD CONNECTION PATTERNS - A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction. | 2022-04-28 |
20220130997 | GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING IMPROVED DEEP SHIELD CONNECTION PATTERNS - A power semiconductor device comprises a semiconductor layer structure comprising a drift region that comprises a wide band-gap semiconductor material and has a first conductivity type, a first gate structure and an adjacent second gate structure in an upper portion of the semiconductor layer structure, a deep shielding region in the drift region, and a connection region protruding upwardly from the deep shielding region and separating the first gate structure and the second gate structure from each other. The deep shielding region extends from underneath the first gate structure to underneath the second gate structure, and the deep shielding region has a second conductivity type that is different from the first conductivity type. | 2022-04-28 |
20220130998 | POWER SEMICONDUCTOR DEVICES INCLUDING ANGLED GATE TRENCHES - A power semiconductor device comprises a semiconductor layer structure comprising a drift region that comprises a wide band-gap semiconductor material that has a first conductivity type, a well region that has a second conductivity type, and a source region that has the first conductivity type in an upper portion of the well region and a gate trench in an upper portion of the semiconductor layer structure and comprising a portion obliquely angled in plan view. Sidewalls of the gate trench may extend along substantially the same crystal plane in the semiconductor layer structure. | 2022-04-28 |
20220130999 | SHIELDED GATE TRENCH MOSFET DEVICES - A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing. | 2022-04-28 |
20220131000 | SHIELDED GATE TRENCH MOSFET DEVICES - A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing. | 2022-04-28 |
20220131001 | SHIELDED GATE TRENCH MOSFET DEVICES - A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing. | 2022-04-28 |
20220131002 | ISOLATION IN A SEMICONDUCTOR DEVICE - According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area. | 2022-04-28 |
20220131003 | MEMORY ARRAYS WITH VERTICAL TRANSISTORS AND THE FORMATION THEREOF - An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line. | 2022-04-28 |
20220131004 | GATE CUT STRUCTURE AND METHOD OF FORMING THE SAME - Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, a gate cut feature extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature, and a liner disposed between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature. | 2022-04-28 |
20220131005 | SEMICONDUCTOR INTEGRATED CIRCUIT COMPONENT - An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region. | 2022-04-28 |
20220131006 | Semiconductor Device and Methods of Forming - In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration. | 2022-04-28 |
20220131007 | EPITAXIAL OXIDE PLUG FOR STRAINED TRANSISTORS - Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments. | 2022-04-28 |
20220131008 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction. | 2022-04-28 |
20220131009 | OXIDE THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE - An oxide thin film transistor includes: a gate electrode, a metal oxide active layer and a source-drain metal layer, which are on a base substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; an electron transfer rate of the carrier transport layer is greater than an electron transfer rate of the carrier isolation layer. The first metal oxide layer includes a primary surface facing toward the base substrate and a primary surface away from the base substrate; the first metal oxide layer further includes a lateral surface around the primary surfaces; the second metal oxide layer covers the lateral surface of the first metal oxide layer. | 2022-04-28 |
20220131010 | METAL OXIDE AND TRANSISTOR INCLUDING THE METAL OXIDE - To provide a novel metal oxide. The metal oxide includes a first region and a second region. A third region is included between the first region and the second region. An interface of the first region is covered with the third region. The crystallinity of the third region is lower than the crystallinity of the first region. The crystallinity of the second region is lower than the crystallinity of the third region. The size of the first region measured from an image observed with a transmission electron microscope is greater than or equal to 1 nm and less than or equal to 3 nm. | 2022-04-28 |
20220131011 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion. | 2022-04-28 |
20220131012 | TRANSISTOR, METHOD OF MANUFACTURING TRANSISTOR, AND DISPLAY DEVICE USING THE SAME - A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer. | 2022-04-28 |
20220131013 | MULTI-CHANNEL GATE-ALL-AROUND HIGH-ELECTRON-MOBILITY TRANSISTOR - Certain aspects of the present disclosure generally relate to a semiconductor device implemented with multiple channels in a gate-all-around (GAA) high-electron-mobility transistor (HEMT) and techniques for fabricating such a device. One example semiconductor device generally includes a substrate; a first gate layer disposed above the substrate; a first barrier layer disposed above the first gate layer; a first channel region disposed above the first barrier layer; a second barrier layer disposed above the first channel region; a second gate layer disposed above the second barrier layer; a third barrier layer disposed above the second gate layer; a second channel region disposed above the third barrier layer; a fourth barrier layer disposed above the second channel region; a source region; and a drain region. | 2022-04-28 |
20220131014 | LIGHTLY-DOPED CHANNEL EXTENSIONS - A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature. | 2022-04-28 |
20220131015 | SIC MOSFET WITH BUILT-IN SCHOTTKY DIODE - A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events. | 2022-04-28 |
20220131016 | CHARGE BALANCED RECTIFIER WITH SHIELDING - SiC Schottky rectifiers are described with a Silicon Carbide (SiC) layer, a metal contact, and an n-type channel region disposed between the SiC layer and the metal contact. A p-pillar may be formed adjacent to the metal contact and extending in a direction of the SiC layer, and a a p-type shielding body adjacent to the metal contact and extending from the metal contact in a direction of the SiC layer. The SiC Schottky rectifiers may include a first channel region of the n-type channel region having a first n-type doping concentration, and disposed between the p-pillar and the p-type shielding body, the first channel region being adjacent to the metal contact. The SiC Schottky rectifiers may include an n-pillar providing a second channel region of the n-type channel region and having a second n-type doping concentration that is lower than the first n-type doping concentration in the first channel region, the n-pillar being disposed adjacent to the first channel region, and to the p-pillar. | 2022-04-28 |
20220131017 | IN-SITU CAP FOR GERMANIUM PHOTODETECTOR - Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer. | 2022-04-28 |
20220131018 | FINGERPRINT SENSOR AND DISPLAY DEVICE INCLUDING THE SAME - A fingerprint sensor, includes: a light sensing layer including a photo-sensing element to flow a sensing current according to incident light; and a collimator layer on the light sensing layer, the collimator layer including: a first light blocking layer having a plurality of first holes; a first light transmitting layer on the first light blocking layer; and a second light blocking layer on the first light transmitting layer, and having a plurality of second holes overlapping with the plurality of first holes. | 2022-04-28 |
20220131019 | FINGERPRINT IDENTIFICATION STRUCTURE AND DISPLAY PANEL - A fingerprint identification structure and a display panel are disclosed. display panel includes a fingerprint identification structure. The fingerprint identification structure includes a light energy switch and a thermosensitive light path adjustment structure. The light energy switch is configured to switch from an open circuit to a closed circuit under light irradiation. The thermosensitive light path adjustment structure is connected to a surface of the light energy switch, is able to transmit light internally, and is configured to adjust a light path of light to drive the light to irradiate the light energy switch when receiving a heat source. | 2022-04-28 |
20220131020 | ELECTRODE STRUCTURE AND PHOTODETECTION ELEMENT - An electrode structure includes: a metal film with an opening formed in a part of the metal film; and a transparent conductive film disposed in the opening, wherein the transparent conductive film is electronically connected to an element and overlaps with the element as viewed in a plan view in a thickness direction of the transparent conductive film. | 2022-04-28 |
20220131021 | OPTICAL SENSOR, METHOD FOR SELECTING AN OPTICAL SENSOR AND DETECTOR FOR OPTICAL DETECTION - Described herein is an optical sensor, a detector for an optical detection including the optical sensor, a method for manufacturing the optical sensor and various uses of the optical detector. The optical sensor includes a stack. | 2022-04-28 |
20220131022 | COVER PLATE AND PHOTOVOLTAIC MODULE - Provided is a cover plate and a photovoltaic module. The cover plate is configured to form a photovoltaic module together with a solar cell string, and the cover plate includes: at least one through hole provided in the cover plate and penetrating through the cover plate, a reinforced region surrounding the at least one through hole, and a flat region adjacent to the reinforced region; wherein a thickness of the cover plate in the reinforced region is greater than a thickness of the cover plate in the flat region. The cover plate and the photovoltaic module according to the embodiments of the present disclosure may solve the problem of poor load resistance capability of the cover plate. | 2022-04-28 |
20220131023 | METHOD FOR REDUCING THERMOMECHANICAL STRESS IN SOLAR CELLS - The present disclosure provides a method of reducing the thermomechanical stress in the silicon solar cells induced in the interconnection process. The front and rear metal electrodes of the solar cell are provided in such a way that the outermost bonding point between the front metal electrodes and the front interconnects (ribbons or wires) is aligned to the outermost bonding point between the rear metal electrodes and the rear interconnects. The method is applicable to busbar-based interconnection using stringing/tabbing process and wire-based interconnection such as Multi-Busbar and smart wire connection technology. The method can be applied to both mono-facial and bifacial solar cells. The reduced-area busbar end in the busbar-based interconnection increases the tolerance of misalignment of the outermost bonding points introduced by the manufacturing processes. | 2022-04-28 |
20220131024 | LOW LEAKAGE CURRENT GERMANIUM-ON-SILICON PHOTO-DEVICES - Germanium (Ge)-Silicon (Si) structures, optoelectronic devices and method for forming same. A structure comprises a Si substrate, a Ge seed layer and a Ge epitaxial layer separated by respective interfaces that share a common plane normal, wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level, and a locally doped region formed in the Si layer adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the structure. | 2022-04-28 |
20220131025 | DETECTION BASE PLATE AND FLAT-PANEL DETECTOR - A detection base plate and a flat-panel detector. The detection base plate comprises multiple detection pixel units arranged in an array. Each detection pixel unit comprises: a thin-film transistor, a sacrificial layer and a photoelectric conversion part that are disposed on a substrate, wherein the sacrificial layer is located between the thin-film transistor and the photoelectric conversion part; the thin-film transistor comprises an active layer, a first electrode and a second electrode; at least part of an orthographic projection of the active layer on the substrate is located within an orthographic projection of the sacrificial layer on the substrate; and the photoelectric conversion part is electrically connected to the sacrificial layer and the first electrode. In the detection base plate, the sacrificial layets of the detection pixel units are mutually independent. | 2022-04-28 |
20220131026 | TRANSPARENT SENSING DEVICE, LAMINATED GLASS, AND METHOD FOR MANUFACTURING TRANSPARENT SENSING DEVICE - One embodiment of the present invention is a transparent sensing device comprising: a transparent substrate; a microsensor arranged on the transparent substrate and having an area of 250,000 μm | 2022-04-28 |
20220131027 | METHOD FOR MANUFACTURING IMAGE DISPLAY DEVICE AND IMAGE DISPLAY DEVICE - A method for manufacturing an image display device includes: providing a second substrate that comprises a first substrate, and a semiconductor layer on the first substrate, the semiconductor layer comprising a light-emitting layer; providing a third substrate comprising a circuit, the circuit comprising a circuit element; bonding the semiconductor layer to the third substrate; forming a light-emitting element by etching the semiconductor layer; covering the light-emitting element with a light-transmissive insulating member; and forming a wiring layer electrically connecting the light-emitting element to the circuit element; wherein: the light-emitting element has a light-emitting surface opposite to a surface of the light-emitting element that is bonded to the third substrate; and the insulating member is configured to cause light radiated from the light-emitting element to have a light distribution in a normal direction of the light-emitting surface toward a light-emitting surface side. | 2022-04-28 |
20220131028 | Light Emitting Diode (LED) Devices With Nucleation Layer - Described are light emitting diode (LED) devices having patterned substrates and methods for effectively growing epitaxial III-nitride layers on them. A nucleation layer, comprising a III-nitride material, is grown on a substrate before any patterning takes place. The nucleation layer results in growth of smooth coalesced III-nitride layers over the patterns. | 2022-04-28 |
20220131029 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor light-emitting device comprises a substrate; a first adhesive layer on the substrate; multiple epitaxial units on the first adhesive layer; a second adhesive layer on the multiple epitaxial units; multiple first electrodes between the first adhesive layer and the multiple epitaxial units, and contacting the first adhesive layer and the multiple epitaxial units; and multiple second electrodes between the second adhesive layer and the multiple epitaxial units, and contacting the second adhesive layer and the multiple epitaxial units; wherein the multiple epitaxial units are totally separated. | 2022-04-28 |
20220131030 | METHOD OF MANUFACTURING DISPLAY APPARATUS AND THE DISPLAY APPARATUS - Provided are a method of manufacturing a display apparatus and the display apparatus. The method includes forming an emissive layer and a driving layer on a first area of a substrate, forming an exposure line electrically connected to the driving layer, on a second area of the substrate, and forming a color conversion layer on the driving layer by emitting light from the emissive layer using the exposure line. | 2022-04-28 |
20220131031 | SOLID STATE LIGHTING DEVICES WITH DIELECTRIC INSULATION AND METHODS OF MANUFACTURING - Semiconductor lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The semiconductor lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure. | 2022-04-28 |
20220131032 | MICRO LIGHT-EMITTING DEVICE - A micro light-emitting device, including a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first type electrode, a second type electrode, and a light reflection layer, is provided. The light-emitting layer is arranged on the first type semiconductor layer. The second type semiconductor layer is arranged on the light-emitting layer. The first type electrode and the second type electrode are both arranged on the second type semiconductor layer. The light reflection layer is arranged between the light-emitting layer and the first type electrode. The light reflection layer includes an oxidized area and a non-oxidized area. A reflectance of the oxidized area is greater than a reflectance of the non-oxidized area. An orthographic projection of a part of the oxidized area on the first type semiconductor layer and an orthographic projection of the first type electrode on the first type semiconductor layer at least partially overlap. | 2022-04-28 |
20220131033 | Growth Structure for a Radiation-Emitting Semiconductor Component, and Radiation-Emitting Semiconductor Component - In an embodiment a growth structure for a radiation-emitting semiconductor component includes a semiconductor substrate containing a material based on arsenide compound semiconductors and a buffer structure arranged on the semiconductor substrate, wherein the buffer structure includes a buffer layer having at least one n-doped layer and wherein the n-doped layer contains oxygen, and a molar fraction of oxygen in the n-doped layer is between 10 | 2022-04-28 |
20220131034 | Optoelectronic Semiconductor Chip and Method for Producing an Optoelectronic Semiconductor Chip - In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a first layer, a second layer and an active layer arranged between the first layer and the second layer, the semiconductor layer sequence having at least one injection region, wherein the first layer includes a first conductivity type, wherein the second layer includes a second conductivity type, wherein the semiconductor layer sequence includes the first conductivity type within the entire injection region, wherein the injection region, starting from the first layer, at least partially penetrates the active layer, wherein side surfaces of the semiconductor layer sequence are formed at least in places by the injection region, and wherein the injection region is configured to inject charge carriers directly into the active layer. | 2022-04-28 |
20220131035 | LIGHT SOURCE USING PHOTONIC CRYSTAL STRUCTURE - The inventive concept includes a substrate, a heterojunction structure including a first encapsulation layer, a graphene layer, and a second encapsulation layer sequentially stacked on the substrate, photonic crystal holes vertically penetrating the first encapsulation layer, the graphene layer, and the second encapsulation layer, and first and second electrodes respectively connected to both end portions of the heterojunction structure, The heterojunction structure includes buffer areas contacting the first and second electrodes, respectively, and emission areas between the buffer areas, The photonic crystal holes are provided in the emission area, and the width of the emission area is smaller than the widths of the buffer areas to provide a light source using a photonic crystal structure. In addition, a light source using the photonic crystal structure may be utilized as a photodetector. | 2022-04-28 |
20220131036 | MICRO LIGHT-EMITTING DEVICE AND DISPLAY APPARATUS THEREOF - A micro light-emitting device includes an epitaxial structure, a first electrode, and a second electrode. The epitaxial structure includes a first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer. The light-emitting layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first-type semiconductor layer includes a first portion and a second portion connected to each other. A distance is present between an edge of the first portion and an edge of the second portion. A bottom area of the first portion is smaller than a top area of the second portion. The first electrode is disposed on the epitaxial structure and located on the first portion of the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure. | 2022-04-28 |
20220131037 | SEMICONDUCTOR STRUCTURES AND SUBSTRATES THEREOF, AND METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SUBSTRATES THEREOF - This application provides a semiconductor structure and substrate thereof, a method of manufacturing the semiconductor structure and substrate thereof. The substrate includes a plurality of unit areas, each of the unit areas includes at least two subunit areas, each of the subunit areas is provided with a groove, the groove is opened from a back side of the substrate; and in one of the unit areas, preset opening ratios of the subunit areas are different. A light-emitting layer is grown on a front side of the substrate; and in one of the unit areas, light-emitting wavelengths of the light-emitting layer in the subunit areas are different. | 2022-04-28 |
20220131038 | DISPLAY DEVICE - A display device including a plurality of pixels, each of the pixels including a first area and a second area and including: a first electrode and a second electrode in the first area; a plurality of light-emitting elements located between the first electrode and the second electrode in the first area; a first insulating layer in the first area and the second area; and a second insulating layer on the first insulating layer, wherein the first insulating layer includes a first opening in the second area, the second insulating layer includes a second opening overlapping the first opening, and a width of the first opening in a first direction is greater than a width of the second opening in the first direction. | 2022-04-28 |
20220131039 | MICRO LIGHT-EMITTING DIODE - A micro light-emitting diode includes an epitaxial structure, an insulation layer, a first electrode, and a second electrode. The epitaxial structure includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The epitaxial structure has a cavity penetrating the second semiconductor layer and the light-emitting layer and exposing a portion of the first semiconductor layer. The insulation layer covers the epitaxial structure, and a side surface and a bottom surface of the cavity. The insulation layer has a first hole exposing a portion of the second semiconductor layer, and a second hole exposing a portion of the bottom surface. The first electrode covers the exposed portion of the bottom surface. The second electrode covers the exposed portion of the second semiconductor layer and is distant from the first electrode. The cavity is distant from an edge of the micro LED. | 2022-04-28 |
20220131040 | MICRO LIGHT-EMITTING DIODE DISPLAY - A micro light-emitting diode display includes a first-type semiconductor base layer, a plurality of semiconductor light-emitting mesas dispersedly disposed on the first-type semiconductor base layer, a semiconductor heightening portion disposed on the first-type semiconductor base layer, a first bonding metal layer disposed on the semiconductor heightening portion, and a plurality of second bonding metal layers respectively disposed on the semiconductor light-emitting mesas. A top surface of the semiconductor heightening portion and a plurality of top surfaces of the semiconductor light-emitting mesas facing away from the first-type semiconductor base layer are coplanar. The top surface of the semiconductor heightening portion forms a first bonding surface adjacent to the first bonding metal layer. The top surfaces of the semiconductor light-emitting mesas respectively form a plurality of second bonding surfaces adjacent to the second bonding metal layers, and the first bonding surface and the second bonding surfaces are coplanar. | 2022-04-28 |
20220131041 | LED ARRAYS HAVING A REDUCED PITCH - Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a method includes forming a plurality of stacks of layers on a surface of a semiconductor, with a p contact at an interface between each stack and a p-type layer of the semiconductor. The semiconductor is etched to form a plurality of mesa shapes corresponding to the plurality of stacks. A dielectric is formed on at least a portion of each mesa shape and at least a portion of each stack. A reflector is formed on at least a portion of the dielectric and at least a portion of the semiconductor to provide an n contact at an interface between the reflector and an n-type layer of the semiconductor. The reflector is physically separated from the p contact for each stack. | 2022-04-28 |
20220131042 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride semiconductor light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, an active layer, and an electron blocking layer comprising at least one layer. The at least one layer of the electron blocking layer includes a peak-containing layer having an n-type impurity concentration peak in an n-type impurity concentration distribution along a stacking direction. The n-type impurity concentration peak appears as a local maximum in the n-type impurity concentration distribution along the stacking direction in the peak-containing layer and has an n-type impurity concentration of not less than 10 times a smallest value of the n-type impurity concentration in a region along the stacking direction between positions that are separated from a position of the peak in the stacking direction on both sides in the stacking direction by 10% of a thickness of the peak-containing layer. | 2022-04-28 |
20220131043 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A nitride semiconductor light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, an active layer provided between the n-type semiconductor layer and the p-type semiconductor layer, and an electron blocking layer comprising Al and being provided between the active layer and the p-type semiconductor layer. The electron blocking layer partially includes a high Al composition portion in at least one cross section orthogonal to a stacking direction, the high Al composition portion having an Al composition ratio higher than a surrounding portion. | 2022-04-28 |
20220131044 | DRIVING BACKPLANE, DISPLAY PANEL AND DISPLAY APPARATUS - A driving backplane, a display panel and a display apparatus are provided. The driving backplane includes: a base substrate, and a plurality of connection electrode groups and a plurality of correction structures disposed on the base substrate, each of the connection electrode groups includes: a first connection electrode and a second connection electrode the first connection electrode and the second connection electrode are arranged on a same layer; a first gap is formed between the first connection electrode and the second connection electrode, and a first group of opposite edges includes: an edge, close to the first gap, of the first connection electrode; and an edge, close to the first gap, of the second connection electrode; a second group of opposite edges includes: an edge, far away from the first gap, of the first connection electrode; and an edge, far away from the first gap, of the second connection electrode. | 2022-04-28 |
20220131045 | DISPLAY DEVICE AND METHOD OF FABRICATING DISPLAY DEVICE - A display device includes a substrate, a first electrode on the substrate, a plurality of light emitting elements on the first electrode, and a second electrode on the plurality of light emitting elements. An area of a first surface of each of the plurality of light emitting elements in contact with the first electrode is different from an area of a second surface of each of the plurality of light emitting elements in contact with the second electrode. Each of the plurality of light emitting elements includes a metal layer in contact with the first electrode and including a fusible alloy or a eutectic alloy. | 2022-04-28 |
20220131046 | MICRO SEMICONDUCTOR DEVICE - A micro semiconductor device, including a semiconductor structure, a current confinement layer, a first type electrode, and a second type electrode, is provided. The current confinement layer is disposed in the semiconductor structure. The current confinement layer includes an oxidized area and a non-oxidized area. The first type electrode and the second type electrode are both disposed on the current confinement layer. An orthographic projection of a part of the oxidized area on a bottom surface of the semiconductor structure away from the first type electrode and the second type electrode is located between an orthographic projection of the first type electrode on the bottom surface and an orthographic projection of the second type electrode on the bottom surface. | 2022-04-28 |
20220131047 | LIGHT EMITTING ELEMENT AND DISPLAY DEVICE INCLUDING THE SAME - A display device comprises a first electrode and a second electrode on a substrate, a first insulating layer on the first electrode and the second electrode, light emitting elements on the first insulating layer each having a first end on the first electrode and a second end on the second electrode, a first connection electrode disposed on the first electrode and electrically contacting the first end of each of the light emitting elements, a second connection electrode disposed on the second electrode and electrically contacting the second end of each of the light emitting elements, a second insulating layer on the light emitting elements, the first connection electrode and the second connection electrode, and a third connection electrode disposed on the second insulating layer and electrically contacting the light emitting elements through an opening formed in the second insulating layer that partially exposes the light emitting elements. | 2022-04-28 |
20220131048 | PIXELATED-LED CHIPS WITH INTER-PIXEL UNDERFILL MATERIALS, AND FABRICATION METHODS - Pixelated-LED chips including a plurality of independently electrically accessible active layer portions supported by a plurality of discontinuous substrate portions to form a plurality of pixels, with underfill material of varying composition provided between sidewalls of adjacent pixels. Underfill materials having different reflection, scattering, absorption, filtering, etch-resistance, and/or light refraction properties may be provided in multiple layers. A method for fabricating a pixelated-LED chip includes defining streets through an active layer and portions of a substrate to form active layer portions, thinning an entire upper portion of a substrate to create openings into the streets and form discontinuous substrate portions bounding the streets, and supplying underfill material through the openings into the streets. | 2022-04-28 |
20220131049 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE - A method for manufacturing a light-emitting device includes forming the quantum dot layer. The forming the quantum dot layer includes: performing first application that involves applying a first solution on a position overlapping with the substrate; performing first light irradiation, that involves irradiating with light, from above the substrate, the position where the first solution is applied; performing second light irradiation, that involves irradiating the position with light to raise a temperature of the quantum dot; and performing third light irradiation, that involves irradiating the position with light to cause the first inorganic precursor to epitaxially grow around the first shell. In the performing third light irradiation, at least one set of the quantum dots adjacent to each other is connected to each other via the second shell. | 2022-04-28 |
20220131050 | TWO COMPONENT GLASS BODY FOR TAPE CASTING PHOSPHOR IN GLASS LED CONVERTERS - The present invention is directed to a method for preparing a glass device comprising the steps of: —preparing a mixture comprising: —at least two glass components, —a solvent, —at least one binder system, —optionally at least one defoamer, —blending the mixture to form a blend mixture, —grinding the blend mixture to form a grinded mixture, —casting the grinded mixture to form a layer, and —drying the layer to form a dried layer of a glass device. The present invention is further directed to a glass device, a wavelength converter and a light emitting device comprising the glass device and/or the wavelength converter. | 2022-04-28 |
20220131051 | WAVELENGTH CONVERSION STRUCTURE, LIGHT-EMITTING APPARATUS AND DISPLAY DEVICE USING THE SAME - The present disclosure provides a wavelength conversion structure, a light-emitting apparatus, and a display device using the wavelength conversion structures. The wavelength conversion structure includes a porous inorganic shell and a plurality of organic complex phosphor particles filled in the porous inorganic shell. Wherein the plurality of organic complex phosphor particles is capable of being excited to emit light with a peak wavelength in the visible light range. | 2022-04-28 |
20220131052 | Optoelectronic Semiconductor Component and Method for Producing An Optoelectronic Semiconductor Component - In an embodiment an optoelectronic semiconductor component includes an optoelectronic semiconductor chip having a radiation exit surface and side surfaces running transversely with respect to the radiation exit surface, the optoelectronic semiconductor chip configured to emit primary radiation through the radiation exit surface, a conversion element arranged on the radiation exit surface, the conversion element configured to convert at least part of the primary radiation into secondary radiation and including a stack of at least two conversion layers and a reflective element laterally surrounding the optoelectronic semiconductor chip, wherein a lateral extent of the conversion layers decreases from a layer which is closest to the radiation exit surface to a layer which is most distant from the radiation exit surface, wherein the conversion element includes a part laterally extending beyond the radiation exit surface and being concavely curved, wherein the conversion element is partly arranged on the reflective element, and wherein the conversion element is arranged on a concavely curved surface of the reflective element. | 2022-04-28 |
20220131053 | WAVELENGTH CONVERSION DEVICE - A wavelength conversion device includes a base plate, at least one wavelength conversion material layer and a balance ring. The base plate has a geometric center, the wavelength conversion material layer is disposed on the base plate, and the balance ring is disposed on the base plate and rotates about a rotation shaft. The balance ring has a balancing part, and the balancing part includes at least one of the following structures: (1) a protrusion formed by a part of an outer periphery of the balance ring protruding in a direction away from the rotation shaft; (2) a recess formed by a part of the outer periphery of the balance ring caving in a direction towards the rotation shaft. | 2022-04-28 |
20220131054 | LIGHT-EMITTING PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light-emitting package includes a black encapsulating member, a plurality of light-emitting components and a circuit structure. The black encapsulating member has a first surface and a second surface opposite to the first surface. The light-emitting components are embedded in the black encapsulating member. Each light-emitting component has a light-emitting surface, a back surface opposite to the light-emitting surface, and a plurality of pads disposed on the back surface. The light-emitting surface of each light-emitting component is exposed on the first surface and is flush with the first surface. The pads of each light-emitting component are exposed on the second surface. The circuit structure is disposed on the second surface and electrically connected to the pads. | 2022-04-28 |
20220131055 | LIGHT SOURCE DEVICE, DISPLAY DEVICE AND MANUFACTURING METHOD OF LIGHT SOURCE DEVICE - A manufacturing method includes: a step of forming a light-emitting element layer by forming a semiconductor layer, a light-emitting layer, and a semiconductor layer in this order from a side with a first substrate on a surface, of the first substrate, on one side; a step of forming a separation trench in the light-emitting element layer to form a plurality of island shape light-emitting element layers; a step of forming a light shielding layer made of a material different from a material of the light-emitting element layer, in the separation trench; and a step of forming a plurality of light-emitting elements each including a corresponding one of the plurality of island shape light-emitting element layers having a height less than a height of the light shielding layer by etching a portion of the semiconductor layers of each of the plurality of island shape light-emitting element layers. | 2022-04-28 |
20220131056 | UV LED Package Having Encapsulating Extraction Layer - A UV LED package includes a substrate having a dam, a LED die on the substrate, a lens bonded to the substrate, an extraction layer covering a light emitting surface of the LED die, and a lens sealing layer between the lens and the dam. The extraction layer can be formed to provide a precise gap G between the lens and the light emitting diode (LED). In addition, the materials for the lens and the extraction layer can be selected, and the gap G can be precisely dimensioned, to reduce refraction and reflection, to improve radiation extraction, to reduce power radiance, and to improve the efficiency of the UV LED package. | 2022-04-28 |
20220131057 | MICRO LIGHT-EMITTING DIODE - A micro light-emitting diode disposed on and electrically connected to a circuit substrate includes: an epitaxial structure, at least one first electrode, a second electrode, and an insulating layer. The epitaxial structure includes a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked sequentially. The first electrode is electrically connected to the first semiconductor layer and extends from a side of the first semiconductor layer along at least one side surface of the epitaxial structure to a position between the second semiconductor layer and the circuit substrate. The second electrode is located below the second semiconductor layer and is electrically connected to the second semiconductor layer. The insulating layer is disposed at least between the at least one first electrode and the light emitting layer of the epitaxial structure and between the at least one first electrode and the second semiconductor layer of the epitaxial layer. | 2022-04-28 |
20220131058 | MULTI-LAYER PCB STACK FOR COLOR MIXING - The invention provides a lighting device ( | 2022-04-28 |
20220131059 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a display device includes a substrate, a drive transistor that is provided on above the substrate, a first insulating layer that is provided above the substrate, a first mounting electrode that is arranged above the first insulating layer, and a light emitting element that is mounted on the first mounting electrode and has a first electrode and a second electrode, the first electrode being electrically connected to the first mounting electrode. The first mounting electrode and the first electrode are made of a metal material and joined to each other. The first mounting electrode has at least one first through hole at a position overlapping the first electrode in plan view. | 2022-04-28 |
20220131060 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting element includes: a semiconductor stack including an n-type layer and a p-type layer and having at least one n exposure portion being a recess where the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer (i) continuously covering inner lateral surfaces of at least one n exposure portion and part of a top surface of the p wiring electrode layer and (ii) having an opening portion that exposes the n-type layer; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer and in contact with the n-type layer in the opening portion; and at least one first n connecting member connected to the n wiring electrode layer in at least one first n terminal region. The n wiring electrode layer and the p-type layer are disposed below at least one first n terminal region. | 2022-04-28 |
20220131061 | LED MODULE AND DISPLAY DEVICE HAVING LED MODULE - An LED module includes a first protrusion and a second protrusion adjacent to the first protrusion arranged on an insulating surface, a first electrode arranged on the first protrusion, and a second electrode arranged on the second protrusion, and an LED chip arranged on upper sides of the first protrusion and the second protrusion. The LED chip is connected to the first electrode and the second electrode via conductive members, and the first protrusion and the second protrusion are insulative and have a height of | 2022-04-28 |
20220131062 | SOLID-STATE THERMOELECTRIC - For thermoelectric heat transfer, a thermoelectric device includes a planar p-type semiconductor that is planar within a first plane, a planar n-type semiconductor that is coplanar with the planar p-type semiconductor within the first plane, a cold side conductor that is coplanar with the planar p-type semiconductor and the planar n-type semiconductor within the first plane and that connects to the planar p-type semiconductor and to the planar n-type semiconductor, and a hot side conductor that is coplanar with the planar p-type semiconductor and the planar n-type semiconductor within the first plane and that connects to the planar p-type semiconductor and to the planar n-type semiconductor. The thermoelectric device further includes a hot side substrate, a hot side thermal insulator, a cold side substrate, and a cold side thermal insulator. The cold side conductor draws heat from the cold side substrate. | 2022-04-28 |
20220131063 | ON-CHIP TUNABLE DISSIPATIONLESS INDUCTOR - A controllable superconducting inductor circuit comprises: a plurality of sub-circuits, each sub-circuit comprising: an inductor element; and a control element coupled to the inductor element to induce current in the inductor element in response to a control signal received at the control element. The inductor elements from the plurality of sub-circuits are arranged in parallel between a first pair of nodes to provide a tunable total inductance L | 2022-04-28 |
20220131064 | SUPERCONDUCTING QUBIT AND PREPARATION METHOD THEREOF, QUANTUM STORAGE DEVICE, AND QUANTUM COMPUTER - The present disclosure provides a superconducting qubit. The superconducting qubit includes: a Josephson junction and a non-Josephson junction area, wherein the non-Josephson junction area includes a first layer of superconducting material, the first layer of superconducting material being superconducting material deposited on the non-Josephson junction area before ion milling on the Josephson junction and the non-Josephson junction area during preparation of the superconducting qubit. | 2022-04-28 |
20220131065 | SENSOR COMPRISING AN INTERCONNECT HAVING A CARRIER FILM - The present invention relates to a sensor, comprising a sensor element and an interconnect. The interconnect is configured to be arranged at the sensor element. The interconnect comprises at least a carrier film provided with metallic layer. The interconnect is configured to provide an electrical connection for the sensor element. Furthermore a device comprising the sensor and a method of manufacturing the sensor is provided. | 2022-04-28 |
20220131066 | DIELECTRIC ELASTOMER TRANSDUCER AND METHOD FOR PRODUCING DIELECTRIC ELASTOMER TRANSDUCER - A dielectric elastomer transducer Al includes a dielectric elastomer layer | 2022-04-28 |
20220131067 | MAGNETIC TUNNEL JUNCTION MEMORY DEVICES EMPLOYING RESONANT TUNNELING AND METHODS OF MANUFACTURING THE SAME - A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration. | 2022-04-28 |
20220131068 | MAGNETIC TUNNEL JUNCTION MEMORY DEVICES EMPLOYING RESONANT TUNNELING AND METHODS OF MANUFACTURING THE SAME - A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration. | 2022-04-28 |
20220131069 | MAGNETIC TUNNEL JUNCTION DEVICE, MAGNETIC MEMORY USING THE SAME AND METHOD FOR MANUFACTURING THE SAME - Disclosed art a magnetic tunnel junction device, a magnetic memory using the same, and a method for manufacturing the same. The method for manufacturing the magnetic tunnel junction device may include the steps of a lamination step of forming an initial multilayer structure including at least one metallic oxide layer and a metallic layer on a substrate; a heat treatment step of heat-treating the initial multilayer structure; and a device forming step of forming a magnetic tunnel junction device of a final multilayer structure in which at least one metallic oxide layer and the metallic layer are converted to at least one ferromagnetic material layer and the oxide layer by heat treatment. | 2022-04-28 |
20220131070 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures. | 2022-04-28 |