17th week of 2010 patent applcation highlights part 28 |
Patent application number | Title | Published |
20100103697 | LAMP UNIT, ILLUMINATION DEVICE, AND DISPLAY APPARATUS - In a lamp unit ( | 2010-04-29 |
20100103698 | BACKLIGHT UNIT - A backlight unit does not show decrease of brightness for the frontal direction even when made thin-shaped. An edge light type backlight unit | 2010-04-29 |
20100103699 | METHOD FOR MANUFACTURING LIGHT GUIDE PANEL, LIGHT GUIDE PANEL AND LIGHT SOURCE UNIT - The invention provides a light guide panel that improves luminance and reduces uneven luminance and color aberration. The light guide panel of the invention may be formed by irradiating laser light from a laser light source to the surface of an acrylic resin plate made of polymethylmethacrylate whose weight-average molecular weight is 10,000 to 100,000 or of a copolymer of 90 to 99.9% by weight of methyl methacrylate and 0.1 to 10% by weight of acrylic ester and whose weight-average molecular weight is 1,000 to 100,000 to form a light scattering pattern including a large number of concave portions each of which also includes a large number of micro-concavities and convexities therein. | 2010-04-29 |
20100103700 | Light source module - A light source module includes at least one light emitting device and a focus adjustable lens array. The light emitting device is adapted to emit a light beam, the focus adjustable lens array is disposed in the transmission path of the light beam and includes a plurality of focus adjustable lenses arranged in an array. Each of the focus adjustable lenses includes a first light transmissive plate disposed in the transmission path of the light beam, a first electrode disposed on a peripheral area of the first light transmissive plate, a second light transmissive plate disposed in the transmission path of the beam, a second electrode disposed on a peripheral area of the second light transmissive plate, and a focus adjustable solution disposed between the first light transmissive plate and the second light transmissive plate. The focus adjustable solution includes a solvent and an electrotaxis solute. | 2010-04-29 |
20100103701 | PUSH BUTTON RELEASE FOR LUMINAIRES IN A TRACK LIGHTING SYSTEM - The invention provides an apparatus for engaging and disengaging a track lighting assembly with respect to a track in a track lighting system. The apparatus includes a track engaging apparatus that includes a housing. The housing includes a rotation inhibitor that has a protruding end that protrudes from the housing for engaging with the track and preventing the track engaging apparatus from rotating with respect to the track. The rotation inhibitor further includes a receiving member for translating a force in a first direction into motion of the rotation inhibitor in a second direction substantially orthogonal to the first direction. The apparatus further includes an actuator for applying the force in the first direction to the receiving member. | 2010-04-29 |
20100103702 | ADAPTIVE INDUCTIVE POWER SUPPLY - A contactless power supply has a dynamically configurable tank circuit powered by an inverter. The contactless power supply is inductively coupled to one or more loads. The inverter is connected to a DC power source. When loads are added or removed from the system, the contactless power supply is capable of modifying the resonant frequency of the tank circuit, the inverter frequency, the inverter duty cycle or the rail voltage of the DC power source. | 2010-04-29 |
20100103703 | ISOLATED DC-DC CONVERTER - A switching circuit arranged to switch the input of an input power supply is connected to a primary winding of a transformer at a primary side of the transformer. A digital control circuit including a switching controller arranged to output control pulses to the switching circuit and a rectifying/smoothing circuit connected to secondary windings of the transformer are disposed at a secondary side of the transformer. The digital control circuit outputs the control pulses via a pulse transformer, calculates the input power-supply voltage on the basis of the on-duty cycle of the control pulses, the output voltage, and the ratio of the number of turns of the primary winding to the number of turns of the secondary windings of the transformer, and performs converter control in accordance with the calculated input power-supply voltage. | 2010-04-29 |
20100103704 | CONTROL DEVICE FOR RECTIFIERS OF SWITCHING CONVERTERS - A control device for a rectifier of a switching converter, the converter powered by an input voltage and suitable for providing an output current. The rectifier is suitable for rectifying an output current of the converter and includes at least one transistor. The control device is suitable for driving the at least one transistor. The control device has a first circuit suitable for identifying the start and the end of every converter switching half-cycle and measuring the duration thereof, a second circuit suitable for generating a signal for turning on the transistor after a given number of measured converter switching half-cycles and when the output current of the converter becomes greater than a reference current. | 2010-04-29 |
20100103705 | SHORT CIRCUIT PROTECTION CIRCUIT FOR A PULSE WIDTH MODULATION (PWM) UNIT - A short circuit protection circuit for a pulse width modulation (PWM) unit which includes a PWM logic control circuit, an under voltage lookout (UVLO) circuit and an internal clock circuit; wherein the UVLO circuit detecting a bias power (Vcc) and delivering an UVLO signal when the bias power is judged excessively low, the PWM unit further comprising: a short circuit detector, a short circuit recovery circuit and a frequency multiplexer. The short circuit detector is to detect the UVLO signal and generate a short signal. The short circuit recovery circuit to set a pre-determined recovery time and generate a recovery signal when the pre-determined recovery time ends. The frequency multiplexer which is triggered by the short signal when the short circuit event occurs to change a switching frequency to a short PWM frequency, and triggered by the recovery signal to restore the switching frequency. | 2010-04-29 |
20100103706 | SNUBBER CIRCUIT - A circuit arrangement for limiting excessive voltages by a forward delay time of a first diode is described. The first diode is alternately switched in a non-conducting direction and a conducting direction by switching a circuit element. The first diode is series-connected to a first capacitor and a pre-charging circuit is provided for the first capacitor, the pre-charging circuit charging the first capacitor while the first diode is switched in the non-conducting direction. The pre-charging circuit charges the first capacitor more strongly than an excessive voltage of the first diode with regard to the amount. | 2010-04-29 |
20100103707 | Contactless Interface - Power extracted from an antenna inductively coupled to an alternating magnetic field is regulated to provide voltage supplies. In some implementations, a first voltage supply (e.g., 3.8 volts) provides regulated voltage to analog circuits and a second, lower, voltage supply (e.g., 1.4 volts) provides regulated voltage to digital circuits. The first voltage supply is regulated, using shunt regulation, by a first voltage regulator circuit. The second voltage supply is regulated, using a series regulation, by a second voltage regulator circuit. The second voltage regulator circuit is supplied by the shunted current from the first voltage regulator. Excess shunt current provided by the first regulator circuit can be bypassed (e.g., bypassed to ground). The second voltage regulator circuit can use a timer circuit to control the amount of charge transferred to a second voltage supply rail. The timer circuit can compensate for different currents from the first voltage regulator circuit. | 2010-04-29 |
20100103708 | POWER SUPPLY SAVING SYSTEM FOR AN ELECTRONIC DEVICE - A power supply saving system includes a power input interface, a power output interface, an alternating current/direct current (AC/DC) converter, a relay, a relay driving circuit, a trigger, and a timing sequence circuit. The AC/DC converter is capable of transforming the AC power signal to direct current (DC) power to supply to the relay, the relay driving circuit, the trigger, and the timing sequence circuit. The timing sequence circuit is capable of controlling the relay driving circuit via the trigger to turn on the relay to connect the power input interface to the power output interface when the timing sequence circuit receives a power-on signal. The timing sequence circuit is capable of controlling the relay driving circuit via the trigger to turn off the relay to cut off connection between the power input interface and the power output interface when the timing sequence circuit receives a power-off signal. | 2010-04-29 |
20100103709 | SYSTEM AND METHOD FOR EMULATING AN IDEAL DIODE IN A POWER CONTROL DEVICE - A system and method for emulating an ideal diode for use in a power control device is provided. In one embodiment, the invention relates to a circuit for emulating an ideal diode, the circuit including at least one field effect transistor including a source, a drain, a gate, and a body diode, an input; an output coupled to the drain, a control circuit including a current sensor coupled between the input and the source, and a control circuit output coupled to the gate, wherein the control circuit is configured to activate the at least one field effect transistor based on whether the current flowing into the source is greater than a predetermined threshold, and wherein the body diode comprises an anode coupled to the source and a cathode coupled to the drain. | 2010-04-29 |
20100103710 | LLC CONVERTER SYNCHRONOUS FET CONTROLLER AND METHOD OF OPERATION THEREOF - A method for operating a power controller is provided. The method includes activating a rectifying FET upon a detection of an activation body diode conduction current occurring in the rectifying FET. The method generates an activation signal for a corresponding primary FET. The method further includes deactivating the corresponding rectifying FET upon a reception of a deactivation signal. The method further includes then deactivating the corresponding primary FET after delaying the deactivation signal, wherein the delay lessens a conduction time of a deactivation body current of the corresponding rectifying FET. The method further includes generating a deactivation signal and deactivating the corresponding rectifying FET upon a reception of the deactivation signal and deactivating the primary FET after delaying the deactivation signal. The delaying lessens a conduction time of a deactivation body current of the corresponding rectifying FET. | 2010-04-29 |
20100103711 | Uninterruptible power supply and method for tripping thereof - Performance failure in an uninterruptible power supply (UPS) is determined independently by itself. A selective tripping can be done within a shorter time than one cycle of an AC output. A UPS converts a DC voltage to an AC voltage and supplies the AC voltage to a load device. A UPS has a control unit conducting a failure determination by using an instantaneous value of an internal voltage and current. It is preferred that a UPS includes an inverter unit and a trip switch. The inverter unit includes a semiconductor bridge circuit generating a sinusoidal AC voltage by modulating a DC voltage with voltage instruction values, and a filter circuit inserted between the semiconductor bridge circuit and the load device. The trip switch connects and trips a connection between the inverter unit and the load device according to the failure determination of the control unit. | 2010-04-29 |
20100103712 | MEMORY TEST DEVICE AND METHODS THEREOF - In accordance with a specific embodiment of the present disclosure, a content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory locations of the CAM. In a test mode of operation, a plurality of test signals are applied to the CAM, and the CAM provides a match value in response to assertion of one of the test signals. The match value is applied to a functional module associated with the CAM to determine a test result. Accordingly, the test signals applied to the CAM provide a flexible way to generate match values and apply those values to the functional module during testing of the data processing device. | 2010-04-29 |
20100103713 | ADJUSTABLE WIDTH STROBE INTERFACE - A memory system comprises a circuit board | 2010-04-29 |
20100103714 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit. | 2010-04-29 |
20100103715 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between a pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays. The reference potential correction capacitor shifts the reference potential by changing the amount of accumulated electric charges according to the correction signal. | 2010-04-29 |
20100103716 | Non-Volatile Memory with Metal-Polymer Bi-Layer - A resistive memory cell that includes a metal-polymer bi-layer proximate a CMOS gate. The memory cell has a substrate having a source contact connected to a source line and a drain contact connected to a drain line, a CMOS gate proximate the substrate electrically connecting the source contact and the drain contact, the bi-layer adjacent the CMOS gate, the bi-layer comprising a thin metal layer and a polymer layer, and a word line connected to the bi-layer. | 2010-04-29 |
20100103717 | TUNING A VARIABLE RESISTANCE OF A RESISTIVE SENSE ELEMENT - Method and apparatus for tuning a variable resistance resistive sense element of an electronic device. In some embodiments, a value indicative of a selected number of consecutive pulses is stored in a memory location and a resistive sense element (RSE) is set to a baseline RSE resistance. A tuning operation is performed by applying the selected number of consecutive pulses to the RSE to tune the baseline RSE resistance to a final adjusted resistance. | 2010-04-29 |
20100103718 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET. | 2010-04-29 |
20100103719 | Two-Stage 8T SRAM Cell Design - An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node. | 2010-04-29 |
20100103720 | BIOSENSOR AND SENSING CELL ARRAY USING THE SAME - A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline). Ingredients of adjacent materials are separated based on electrical characteristics of ingredients by sensing magnetic susceptibility and dielectric constant depending on the sizes of the ingredients. | 2010-04-29 |
20100103721 | Heater and memory cell, memory device and recording head including the heater - A heater includes at least two leads, and a heating element which is formed between the at least two leads, a material of the heating element being different from a material of the at least two leads such that a location of a hot spot in the heater is controllable based on a polarity of current in the heater. | 2010-04-29 |
20100103722 | METHOD OF PROGRAMMING RESISTIVITY CHANGING MEMORY - A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value. | 2010-04-29 |
20100103723 | NONVOLATILE MEMORY APPARATUS - Provided are a plurality of memory cell arrays | 2010-04-29 |
20100103724 | Variable Resistance memory device - The variable resistance memory device may include a memory cell array including a plurality of memory blocks, a bit line selection circuit including a plurality of bit lines connected to the plurality of memory blocks, at least one readout Y-pass driver configured to control a connection of the bit line selection circuit when a readout operation is performed, and a write Y-pass driver configured to control a connection of the bit line selection circuit when a write operation is performed. The write Y-pass driver is configured to control at least two of the plurality of bit lines connections. | 2010-04-29 |
20100103725 | Resistance Variable Memory Device for Protecting Coupling Noise - The present invention relates to a resistance variable memory device, and more particularly, to a resistance variable memory device capable of preventing an effect of coupling noise. The resistance variable memory device includes: a memory cell connected to a bit line; a precharge circuit precharging the bit line in response to a precharge signal; a bias circuit providing a bias voltage to the bit line in response to,a bias signal; and a control logic controlling the precharge signal and the bias signal. The control logic provides the bias signal to the bias circuit at a precharge interval. Accordingly, the resistance variable memory device according to the present invention can prevent an effect coupling noise. | 2010-04-29 |
20100103726 | PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS - A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells. | 2010-04-29 |
20100103727 | ST-RAM EMPLOYING A MAGNETIC RESONANT TUNNELING DIODE AS A SPACER LAYER - A memory cell that includes a first magnetic layer, the magnetization of which is free to rotate under the influence of spin torque; a tunneling layer comprising a magnetic resonant tunneling diode (MRTD); and a second magnetic layer, wherein the magnetization of the second magnetic layer is pinned, wherein the tunneling layer is between the first magnetic layer and the second magnetic layer. | 2010-04-29 |
20100103728 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the free magnetic layer the forming a magnetic field modified magnetic tunnel junction data cell, the magnetic field rotates the magnetization orientation of the free magnetic layer without switching a resistance state of the magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a destabilizing magnetic field to the MTJ and then writing the desired resistance state are also disclosed. | 2010-04-29 |
20100103729 | SPIN-TRANSFER TORQUE MEMORY SELF-REFERENCE READ AND WRITE ASSIST METHODS - A spin-transfer torque memory apparatus and self-reference read and write assist schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage. A magnetic field is applied through the magnetic tunnel junction data cell forming a magnetic field modified magnetic tunnel junction data cell. Then a second read current is applied thorough the magnetic field modified magnetic tunnel junction data cell forming a second bit line read voltage and the bit line read voltage is stored and compared with the first bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state. Methods of applying a magnetic field to the MTJ and then writing the desired resistance state are also disclosed. | 2010-04-29 |
20100103730 | MAGNETIC MEMORY CELL - The present invention relates to a magnetic memory cell, which controls the magnetization direction of the free magnetic layer of a Magnetic Tunnel Junction (MTJ) device using a spin torque transfer, and enables the implementation of a magnetic logic circuit, in which memory and logic circuit functions are integrated. The magnetic memory cell includes an MTJ device ( | 2010-04-29 |
20100103731 | METHOD ANALYZING THRESHOLD VOLTAGE DISTRIBUTION IN NONVOLATILE MEMORY - A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by reading data stored in the memory cells and determining read index data from the read data, and estimating a distribution characteristic for at least one of the overlapping threshold voltage distributions using the read index data. | 2010-04-29 |
20100103732 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 2010-04-29 |
20100103733 | PROGRAMMING NON-VOLATILE MEMORY WITH VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of the non-volatile storage elements to a set of target conditions using programming pulses. For at least a subset of the programming processes, a programming pulse associated with achieving an intermediate result for a respective programming process is identified, a pulse increment between programming pulses is decreased for the respective programming process while continuing the respective programming process to program non-volatile storage elements to the respective one or more targets and the identified programming pulse is used to adjust a starting programming voltage for a subsequent programming process. | 2010-04-29 |
20100103734 | PROGRAMMING NON-VOLATILE MEMORY WITH HIGH RESOLUTION VARIABLE INITIAL PROGRAMMING PULSE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results. | 2010-04-29 |
20100103735 | MEMORY DEVICE AND PROGRAM METHOD THEREOF - Provided are a flash memory system and a driving method thereof. A flash memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, and a control logic. The control logic performs control for one-bit information to be stored in the plurality of memory cells. The control logic controls storing data in the plurality of memory cells multiple times without an erasion operation. Accordingly, the flash memory device does not execute an erasion operation, increasing an operation speed. | 2010-04-29 |
20100103736 | NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE - A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line. | 2010-04-29 |
20100103737 | Read Compensation Circuits and Apparatus Using Same - A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells. | 2010-04-29 |
20100103738 | MEMORY AND OPERATING METHOD THEREOF - A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined whether there is an empty manufacture-defined block among a number of user-defined blocks in the memory. If so, an information block in the memory is programmed to store the programming address and a replacing address pointing to the empty manufacture-defined block. The empty manufacture-defined block is programmed to store the programming data. | 2010-04-29 |
20100103739 | MEMORY CONFIGURATION OF A COMPOSITE MEMORY DEVICE - The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access. | 2010-04-29 |
20100103740 | Nonvolatile Memory Device, Methods of Programming the Nonvolatile Memory Device and Memory System Including the Same - A nonvolatile memory device is provided. A counter counts an amount of data to be program-inhibited among data to be written to memory cells to provide a first count value. The counter also counts an amount of program-inhibited data among data written to the memory cells to provide a second count value. Control logic controls a program operation by comparing the first count value with the second count value. | 2010-04-29 |
20100103741 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells. | 2010-04-29 |
20100103742 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM - A method of operating a nonvolatile memory device includes; performing a verification operation on memory cells while controlling a verification voltage until the memory cells are verification-passed, controlling a level of a bias voltage to be applied to the memory cells according to a level of the verification voltage when the memory cells are verification-passed, and applying the bias voltage to the memory cells. | 2010-04-29 |
20100103743 | Flash memory device and method of testing the flash memory device - A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state. | 2010-04-29 |
20100103744 | Non-volatile memory device and method of driving the same - A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors. | 2010-04-29 |
20100103745 | Nand Flash Memory With a Programming Voltage Held Dynamically in a Nand Chain Channel Region - Operating voltages to a group of memory cells in an array are supplied via access lines such as word lines and bit lines. The capacitance of associated nodes of the memory cells can latch some of these voltages. Memory operation can continue using the latched voltages even when the access lines are disconnected. In a memory have an array of NAND chains, the capacitance of the channel of each NAND chain can latch a voltage to either enable or inhibit programming. The bit lines can then be disconnected during programming of the group and be used for another memory operation. In one embodiment, the bit lines are precharged for the next verifying step of the same group. In another embodiment, two groups of memory cells are being programmed contemporarily, so that while one group is being programmed, the other group can be verified with the use of the bit lines. | 2010-04-29 |
20100103746 | MULTI-PHASE DUTY-CYCLE CORRECTED CLOCK SIGNAL GENERATOR AND MEMORY HAVING SAME - Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such clock signal generator includes a delay-locked loop having a first multi-tap adjustable delay line configured to delay a reference signal to provide a plurality of clock signals having different phases relative to the reference clock signal. A periodic signal generated by the delay-locked loop is provided to a second multi-tap adjustable delay line as an input clock signal. Clock signals from taps of the second multi-tap adjustable delay line are provided as the multi-phase duty cycle corrected clock signals. | 2010-04-29 |
20100103747 | Memory device and method of operating such a memory device - A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power. | 2010-04-29 |
20100103748 | CLOCK PATH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal. | 2010-04-29 |
20100103749 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell region including memory cells that store data. An input buffer is disposed on one side of the memory cell region. On the other hand, an output buffer is disposed on another side opposite to the input buffer in the memory cell region. | 2010-04-29 |
20100103750 | ANTIFUSE REPLACEMENT DETERMINATION CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY DEVICE - An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed; a comparison and determination circuit for comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and a determination part for determining, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination circuit, whether or not replacement of the bad memory cell has been performed normally by using the antifuse element. | 2010-04-29 |
20100103751 | CIRCUIT WITH A MEMORY ARRAY AND A REFERENCE LEVEL GENERATOR CIRCUIT - A circuit comprises an array of memory cells ( | 2010-04-29 |
20100103752 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR READING/WRITING DATA THEREOF - A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal | 2010-04-29 |
20100103753 | DATA DETECTING APPARATUS AND METHODS THEREOF - A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit. | 2010-04-29 |
20100103754 | CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY - A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency. | 2010-04-29 |
20100103755 | Read Assist for Memory Circuits - A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage. | 2010-04-29 |
20100103756 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode. | 2010-04-29 |
20100103757 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a reference potential. The second signal line is disposed in a first side of the first signal line. The second signal line is supplied with a second signal. The second signal is smaller in amplitude than the potential difference. The first shield line is disposed in a second side of the first signal line. The second side is opposite to the first side. The first shield line reduces a coupling noise that is applied to the first shield line from the second side. | 2010-04-29 |
20100103758 | Semiconductor memory device having sense amplifier - To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance arranged between the first power supply wiring and the third power supply wiring. With this configuration, a capacitance value applied to the lower-side write potential and a capacitance value applied to the overdrive potential inevitably match, and thus fluctuation of the lower-side write potential and fluctuation of the overdrive potential at an initial stage of a sense operation are offset. | 2010-04-29 |
20100103759 | POWER LINE DECODING METHOD FOR AN MEMORY ARRAY - A method for selectively providing power supply voltage to a memory device. The method provides an integrated circuit memory device including a first plurality of memory cells. Each memory cell includes a power terminal and a ground terminal. The method includes selecting a second plurality of memory cells from the first plurality of memory cells. The method provides a first power voltage to the power terminal of each of the selected memory cells and a second power voltage to the power terminal of each of the unselected memory cells. The second power voltage is lower than the first power voltage. In an embodiment, the method applies a first ground voltage to the ground terminal of each of the selected memory cells and applies a second ground voltage to the ground terminal of each of the unselected memory cells. The second ground voltage is higher than the first ground voltage. | 2010-04-29 |
20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 2010-04-29 |
20100103761 | MEMORY DEVICES HAVING REDUNDANT ARRAYS FOR REPAIR - Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes a first number of columns of memory cells, and one or more global input/output (I/O) lines shared by the first number of columns for data transmission. The memory device also includes one or more multiplexers/demultiplexers, wherein each of the multiplexers/demultiplexers is electrically coupled to one or more, but not all, of the global I/O lines. The memory device further includes a plurality of local I/O lines, each configured to provide a data path between one of the multiplexers/demultiplexers and one or more, but less than the first number, of the columns in the sub-array. This configuration allows local I/O line repairability with fewer redundant elements, and shorter physical local I/O lines, which translate to improved speed and die size reduction. | 2010-04-29 |
20100103762 | Memory device and method - A memory device and method may include separating alternating read and write accesses to different banks of a memory device. | 2010-04-29 |
20100103763 | METHOD AND APPARATUS TO REPRODUCE PRODUCST MADE OF COMPOSITE MATERIAL HAVING SOLID PARTICLES EMBEDDED IN A POLYMERIC MATRIX AND METHOD AND DEVICE FOR DISPERSING SOLIDE PARTICLES INTO A VISCOUS LIQUID - A method to produce products made of composite material having solid particles embedded in a polymeric matrix provides for conveying a viscous liquid suitable to define the polymeric matrix along a first path; conveying agglomerates of elementary solid particles along a second path; combining the agglomerates with the viscous liquid; infiltrating the viscous liquid into the elementary solid particles along a third path by an infiltrating device; and dispersing the elementary solid particles into the viscous liquid along the third path by a dispersing device arranged downstream of the infiltrating device. | 2010-04-29 |
20100103764 | WORKING TROUGH AND METHOD FOR MAINTAINING UNIFORM TEMPERATURE OF WORKING FLUID - The invention provides a working trough and a method for maintaining a uniform temperature of a working fluid. The working trough is applied to an electrical discharge machine that performs wire cutting using the working fluid. The method for maintaining a uniform temperature of the working fluid is applied to the working trough and characterized by forming opening structures in a receiving slot of the working trough such that a spiral swirl having a predetermined height is allowed to be formed in the working fluid, thereby maintaining a uniform temperature of the working fluid in the receiving slot when a wire cutting process is performed in the working fluid by the electrical discharge machine. The disturbance of the spiral swirl also facilitates the discharge of scraps. The present invention further has an advantage of low cost. | 2010-04-29 |
20100103765 | LIQUID INJECTOR FOR SILICON PRODUCTION - The present invention relates generally to a liquid injector for silicon production. In one embodiment, the injector includes a tube having at least one opening at a first end of said tube, a moveable sealing means disposed inside the tube for sealing the at least one opening and a heating means coupled to the tube for controlling a temperature of a liquid exiting the tube through the at least one opening. | 2010-04-29 |
20100103766 | LOW-PRESSURE -DROP MIXING DEVICE AND USE THEREOF IN THE MIXING OF TWO GASES/VAPOURS - Mixing device for two gases/vapours (hereinafter gases) comprising: a) a plurality of tubes arranged in a bundle ( | 2010-04-29 |
20100103767 | Inner-Circulation Emulsifying and Dispersing Arrangement - An emulsifying and dispersing arrangement is provided, in which a handled material undergoes multi-time handling and a dispersion process, for achieving dispersion characteristics exhibiting uniformity of particle size. In addition, the temperature generated in the arrangement is controllable. | 2010-04-29 |
20100103768 | CAVITATION GENERATOR - A method and device are provided for mixing and manipulating fluids that comprises feeding fluid in a multi-stage flow-through hydrodynamic cavitation system, subjecting said fluid to a controlled multi-stage cavitation and continuing the treatment for a period of time sufficient for obtaining desirable changes in physical and/or chemical properties and generating upgraded products. | 2010-04-29 |
20100103769 | MIXER FOR A CONTINOUS FLOW REACTOR, CONTINUOS FLOW REACTOR, MEHTOD OF FORMING SUCH A MIXER, AND METHOD OF OPERATING SUCH A REACTOR | 2010-04-29 |
20100103770 | Rotational Motion Compensated Seabed Seismic Sensors and Methods of use in Seabed Seismic Data Acquisition - Apparatus and methods for acquiring seismic data using a seabed seismic data cable positioned on a seabed are described, including correcting for the effect of one or more sensor non-linear motions, which improves accuracy of seismic data. One or multiple non-linear movements of the sensor may be corrected for. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2010-04-29 |
20100103771 | PROVIDING A SURVEY CARRIER STRUCTURE HAVING EQUIDISTANT SURVEY SENSORS - A marine survey carrier structure includes sensor assemblies each containing a corresponding set of survey sensors, and an equipment assembly in-line with two of the sensor assemblies. The equipment assembly contains at least one survey sensor to enable the survey sensors along a length of the marine survey carrier structure to be regularly spaced. | 2010-04-29 |
20100103772 | Marine Seismic Acquisition - A method of conducting multiple source, multiple signal seismic surveys in a marine environment are provided. | 2010-04-29 |
20100103773 | Simultaneous Multiple Source Extended Inversion - Methods for improving the range and resolution of simultaneous multiple vibratory source seismic system including ZENSEIS™ are provided. | 2010-04-29 |
20100103774 | VSP IMAGING OF ACOUSTIC INTERFACES - A method to generate images of acoustic contrasts for structures located between at least one acoustic source and at least one receiver, said structures converting a part of the compressional energy to shear. | 2010-04-29 |
20100103775 | SONAR IMAGING SYSTEM FOR MOUNTING TO WATERCRAFT - A system for use with a boat to provide underwater sonar images includes a GPS receiver for providing GPS position data, a left side scan sonar transducer for transmitting left side scan sonar pulses and for receiving left side scan sonar return signals, and a right side scan sonar transducer for transmitting right side scan sonar pulses and for receiving right side scan sonar return signals. The system further includes signal processing circuitry for processing the left and right side scan sonar return signals to produce side scan image data and a digital processor for causing a display to display an underwater image based upon the side scan image data, wherein the digital processor associates GPS position and side scan image data. | 2010-04-29 |
20100103776 | AUDIO SOURCE PROXIMITY ESTIMATION USING SENSOR ARRAY FOR NOISE REDUCTION - Estimating the proximity of an audio source is accomplished by transforming audio signals from a plurality of sensors to frequency domain. The amplitudes of the transformed audio signals are then determined. The proximity of the audio source is determined based on a comparison of the frequency domain amplitudes. This estimation permits a device to differentiate between relatively distant audio sources and audio sources at close proximity to the device. The technique can be applied to mobile handsets, such as cellular phones or PDAs, hands-free headsets, and other audio input devices. Devices taking advantage of this “close proximity” detection are better able to suppress background noise and deliver an improved user experience. | 2010-04-29 |
20100103777 | SEISMOGRAPH SYSTEM - A seismograph system includes a seismometer, a positioning unit, a transmitter, a remote processing device. The seismometer includes a micro electromechanical system (MEMS) accelerometer and a MEMS gyroscope. The seismometer, the positioning unit, and the transmitter being located at a detecting site. The MEMS accelerometer and the MEMS gyroscope are respectively configured for measuring an acceleration and an angular velocity of the movement of the earth at the detecting site. The positioning unit is configured for providing a location at the detecting site. The transmitter is configured for transmitting the measured acceleration, the measured angular velocity, and the provided location to the remote processing device. The remote processing device is positioned at a remote site and configured for analyzing recording the measured acceleration, the measured angular velocity, and the provided location. | 2010-04-29 |
20100103778 | Sensory signal output apparatus - The present invention provides a sensory signal output apparatus, which is constructed such that several frequencies of output can be realized. The sensory signal output apparatus includes a coil ( | 2010-04-29 |
20100103779 | EVENT-BASED REMINDER SYSTEM - An Event-Based Reminder System that can be used for setting prompts to become active at instances specific to the device into which it is installed. More particularly, it pertains to handheld and communication devices for example contemporary mobile phones, wherein there is a need for a reminder system that goes beyond the calendar based ones and removes the rigidity of associating a time and date for each required event | 2010-04-29 |
20100103780 | DEVICE THAT ASSISTS IN MAINTAINING THE POSITION OF A DATE INDICATOR DISC FOR A TIMEPIECE - Device that assists in maintaining the position of a date indicator disc ( | 2010-04-29 |
20100103781 | TIME SYNCHRONIZATION IN CLUSTER SYSTEMS - Techniques are described herein for synchronizing cluster time. According to one technique, a master node is appointed in a cluster. Other “slave” nodes periodically synchronize their clocks with the master node. To synchronize its clock with the master node, a slave node sends a timestamped message to the master node, which also timestamps the message and sends the message back to the slave node, which then timestamps the message again. Based on the timestamps, the slave node is able to determine the difference between the master node's clock's time and slave node's clock's time, compensating for the message travel time between master node and slave node. Depending on various circumstances, and based on the determined difference, the slave node adjusts its clock so that the time indicated by the slave node's clock at least begins to approach more closely the time indicated by the master node's clock. | 2010-04-29 |
20100103782 | TIMEPIECE MOVEMENT WITH A KARUSSEL - The timepiece movement ( | 2010-04-29 |
20100103783 | THERMALLY ASSISTED MAGNETIC HEAD - A magnetic write head arranged to maximize efficiency of an optical device used to locally heat a magnetic medium during use, also to maximize efficiency of a heater element for thermal fly height control. The magnetic head is constructed with a read head, a write head and a slider body. The write head is located between the read head and the slider body. A heater element can be located between the read head and the write head and an optical device such as an optical waveguide can be located between the write head and the slider body. The write head can be constructed to have a write pole that is closer to the slider body than the return pole is, thereby allowing the write pole to be adjacent to the optical device. | 2010-04-29 |
20100103784 | OPTICAL DISC APPARATUS - An optical disc apparatus reliably executes a seek operation even if an optical disc is warped. Tilt adjustment values spanning from the inner circumference to the outer circumference of an optical disc are stored. When seeking from a start address to a destination address, a tilt adjustment value A at the start address and a tilt adjustment address C at the destination address are not directly used. A tilt adjustment value k·C (k<1) is used during a coarse seek operation until the neighborhood of the destination address and a tilt adjustment value C is used during a fine seek operation from the neighborhood of the destination address to the destination address. | 2010-04-29 |
20100103785 | TABLE-DRIVEN POWER UTILIZATION METRICS - An apparatus and method for determining the power consumption of one or more disk arrays are described. Power consumption information for various hardware components of the array, especially that for the disk drives since these consume more than 90% of the required power, are stored in a static data table in a database which may be controller firmware. Through inspection of this table and the chosen state of the individual disk drives as directed by a controller, one may determine the power use of the array. | 2010-04-29 |
20100103786 | POWER CALIBRATION IN OPTICAL DISC DRIVES - A method comprising performing a first set of power calibration procedures on an optical record carrier at a first recording speed in a first set of calibration areas and performing a further set of power calibration procedures on the optical record carrier at a recording speed different from the first recording speed, wherein the further set of power calibration procedures partly uses information from the first set of calibration areas is disclosed. The technique is useful in scenarios where the recording is required to be done with more than one speed on the same optical record carrier. The technique reduces the overall power calibration time and increases the number of power calibrations that can be done on the optical record carrier. The technique is useful for data, audio and video recorders. | 2010-04-29 |
20100103787 | MULTI-LAYERED INFORMATION RECORDING MEDIUM, RECORDING APPARATUS, AND RECORDING METHOD - A multi-layered information recording medium including a plurality of recording layers, the multi-layered information recording medium comprising: a user data area for recording user data; and a plurality of spare areas including at least one replacement region, wherein when the user data area includes at least one defect region, the at least one replacement region may be used in place of the at least one defect region, wherein a first spare area of the plurality of spare areas is positioned so as to be contiguous to a first user data area of a first recording layer, a second spare area of the plurality of spare areas is positioned so as to be contiguous to a second user data area of a second recording layer, and the first spare area and the second spare area are positioned approximately at the same radial position on the multi-layered information recording medium. | 2010-04-29 |
20100103788 | OPTICAL DISC, OPTICAL DISC RECORDING METHOD AND APPARATUS, AND OPTICAL DISC REPRODUCING METHOD AND APPARATUS - As a synchronization signal pattern to be added, a pattern is generated (second SYNC pattern), which has a pattern that breaks a maximum run inserted in a pattern excluding a minimum run is used so that intersymbol interference does not occur readily on a high-density disc, and addition processing of a conventional synchronization signal pattern (first SYNC pattern) is switched according to identification information indicating whether or not a high-density disc for generation. | 2010-04-29 |
20100103789 | REPRODUCING SYSTEM AND CORRESPONDING INFORMATION RECORDING MEDIUM HAVING WOBBLED LAND PORTIONS - An information recording medium is at least composed of a substrate having a microscopic pattern constituted by a continuous substrate of grooves formed with a groove portion and a land portion alternately, a recording layer formed on the microscopic pattern for recording information, and a light transmitting layer formed on the recording layer. The microscopic pattern is formed with satisfying a relation of P≦λ/NA, wherein P is a pitch of the land portion or the groove portion, λ is a wavelength of reproducing light for reproducing the recording layer, and NA is a numerical aperture of an objective lens. The land portion is formed with wobbling so as to be parallel with each other for both sidewalls of the land portion. An auxiliary information based on data used supplementally when recording the information and a reference clock based on a clock used for controlling a recording speed when recording the information is recorded alternately. Information is recorded in the recording layer corresponding to only a land portion by at least either one change of reflectivity difference and refractive index difference in the recording layer so as to be more than 5% for reflectivity and so as to be more than 0.4 for modulated amplitude of signal recording. | 2010-04-29 |
20100103790 | DISK RECORDING MEDIUM, DISK PRODUCTION METHOD, DISK DRIVE APPARATUS - A disk recording medium which can implement a recording method having a high degree of reliability for additional information is disclosed. The disk recording medium has a recording and reproduction region into and from which first data can be recorded and reproduced in accordance with a rewritable or write-once-read-many recording method and from which second data recorded in the form of wobbling of a groove can be reproduced. The second data includes address information and additional information. The additional information of the second data is coded in accordance with a first error correction method, and the coded additional information and the address information are recorded in a state coded in accordance with a second error correction method. | 2010-04-29 |
20100103791 | INFORMATION READOUT APPARATUS - An offset corrector of an information readout apparatus receives a digital signal DRF output from an A/D converter, and performs offset correction. The offset corrector is capable of switching between a level-correction operation that corrects the offset so that the DC level of the shortest period signal included in the readout signal assumes a zero amplitude reference and a HPF operation that matches the level of the readout signal with the zero amplitude reference. The offset corrector corrects the offset in the level correction operation during a normal reproduction, and switches to the HPF operation for offset correction when a defect judgment unit detects a defective area. The information readout apparatus is stable and has a superior performance without a symmetry deviation if there occurs a waveform fluctuation caused by a defect etc. | 2010-04-29 |
20100103792 | OPTICAL DISK DEVICE - Provided is an optical disk device, including a top case and a bottom case which constitute a housing having a substantially box shape in which: the top case includes, on one side thereof, a hook which engages with the bottom case; the bottom case includes an engaging portion which is provided with a cutout which engages with the hook; and a shielding portion for preventing an air flow passing through the cutout is provided in an inside of the cutout. | 2010-04-29 |
20100103793 | MULTILAYER OPTICAL INFORMATION RECORDING MEDIUM, METHOD FOR RECORDING INFORMATION IN THE MULTILAYER OPTICAL INFORMATION RECORDING MEDIUM, RECORDING/REPRODUCING APPARATUS - The present invention provides a novel physical structure for a multilayer optical information recording medium including a plurality of information recording layers, and a recording method and a recording/reproduction apparatus for such a recording medium using the same. The multilayer optical information recording medium according to the present invention includes a test recording area for performing test recording for data recording and/or reproduction conditions in at least one of an inner zone and an outer zone. The test recording area is categorized as one of at least two categories of test recording areas (OPC-A area and OPC-B area). In the OPC-B area, an upper limit value is set on a recording power for the test recording. | 2010-04-29 |
20100103794 | SCANNING DEVICE HAVING A HOLDING FIXTURE FOR COOLING OF A PICKUP - The device comprises a scanning apparatus with a pickup for reading and/or recording data on a storage medium, a holding fixture for providing a parking position for the scanning apparatus, and a magnetic drive actuator for a movement of the scanning apparatus, wherein the holding fixture comprises a heat sink for cooling down the pickup. The scanning apparatus is in particular of a swing arm type and the pickup is an optical pickup comprising a laser diode. | 2010-04-29 |
20100103795 | DATA STORAGE MEDIA CONTAINING INORGANIC NANOMATERIAL DATA LAYER - Optical information media having a support substrate and an inorganic nanomaterial data layer are disclosed. The data layer provides enhanced stability and optical performance as compared to conventional data layers. | 2010-04-29 |
20100103796 | METHOD OF READING A FOURIER HOLOGRAM RECORDED ON A HOLOGRAPHIC STORAGE MEDIUM AND A HOLOGRAPHIC STORAGE SYSTEM - The invention relates to a method for reading a Fourier hologram recorded on a holographic storage medium with a holographic storage system. The method comprises the steps of: —calculating a characteristic value from a detected image of a reconstructed Fourier hologram in at least two relative positions of a reference beam and said storage medium, each of the characteristic values being indicative of a misalignment of the reference beam and said storage medium at the respective relative position, —calculating a servo value from the measured characteristic values, —determining an aligned relative position of said reference beam and said storage medium by means of a predetermined servo function using the calculated servo value, —setting the relative position of the reference beam and said storage medium to said aligned relative position, and —detecting an image at said aligned relative position. The invention also relates to a holographic storage system for reading a Fourier hologram recorded on a holographic storage medium, said system comprising reference beam generating means, storage medium receiving means and a detector for detecting a reconstructed hologram. The system further comprises a servo control unit for executing the method according to the invention. | 2010-04-29 |