18th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150115295 | Flip-Chip Light Emitting Diode and Fabrication Method - A flip-chip light emitting diode (LED) includes: a substrate having a P-type pad electrode and an N-type pad electrode; a light-emitting epitaxial layer flip-chip mounted over the substrate, including, from top down, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer is divided into a light-emitting region, an isolation region, and an electrode region. The light-emitting region and the electrode region are electrically isolated by the isolation region. The active layer and the p-type semiconductor layer are below the light-emitting region. The p-type semiconductor layer connects with the P-type pad electrode. The electrode region of the n-type semiconductor layer connects with the N-type pad electrode. A conductive connection portion on the n-type semiconductor layer connects the electrode region of the n-type semiconductor layer and the light-emitting region, realizing vertical current injection into the light-emitting epitaxial layer when an external power is connected. | 2015-04-30 |
20150115296 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - Discussed is a display device including a wiring substrate having a first substrate layer and a second substrate layer, a conductive adhesive layer configured to cover the wiring substrate, and a plurality of semiconductor light emitting devices coupled to the conductive adhesive layer, and electrically connected to a first electrode and a second electrode, wherein the first electrode is disposed at the first substrate layer, and the second substrate layer includes one surface facing the conductive adhesive layer and the other surface covering the first electrode, and an auxiliary electrode electrically connected to the first electrode and the second electrode are disposed on one surface of the second substrate layer. | 2015-04-30 |
20150115297 | DISPLAY DEVICE - A display device may include a display panel, a window substrate and a light shielding member. The display panel may include an active area in which pixels are disposed, and a non-active area at the periphery of the active area. The window substrate may be disposed above the display panel, and may include a frame pattern layer formed thereon. In the window substrate, the frame pattern layer may cover a portion including an outer edge in the non-active area. The light shielding member may include a light shielding sheet disposed below the display panel, and an adhesive layer disposed between the light shielding sheet and the display panel. In the display device, the adhesive layer includes an opening formed in at least one area between the frame pattern layer and the active area in an area corresponding to the non-active area. | 2015-04-30 |
20150115298 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, the fluorescer layer is provided on the first surface side. The fluorescer layer has a side surface provided at an obtuse angle with respect to the first surface. The fluorescer layer includes a plurality of fluorescers and a binder. The plurality of fluorescers is configured to be excited by light emitted from the light emitting layer to emit light of a wavelength different from a wavelength of the light emitted from the light emitting layer. The binder is configured to combine the plurality of fluorescers in a single body and transmit the light emitted from the light emitting layer and light emitted from the fluorescers. | 2015-04-30 |
20150115299 | III-NITRIDE LIGHT EMITTING DEVICE - A device includes a substrate ( | 2015-04-30 |
20150115300 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, the n-side electrode has a corner and a plurality of straight portions. The plurality of straight portions extends in different directions. The corner connects the plurality of straight portions. A first insulating film is provided between the semiconductor layer and the corner of the n-side electrode. The corner is not in contact with the semiconductor layer. The straight portions of the n-side electrode are in contact with the semiconductor layer. | 2015-04-30 |
20150115301 | ELECTRODE STRUCTURE AND LIGHT EMITTING DIODE STRUCTURE HAVING THE SAME - An electrode structure includes at least one reflection layer, a barrier layer, and a conductive pad. The barrier layer includes a first barrier layer and a second barrier layer. The first and second barrier layers are stacked on the reflection layer in sequence. The first and second barrier layers are made of different materials. The conductive pad is located on the barrier layer. | 2015-04-30 |
20150115302 | OPTOELECTRONIC DEVICES CONTAINING A CONVERTER CARRIER LAYER, AND METHODS OF PRODUCING AN OPTOELECTRONIC DEVICE CONTAINING A CONVERTER CARRIER LAYER - An optoelectronic device includes a layer sequence having an active layer that emits electromagnetic primary radiation, and at least one converter carrier layer arranged in the beam path of the electromagnetic primary radiation. The at least one converter carrier layer includes converter particles and an inorganic-organic hybrid material and/or a silicate glass. | 2015-04-30 |
20150115303 | LED Module with Circuit Board - The present invention relates to an LED module | 2015-04-30 |
20150115304 | Optoelectronic component and method for producing an optoelectronic component - An optoelectronic component may include a carrier element having a heat sink, at least one semiconductor chip for emitting electromagnetic radiation which is mounted and electrically contact-connected on the carrier element, a radiation-transmissive cover disposed downstream of the at least one semiconductor chip, a converter layer applied on the radiation-transmissive cover and spaced apart from the at least one semiconductor chip, a frame composed of thermally conductive material, which frame extends around the at least one semiconductor chip and is in direct contact with the converter layer, and at least one connecting element for thermally connecting the frame to the heat sink. | 2015-04-30 |
20150115305 | OPTOELECTRONIC COMPONENT - An optoelectronic component comprising a semiconductor body, a first connection layer, an insulation layer and a second connection layer, wherein the semiconductor body has an active region for generating electromagnetic radiation and the second connection layer comprises a first partial layer and a second partial layer is specified, wherein
| 2015-04-30 |
20150115306 | LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE INCLUDING A FLUORESCENT MATERIAL LAYER - A semiconductor light-emitting device includes a semiconductor light-emitting layer, a pair of electrodes, a fluorescent material layer and a chromaticity adjusting layer. The semiconductor light-emitting layer emits first light. The pair of electrodes is connected to the semiconductor light-emitting layer. The fluorescent material layer covers at least a center portion of the semiconductor light-emitting layer, and contains a fluorescent material to absorb the first light and radiate second light. The chromaticity adjusting layer covers at least a peripheral portion of the semiconductor light-emitting layer, is exposed to outside, and contains a fluorescent material with a concentration lower than a concentration of the fluorescent material in the fluorescent material layer. | 2015-04-30 |
20150115307 | SAPPHIRE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - [Technical Problem] | 2015-04-30 |
20150115308 | LIGHT-EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a light-emitting diode package, including: a carrier; a light-emitting diode chip disposed over the carrier and electrically connected to the carrier, wherein the light-emitting diode chip includes at least two recesses at corners located on a diagonal line of the light-emitting diode chip; a eutectic layer disposed between the light-emitting diode chip and the carrier, wherein the eutectic layer includes at least two metal pillars embedded into the at least two recesses respectively, wherein an upper portion of the metal pillars covers a portion of a top surface of the light-emitting diode chip. The present disclosure also provides a method for manufacturing a light-emitting diode package. | 2015-04-30 |
20150115309 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure includes a substrate, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a composite conductive layer, a first electrode, and a second electrode. The N-type semiconductor layer is located on the substrate. The light emitting layer is located on a portion of the N-type semiconductor layer. The P-type semiconductor layer is located on the light emitting layer. The composite conductive layer sequentially has a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is attached to the P-type semiconductor layer, and the resistance of the first conductive layer is greater than the resistance of the third conductive layer. The first electrode is located on the third conductive layer. The second electrode is located on another portion of the N-type semiconductor layer that is not covered by the light emitting layer. | 2015-04-30 |
20150115310 | ARRAY SUBSTRATE FOR MOUNTING CHIP AND METHOD FOR MANUFACTURING THE SAME - Provided is an array substrate for mounting a chip. The array substrate includes a plurality of conductive layers unidirectionally stacked with respect to an original chip substrate; a plurality of insulating layers alternately stacked with the plurality of conductive layers, and electrically separate the plurality of conductive layers; and a cavity having a groove of a predetermined depth with respect to a region including the plurality of insulating layers in an upper surface of the original chip substrate. Accordingly, since the optical device array of a single structure is used as a line source of light, an emission angle emitted from the optical device is great, it is not necessary to form an interval for supplying an amount of light, and a display device can be simply constructed. Further, since it is not necessary to perform soldering a plurality of LED packages on a printed circuit board, a thickness of a back light unit can be reduced. | 2015-04-30 |
20150115311 | Film-Like Thermosetting Silicone Sealing Material - The present invention relates to a film-like thermosetting silicone sealing material for sealing a semiconductor element by means of compression molding, the sealing material having an initial torque value of less than 15 dN·m as measured by an MDR (Moving Die Rheometer) at a molding temperature of from room temperature to 200° C., to a method for producing an LED by means of compression molding using the same, and to an LED produced by this method. The sealing material has excellent moldability, causes no problems such as overflow from a die, and has no defects such as voids. | 2015-04-30 |
20150115312 | GROUP III NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - In a group III nitride semiconductor device according to one aspect of the present invention, in a p-type group III nitride semiconductor region formed on a semi-polar plane substrate, the concentration of hydrogen (H) contained in the p-type group III nitride semiconductor region is 25% or less of the concentration of a p-type dopant therein, and the concentration of oxygen contained in the p-type group III nitride semiconductor region is 5×10 | 2015-04-30 |
20150115313 | Semiconductor Device Package - In an embodiment, a semiconductor device package includes a bidirectional switch circuit. The bidirectional switch circuit includes a first semiconductor transistor mounted on a first die pad, a second semiconductor transistor mounted on a second die pad, the second die pad being separate from the first die pad, and a conductive connector extending between a source electrode of the first transistor and a source electrode of the second transistor. | 2015-04-30 |
20150115314 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a semiconductor device, a trench includes a first trench that has an opening portion on a surface of a base layer, and a second trench that is communicated with the first trench and in which a distance between opposed side walls is greater than opposed side walls of the first trench and a bottom portion is located in a drift layer. A wall surface of a connecting portion of the second trench connecting to the first trench is rounded. Therefore, an occurrence of a large electrical field concentration in the vicinity of the connecting portion between the first trench and the second trench can be suppressed. Also, when electrons are supplied from a channel region to the drift layer, it is less likely that a flow direction of the electrons will be sharply changed in the vicinity of the connecting portion. Therefore, an on-state resistance can be reduced. | 2015-04-30 |
20150115315 | High Voltage Semiconductor Power Switching Device - A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET. | 2015-04-30 |
20150115316 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drift layer having a first conduction type; a base layer having a second conduction type and formed on the drift layer; an emitter layer having the first conduction type and formed in a surface layer portion of the base layer; a buffer layer having the first conduction type and formed in the drift layer separated from the base layer; a collector layer having the second conduction type and formed selectively in the buffer layer; a gate insulation film in contact with a channel region of the base layer between the drift layer and the emitter layer; a gate electrode formed on the gate insulation film; a first electrode electrically connected to the base layer and the emitter layer; and a second electrode electrically connected to the buffer layer and the collector layer. The buffer layer has a carrier density smaller than a space charge density. | 2015-04-30 |
20150115317 | PROTECTION DEVICES FOR PRECISION MIXED-SIGNAL ELECTRONIC CIRCUITS AND METHODS OF FORMING THE SAME - Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region. | 2015-04-30 |
20150115318 | SEMICONDUCTOR PHOTO-DETECTING DEVICE - An ultraviolet (UV) photo-detecting device, including: a first nitride layer; a secondary light absorption layer disposed on the first nitride layer; a primary light absorption layer disposed on the secondary light absorption layer; and a Schottky junction layer disposed on the primary light absorption layer. The secondary light absorption layer includes a nitride layer having lower band-gap energy than the primary light absorption layer. | 2015-04-30 |
20150115319 | PLANAR AVALANCHE PHOTODIODE - An avalanche photodiode includes a first semiconductor layer, a multiplication layer, a charge control layer, a second semiconductor layer, a graded absorption layer, a blocking layer and a second contact layer. The multiplication layer is located between the charge control layer and the first semiconductor layer. The charge control layer is located between the second semiconductor layer and the multiplication layer. The second semiconductor layer is located between the charge control later and the graded absorption layer. The graded absorption layer is located between the second semiconductor layer and the blocking layer. | 2015-04-30 |
20150115320 | Lattice-Mismatched Semiconductor Structures and Related Methods for Device Fabrication - Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures. | 2015-04-30 |
20150115321 | SUBSTRATE STRUCTURE, COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE - A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure. | 2015-04-30 |
20150115322 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 2015-04-30 |
20150115323 | SEMICONDUCTOR DEVICE - A semiconductor device including a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap wider than that of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer to reach the middle of the first nitride semiconductor layer, a conductive film formed at a corner portion corresponding to an end portion of a bottom surface of the trench and a gate electrode disposed via a gate insulating film inside the trench including a region on the conductive film. | 2015-04-30 |
20150115324 | Switching Circuit - In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and an overheating detection circuit for detecting overheating of the switching circuit. | 2015-04-30 |
20150115325 | Spacer Supported Lateral Channel FET - A semiconductor device includes a semiconductor material and trenches extending into the semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches. The device also includes a field plate in the trenches, a body region in the mesas, a source region in contact with the body region in the mesas, and a gate electrode on the first main surface of the semiconductor material and defining a lateral channel region in each of the body regions under the gate electrodes. A drain region is at the opposing main surface of the semiconductor material. The gate electrodes adjacent opposing sides of the same field plate have the same alignment with respect to that field plate. The device can be a MOSFET or HEMT. Corresponding methods of manufacture are also provided. | 2015-04-30 |
20150115326 | Electronic Device - In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile. | 2015-04-30 |
20150115327 | Group III-V Device Including a Buffer Termination Body - There are disclosed herein various implementations of a III-Nitride device and method for its fabrication. The III-Nitride device includes a III-Nitride buffer layer situated over a substrate, the III-Nitride buffer layer having a first bandgap. In addition, the device includes a III-Nitride heterostructure situated over the III-Nitride buffer layer and configured to produce a two-dimensional electron gas (2DEG); the III-Nitride heterostructure including a channel layer having a second bandgap smaller than the first bandgap. The III-Nitride device also includes a buffer termination body situated between the III-Nitride buffer layer and the channel layer, the buffer termination body including a III-Nitride material having a third bandgap smaller than the first bandgap and larger the second bandgap. | 2015-04-30 |
20150115328 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer. | 2015-04-30 |
20150115329 | Method and Apparatus for Repairing Monolithic Stacked Integrated Circuits - Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects. | 2015-04-30 |
20150115330 | IMAGE SENSOR USING BACKSIDE ILLUMINATION PHOTODIODE AND METHOD FOR MANUFACTURING THE SAME - A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers. | 2015-04-30 |
20150115331 | SENSOR USING SENSING MECHANISM HAVING COMBINED STATIC CHARGE AND FIELD EFFECT TRANSISTOR - The present invention relates to a sensor that uses a sensing mechanism having a combined static charge and a field effect transistor, the sensor including: a substrate; source and drain units formed on the substrate and separated from each other; a channel unit interposed between the source and drain units; a membrane separated from the channel unit, disposed on a top portion and displaced in response to an external signal; and a static charge member formed on a bottom surface of the membrane separately from the channel unit and generating an electric field. Accordingly, since the sensor using a sensing mechanism having a combined static charge and a field effect transistor according to an embodiment of the present invention can measure the displacement or movement of the sensor by measuring a change of the electric field of the channel unit of the field effect transistor by using a static member, the electric field can be formed so as to be proportional to an amount of charge and inversely proportional to a squared distance regardless of the intensity and distribution of an external electric field. Therefore, sensitivity is improved without being affected by an external electric field. | 2015-04-30 |
20150115332 | CMOS IMAGE SENSOR WITH GLOBAL SHUTTER, ROLLING SHUTTER, AND A VARIABLE CONVERSION GAIN, HAVING PIXELS EMPLOYING SEVERAL BCMD TRANSISTORS COUPLED TO A SINGLE PHOTODIODE AND DUAL GATE BCMD TRANSISTORS FOR CHARGE STORAGE AND SENSING - The invention describes image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for storing and sensing charge for a single photodiode. This configuration improves the Dynamic Range (DR) of the sensor, by allowing sensing different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. Signal processing circuits can process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed are pixels that use multiple-gate BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and, at the same time, low level signals with high conversion gain and low noise. | 2015-04-30 |
20150115333 | LATERAL SUPER JUNCTIONS WITH HIGH SUBSTRATE BREAKDOWN AND BUILD IN AVALANCHE CLAMP DIODE - This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance. | 2015-04-30 |
20150115334 | Gate Device Over Strained Fin Structure - A method for forming a semiconductor device includes forming a fin structure on a substrate, forming a shallow trench isolation region adjacent the fin structure so that an upper portion of the fin structure is exposed, forming a dummy gate over the exposed fin structure, forming an interlayer dielectric layer around the dummy gate, removing the dummy gate to expose the fin structure, and after removing the dummy gate, introducing a strain into a crystalline structure of the exposed fin structure. | 2015-04-30 |
20150115335 | MECHANISM FOR FORMING METAL GATE STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings. | 2015-04-30 |
20150115336 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC INSTRUMENT - Disclosed herein is a solid-state imaging device including, a first semiconductor region of the first conduction type, a photoelectric conversion part having a second semiconductor region of the second conduction type formed in the region separated by the isolation dielectric region of the first semiconductor region, pixel transistors formed in the first semiconductor region, a floating diffusion region of the second conduction type which is formed in the region separated by the isolation dielectric region of the first semiconductor region, and an electrode formed on the first semiconductor region existing between the floating diffusion region and the isolation dielectric region and is given a prescribed bias voltage. | 2015-04-30 |
20150115337 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate, an imaging pixel array disposed on a first region of the substrate, a first isolation disposed in the first region, a periphery circuitry disposed on a second region of the substrate, and a second isolation disposed in the second region. The imaging pixel array has a plurality of imaging pixels configured to capture image data. The periphery circuitry has a transistor configured to receive and process the image data. The first isolation has a first depth and a first protrusion projected from a surface of the substrate. The second isolation has a second depth and a second protrusion projected from the surface of the substrate. The first protrusion has a substantially same height as the second protrusion. The first depth is different from the second depth. | 2015-04-30 |
20150115338 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE - A solid-state imaging device according to an embodiment includes photoelectric conversion devices, a dopant layer, a low concentration region, and a transistor. The photoelectric conversion devices are disposed on a semiconductor layer. The dopant layer is disposed on a layer same as the semiconductor layer where photoelectric conversion devices are arrayed, and includes dopant having a conductivity type reverse to a charge accumulating region of the photoelectric conversion device. The low concentration region is disposed inside the dopant layer and has dopant concentration lower than the dopant layer. A transistor includes an active region disposed on the dopant layer. | 2015-04-30 |
20150115339 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line. | 2015-04-30 |
20150115340 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device includes plural photodiodes which are formed in a photodiode area of a unit pixel with no element separating area interposed therebetween and in which impurity concentrations of pn junction areas are different from each other. | 2015-04-30 |
20150115341 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of aMOS transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of aMOS transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion. | 2015-04-30 |
20150115342 | Semiconductor Device - Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other. | 2015-04-30 |
20150115343 | TRANSISTOR ARRANGEMENT - A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure. | 2015-04-30 |
20150115344 | THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A 3D stacked semiconductor structure is provided, comprising a plurality of stacks formed on a substrate; at least a contact hole formed vertically in one of the stacks; a conductor formed in the contact hole; and a charging trapping layer at least formed at sidewalls of the stacks. One of the stacks comprises a multi-layered pillar, including a plurality of insulating layers and a plurality of conductive layers arranged alternately, and a dielectric layer formed on the multi-layered pillar. The contact hole is formed vertically in one of the stacks, and the contact hole penetrates the dielectric layer, the insulating layers and the conductive layers of the corresponding stack. Also, a top surface of the conductor is higher than a top surface of the multi-layered pillar for the corresponding stack. | 2015-04-30 |
20150115345 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel, a conductive pattern, gate electrodes, a bit line and a conductive line. A plurality of the channels and the conductive patterns extend in a vertical direction from a top surface of a substrate. The gate electrodes surround outer sidewalls of the channels and the conductive patterns. The gate electrodes are stacked in the vertical direction to be spaced apart from each other. The bit line is electrically connected to the channels. The conductive line is electrically connected to the conductive patterns. | 2015-04-30 |
20150115346 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes a substrate, shallow trench isolations protruding from the substrate, a floating gate formed conformally on the surface of the recess between each shallow trench isolation, a tunnel layer formed between each floating gate and the substrate, a dielectric layer formed conformally on the floating gates, and a control gate formed on the dielectric layer. | 2015-04-30 |
20150115347 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer. | 2015-04-30 |
20150115348 | VERTICAL-TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer. | 2015-04-30 |
20150115349 | METHODS OF FABRICATING MEMORY DEVICES HAVING CHARGED SPECIES AND METHODS OF ADJUSTING FLATBAND VOLTAGE IN SUCH MEMORY DEVICES - Methods for fabricating memory devices having charged species, and methods for adjusting flatband voltages in such memory devices. In one such method, a dielectric material is formed adjacent to a semiconductor. A charged species is introduced into the dielectric material, wherein the charged species has an energy barrier in a range of greater than about 0.5 eV to about 3.0 eV. A control gate is formed adjacent to the dielectric material. A flatband voltage of the memory device can be adjusted by moving the charged species to different levels within the dielectric material, thus programming different states into the device. | 2015-04-30 |
20150115350 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks. | 2015-04-30 |
20150115351 | Integrated Circuit and Method of Manufacturing an Integrated Circuit - An integrated circuit includes a power component including a plurality of first trenches in a cell array and a first conductive material in the first trenches electrically coupled to a gate terminal of the power component, and a diode component including a first diode device trench and a second diode device trench disposed adjacent to each other. A second conductive material in the first and the second diode device trenches is electrically coupled to a source terminal of the diode component. The first trenches, the first diode device trench and the second diode device trench are disposed in a first main surface of a semiconductor substrate. The integrated circuit further includes a diode gate contact including a connection structure between the first and the second diode device trenches. The connection structure is in contact with the second conductive material in the first and the second diode device trenches. | 2015-04-30 |
20150115352 | SEMICONDUCTOR DEVICE - The present disclosure relates to a semiconductor device. Such a semiconductor device includes a trench metal-oxide-semiconductor (MOS) transistor having two or more electrodes in a trench formed on a substrate of the semiconductor, where a part of a shield electrode positioned at a bottom of the trench is formed to have a large thickness, and a groove is formed in a gate electrode that is stacked on the shield electrode, such that a part of the shield electrode protrudes to a surface of the semiconductor device so as to be connected with a source power. | 2015-04-30 |
20150115353 | FIELD EFFECT SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa. | 2015-04-30 |
20150115354 | Semiconductor Device - The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer. | 2015-04-30 |
20150115355 | SUPERJUNCTION DEVICE AND SEMICONDUCTOR STRUCTURE COMPRISING THE SAME - The present disclosure relates to a superjunction device and a semiconductor structure having the same. The superjunction device includes a body region of a second conduction type, a drain region of a first conduction type, a drift region located between said body region and said drain region. The drift region includes first regions of a first conduction type and second regions of a second conduction type arranged alternately along a direction being perpendicular to the direction from the body region to the drain region, and a plurality of trench gate structures, each of them comprising a trench extending into said drift region from an upper surface of said body region and a gate electrode in said trench surrounded by a first dielectric layer filling said trench, and a source region of a first conduction type embedded into said body region. There is no source region along at least 10% of the total interface length between the first dielectric layer and the body region. | 2015-04-30 |
20150115356 | Method for Manufacturing a Vertical Semiconductor Device and Vertical Semiconductor Device - Producing a vertical semiconductor device includes: providing a semiconductor wafer including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type forming a first pn-junction with the first layer, and a third semiconductor layer of the first conductivity type forming a second pn-junction with the second layer and extending to a main surface of the wafer; forming a hard mask on the main surface that includes hard mask portions spaced apart from each other by first openings; using the hard mask to etch deep trenches from the main surface into the first layer so that mesa regions covered at the main surface by respective hard mask portions are formed between adjacent trenches; filling the trenches and first openings of the hard mask; and etching the hard mask to form second openings in the hard mask at the main surface of the mesas. | 2015-04-30 |
20150115357 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device. The semiconductor device includes a plurality of trench transistors in an active region, and an interconnection disposed in an edge region, the interconnection configured to transfer a voltage to the plurality of trench transistors, in which the edge region comprises a substrate, a first insulating layer, a first electrode, a second insulating layer, and a second electrode, disposed in that order. | 2015-04-30 |
20150115358 | Semiconductor Device - The present disclosure provides a semiconductor device, including a compensation area that includes p-regions and n-regions, a plurality of transistor cells including gate electrodes on the compensation area, and one or more interconnections for electrically connecting gate electrodes. The gate electrodes may have a width smaller than ½ of a pitch of the cells. | 2015-04-30 |
20150115359 | SEMICONDUCTOR DEVICE - In a semiconductor device, a lightly doped second semiconductor layer of a first conductive type is joined with a heavily doped first semiconductor layer of the first conductive type. A power transistor having a first conductive type channel and a transistor are formed in surface regions of the second semiconductor layer, respectively. A first diffusion layer of a second conductive type is formed in a surface region of the second semiconductor layer to provide a boundary between the power transistor and the transistor. The first semiconductor layer functions as a drain of the power transistor. The first diffusion layer region is set to the same voltage as that of the drain. | 2015-04-30 |
20150115360 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW). | 2015-04-30 |
20150115361 | Lateral Diffused Metal Oxide Semiconductor - A lateral diffused N-type metal oxide semiconductor device includes a semiconductor substrate, an epi-layer on the semiconductor substrate, a patterned isolation layer on the epi-layer, a N-type double diffused drain (NDDD) region in a first active region of the patterned isolation layer, a N+ heavily doped drain region disposed in the NDDD region, a P-body diffused region disposed in a second active region of the patterned isolation layer, a neighboring pair of a N+ heavily doped source region and a P+ heavily doped source region disposed in the P-body diffused region, a first gate structure disposed above a channel region of the patterned isolation layer and a second gate structure disposed above the second active region. The second gate structure and the first gate structure are spaced at a predetermined distance. | 2015-04-30 |
20150115362 | Lateral Diffused Metal Oxide Semiconductor - A lateral diffused N-type metal oxide semiconductor device includes a semiconductor substrate, an epi-layer on the semiconductor substrate, a patterned isolation layer on the epi-layer, a N-type double diffused drain (NDDD) region in a first active region of the patterned isolation layer, a N+ heavily doped drain region disposed in the NDDD region, a P-body diffused region disposed in a second active region of the patterned isolation layer, a neighboring pair of a N+ heavily doped source region and a P+ heavily doped source region disposed in the P-body diffused region, a first gate structure disposed above a channel region of the patterned isolation layer and a second gate structure disposed above the second active region. The second gate structure and the first gate structure are spaced at a predetermined distance. A making method of the NDDD region includes using an ion implant and an epitaxy layer doping. | 2015-04-30 |
20150115363 | MECHANISMS FOR FORMING FINFET DEVICE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode. | 2015-04-30 |
20150115364 | SELF-PROTECTED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - Device structures, design structures, and fabrication methods for a metal-oxide-semiconductor field-effect transistor. A gate structure is formed on a top surface of a substrate. First and second trenches are formed in the substrate adjacent to a sidewall of the gate structure. The second trench is formed laterally between the first trench and the first sidewall. First and second epitaxial layers are respectively formed in the first and second trenches. A contact is formed to the first epitaxial layer, which serves as a drain. The second epitaxial layer in the second trench is not contacted so that the second epitaxial layer serves as a ballasting resistor. | 2015-04-30 |
20150115365 | CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS - Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed. | 2015-04-30 |
20150115366 | CIRCULAR SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) DEVICE AND FUNCTIONAL DEVICE - One or more semiconductor devices with an electrostatic discharge (ESD) device and a functional device in a circular arrangement are provided herein. The semiconductor device comprises a first circular sector, a second circular sector, and at least two disconnect regions disposed between the first circular sector and the second circular sector. The first circular sector comprises at least one ESD device. The second circular sector comprises at least one functional device. A single semiconductor device having a circular arrangement or configuration thus has an ESD device and a functional device. | 2015-04-30 |
20150115367 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first mask on a substrate; defining a first doped region through an opening of the first mask; forming a second mask on the first mask and filling in the opening of the first mask with the second mask; defining a second doped region through an opening of the second mask; and stripping the first mask and the second mask from the substrate. The present disclosure provides a semiconductor structure, including a substrate having a top surface; a first doped region having a first surface; and a second doped region having a second surface. The first surface and the second surface are coplanar with the top surface of the substrate. Either of the doped regions has a monotonically decreasing doping profile from the top surface of the substrate to a bottom of the doped region. | 2015-04-30 |
20150115368 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a semiconductor substrate. Each of the unit cells may include a buried insulating pattern buried in the semiconductor substrate, a first active pattern provided on the buried insulating pattern, and a second active pattern provided on the buried insulating pattern and spaced apart from the first active pattern. The buried insulating pattern may define a unit cell region, in which each of the unit cells may be disposed. | 2015-04-30 |
20150115369 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 2015-04-30 |
20150115370 | SEMICONDUCTOR DEVICE PROVIDING ENHANCED FIN ISOLATION AND RELATED METHODS - A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin. | 2015-04-30 |
20150115371 | FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME - The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps. | 2015-04-30 |
20150115372 | METAL GATE FINFET DEVICE - A device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer. | 2015-04-30 |
20150115373 | STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE ACTIVE REGIONS - A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region. | 2015-04-30 |
20150115374 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure. | 2015-04-30 |
20150115375 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode. | 2015-04-30 |
20150115376 | MEMS Device with Outgassing Shield - A capped micromachined device has a movable micromachined structure in a first hermetic chamber and one or more interconnections in a second hermetic chamber that is hermetically isolated from the first hermetic chamber, and a barrier layer on its cap where the cap faces the first hermetic chamber, such that the first hermetic chamber is isolated from outgassing from the cap. | 2015-04-30 |
20150115377 | MEMS DEVICE WITH INTEGRATED TEMPERATURE STABILIZATION - An apparatus for providing localized heating as well as protection for a vibrating MEMS device. A cap over a MEMS gyroscope includes an embedded temperature sensor and a heater. The temperature sensor is a trace made of a material with a known temperature/resistance coefficient, which loops back along itself to reduce electromagnetic interference. The heater is a resistive metal trace which also loops back along itself. The temperature sensor and the heater provide localized temperature stabilization for the MEMS gyroscope to reduce temperature drift in the MEMS gyroscope. | 2015-04-30 |
20150115378 | METHOD FOR MANUFACTURING A DIE ASSEMBLY HAVING A SMALL THICKNESS AND DIE ASSEMBLY RELATING THERETO - A method for manufacturing a die assembly, including the steps of: bonding a first wafer of semiconductor material to a second wafer, the second wafer including a respective semiconductor body having a respective initial thickness and forming an integrated electronic circuit; and subsequently reducing the initial thickness of the semiconductor body of the second wafer; and subsequently bonding the second wafer to a third wafer, the third wafer forming a micro-electromechanical sensing structure. | 2015-04-30 |
20150115379 | COBALT (CO) AND PLATINUM (PT)-BASED MULTILAYER THIN FILM HAVING INVERTED STRUCTURE AND METHOD FOR MANUFACTURING SAME - The present invention relates to a cobalt (Co) and platinum (Pt)-based multilayer thin film having a novel structure and perpendicular magnetic anisotropy, and to a fabrication method thereof. More specifically, the invention relates to a cobalt and platinum-based multilayer thin film having perpendicular magnetic anisotropy (PMA), which includes thin cobalt layers and thin platinum layers alternately deposited over a substrate, and has an inverted structure in which a thickness of the thin cobalt layers is greater than that of the thin platinum layers, and to a fabrication method thereof. The cobalt and platinum-based multilayer thin film has a new structure in which the thickness of a magnetic thin layer is greater than that of a non-magnetic thin layer. The multilayer thin film may be easily applied as a free layer and a pinned layer in a magnetic tunnel junction by controlling the perpendicular magnetic anisotropy energy depending on the thickness ratio of the layers. Also, the multilayer thin film has excellent thermal stability, and thus maintains its PMA energy density even after being subjected to a heat treatment process. In addition, it enables a fine amount of in-plane magnetic anisotropy to be formed by heat treatment so as to reduce the critical current density required for magnetization switching. Therefore, it may be advantageously used for high-performance and high-density MRAM. | 2015-04-30 |
20150115380 | MAGNETIC MEMORY DEVICE - A magnetic memory device is provided. The magnetic memory device includes a first vertical magnetic layer and a second vertical magnetic layer on a substrate, a tunnel barrier layer between the first vertical magnetic layer and the second vertical magnetic layer, and an exchange-coupling layer between a first sub-layer of the first vertical magnetic layer and a second sub-layer of the first vertical magnetic layer. | 2015-04-30 |
20150115381 | MECHANISMS FOR FORMING RADIO FREQUENCY (RF) AREA OF INTEGRATED CIRCUIT STRUCTURE - Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region. | 2015-04-30 |
20150115382 | Image Sensor Comprising Reflective Guide Layer and Method of Forming the Same - Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters. | 2015-04-30 |
20150115383 | OPTICAL DEVICE AND SOLID-STATE IMAGE SENSING DEVICE - According to one embodiment, an optical device includes a plurality of optical elements arrange in array. At least of the optical elements includes an optical layer constituted by a plurality of patterns. The plurality of patterns are formed by a layered body including metal layers and a dielectric layer interlayered between the metal layers, and formed as a plurality of regularly-arranged loop-like patterns with a density decreasing from the center toward the periphery of the loop. | 2015-04-30 |
20150115384 | LIGHT RECEIVING DEVICE - A light receiving device includes an optical substrate disposed over a light receiving surface. In the optical substrate, a first optical multilayer film is formed on an incident surface, a second optical multilayer film is formed on a surface opposite the incident surface, and a third optical multilayer film is formed on the light receiving surface. Light of two wavelength regions separated from each other is transmitted, and light of wavelength regions other than the two wavelength regions is blocked. The two wavelength regions include a first wavelength region on the short wavelength side and a second wavelength region on the long wavelength side. At least a predetermined proportion of light of the second wavelength region is transmitted, and the transmittance of light of the first wavelength region is limited within a predetermined range less than the predetermined proportion. | 2015-04-30 |
20150115385 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND CAMERA WITH ALTERNATELY ARRANGED PIXEL COMBINATIONS - A solid-state imaging device includes a semiconductor substrate; and a pixel unit having a plurality of pixels on the semiconductor substrate, wherein the pixel unit includes first pixel groups having two or more pixels and second pixel groups being different from the first pixel groups, wherein a portion of the pixels in the first pixel groups and a portion of the pixels in the second pixel groups share a floating diffusion element. | 2015-04-30 |
20150115386 | Semiconductor Devices, Methods of Manufacturing Thereof, and Image Sensor Devices - Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. | 2015-04-30 |
20150115387 | METHOD OF MANUFACTURING A DEVICE COMPRISING AN INTEGRATED CIRCUIT AND PHOTOVOLTAIC CELLS - According to one embodiment, the present invention relates to a method for manufacturing a photovoltaic device comprising a photovoltaic cell or a plurality of photovoltaic cells (PV cells) connected to an electronic integrated circuit having at least one electrical contact area. A stack comprising the PV cell(s) is produced separately from the electronic integrated circuit, the electronic integrated circuit is then transferred to said stack comprising the PV cell(s). During this transfer, connection areas carried by the PV cell(s) are brought into contact with matching connection areas carried by the electronic integrated circuit. | 2015-04-30 |
20150115388 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a plurality of photoelectric transducers disposed in an array in a semiconductor layer. Each photoelectric transducer includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first and second regions are in direct contact. An isolation region is between each adjacent pair of photoelectric transducers. The isolation region includes an insulating material extending from a surface of the semiconductor layer and a third semiconductor region of the first conductivity type surrounding the insulating material. The third semiconductor region is between the insulating material and the first semiconductor region, and the first semiconductor region is between the second and third semiconductor regions. | 2015-04-30 |
20150115389 | Semiconductor Devices, Methods of Manufacturing Thereof, and Image Sensor Devices - Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device includes a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. A guard structure is disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region. A portion of the guard structure is disposed within a substrate of the semiconductor chip. | 2015-04-30 |
20150115390 | TRANSIENT VOLTAGE SUPPRESSOR AND ITS MANUFACTURING METHOD - A transient voltage suppressor and its manufacturing method are provided, which can easily control voltage withstanding characteristics of a Zener diode by analogizing growth of a buried layer by forming a portion of the buried layer by performing ion implantation on a first epitaxial layer and then forming the other portion of the buried layer while depositing a second epitaxial layer having the same impurity concentration with the first epitaxial layer, and which can improve a current distribution characteristic by forming a doping region in a ring shape to increase a current pass region by increasing a PN junction area of a Zener diode in a small area. | 2015-04-30 |
20150115391 | Semiconductor Device Having a Locally Reinforced Metallization Structure and Method for Manufacturing Thereof - A method for forming a semiconductor device includes providing a semiconductor substrate having a first area and a second area. A first metal layer structure is formed which includes at least a first metal portion in the first area and a second metal portion in the second area. A plating mask is formed on the first metal layer structure to cover the second metal portion, and a second metal layer structure is plated on and in ohmic contact with the first metal portion of the first metal layer structure. | 2015-04-30 |
20150115392 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line. | 2015-04-30 |
20150115393 | METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices. | 2015-04-30 |
20150115394 | Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers. | 2015-04-30 |