18th week of 2020 patent applcation highlights part 69 |
Patent application number | Title | Published |
20200135540 | SEMICONDUCTOR STRUCTURE INCLUDING ISOLATIONS - A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate. | 2020-04-30 |
20200135541 | METHOD FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE - Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness. | 2020-04-30 |
20200135542 | SPACER-DEFINED PROCESS FOR LITHOGRAPHY-ETCH DOUBLE PATTERNING FOR INTERCONNECTS - One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material. | 2020-04-30 |
20200135543 | METHODS OF MANUFACTURING REDISTRIBUTION CIRCUIT STRUCTURES - Methods of manufacturing redistribution circuit structures are disclosed and one of the methods includes the following steps. A seed layer is formed over a die and an encapsulant encapsulating the die. A photoresist material is formed over the seed layer. The photoresist material is exposed through a phase shift mask to an I-line wavelength within an I-line stepper using a numerical aperture equal to or less than 0.18. The photoresist material is developed to form a photoresist layer including photoresist patterns and openings therebetween. A conductive material is formed in the openings. The photoresist patterns are removed to form conductive patterns. By using the conductive patterns as a mask, the seed layer is partially removed, to form seed layer patterns under the conductive patterns, wherein redistribution conductive patterns include the seed layer patterns and the conductive patterns respectively. | 2020-04-30 |
20200135544 | SELECTIVE DEPOSITION OF DIELECTRICS ON ULTRA-LOW K DIELECTRICS - A method for fabricating a semiconductor device includes forming a via in a first dielectric layer arranged on a metal layer. The via exposes a portion of the metal layer. The method includes forming a trench in the first dielectric layer. The method further includes depositing, by a selective process, a second dielectric layer on the first dielectric layer such that the second dielectric layer lines sidewalls of the via and the trench and is selectively deposited onto the first dielectric layer. | 2020-04-30 |
20200135545 | SMOOTH SIDEWALL STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures. | 2020-04-30 |
20200135546 | Method for Shrinking Openings in Forming Integrated Circuits - A method includes forming a first hard mask layer and a second hard mask layer over the first hard mask layer, and forming a tri-layer including a bottom layer, a middle layer, and a patterned upper layer. The method further includes etching the middle layer to extend an opening in the patterned upper layer into the middle layer, wherein the opening has a first portion in the middle layer, and the first portion has a first top width and a first bottom width smaller than the first top width; etching the bottom layer to extend the opening into the bottom layer; and etching the second hard mask layer to extend the opening into the second hard mask layer. The opening has a second portion in the second hard mask layer, and the second portion has a second top width and a second bottom width smaller than the second top width. | 2020-04-30 |
20200135547 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - Methods of patterning openings for conductive contacts in a target layer of a semiconductor device and methods of forming conductive contacts. The method of patterning openings may be used to form contact openings in an inter-layer dielectric (ILD) layer of a semiconductor substrate for contacts to source/drain regions of FinFET devices. A hard mask layer may be patterned to form a cut mask by transferring slotted openings of a first middle layer of a tetra-layer photoresist and a cut MD pattern of a photoresist layer formed over the first middle layer of the tetra-layered photoresist using photolithography techniques. Once the cut mask is formed, contact openings are formed within the ILD layer down to the source/drain regions of the FinFET devices of the semiconductor substrate. The contact openings may be filled with conductive material(s) to define conductive contacts (e.g., conductive plugs). | 2020-04-30 |
20200135548 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a metal pattern, and forming an etch stop layer over the substrate. The etch stop layer includes a first material. The method also includes forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer, and forming an insulative layer over the etch stop layer. The diffused area includes a lower etch rate to a first etchant than the insulative layer. A semiconductor device is also provided. | 2020-04-30 |
20200135549 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via. | 2020-04-30 |
20200135550 | Semiconductor Device and Method - In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD. | 2020-04-30 |
20200135551 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method is provided. Plural semiconductor fins are formed on a substrate, and plural trenches each of which is formed between two adjacent semiconductor fins. A silicon liner layer is deposited to be conformal to the semiconductor fins and the trenches. The silicon liner layer is deposited by using a silane compound. Then, an oxide layer is deposited on the silicon liner layer to fill the trenches and cover the semiconductor fins, in which depositing the oxide layer forms water in the oxide layer. Next, a surface of the silicon liner layer is reacted with the water, so as to remove the water from the oxide layer. | 2020-04-30 |
20200135552 | HIGH BREAKDOWN VOLTAGE INTER-METAL DIELECTRIC LAYER - The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer. | 2020-04-30 |
20200135553 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer. | 2020-04-30 |
20200135554 | Water Vapor Based Fluorine Containing Plasma For Removal Of Hardmask - Apparatus, systems, and methods for conducting a hardmask (e.g., boron doped amorphous carbon hardmask) removal process on a workpiece are provided. In one example implementation, a method includes supporting a workpiece on a workpiece support in a processing chamber. The method can include generating a plasma from a process gas in a plasma chamber using a plasma source. The plasma chamber can be separated from the processing chamber by a separation grid. The method can include exposing the workpiece to one or more radicals generated in the plasma to perform a plasma strip process on the workpiece to at least partially remove the hardmask layer from the workpiece. The method can include exposing the workpiece to water vapor as a passivation agent during the plasma strip process. | 2020-04-30 |
20200135555 | METHOD FOR FORMING AN INTERCONNECT STRUCTURE - The present disclosure relates to a method of forming an interconnect structure. The method can include providing a semiconductor substrate; depositing a photoresist and a BARC layer on the semiconductor substrate; forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate; depositing a conductive material to fill the opening; and planarizing the conductive material and the semiconductor substrate. | 2020-04-30 |
20200135556 | CONTROLLING GRAIN BOUNDARIES IN HIGH ASPECT-RATIO CONDUCTIVE REGIONS - Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level. | 2020-04-30 |
20200135557 | Selective Deposition for Integrated Circuit Interconnect Structures - Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess. | 2020-04-30 |
20200135558 | COBALT INTERCONNECT STRUCTURE - Interconnect structures and processes of fabricating the interconnect structures generally includes partially or completely cobalt filled openings. The cobalt metal is conformally deposited onto a noble metal layer and thermally annealed to reflow the cobalt metal and partially or completely fill the openings. | 2020-04-30 |
20200135559 | Contact Etchback in Room Temperature Ionic Liquid - The present disclosure provides an integrated circuit with an interconnect structure and a method for forming the integrated circuit. In one embodiment, a method of the present disclosure includes receiving a workpiece that includes a first recess in a dielectric layer over the workpiece, depositing a contact fill in the first recess and over the dielectric layer to form a contact feature, planarizing a top surface of the workpiece to remove the contact fill over the dielectric layer, depositing an interlayer dielectric layer over the planarized top surface of the workpiece, forming a second recess in the interlayer dielectric layer to expose the contact fill in the dielectric layer, recessing the contact fill by soaking the workpiece in a room temperature ionic liquid, and depositing a conductive layer over the recessed contact fill. The material forming the contact fill is soluble in the room temperature ionic liquid. | 2020-04-30 |
20200135560 | STRUCTURE AND METHOD FOR FORMING FULLY-ALIGNED TRENCH WITH AN UP-VIA INTEGRATION SCHEME - A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches. | 2020-04-30 |
20200135561 | TRANSISTOR WITH IMPROVED SELF-ALIGNED CONTACT - Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity. | 2020-04-30 |
20200135562 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED VIAS - A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via. | 2020-04-30 |
20200135563 | LASER PROCESSING METHOD - A laser processing method for a substrate with a device formed on a front surface thereof and including an electrode pad, the method including: a laser beam applying step of applying the laser beam to the back surface of the substrate to form a fine hole in the substrate at a position corresponding to the electrode pad; a detecting step of detecting first plasma light emitted from the substrate at the same time that the fine hole is formed in the substrate by the laser beam applied thereto, and second plasma light emitted from the electrode pad; and a laser beam irradiation finishing step of stopping application of the laser beam when the second plasma light is detected in the detecting step. A peak power density of the laser beam to be applied is set in a range from 175 GW/cm | 2020-04-30 |
20200135564 | Preliminary Trenches Formed in Kerf Regions for Die Singulation - A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches. | 2020-04-30 |
20200135565 | REUSABLE WIDE BANDGAP SEMICONDUCTOR SUBSTRATE - Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer. | 2020-04-30 |
20200135566 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WAFER-ATTACHED STRUCTURE - A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step. | 2020-04-30 |
20200135567 | SEMICONDUCTOR PACKAGE AND METHODS OF FORMING THE SAME - A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies. | 2020-04-30 |
20200135568 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs. | 2020-04-30 |
20200135569 | Configuring Different Via Sizes for Bridging Risk Reduction and Performance Improvement - A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via. | 2020-04-30 |
20200135570 | CONTROLLING FIN HARDMASK CUT PROFILE USING A SACRIFICIAL EPITAXIAL STRUCTURE - Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask. | 2020-04-30 |
20200135571 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH GATE-ALL-AROUND STRUCTURE - A method of fabricating semiconductor devices is provided. The method includes forming a fin protruding from a substrate, and forming a disposable mandrel fin on the fin. The method also includes epitaxially growing channel fins on sidewalls of the disposable mandrel fin. The method further includes removing the disposable mandrel fin to form a space between the channel fins, and forming a gate structure to fill the space between the channel fins and to wrap the channel fins. In addition, the method includes forming source and drain structures on opposite sides of the gate structure. | 2020-04-30 |
20200135572 | FINFET GATE STRUCTURE AND RELATED METHODS - A method for fabricating a semiconductor device having a dielectric footing region includes forming a plurality of fin elements extending from a substrate. In some embodiments, a dielectric layer is deposited over each of the plurality of fin elements. After depositing the dielectric layer, a dummy gate electrode is formed over the plurality of fin elements and over the dielectric layer. In some examples, and after forming the dummy gate electrode, a first spacer layer is formed on opposing sidewalls of the dummy gate electrode and over the dielectric layer. In various embodiments, the dielectric layer extends laterally beneath the first spacer layer on each of the opposing sidewalls of the dummy gate electrode to provide the dielectric footing region. | 2020-04-30 |
20200135573 | STRUCTURE AND METHOD OF FORMING FIN DEVICE HAVING IMPROVED FIN LINER - A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device. | 2020-04-30 |
20200135574 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes. | 2020-04-30 |
20200135575 | GATE CUT CRITICAL DIMENSION SHRINK AND ACTIVE GATE DEFECT HEALING USING SELECTIVE DEPOSITION - Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material. | 2020-04-30 |
20200135576 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE - A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer. | 2020-04-30 |
20200135577 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a circuit including a MOSFET disposed in a MOSFET region and a negative capacitance FET (NCFET) disposed in a NCFET region, a dielectric layer is formed over a channel layer in the MOSFET region and the NCFET region. A first metallic layer is formed over the dielectric layer in the MOSFET region and the NCFET region. After the first metallic layer is formed, an annealing operation is performed only in the NCFET region. After the annealing operation, the first metallic layer is removed from the MOSFET region and the NCFET region. The annealing operation includes irradiating the first metallic layer and the dielectric layer in the NCFET region with an energy beam. | 2020-04-30 |
20200135578 | Integrated Circuits with Buried Interconnect Conductors - Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor. | 2020-04-30 |
20200135579 | Semiconductor Device and Method - In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold. | 2020-04-30 |
20200135580 | Dielectric Fins With Different Dielectric Constants and Sizes in Different Regions of a Semiconductor Device - A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant. | 2020-04-30 |
20200135581 | Method and Structure for FinFET Isolation - A semiconductor device includes a substrate and a fin protruding from the substrate, the fin having a first fin segment and a second fin segment discontinued from the first fin segment. The semiconductor device further includes an isolation feature disposed between the first and second fin segments and a spacer feature disposed on sidewalls of an upper portion of the isolation feature and surrounding the isolation feature from a top view. | 2020-04-30 |
20200135582 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure. | 2020-04-30 |
20200135583 | TRANSISTOR STRUCTURE WITH MULTIPLE HALO IMPLANTS HAVING EPITAXIAL LAYER OVER SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - A transistor structure can include a semiconductor-on-insulator substrate that includes an upper substrate region separated from a lower substrate region by a buried insulator. Shallow halo implant regions can be formed in an upper substrate region having a peak concentration at a first depth within the upper substrate region. Deep halo implant regions can be formed in the upper substrate region having a peak concentration at a second depth lower than the first depth. An epitaxial layer can be formed on top of the upper substrate region and below the control gate. Source and drain regions both of a second conductivity type formed in at least the epitaxial layer. In some embodiments, a lower substrate region can be biased for a double-gate effect. | 2020-04-30 |
20200135584 | FINFET DEVICES AND METHODS OF FORMING THE SAME - Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin. | 2020-04-30 |
20200135585 | MASKLESS TOP SOURCE/DRAIN EPITAXIAL GROWTH ON VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR - A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO | 2020-04-30 |
20200135586 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first transistor with a first conductive region and a second transistor with a second conductive region, wherein the first transistor and the second transistor have different conductive types. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate after the amorphization. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region after the formation of the pre-silicide layer. | 2020-04-30 |
20200135587 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space. | 2020-04-30 |
20200135588 | Fin Field-Effect Transistor Device and Method - A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first recess and in the second recess; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide. | 2020-04-30 |
20200135589 | METHOD OF METAL GATE FORMATION AND STRUCTURES FORMED BY THE SAME - A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench. | 2020-04-30 |
20200135590 | AIR GAP FORMATION BETWEEN GATE SPACER AND EPITAXY STRUCTURE - A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer. | 2020-04-30 |
20200135591 | CONTACT AIR GAP FORMATION AND STRUCTURES THEREOF - A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer. | 2020-04-30 |
20200135592 | Systems and Methods For Manufacturing Microelectronic Devices - In one embodiment, a method includes obtaining wafer measurements of a characteristic of a semiconductor wafer at each of a plurality of process steps during a semiconductor wafer fabrication process, where each of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained. The method may further include creating a process step fingerprint from the obtained wafer measurements for each process step. The method may further include correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function. | 2020-04-30 |
20200135593 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer. | 2020-04-30 |
20200135594 | SEMICONDUCTOR PACKAGE INCLUDING TEST PAD - A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer. | 2020-04-30 |
20200135595 | DISPLAY DEVICE - A display device includes a display area, a peripheral area, a pad portion, a bending area, a first crack detection circuit, and a first crack detection line. The display area includes pixels and data lines. The peripheral area is disposed outside the display area. The pad portion is disposed in the peripheral area. The bending area is disposed in the peripheral area. The bending area is bendable or in a bent state. The first crack detection circuit is disposed between the display area and the pad portion. The first crack detection circuit includes switches. The first crack detection line includes a first curved portion disposed in the bending area. The first crack detection line is connected between the pad portion and the first crack detection circuit. | 2020-04-30 |
20200135596 | COVER GLASS AND AIRTIGHT PACKAGE USING SAME - A cover glass of the present invention includes a sealing material layer on one surface, wherein the sealing material layer has a gap formed therein. | 2020-04-30 |
20200135597 | DIE CARRIER PACKAGE AND METHOD OF FORMING SAME - Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity. | 2020-04-30 |
20200135598 | ELECTRONIC MODULE AND METHOD FOR MANUFACTURING SAME - An electronic module includes a substrate having flexibility and an electrical insulation property, a circuit unit in which an electronic device is mounted on a wiring pattern formed on at least any one of surfaces of the substrate, and a resin body in which the circuit unit is sealed with an electrical insulating resin, wherein the substrate has flexibility to be deformable due to a pressure during sealing with the electrical insulating resin. | 2020-04-30 |
20200135599 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor chip structure includes a substrate having a top surface, a bottom surface, and a lateral surface connecting the top surface and the bottom surface. The lateral surface includes a first portion having a first surface roughness and being in proximity to the top surface, and a second portion having a second surface roughness and being in proximity to the bottom surface. The first surface roughness is greater than the second surface roughness. A method for manufacturing the semiconductor chip structure is also provided. | 2020-04-30 |
20200135600 | Integrated Circuit Package and Method - In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer. | 2020-04-30 |
20200135601 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a plurality of first dies, a first encapsulant, and a first redistribution structure. The first encapsulant encapsulates the first dies. The first redistribution structure is disposed on the first dies and the first encapsulant. The first redistribution structure includes a dielectric layer covering a top surface and sidewalls of the first encapsulant. | 2020-04-30 |
20200135602 | SOLDER MASK DESIGN FOR DELAMINATION PREVENTION - Embodiments described herein provide techniques for forming a solder mask having a repeating pattern of features formed therein. The repeating pattern of features can be conceptually understood as a plurality of groove structures formed in the solder mask. The solder mask can be included in a semiconductor package that comprises the solder mask over a substrate and a molding compound over the solder mask that conforms to the repeating pattern of features. Several advantages are attributable to embodiments of the solder mask described herein. One advantage is that the repeating pattern of features formed in the solder mask increase the contact area between the solder mask and the molding compound. Increasing the contact area can assist with increasing adherence and conformance of the molding compound to the solder mask. This increased adherence and conformance assists with minimizing or eliminating interfacial delamination. | 2020-04-30 |
20200135603 | INTEGRATED CIRCUIT STRUCTURES WITH EXTENDED CONDUCTIVE PATHWAYS - Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side. | 2020-04-30 |
20200135604 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant. | 2020-04-30 |
20200135605 | Integrated Circuit Package and Method of Forming Same - An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure. | 2020-04-30 |
20200135606 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes attaching a first semiconductor device to a first surface of a substrate; forming a sacrificial structure on the first surface of the substrate around the first semiconductor device, the sacrificial structure encircling a first region of the first surface of the substrate; and forming an underfill material in the first region. | 2020-04-30 |
20200135607 | SEMICONDUCTOR DEVICE - The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface. | 2020-04-30 |
20200135608 | CONDUCTION COOLING FOR CIRCUIT BOARDS - Disclosed is a cooling assembly for circuit boards. In one embodiment, the assembly includes a circuit board that is thermally and physically coupled to a heat spreader by a thermal interface. In one configuration, the circuit board is formed from a semiconductor material and includes a first board surface on which integrated circuits are mounted and a second board surface opposite the first board surface. The heat spreader is formed from a thermally conductive material and includes a plurality of vanes that are spaced apart from one another. The thermal interface is coupled between at least one area of the second board surface of the circuit board and a contact area of each of the plurality of vanes. Heat generated by the integrated circuits is conducted from at least one integrated circuit to the plurality of vanes of the heat spreader through the circuit board and the thermal interface. | 2020-04-30 |
20200135609 | CIRCUIT BOARD AND PACKAGED CHIP - A circuit board includes an upper circuit and a lower surface that are opposite to each other, a plurality of heat sink bonding pads, and a plurality of heat sink conductive pads. The heat sink bonding pads are disposed on the upper surface and electrically insulated from one another, and are used to electrically connect to a heat sink. The heat sink conductive pads are disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively. | 2020-04-30 |
20200135610 | SEMICONDUCTOR STRUCTURE - The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block. | 2020-04-30 |
20200135611 | IMPLEMENTING STRAIN SENSING THERMAL INTERFACE MATERIALS - Methods and structures are provided for implementing strain sensing thermal interface materials (TIMs). An in situ strain sensing thermal interface material (TIM) layer is provided within a packaging assembly structure. The strain sensing TIM is formed by graphene incorporated into the TIM layer. Electrical leads are coupled to the strain sensing TIM layer providing electrical contacts for measuring the electrical property change of the TIM which correlates to mechanical strain. | 2020-04-30 |
20200135612 | POWER MODULE SUBSTRATE AND POWER MODULE - A power module substrate includes an insulating substrate and a metal plate. The metal plate is joined to the insulating substrate with a brazing material in between. As to surface roughness of a lateral surface of the metal plate in a thickness direction, the surface roughness of at least a corner part farthest from a center of the metal plate in plan view is larger than the surface roughness of plane parts sandwiching the corner part. | 2020-04-30 |
20200135613 | SEMICONDUCTOR DEVICE WITH ENHANCED THERMAL DISSIPATION AND METHOD FOR MAKING THE SAME - A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ≥50 W/mK. | 2020-04-30 |
20200135614 | HEAT SINKS WITH VIBRATION ENHANCED HEAT TRANSFER FOR NON-LIQUID HEAT SOURCES - The heat sinks with vibration enhanced heat transfer for non-liquid heat sources are heat sinks formed from a first body of high thermal conductivity material received within a thermally conductive housing such that at least one contact face of the first body of high thermal conductivity material is exposed, forming a direct contact interface with a heat source requiring cooling. The heat source requiring cooling may be any non-liquid heat source, including a processor chip, an integrated circuit chip, a modular circuit package, or the like. The thermally conductive housing may be disposed such that at least one contact face of the thermally conductive housing is in direct contact with the vibrating base. Alternatively, the vibrating base may be attached to a support attached to the heat source. The vibrating base applies oscillating waves to the heat sink, thereby increasing heat transfer between the heat source and the heat sink. | 2020-04-30 |
20200135615 | CHIP PACKAGE STRUCTURE - This application provides a chip package structure. The chip package structure includes: a substrate and a chip, and further includes: a heat dissipation ring fastened onto the substrate and a planar heat pipe radiator covering the heat dissipation ring. The substrate, the heat dissipation ring, and the planar heat pipe radiator form a space to enclose the chip. A first metal thin film is disposed on a surface, facing the chip, of the planar heat pipe radiator, and the chip is thermally coupled to the first metal thin film by using a sintered metal layer. | 2020-04-30 |
20200135616 | CHOKED FLOW COOLING - Embodiments disclosed herein include electronic packages with chocked flow cooling. In an embodiment, an electronic package may comprise a package substrate, a die electrically and mechanically coupled to the package substrate, and a lid over the die. In an embodiment, the lid has a first opening and a second opening that is opposite from the first opening. In an embodiment, the electronic package may further comprise a coolant plate covering the first opening. In an embodiment, the coolant plate comprises a first surface facing away from the die and a second surface facing the die, and a plurality of vents from the first surface to the second surface. In an embodiment, the first openings of the plurality of vents have a first dimension and second openings of the plurality of vents have a second dimension that is smaller than the first dimension. | 2020-04-30 |
20200135617 | ION THROUGH-SUBSTRATE VIA - Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV. | 2020-04-30 |
20200135618 | Construction Of Integrated Circuitry And A Method Of Forming An Elevationally-Elongated Conductive Via To A Diffusion Region In Semiconductive Material - A construction of integrated circuitry comprises a trench isolation region in semiconductive material. The trench isolation region comprises laterally-opposing laterally-outermost first regions which comprise a first material and a second region laterally-inward of the first regions. The second region comprises a second material of different composition from that of the first material. A diffusion region is in the uppermost portion of the semiconductive material directly against a sidewall of one of the first regions. Insulator material is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the one first region. The conductive via is directly against a top surface of the diffusion region, is directly against an upper portion of a sidewall of the diffusion region, and is directly against a laterally-outer sidewall of the second material of the second region of the trench isolation material. Other embodiments, including method, are disclosed. | 2020-04-30 |
20200135619 | Semiconductor Package and Method of Fabricating a Semiconductor Package - In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board. | 2020-04-30 |
20200135620 | SEMICONDUCTOR DEVICE PACKAGES WITH ELECTRICAL ROUTING IMPROVEMENTS AND RELATED METHODS - Semiconductor device packages may include a die-attach pad and a semiconductor die supported above the die-attach pad. A spacer comprising an electrically conductive material may be supported above the semiconductor die or between the semiconductor die and the die-attach pad. A wire bond may extend from a bond pad on an active surface of the semiconductor die to the spacer. Another wire bond may extend from the spacer to a lead finger or the die-attach pad. An encapsulant material may encapsulate the semiconductor die, the spacer, the wire bond, the other wire bond, the die-attach pad, and a portion of any lead fingers. | 2020-04-30 |
20200135621 | LEADS FOR LEADFRAME AND SEMICONDUCTOR PACKAGE - A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed. | 2020-04-30 |
20200135622 | POWER CONTROL MODULES - A power control module includes a power device having a first side and a second side opposite from the first. The power control module includes a printed wiring board (PWB) spaced apart from the first side of the power device. The PWB is electrically connected to the power device. A heat sink plate is soldered to a second side of the transistor for heat dissipation from the transistor. The PWB and/or the heat sink plate includes an access hole defined therein to allow for access to the transistor during assembly. A method of assembling a power control module includes soldering at least one lead of a power device to a printed wiring board (PWB), pushing the power device toward a heat sink plate, and soldering the power device to the heat sink plate. | 2020-04-30 |
20200135623 | QFN PRE-MOLDED LEADFRAME HAVING A SOLDER WETTABLE SIDEWALL ON EACH LEAD - The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board. | 2020-04-30 |
20200135624 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first electrode terminal; a second electrode terminal; a semiconductor element having an electrode on one surface connected to one surface of the first electrode terminal; a wire that connects an electrode on the other surface of the semiconductor element and the second electrode terminal; and a resin portion formed of an insulator covering the semiconductor element, a part of the second electrode terminal, and the one surface of the first electrode terminal, wherein a chamfered portion is formed on at least one of end portions where the first electrode terminal and the second electrode terminal face each other. | 2020-04-30 |
20200135625 | SEMICONDUCTOR PACKAGE HAVING DIE PAD WITH COOLING FINS - Embodiments of the present disclosure are directed to leadframe semiconductor packages having die pads with cooling fins. In at least one embodiment, the leadframe semiconductor package includes leads and a semiconductor die (or chip) coupled to a die pad with cooling fins. The cooling fins are defined by recesses formed in the die pad. The recesses extend into the die pad at a bottom surface of the semiconductor package, such that the bottom surfaces of the cooling fins of the die pad are flush or coplanar with a surface of the package body, such as an encapsulation material. Furthermore, bottom surfaces of the cooling fins of the die pad are flush or coplanar with exposed bottom surfaces of the leads. | 2020-04-30 |
20200135626 | Semiconductor Package with Leadframe Interconnection Structure - An embodiment of a semiconductor package includes a leadframe and a mold compound partly encasing the leadframe so that leads protrude from the mold compound and at least two die pads have a surface at a first side of the leadframe which is not covered by the mold compound. A laser module is attached to the surface of the at least two die pads which is not covered by the mold compound. A driver die is attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module. The driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and driver die to the leadframe. | 2020-04-30 |
20200135627 | SUBSTRATES WITH SOLDER BARRIERS ON LEADS - A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump. | 2020-04-30 |
20200135628 | LEADFRAME AND LEADFRAME PACKAGE - A leadframe includes a substrate and a surface layer covering the substrate. The surface layer includes an acicular oxide containing CuO at a higher concentration than any other component of the acicular oxide. A leadframe package includes the leadframe, a semiconductor chip mounted on the leadframe, and a resin that covers the semiconductor chip and at least a part of the leadframe. | 2020-04-30 |
20200135629 | POWER MODULE OF DOUBLE-FACED COOLING - A power module of double-faced cooling includes: an upper substrate; a lower substrate on which a plurality of semiconductor chips are disposed; and a first spacer disposed between the upper substrate and the lower substrate, electrically connecting the upper substrate and the lower substrate to each other, and disposed on the lower substrate to be equally distanced from each of the semiconductor chips. Power is supplied to the semiconductor chips on the lower substrate through the upper substrate and the first spacer. | 2020-04-30 |
20200135630 | INTERCONNECT SUBSTRATE WITH ETCHING STOPPERS WITHIN CAVITY AND METAL LEADS AROUND CAVITY AND SEMICONDUCTOR ASSEMBLY USING THE SAME - The interconnect substrate includes etching stoppers within a cavity and a plurality of metal leads disposed around the cavity. The cavity is formed by etching a sacrificial metal slug of a leadframe and laterally surrounded by a resin compound. The etching stoppers are deposited in pits of the metal slug and contact a routing circuitry. By removal of the metal slug, the etching stoppers are exposed from the cavity to provide electrical contacts for device connection within cavity. Due to high etch resistance of the etching stoppers, the integrity of the electrical contacts can be ensured during the cavity formation. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the reliable electrical contacts at the floor of the cavity. | 2020-04-30 |
20200135631 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and an interconnect structure disposed on the semiconductor chip and the encapsulant. The interconnect structure includes a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, the first redistribution layer is electrically connected to the connection pad, and when a thickness of the first redistribution layer is a, and a gap between patterns of the first redistribution layer is b, b/a is 4 or less. | 2020-04-30 |
20200135632 | DIE ISOLATION ON A SUBSTRATE - In a described example, an apparatus includes a substrate with a first surface and an opposing second surface. The substrate includes a trench extending into the substrate from the first surface, a die mounting area adjacent to the trench, a first plurality of leads, and a second plurality of leads. The second plurality of leads are spaced from the trench to electrically isolate the second plurality of leads. The apparatus further includes a first mold compound in the trench forming a filled trench and in the space between the trench and the second plurality of leads. A first die is attached to the first surface of the substrate and a second die is attached to a surface of the first mold compound in the filled trench. | 2020-04-30 |
20200135633 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness. | 2020-04-30 |
20200135634 | Buried Power Rail and Method Forming Same - A method includes etching a semiconductor substrate to form two semiconductor strips. The two semiconductor strips are over a bulk portion of the semiconductor substrate. The method further includes etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, forming a liner dielectric layer lining the trench, forming a buried contact in the trench, forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips, and forming isolation regions on opposite sides of the two semiconductor strips. The buried power rail is underlying a portion of the isolation regions. | 2020-04-30 |
20200135635 | INTEGRATION OF ARTIFICIAL INTELLIGENCE DEVICES - Techniques that facilitate integration of artificial intelligence devices are provided. In one example, a device includes a first dual-damascene layer, a second dual-damascene layer and an artificial intelligence memory device. The first dual-damascene layer comprises a first set of copper connections formed in first dielectric material. The second dual-damascene layer that comprises a second set of copper connections formed in second dielectric material. The artificial intelligence memory device is integrated between the first dual-damascene layer and the second dual-damascene layer. A through-level via (TLV) electrical connection associated with the artificial intelligence memory device provides an interconnection between the first set of copper connections and the second set of copper connections. | 2020-04-30 |
20200135636 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion. | 2020-04-30 |
20200135637 | LINE SPACE, ROUTING AND PATTERNING METHODOLOGY - A method of manufacturing a semiconductor device including the operations of defining a first metal pattern (MX- | 2020-04-30 |
20200135638 | ELECTRONIC COMPONENT HAVING A TRANSISTOR AND INTERDIGITATED FINGERS TO FORM AT LEAST A PORTION OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT - An electronic component includes a part incorporating a transistor provided with a control electrode and with first and second electrodes. The electronic component includes first, second, and third electrical connection terminals extending on a connection face of the part incorporating the transistor, the first electrical connection terminal being electrically linked with the first electrode, the second electrical connection terminal being electrically linked with the second electrode and the third electrical connection terminal being electrically linked with the control electrode. The electronic component includes a first set of electrically conductive fingers and a second set of electrically conductive fingers, the fingers of the first and second sets of fingers being interdigitated, at the level of the connection face, to form at least a part of a capacitive component. The fingers of the first set of fingers are electrically linked to the first electrical connection terminal. | 2020-04-30 |
20200135639 | PLANE-LESS VOLTAGE REFERENCE INTERCONNECTS - An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads. | 2020-04-30 |