18th week of 2020 patent applcation highlights part 70 |
Patent application number | Title | Published |
20200135640 | INTEGRATED CIRCUIT INCLUDING SUPERVIA AND METHOD OF MAKING - An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line. | 2020-04-30 |
20200135641 | CONDUCTIVE FEATURES HAVING VARYING RESISTANCE - Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities. | 2020-04-30 |
20200135642 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a frame including wiring layers and having a recess portion in which a stopper layer is disposed on a bottom surface, a semiconductor chip having an active surface and an inactive surface, the inactive surface being disposed in the recess portion and facing the stopper layer, a first connection portion on the connection pad, a second connection portion on the uppermost wiring layer, a stiffener on the upper surface of the frame and surround at least a portion of the second connection portion, the stiffener being spaced apart from second connection portion, an encapsulant covering at least portions of each of the frame and the semiconductor chip, and filling at least a portion of the recess portion, and a connection structure on the frame and the semiconductor chip, and including a redistribution layer electrically connected to the first and second connection portions. | 2020-04-30 |
20200135643 | VIA SIZING FOR IR DROP REDUCTION - A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules. | 2020-04-30 |
20200135644 | INTEGRATED CIRCUIT STRUCTURE - An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width. | 2020-04-30 |
20200135645 | POWER DISTRIBUTION NETWORKS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES - Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers. | 2020-04-30 |
20200135646 | POWER DISTRIBUTION NETWORKS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES - Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers. | 2020-04-30 |
20200135647 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate. | 2020-04-30 |
20200135648 | SEMICONDUCTOR PACKAGE HAVING NONSPHERICAL FILLER PARTICLES - Semiconductor packages having nonspherical filler particles are described. In an embodiment, a semiconductor package includes a package substrate having a dielectric layer over an electrical interconnect. The dielectric layer includes nonspherical filler particles in a resin matrix. The nonspherical filler particles have an aspect ratio greater than one. | 2020-04-30 |
20200135649 | PACKAGE STRUCTURE, SEMICONDUCTOR PACAKGE AND METHOD OF FABRICATING THE SAME - A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the interconnect structure. | 2020-04-30 |
20200135650 | PHOTONICS INTEGRATED CIRCUIT PACKAGE - An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie. | 2020-04-30 |
20200135651 | PACKAGE STRUCTURE WITH BUMP - A package structure is provided. The package structure includes a redistribution layer and a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer. The package structure also includes first bumps electrically connected to the first integrated circuit chip through the redistribution layer. In addition, the first bumps overlap the first integrated circuit chip and are arranged along a first chip edge of the first integrated circuit chip. The package structure further includes second bumps electrically connected to the first integrated circuit chip through the redistribution layer without overlapping the first integrated circuit chip and the second integrated circuit chip. In addition, none of the second bumps is arranged between the first chip edge and the second chip edge. | 2020-04-30 |
20200135652 | CHIP PACKAGE WITH FAN-OUT STRUCTURE - A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a first dielectric layer over the semiconductor die and the protection layer. The first dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the first dielectric layer. In addition, the chip package includes a second dielectric layer over the conductive layer and filling some of the cutting scratches. Bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die. | 2020-04-30 |
20200135653 | STRUCTURE AND FORMATION METHOD OF PACKAGE STRUCTURE WITH FAN-OUT STRUCTURE - Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die. | 2020-04-30 |
20200135654 | SEMICONDUCTOR PACKAGE AND ANTENNA MODULE COMPRISING THE SAME - A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other. | 2020-04-30 |
20200135655 | Graphene Layer for Reduced Contact Resistance - A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material. | 2020-04-30 |
20200135656 | IC PACKAGE - Aspects of the disclosure provide an integrated circuit (IC) package. The IC package includes a package substrate, one or more IC chips, a marking plate and a plastic structure. The one or more IC chips are interconnected with the package substrate. The marking plate has a first major surface and a second major surface. The marking plate is stacked on the one or more IC chips with the first major surface facing the one or more IC chips. The plastic structure is configured to encapsulate the one or more IC chips and the marking plate with the second major surface of the marking plate being a portion of an outer surface of the IC package. | 2020-04-30 |
20200135657 | LOW FREQUENCY ELECTROMAGNETIC INTERFERENCE SHIELDING - A semiconductor package device includes a substrate, an insulation layer disposed on the substrate, and a shielding layer. The shielding layer includes an adhesive layer and a base layer. The adhesive layer is disposed between the base layer and the insulation layer. The adhesive layer and the base layer include a filler including at least a resin. The shielding layer passes a peeling test class of at least 3 B of a cross-cut method and the shielding effectiveness of the shielding layer is at least or equal to 30 dB. | 2020-04-30 |
20200135658 | Redistribution-Layer Fanout Package Stiffener - An apparatus may include a packaging substrate. The apparatus may further include multiple semiconductor devices attached to the packaging substrate, the multiple semiconductor devices defining a path along the packaging substrate between a pair of the multiple semiconductor devices. The apparatus may also include a stiffener structure coupled to the packaging substrate and positioned with a longitudinal axis of the stiffener structure being perpendicular to the path. | 2020-04-30 |
20200135659 | POST-PASSIVATION INTERCONNECT STRUCTURE - A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region. | 2020-04-30 |
20200135660 | METHOD OF MAKING PACKAGE ASSEMBLY INCLUDING STRESS RELIEF STRUCTURES - A method includes bonding a plurality of dies to a substrate. A first die of the plurality of dies is larger than a second die of the plurality of dies. The method includes adhering a first stress relief structure to the substrate. A distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method includes adhering a second stress relief structure to the substrate. A distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance. The first stress relief structure is discontinuous with respect to the second stress relief structure. | 2020-04-30 |
20200135661 | PACKAGE STRUCTURE - Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer. | 2020-04-30 |
20200135662 | MITIGATING MOISTURE-DRIVEN DEGRADATION OF FEATURES DESIGNED TO PREVENT STRUCTURAL FAILURE OF SEMICONDUCTOR WAFERS - Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic. | 2020-04-30 |
20200135663 | CUSTOMISATION OF AN INTEGRATED CIRCUIT DURING THE REALISATION THEREOF - A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function. | 2020-04-30 |
20200135664 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure. | 2020-04-30 |
20200135665 | Info Structure and Method Forming Same - A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package component. The portion of the encapsulating material is patterned to form an opening revealing a conductive feature in the package component. A redistribution line extends into the opening to contact the conductive feature. An electrical connector is formed over and electrically coupling to the conductive feature. | 2020-04-30 |
20200135666 | ESD PROTECTION IN AN ELECTRONIC DEVICE - According to one configuration, a fabricator produces an electronic device to include: a substrate; a transistor circuit disposed on the substrate; silicide material disposed on first regions of the transistor circuit; and the silicide material absent from second regions of the transistor circuit. Absence of the silicide material over the second regions of the respective of the transistor circuit increases a resistance of one or more parasitic paths (such as one or more parasitic transistors) in the transistor circuit. The increased resistance in the one or more parasitic paths provides better protection of the transistor circuit against electro-static discharge conditions. | 2020-04-30 |
20200135667 | COWOS INTERPOSER WITH SELECTABLE/PROGRAMMABLE CAPACITANCE ARRAYS - An interposer circuit includes a substrate and a dielectric layer that is disposed on top of the substrate. The interposer circuit includes two or more connection layers including a first connection layer and a second connection layer that are disposed at different depths in the dielectric layer. The interposer circuit includes a fuse that is disposed in the first connection layer. The first connection layer is coupled to a first power node and the second connection layer is coupled to a first ground node. The interposer circuit further includes a first capacitor that is in series with the fuse and is connected between the first and the second connection layers. The interposer circuit also includes first, second, and third micro-bumps on top of the dielectric layer such that the fuse is coupled between the first and second micro-bumps and the first capacitor is coupled between the second and third micro-bumps. | 2020-04-30 |
20200135668 | SEMICONDUCTOR DEVICE - This semiconductor device includes: a circuit substrate; a printed substrate disposed so as to face the circuit substrate; switching elements attached to the circuit substrate; a circuit impedance reduction element attached to the printed substrate; a first conductive post; a second conductive post; a first external connection terminal; and a second external connection terminal. The switching elements collectively have a first electrode and a second electrode. The circuit impedance reduction element includes a third electrode and a fourth electrode. A length of a current path between the first external connection terminal and the third electrode is shorter than a length of a current path between the first external connection terminal and the first electrode. A length of a current path between the second external connection terminal and the fourth electrode is shorter than a length of a current path between the second external connection terminal and the second electrode. | 2020-04-30 |
20200135669 | SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDCUTOR PACKAGE - A semiconductor package includes an encapsulated semiconductor device, a first redistribution structure, an insulating layer, and an antenna. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure is disposed on a first side the encapsulated semiconductor device and electrically connected to the semiconductor device. The insulating layer is disposed on a second side of the encapsulated semiconductor device and comprises a groove pattern. The antenna is filled the groove pattern, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer. | 2020-04-30 |
20200135670 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure. | 2020-04-30 |
20200135671 | FAN-OUT ANTENNA PACKAGING STRUCTURE AND PACKAGING METHOD - Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole. | 2020-04-30 |
20200135672 | LAND GRID ARRAY PATTERNS FOR MODULAR ELECTRONICS PLATFORMS AND METHODS OF PERFORMING THE SAME - Provided are methods, systems, and apparatuses related to modular electronics platforms for mobile computing devices. One such apparatus may include a system on module (SOM) having a first surface that is configured to be coupled electrically to one or more chipsets. The apparatus may include a land grid array (LGA) disposed on a second surface of the SOM. The LGA may include one or more center anchor pads, one or more corner anchor pads, a digital signal array, one or more communications pads, and one or more ground pads. The various pads of the LGA may be configured to be coupled to one or more pads or pins disposed on a surface of a main logic board (MLB). | 2020-04-30 |
20200135673 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - The present disclosure provides a method of fabricating an integrated fan-out package including the following steps. A semiconductor die is laterally encapsulated by an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor die, and the redistribution circuit structure is electrically connected to the semiconductor die. A forming method of the redistribution circuit structure includes the following steps. A conductive wiring is formed over the insulating encapsulant and the semiconductor die. A dielectric material is formed on the insulating encapsulant and the semiconductor die to cover the conductive wiring. A sacrificial layer is formed on the dielectric material, wherein a first top surface of the sacrificial layer is flatter than a second top surface of the dielectric material. The sacrificial layer and a portion of the dielectric material are removed until the conductive wiring is revealed to form a dielectric layer, wherein the conductive wiring is embedded in the dielectric layer. | 2020-04-30 |
20200135674 | Patterning Polymer Layer to Reduce Stress - A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer. | 2020-04-30 |
20200135675 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure. | 2020-04-30 |
20200135676 | SIDEWALL SPACER TO REDUCE BOND PAD NECKING AND/OR REDISTRIBUTION LAYER NECKING - In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure. | 2020-04-30 |
20200135677 | Metal-Bump Sidewall Protection - A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. | 2020-04-30 |
20200135678 | Protrusion Bump Pads for Bond-on-Trace Processing - An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. | 2020-04-30 |
20200135679 | SURFACE FINISHES WITH LOW RBTV FOR FINE AND MIXED BUMP PITCH ARCHITECTURES - Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV). | 2020-04-30 |
20200135680 | SEMICONDUCTOR PACKAGE STRUCTURE WITH CONDUCTIVE LAYER - A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer | 2020-04-30 |
20200135681 | POWER ELECTRONIC ASSEMBLIES WITH HIGH PURITY ALUMINUM PLATED SUBSTRATES - An assembly that includes a first substrate, a second substrate, and a stress mitigation layer disposed between the first and the second substrates. The stress mitigation layer is directly bonded onto the second substrate, and the second substrate is separated from the intermetallic compound layer by the stress mitigation layer. The stress mitigation layer has a high purity of at least 99% aluminum such that the stress mitigation layer reduces thermomechanical stresses on the first and second substrates. The assembly further includes an intermetallic compound layer disposed between the first substrate and the stress mitigation layer such that the stress mitigation layer is separated from the first substrate by the intermetallic compound layer. | 2020-04-30 |
20200135682 | SEMICONDUCTOR ELEMENT BONDING SUBSTRATE, SEMICONDUCTOR DEVICE, AND POWER CONVERSION DEVICE - A semiconductor element bonding substrate according to the present invention includes an insulating plate, and a metal pattern bonded to a main surface of the insulating plate. A main surface of the metal pattern on an opposite side of the insulating plate includes a bonding region to which a semiconductor element is bonded by a solder. The metal pattern includes at least one concave part located in the main surface. The at least one concave part is located closer to an edge of the bonding region in relation to a center part of the bonding region in the bonding region. | 2020-04-30 |
20200135683 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively. | 2020-04-30 |
20200135684 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively. | 2020-04-30 |
20200135685 | METHOD FOR DETERMINING BONDING PAD SPACING ON THE SURFACE OF BONDING WIRE CHIP - A method for determining a bonding pad spacing on the surface of a bonding wire chip includes the steps of setting a loop height (“K”); selecting a capillary, measuring an expansion angle of a capillary sharp mouth (“C”); measuring the diameter of the capillary sharp mouth (“T”); measuring the hole diameter of the capillary (“H”); and determining a bonding pad spacing on the surface of a bonding wire chip (“P”). The formula is as follows: P=(T+H)/2+[tan(C/2)]*K. This method more accurately determines bonding pad spacing on the surface of a bonding wire chip, thereby providing a wider performance adjustment space. Additionally, problems, such as mutual inductance abnormalities caused by wire deformation or even by short circuits with other circuits due to the contact between a packaged capillary and a bonded wire can be lowered, thereby improving the working efficiency and reducing the number of times verification is performed. | 2020-04-30 |
20200135686 | SEMICONDUCTOR DIE WITH MULTIPLE CONTACT PADS ELECTRICALLY COUPLED TO A LEAD OF A LEAD FRAME - The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire. | 2020-04-30 |
20200135687 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire. | 2020-04-30 |
20200135688 | APPARATUS AND METHOD FOR STACKING SEMICONDUCTOR DEVICES - A method of directly transferring a first semiconductor device die to a substrate includes loading a wafer tape into a first frame, loading a substrate into a second frame, arranging at least one of the first frame or the second frame such that a surface of the substrate is adjacent to a first side of the wafer tape, and orienting a needle to a position adjacent to a second side of the wafer tape, the needle extending in a direction toward the wafer tape. The method also includes activating a needle actuator connected to the needle to move the needle to a die transfer position at which the needle contacts the second side of the wafer tape to press the first semiconductor device die into contact with the second semiconductor device die. | 2020-04-30 |
20200135689 | WAFER-LEVEL PACKAGING METHODS USING A PHOTOLITHOGRAPHIC BONDING MATERIAL - A wafer-level packaging method using a photolithographic bonding material includes providing a base substrate; providing a plurality of first chips; forming a photolithographic bonding layer on the base substrate or on the first chips; forming a plurality of first vias in the photolithographic bonding layer; pre-bonding the first chips to the base substrate through the photolithographic bonding layer with each first chip corresponding to a first via; using a thermal compression bonding process to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate; etching the base substrate to form a plurality of second vias through the base substrate with each second via connected to a first via to form a first conductive via; and forming a first conductive plug in the first conductive via to electrically connect to a corresponding first chip. | 2020-04-30 |
20200135690 | METHODS FOR BONDING SUBSTRATES - Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate. | 2020-04-30 |
20200135691 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SOLDERING SUPPORT JIG - A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member. | 2020-04-30 |
20200135692 | SEMICONDCUTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device. | 2020-04-30 |
20200135693 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME - A semiconductor package structure includes a circuit build-up substrate, a chip, a plurality of conductive pillar, a molding layer and at least a memory module. The circuit build-up substrate has a first surface. A plurality of flip-chip bonding pads and a plurality of first bonding pads are exposed from the first surface. The chip is electrically connected to the flip-chip bonding pads. The conductive pillars are disposed on the first surface of the circuit build-up substrate and electrically connected to the first bonding pads. The molding layer is disposed on the first surface of the circuit build-up substrate to cover the chip and the conductive pillars. A second side of the chip and a first end of each conductive pillar are exposed from the molding layer. The memory module is disposed on the molding layer and electrically connected to the first end of the conductive pillar. | 2020-04-30 |
20200135694 | Three-Layer Package-on-Package Structure and Method Forming Same - A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die. | 2020-04-30 |
20200135695 | CHIP ON FILM PACKAGE - A chip on film package including a flexible film, a first patterned circuit layer, one or more first chips, a second patterned circuit layer, and one or more second chips. The flexible film includes a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The one or more first chips are mounted on the first surface and electrically connected to the first patterned circuit layer. The second patterned circuit layer is disposed on the second surface. The one or more second chips are mounted on the second surface and electrically connected to the second patterned circuit layer. | 2020-04-30 |
20200135696 | SEMICONDUCTOR MODULE - The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module | 2020-04-30 |
20200135697 | Power and Temperature Management for Functional Blocks Implemented by a 3D Stacked Integrated Circuit - A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die, a volatile memory die, a logic die, and a thermal management component. The non-volatile memory die, the volatile memory die, the logic die, and the thermal management component are stacked. The thermal management component can be stacked in between the non-volatile memory die and the logic die, stacked in between the volatile memory die and the logic die, or both. | 2020-04-30 |
20200135698 | DIE STACK STRUCTURE, SEMICONDUCTOR PACKAGE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold. | 2020-04-30 |
20200135699 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip. | 2020-04-30 |
20200135700 | MULTI-CHIP MODULE HAVING A STACKED LOGIC CHIP AND MEMORY STACK - An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip. | 2020-04-30 |
20200135701 | Integrated Circuit Chip Carrier with In-Plane Thermal Conductance Layer - An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover. | 2020-04-30 |
20200135702 | SEMICONDUCTOR MODULE - In a semiconductor module, two switching elements are connected in parallel to each other. Each of the switching elements includes a first main electrode formed on one surface side, and a second main electrode and a gate electrode formed on a rear surface side opposite to the one surface side. A first conductor plate is coupled with two first main terminals at first coupling portions and is electrically connected with the first main electrodes. A second conductor plate is coupled with one second main terminal at a second coupling portion and is electrically connected with the second main electrodes. The second coupling portion is disposed between the switching elements in an alignment direction of the switching elements, and the first coupling portions are provided on both sides of the second coupling portion in the alignment direction. | 2020-04-30 |
20200135703 | LIGHT FIELD DISPLAY FOR HEAD MOUNTED APPARATUS USING METAPIXELS - Embodiments disclosed herein include 3D displays with meta-surfaces and methods of forming such displays. In an embodiment, a display may comprise a display backplane substrate, and a light emission source on the display backplane substrate. In an embodiment, a meta-surface may be formed over the light emission source. In an embodiment, the meta-surface comprises a plurality of nano-features for modifying a path of light emitted by the light emission source. | 2020-04-30 |
20200135704 | Light emitting device with small size and large density - This application describes a light emitting device, an assembly of light emitting devices, a display comprising assemblies of light emitting devices, and methods of fabricating same. The light emitting device comprises a transistor, an LED that at least partially overlies the transistor, a reflector layer disposed between the LED and transistor, and conductive wires that connect electrically the transistor to the LED. The assembly comprises a plurality of light emitting devices, and the display comprises a plurality of assemblies. | 2020-04-30 |
20200135705 | Light-Emitting Semiconductor Chip, Light-Emitting Component and Method for Producing a Light-Emitting Component - A light-emitting semiconductor chip, a light-emitting component and a method for producing a light-emitting component are disclosed. In an embodiment a light-emitting semiconductor chip includes a light-transmissive substrate having a top surface, a bottom surface opposite the top surface, a first side and a second side surface arranged opposite the first side surface, a semiconductor body arranged on the top surface of the substrate and a contacting including a first current distribution structure and a second current distribution structure, wherein the first current distribution structure and the second current distribution structure are freely accessible from a side of the semiconductor body facing away from the substrate, and wherein the semiconductor chip, on the side of the semiconductor body facing away from the substrate and on the bottom surface of the substrate, is free of any connection point configured to electrically contact the first and second current distribution structures. | 2020-04-30 |
20200135706 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - Display devices and methods of fabricating display devices are provided. The display device includes a circuit board; a first light-emitting device array substrate mounted on the circuit board; and a second light-emitting device array substrate mounted on the circuit board adjacent the first light-emitting device array substrate in a first direction. The circuit board defines a groove that overlaps a boundary between the first light-emitting device array substrate and the second light-emitting device array substrate. | 2020-04-30 |
20200135707 | OPTICAL TRANSCEIVER AND MANUFACTURING METHOD THEREOF - An optical transceiver including a photonic integrated circuit component, an electric integrated circuit component and an insulating encapsulant is provided. The photonic integrated circuit component includes at least one optical input/output portion and at least one groove located in proximity of the at least one optical input/output portion. The electric integrated circuit component is disposed on and electrically connected to the photonic integrated circuit component. | 2020-04-30 |
20200135708 | PACKAGE STRUCTURE, DIE AND METHOD OF MANUFACTURING THE SAME - A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure. | 2020-04-30 |
20200135709 | SOLENOID INDUCTORS WITHIN A MULTI-CHIP PACKAGE - An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor. | 2020-04-30 |
20200135710 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material. | 2020-04-30 |
20200135711 | SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR - A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion. | 2020-04-30 |
20200135712 | IMPLANTABLE DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed is an implantable device including: a first insulation layer; a second insulation layer arranged on the first insulation layer; a first semiconductor layer arranged between the first and second insulation layers; a second semiconductor layer doped into the first semiconductor layer, with the second semiconductor layer forming a closed loop as seen in a top view; a metal layer disposed on the second insulation layer, with the metal layer forming an electrode; a third insulation layer covering the metal layer; and an insulation region including the first and second semiconductor layers. | 2020-04-30 |
20200135713 | TRENCH TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A trench transistor structure includes a substrate structure, a transistor device, and an electrostatic discharge (ESD) protection device. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. The transistor device is located in the first region and includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. The ESD protection device is located in the second region and includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other. | 2020-04-30 |
20200135714 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR - A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the high-side steering diode and/or the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the breakdown voltage of the TVS device is tailored by connecting two or more forward biased diodes in series. The low capacitance TVS device can be configured for unidirectional or bidirectional applications. In some embodiments, the TVS device includes a MOS-triggered silicon controlled rectifier as the high-side steering diode. The breakdown voltage of the TVS device can be adjusted by adjusting the threshold voltage of the MOS transistor. | 2020-04-30 |
20200135715 | SILICON-CONTROLLED RECTIFIERS WITH WELLS LATERALLY ISOLATED BY TRENCH ISOLATION REGIONS - Silicon-controlled rectifiers and methods for forming a silicon-controlled rectifier. A first well of a first conductivity type is arranged in a substrate, and second and third wells of a second conductivity type are arranged in the substrate between the first well and the top surface of the substrate. A deep trench isolation region is laterally arranged between the first well of the second conductivity type and the second well of the second conductivity type. The second well is adjoined with the first well along a first interface, the third well is adjoined with the first well along a second interface, and the deep trench isolation region extends the top surface of the substrate past the first interface and the second interface and into the first well. A doped region of the first conductivity type is arranged in the substrate between the second well and the top surface of the substrate. | 2020-04-30 |
20200135716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a guard active area formed in a substrate, a plurality of transistors disposed in an element area adjacent to the guard active area, each of the transistors including an active area and a gate structure crossing the active area, and a diode transistor disposed between a first transistor and a second transistor among the transistors, and having a diode gate structure connected to the guard active area, a first active area connected to a gate structure of the first transistor, and a second active area connected to a gate structure of the second transistor. | 2020-04-30 |
20200135717 | SEMICONDUCTOR DEVICE - A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a p | 2020-04-30 |
20200135718 | ARCHITECTURE FOR MONOLITHIC 3D INTEGRATION OF SEMICONDUCTOR DEVICES - A three-dimensional (3D) integrated circuit (IC) includes a substrate having a substrate surface, a power rail provided in the substrate, and a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate. A wiring tier is provided in the substrate, and a second tier of semiconductor devices is provided in the substrate and positioned over the wiring tier along the thickness direction. The second tier of semiconductor devices is stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices. A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices. A second vertical interconnect structure extends upward from the wiring tier to the second tier of semiconductor devices to electrically connect the wiring tier to a device within the second tier of semiconductor devices. | 2020-04-30 |
20200135719 | Functional Blocks Implemented by 3D Stacked Integrated Circuit - A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller. | 2020-04-30 |
20200135720 | 3D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO ACCELERATE ARTIFICIAL NEURAL NETWORK (ANN) COMPUTATION - A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a memory die having an array of memory partitions. Each partition of the array of memory partitions is configured to store parameters of a set of neurons. The 3D SIC also has a processing logic die having an array of processing logic partitions. Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data. | 2020-04-30 |
20200135721 | INTEGRATED CIRCUIT HAVING VERTICAL TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE INTEGRATED CIRCUIT - An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively. | 2020-04-30 |
20200135722 | APPARATUS AND CIRCUITS INCLUDING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND METHODS OF FABRICATING THE SAME - Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages. | 2020-04-30 |
20200135723 | FINFET STRUCTURE WITH DIELECTRIC BAR CONTAINING GATE TO REDUCE EFFECTIVE CAPACITANCE, AND METHOD OF FORMING SAME - A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate. | 2020-04-30 |
20200135724 | Integrated Circuit Device Including a Power Supply Line and Method of Forming the Same - A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line. | 2020-04-30 |
20200135725 | METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE - A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer. | 2020-04-30 |
20200135726 | Semiconductor Device Having Fins - A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin. | 2020-04-30 |
20200135727 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fin field effect transistor. The semiconductor device includes a first gate electrode, a first source/drain (S/D) region disposed adjacent to the first gate electrode, a first S/D contact disposed on the first S/D region, a first spacer layer disposed between the first gate electrode and the first S/D region, a first contact layer in contact with the first gate electrode and the first S/D contact, and a first wiring layer integrally formed with the first contact layer. There is no interface between the first contact layer and the first wiring layer in a cross sectional view, and the first contact layer has a smaller area than the first wiring layer in plan view. | 2020-04-30 |
20200135728 | SEMICONDUCTOR DEVICE - A semiconductor device includes a dielectric dummy gate, a plurality of first semiconductor fins, and a plurality of second semiconductor fins. The dielectric dummy gate extends along a first direction. The first semiconductor fins extend along a second direction within a first core circuit region on a first side of the dielectric dummy gate, and the second direction is substantially perpendicular to the first direction. The second semiconductor fins extend along the second direction within a second core circuit region on a second side of the dielectric dummy gate opposite the first side of the dielectric dummy gate. A number of the second semiconductor fins within the second core circuit region is less than a number of the first semiconductor fins within the first core circuit region, and each of the second semiconductor fins has a width less than a width of each of the first semiconductor fins. | 2020-04-30 |
20200135729 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH HYBRID FINS - A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance. | 2020-04-30 |
20200135730 | BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins. | 2020-04-30 |
20200135731 | SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND VEHICLE - A semiconductor integrated circuit includes a first MOS transistor, a second MOS transistor, and a P+ region. The first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which a first power supply voltage is supplied to the first N-type region. The second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which a second power supply voltage higher than the first power supply voltage is supplied to the third N-type region. The P+ region is supplied with the first power supply voltage. In plan view of the semiconductor substrate, the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and the P+ region is located between the first N-type region and the third N-type region. | 2020-04-30 |
20200135732 | DOUBLE RULE INTEGRATED CIRCUIT LAYOUTS FOR A DUAL TRANSMISSION GATE - Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate. | 2020-04-30 |
20200135733 | APPARATUS AND CIRCUITS WITH DUAL THRESHOLD VOLTAGE TRANSISTORS AND METHODS OF FABRICATING THE SAME - Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material. | 2020-04-30 |
20200135734 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other. | 2020-04-30 |
20200135735 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate. | 2020-04-30 |
20200135736 | ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES - A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer. | 2020-04-30 |
20200135737 | SEMICONDUCTOR STRUCTURE - Semiconductor structures are provided. A semiconductor structure includes a first P-type transistor including a first SiGe channel region, and a second P-type transistor including a second SiGe channel region. The first SiGe channel region has higher Ge atomic concentration than the second SiGe channel region. The first and second P-type transistors are formed in the same N-type well region. | 2020-04-30 |
20200135738 | High Density Vertical Thyristor Memory Cell Array with Improved Isolation - Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed. | 2020-04-30 |
20200135739 | DRAM Circuitry, And Integrated Circuitry - Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed. | 2020-04-30 |