18th week of 2022 patent applcation highlights part 71 |
Patent application number | Title | Published |
20220139734 | SUBSTRATE PROCESSING APPARATUS, MIXING METHOD, AND SUBSTRATE PROCESSING METHOD - A substrate processing method includes: generating a mixture liquid by mixing a phosphoric acid aqueous solution with an additive that suppresses precipitation of silicon oxide in a tank and circulating the mixture liquid through a circulation path that exits and returns to the tank, the circulation path including a back pressure valve; sending the mixture liquid to a processing bath through a liquid path diverging from the circulation path and positioned upstream from the back pressure valve; and supplying a silicon-containing compound aqueous solution to the mixture liquid generated in the generating. The back pressure valve is fully open in the generating and throttled in the sending. A substrate processing apparatus includes a processing bath, a mixing device, a liquid path, and a silicon solution supply. | 2022-05-05 |
20220139735 | DEVICE AND METHOD FOR BONDING OF TWO SUBSTRATES - A device, a system and a method for bonding two substrates. A first substrate holder has a recess and an elevation. | 2022-05-05 |
20220139736 | SEMICONDUCTOR PROCESSING SYSTEM INCLUDING TEMPERATURE CONTROLLER - A semiconductor processing system includes; a chamber, a substrate support disposed in the chamber, and a temperature controller including a thermal section disposed under the substrate support and a coupling section including at least one coupling section member. The thermal section includes a first plate and a second plate spaced apart under the substrate support, and each of the first plate and the second plate is coupled to a side portion of the substrate by at least one coupling section member. | 2022-05-05 |
20220139737 | TEMPERATURE SENSOR, HEATER UNIT, AND SUBSTRATE PROCESSING APPARATUS - There is provided a configuration installed on a mount provided with an opening, that includes a main body connected to the mount to penetrate the opening while providing a micro space; a first positioner attached to a side of a leading end portion of the main body with respect to the mount; and a second positioner attached to a side of a tail end portion of the main body with respect to the mount, wherein the main body is movable within a range determined by the micro space, the first positioner, and the second positioner. | 2022-05-05 |
20220139738 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - The inventive concept relates to a substrate treating apparatus including a process chamber having a first and a second body, a support unit supporting a substrate, a heating unit heats the substrate, a driver moves any one of the first body and the second body, an interval state detection unit that detects an interval state between a side wall of the first body and a side wall of the second body when the first and the second body are placed in a process location, and a controller that controls the driver and the interval state detection unit, wherein the interval state detection unit includes a pressure provision line that provides a positive pressure or a negative pressure between the side wall of the first body and the side wall of the second body, and a pressure measurement member that measures a change in a pressure of the pressure provision line. | 2022-05-05 |
20220139739 | APPARATUS FOR TRANSFERRING DIE IN BONDING EQUIPMENT AND METHOD THEREOF - An apparatus for transferring dies in bonding equipment includes an ejector configured to push up a die attached to a dicing tape, an ejector controller controlling the ejector to move up or move down, a gas passage disposed in the ejector and forming a gas channel for applying vacuum pressure or pneumatic pressure, a gas stream controller controlling the vacuum pressure or the pneumatic pressure through the gas passage, a tape suction unit disposed outside the ejector and suctioning the dicing tape using vacuum pressure, a picker suctioning and transferring the die from above, and a picker controller moving-up and moving down the picker. | 2022-05-05 |
20220139740 | CHAMBER INTERFACE FOR LINKED PROCESSING TOOLS - Embodiments described herein provide for link tools and linked processing systems having two or more processing tools connected by one or more link tools. Each arrangement of the link processing system includes adjacent processing tools coupled to a link chamber at the transfer modules at the backend of the processing tools. The backend coupling utilizes of floor space away from the factory interfaces of the processing tools. The link chambers have at least five facets. The system further includes two or more transfer vias. Each transfer via is coupled to a facet of the link chamber. The transfer vias are connectable to transfer modules of processing tools. The system further includes a link robot disposed in the link chamber operable to transfer one or more substrates between the transfer vias connectable to the transfer modules of the processing tools. | 2022-05-05 |
20220139741 | METHOD, DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR DETERMINING TIMING OF REMOVING SUBSTRATE FROM CASSETTE IN SUBSTRATE PROCESSING DEVICE, AND SUBSTRATE PROCESSING DEVICE - Provided is a method, device, and program for determining a timing of removing a substrate from a cassette in substrate processing device, and substrate processing device. In the method, a tentative removal time point of each substrate is calculated by adding a transfer time to a tentative removal time point of the one previous substrate, wherein the transfer time is required from the start of an action of removing a substrate from the cassette to the end of an action of delivering the substrate to an exchanger. | 2022-05-05 |
20220139742 | SYSTEM AND METHOD FOR OPERATING THE SAME - A system includes a cleaning device and a concentration measuring device. The cleaning device includes a first pipe and a first pump. The first pump is configured to move first liquid in the first pipe. Two terminals of the first pump are respectively coupled to the first pipe. The concentration measuring device includes a tube, a cooler, a concentration meter and a second pump. The tube is coupled to the first pipe, and is configured to retrieve the first liquid. The cooler covers the tube to cool the first liquid. The concentration meter is configured to measure a concentration of the first liquid cooled by the cooler. The second pump is coupled to the tube, and is configured to move the first liquid according to the concentration. | 2022-05-05 |
20220139743 | Optical Sensor for Inspecting Pattern Collapse Defects - An apparatus for detecting defects on a sample is provided. The apparatus includes a stage for receiving a sample to be inspected, and a first light source configured to generate an incident light beam to illuminate the sample on the stage. The first light source is configured to sequentially emit light of different wavelengths in wavelength sweeps. The apparatus also includes imaging optics for collecting light scattered from the sample and for forming a detection light beam, a detector for receiving the detection light beam and acquiring images of the sample, collection optics disposed within the detection light beam and configured to direct the detection light beam to the detector, and a first light modulator. The first light modulator is configured to filter out signals from the detection light beam, where the signals originate from uniform periodicity of uniformly repeating structures on the sample. | 2022-05-05 |
20220139744 | WAFER DEFECT ANALYSIS METHOD AND SYSTEM, DEVICE AND MEDIUM - Provided are a wafer defect analysis method and system, a device and a medium. The wafer defect analysis method includes: acquiring batch information and defect information of each wafer in a semiconductor manufacturing process, the defect information including hot spot defect information; setting a hot spot defect feature, and selecting target hot spot defect information associated with the hot spot defect feature from the hot spot defect information; tracking, according to the batch information, a first wafer corresponding to the target hot spot defect information associated with the hot spot defect feature, and determining a defect source. | 2022-05-05 |
20220139745 | Method of Manufacturing Semiconductor Device and Non-transitory Computer-readable Recording Medium - Described herein is a technique capable of detecting a substrate state without contacting the substrate. According to one aspect of the technique, there is provided (a) loading a substrate retainer, where a plurality of substrates is placed, into a reaction tube; (b) processing the plurality of the substrates by supplying a gas into the reaction tube; (c) unloading the substrate retainer out of the reaction tube after the plurality of the substrates is processed; and (d) detecting the plurality of the substrates placed on the substrate retainer after the substrate retainer is rotated by a first angle with respect to a transferable position, wherein the plurality of the substrates is transferable to/from the substrate retainer in the transferable position. | 2022-05-05 |
20220139746 | AIR PROCESSING SYSTEM FOR SEMICONDUCTOR CONTAINER - A container includes a container body and an air processing system. The container body includes a plurality of walls defining an interior space for receiving wafers. The air processing system is attached to the container body. The air processing system includes an exchange module, an air extraction module, a first contaminant removal module, a processing module, a second contaminant removal module, a controller module and a power module. The exchange module is coupled to one of the walls of the container body. The air extraction module extracts air from the container body. The first contaminant removal module is coupled to the air extraction module and the exchange module. The processing module is coupled to the air extraction module. The second contaminant removal module is coupled to the processing module and the exchange module. The controller module is configured to turn the air extraction module on and off. | 2022-05-05 |
20220139747 | DEVICE FOR SELF-ASSEMBLING SEMICONDUCTOR LIGHT-EMITTING DIODES - Discussed is a device for self-assembling semiconductor light-emitting diodes, the device including an assembly chamber having a space for accommodating a fluid; and a substrate chuck having a substrate support part configured to support a substrate, and a vertical moving part for lowering the substrate so that one surface of the substrate is in contact with the fluid in a state in which the substrate is supported by the substrate support part. | 2022-05-05 |
20220139748 | APPARATUS FOR TRANSFERRING LED - The present disclosure relates to an apparatus for transferring a light emitting diode (LED). The apparatus for transferring an LED includes: a pick-up unit configured to pick up at least some of multiple light emitting diodes (LEDs) arranged on one substrate, and, according to a received control signal, put down LEDs selected from among the picked-up LEDs on another substrate; and a controller configured to transmit the control signal to the pick-up unit so as to enable the pick-up unit to individually pick up or put down each of the multiple LEDs. | 2022-05-05 |
20220139749 | Wafer Transfer Module and Method Thereof for Transferring To-Be-Transferred Wafer - The present application relates to a wafer transfer module in a semiconductor manufacturing machine, relating to semiconductor integrated circuit manufacturing machines, wherein two sets of transmitter/receivers are provide on sidewalls of the wafer transfer module to monitor the travel position of an elevator, two sets of transmitter/receivers are provide on the sidewalls of the wafer transfer module to monitor the position of a transfer arm, a signal received by the receiver is transmitted to a control system such that the control system determines, according to the travel position of the elevator and the transfer arm position, whether the transfer arm can obtain a to-be-transferred wafer, thereby preventing the problem of a wafer scratch caused by an elevator position deviation or a transfer arm position deviation. | 2022-05-05 |
20220139750 | INTERFACE APPARATUS AND CONTAINER TRANSPORTING SYSTEM WITH THE APPARATUS - Provided are an interface apparatus for resolving congestion through a non-stop interface between a transporting device and a logistics automation storage device, and a container transporting system having the same. The interface apparatus includes a saddle for receiving a container from a container transporting device; and a circulating path for providing a route for transporting the container seated on the saddle to a container storage device, wherein the saddle receives the container while moving together with the container transporting device. | 2022-05-05 |
20220139751 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE AND CLAMP APPARATUS - A method for manufacturing a semiconductor package structure and a clamp apparatus are provided. The method includes: (a) providing a package body disposed on a chuck, wherein the package body includes at least one semiconductor element encapsulated in an encapsulant; (b) moving a pressing tool transversely to above the package body; and (c) pressing the package body on the chuck through the pressing tool. | 2022-05-05 |
20220139752 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method includes supplying a voltage to an electrode provided in an electrostatic chuck, thereby adsorbing a substrate onto an upper surface of the electrostatic chuck; after the voltage supplied to the electrode of the electrostatic chuck is stabilized, cutting off the supply of the voltage to the electrode, thereby bringing the electrode into a floating state; and after the voltage supplied to the electrode of the electrostatic chuck is stabilized, performing a predetermined processing with plasma on a surface of the substrate adsorbed onto the electrostatic chuck. | 2022-05-05 |
20220139753 | INSTALLATION FIXTURE FOR ELECTRODE PLATE OF SEMICONDUCTOR EQUIPMENT - The present disclosure relates to an installation fixture for an electrode plate of a semiconductor equipment. The installation fixture includes: an alignment assembly, including a support disc and at least two guide shafts, where the support disc is provided with at least two positioning holes, at least two fixing holes and at least two mounting holes; a drive assembly, including a mounting plate assembly, at least two support rods and a drive rod assembly, where the support rods are connected to the mounting plate assembly, and one end of each of the support rods is connected to one of the mounting holes; and the drive rod assembly is connected to the mounting plate assembly; and a support assembly, including at least two support bases, where each of the support bases is provided with a mounting groove. | 2022-05-05 |
20220139754 | PROTECTIVE FILM AGENT FOR LASER DICING - A protective film agent for laser dicing that includes a solution in which at least a water-soluble resin, an organic solvent, and an ultraviolet absorber are mixed and in which the content of sodium (Na) of the solution is equal to or lower than 100 ppb in weight ratio. Preferably, the solution further includes an antioxidant. | 2022-05-05 |
20220139755 | SEMICONDUCTOR MANUFACTURING APPARATUS AND CHIP HANDLING METHOD - A semiconductor manufacturing apparatus comprises an adsorption unit defining a plurality of pressing holes in the adsorption unit, the plurality of pressing holes configured to eject gas, and defining a plurality of suction holes in the adsorption unit, the plurality of suction holes configured to suction the gas and to handle a semiconductor chip through the gas. At least one of the suction holes is adjacent to at least one of an apex of the adsorption unit or an edge of the adsorption unit. | 2022-05-05 |
20220139756 | TRANSFER HAND AND SUBSTRATE PROCESSING APPARATUS - The inventive concept provides a transfer hand for transferring a substrate. The transfer hand for transferring the substrate comprises: a body; and a vacuuma assembly installed in the body and providing decompression to the bottom surface of a substrate to support the substrate at the upper part of the body; wherein the vacuum assembly comprises: an vacuum pad with conductivity contacting the substrate; and a sealing member provided between the vacuum pad and the body, the sealing member electrically connected to the vacuum pad; wherein the sealing member is grounded. | 2022-05-05 |
20220139757 | WAFER FRAME SORTER AND STOCKER - A wafer sorting and stoking system provides automated storage and retrieval of wafer frames carrying semiconductor wafers. A wafer frame cassette is received at a transfer port from a transfer system. A robot arm retrieves the wafer frames from the cassette and stores each wafer frame in a respective storage slot in one of a plurality of storage towers. The storage location of each wafer frame is recorded. Each wafer frame can be selectively retrieved and loaded into a wafer frame cassette by the robot arm for further processing. | 2022-05-05 |
20220139758 | MULTI-WAFER DEPOSITION TOOL FOR REDUCING RESIDUAL DEPOSITION ON TRANSFER BLADES AND METHODS OF OPERATING THE SAME - A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages. | 2022-05-05 |
20220139759 | SUBSTRATE HOLDER, SUBSTRATE TRANSFER DEVICE, AND METHOD OF MANUFACTURING SUBSTRATE HOLDER - There is provided a substrate holder. The substrate holder that holds a substrate and is installed in a device for transferring the substrate. The substrate holder includes: a ceramic main body; and a heat pipe which includes a flow path of a working fluid. The flow path is formed inside the main body. | 2022-05-05 |
20220139760 | SUBSTRATE PROCESSING APPARATUS, SUSCEPTOR COVER, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING METHOD - According to one aspect of the technique in the disclosure, there is provided a substrate processing apparatus including: a process chamber in which a substrate is accommodated; a susceptor configured to support the substrate in the process chamber; and a susceptor cover provided on an upper surface of the susceptor, wherein the susceptor includes: a heating element; and a first through-hole located so as to avoid the heating element, and the susceptor cover includes a second through-hole communicating with the first through-hole and having a diameter greater than a diameter of the first through-hole. | 2022-05-05 |
20220139761 | LOAD LOCK DEVICE - A load lock device includes a load lock chamber, and a substrate holding structure configured to hold a substrate in the load lock chamber, wherein the substrate holding structure includes a facing surface facing the substrate, and is configured to allow a gas to flow through a space between the substrate and the facing surface, and in a state in which the substrate is held by the substrate holding structure, a distance between the substrate and a portion located inside an outer edge of the facing surface is larger than a distance between the substrate and the outer edge of the facing surface. | 2022-05-05 |
20220139762 | TRANSISTOR STRUCTURE WITH AIR GAP AND METHOD OF FABRICATING THE SAME - A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer. | 2022-05-05 |
20220139763 | FORMING METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - A forming method for a semiconductor structure and the semiconductor structure are provided. The forming method of the semiconductor structure includes: providing a substrate, wherein separate bit line structures are formed on the substrate; forming a first sacrificial layer on a sidewall of a bit line structure; forming first dielectric layer filling gaps between adjacent bit line structures; patterning a first dielectric layer to form vias, wherein the vias expose active regions of the substrate, and the vias and remaining parts of the first dielectric layers are alternately arranged in an extension direction of the bit line structures; forming a second sacrificial layer on sidewalls of a via, and filling the via to form a contact plugs; forming a contact structure on the contact plug; and removing the first sacrificial layer to form first air gap, and removing the second sacrificial layer to form a second air gap. | 2022-05-05 |
20220139764 | ISOLATION STRUCTUE AND MANUFACTURING METHOD THEREOF - A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions. | 2022-05-05 |
20220139765 | FLOWABLE CHEMICAL VAPOR DEPOSITION OF METAL OXIDES - Exemplary deposition methods may include introducing a vapor of a metal alkoxide into a processing volume of a semiconductor processing chamber. A substrate defining a trench may be housed in the processing volume. The methods may include condensing the vapor into a liquid metal alkoxide within the trench on the substrate. The methods may include forming a plasma external to the processing volume of the semiconductor processing chamber. The methods may include introducing plasma-generated species into the processing volume. The methods may include exposing the liquid metal alkoxide in the trench to the plasma-generated species. The methods may also include forming a metal oxide film in the trench through a reaction between the liquid metal alkoxide and the plasma-generated species. | 2022-05-05 |
20220139766 | GAP-FILL LAYERS, METHODS OF FORMING THE SAME, AND SEMICONDUCTOR DEVICES MANUFACTURED BY THE METHODS OF FORMING THE SAME - A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer. | 2022-05-05 |
20220139767 | SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFER - Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers. | 2022-05-05 |
20220139768 | METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - A method for fabricating a semiconductor-on-insulator structure involves providing a donor substrate comprising a weakened zone delimiting a layer to be transferred, providing a receiver substrate, and bonding the donor substrate to the receiver substrate. The layer to be transferred is located on the bonding-interface side. A bonding wave is initiated at a first region on the periphery of the interface, and the wave is propagated toward a second region on the periphery of the interface opposite the first region. The difference in speed of propagation of the bonding wave between a central portion of the interface and a peripheral portion of the interface is controlled such that the speed of propagation of the bonding wave is lower in the central portion than in the peripheral portion. The donor substrate is detached along the weakened zone to transfer the layer to be transferred to the receiver substrate. | 2022-05-05 |
20220139769 | FABRICATION METHOD OF METAL-FREE SOI WAFER - Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer. | 2022-05-05 |
20220139770 | HIGH-TRANSPARENCY SEMICONDUCTOR-METAL INTERFACES - Techniques that can facilitate high-transparency semiconductor-metal interfaces are provided. In one example, a method can comprise forming a silicon on insulator (SOI) over a wafer. The method can further comprise depositing a metal on the SOI. The method can further comprise forming a structure by dry-etching the metal and dry-etching the SOI. The method can further comprise forming a template over the structure. The method can further comprise etching a portion of the SOI for removal under the metal. The method can further comprise growing a semiconductor where the portion of SOI was removed. | 2022-05-05 |
20220139771 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure includes a first die, a second die over the first die, and a positioning member disposed within a bonding dielectric and configured to align the second die with the first die. A method for forming a semiconductor structure includes receiving a first die having a first bonding layer; forming a recess on the first bonding layer; forming a positioning member on a second die; bonding the second die over the first die using the first bonding layer; and disposing the positioning member into the recess. | 2022-05-05 |
20220139772 | INTERCONNECT STRUCTURES WITH AREA SELECTIVE ADHESION OR BARRIER MATERIALS FOR LOW RESISTANCE VIAS IN INTEGRATED CIRCUITS - Integrated circuit interconnect structures including an interconnect metallization feature with a liner material of a greater thickness between a fill metal and dielectric material, and of a lesser thickness between the fill metal and a lower-level interconnect metallization feature. The liner material may be substantially absent from an interface between the fill metal and the lower-level interconnect metallization feature. Liner material of reduced thickness at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive liner material that may enhance the scalability of interconnect structures. In some embodiments, liner material is deposited upon dielectric surfaces with an area selective atomic layer deposition process. For single damascene implementations, both a via and a metal line may include a selectively deposited liner material. | 2022-05-05 |
20220139773 | SELF-ALIGNED BARRIER FOR METAL VIAS - An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure. | 2022-05-05 |
20220139774 | Integrated Circuit Package and Method - In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings. | 2022-05-05 |
20220139775 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH ULTRA-THIN METAL CHALCOGENIDE BARRIER MATERIALS - Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer. | 2022-05-05 |
20220139776 | METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH A LOW-RESISTIVITY METAL - A method for filling recessed features with a low-resistivity metal includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, and depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature. The method further includes removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature, where the removing includes exposing the patterned substrate to an etching gas containing ozone. | 2022-05-05 |
20220139777 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTERVENING LAYER - A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer | 2022-05-05 |
20220139778 | MANUFACTURING METHOD OF CONTACT STRUCTURE - A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer. | 2022-05-05 |
20220139779 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies. | 2022-05-05 |
20220139780 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - The following are performed in this method for producing a semiconductor device: a step for forming multiple surface electrode metals joined to a surface of a semiconductor layer on a wafer on which multiple semiconductor devices are attached; a step for excavating a semiconductor layer outside an outer edge of the surface electrode metal to form an outermost edge trench of the semiconductor device; a dicing step for cutting out individual semiconductor devices from the wafer; and a kerf check performed after the dicing step by checking the distance from the outermost edge trench to the chip outline position of the semiconductor device. | 2022-05-05 |
20220139781 | SYSTEMS AND METHODS FOR MANUFACTURING FLEXIBLE ELECTRONICS - Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank. | 2022-05-05 |
20220139782 | METHOD FOR MANUFACTURING MOS TRANSISTORS COMPRISING DIELECTRIC SPACERS AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes metal-oxide-semiconductor “MOS” transistors formed on a semiconductor substrate. The MOS transistors have gate stacks belonging to at least one gate stack category and dielectric regions of sidewall spacers on the sides of the gate stacks. At least a first MOS transistor has a gate stack of said at least one gate stack category that includes dielectric regions of sidewall spacers having a first width. At least a second MOS transistor has a gate stack of the same gate stack category with dielectric regions of sidewall spacers having a second width different from the first width. | 2022-05-05 |
20220139783 | METHOD FOR DESIGNING THREE DIMENSIONAL METAL LINES FOR ENHANCED DEVICE PERFORMANCE - A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening. | 2022-05-05 |
20220139784 | METHOD OF SIMULTANEOUS SILICIDATION ON SOURCE AND DRAIN OF NMOS AND PMOS TRANSISTORS - A method and apparatus for the formation of a metal-oxide semiconductor FET (MOSFET) device is disclosed herein. The method of formation includes the utilization of a silicon-germanium seed layer deposited over an n-channel metal-oxide semiconductor (NMOS) device and a p-channel metal-oxide semiconductor (PMOS) device. The seed layer may be one seed layer deposited over both the NMOS source/drain regions and the PMOS source/drain regions or two doped seed layers wherein a first doped seed layer is deposited over the PMOS source/drain regions and a second doped seed layer is deposited over the NMOS source/drain regions. The seed layer enables simultaneous formation of a silicide over both the PMOS source/drain regions and the NMOS source/drain regions. The silicide formation consumes the seed layer and forms a silicide layer which varies in composition depending upon the composition of the absorbed seed layer. | 2022-05-05 |
20220139785 | FABRICATING METHOD OF DECREASING HEIGHT DIFFERENCE OF STI - A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed. | 2022-05-05 |
20220139786 | HIGH PRECISION 3D METAL STACKING FOR A PLURALITY OF 3D DEVICES - Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include providing a substrate. The substrate can include a first type region and a second type region. The method can also include forming a multilayer stack on the substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming first and second openings through the multilayer stack to uncover the first and second type regions, respectively. The method can also include forming first and second vertical channel structures within the first and second openings, respectively. Each of the first and second vertical channel structures can have source, gate and drain regions being in contact with vertical sidewalls of the metal layers of the multilayer stack uncovered by a respective one of the first and second openings. | 2022-05-05 |
20220139787 | FINFET COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICES - A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins. | 2022-05-05 |
20220139788 | DIMENSION MEASUREMENT APPARATUS, DIMENSION MEASUREMENT PROGRAM, AND SEMICONDUCTOR MANUFACTURING SYSTEM - The disclosure relates to a dimension measurement apparatus that reduces time required for dimension measurement and eliminates errors caused by an operator. Therefore, the dimension measurement apparatus uses a first image recognition model that extracts a boundary line between a processed structure and a background over the entire cross-sectional image and/or a boundary line of an interface between different kinds of materials, and a second image recognition that output information for dividing the boundary line extending over the entire cross-sectional image obtained from the first image recognition model for each unit pattern constituting a repetitive pattern, obtains coordinates of a plurality of feature points defined in advance for each unit pattern, and measures a dimension defined as a distance between two predetermined points of the plurality of feature points. | 2022-05-05 |
20220139789 | PACKAGE STRUCTURE AND MEASUREMENT METHOD FOR THE PACKAGE STRUCTURE - The present disclosure provides a measurement method including providing a base, a device disposed on the base, and a lid disposed over the base and the device; irradiating a top surface of the device through an opening of the lid to obtain a first focal plane associated with a top surface of the device; irradiating the lid at the lower end of the opening to obtain a second focal plane associated with the lid at the lower end of the opening; and deriving a distance between the top surface of the device and an interior surface of the lid facing the top surface of the device based on a difference between a level of the first focal plane and a level of the second focal plane. The present disclosure also provides a package structure for the measurement. | 2022-05-05 |
20220139790 | SEMICONDUCTOR DEVICE WITH TESTING STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first testing area, a word line structure positioned in the first testing area and arranged parallel to a first axis, a first column of capacitor contact structures positioned in the first testing area and arranged parallel to a second axis perpendicular to the first axis, a second column of capacitor contact structures positioned adjacent to the first column of capacitor contact structures and arranged parallel to the first column of capacitor contact structures, and a first testing structure including a first drain portion extended along the second axis and a first source portion extended along the second axis. The first drain portion is positioned on the first column of capacitor contact structures and the first source portion is positioned on the second column of capacitor contact structures. | 2022-05-05 |
20220139791 | METHODS AND SYSTEMS FOR TRANSPOSITION CHANNEL ROUTING - Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route. | 2022-05-05 |
20220139792 | ELECTRONIC SUBSTRATES HAVING HETEROGENEOUS DIELECTRIC LAYERS - An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate. | 2022-05-05 |
20220139793 | POWER SEMICONDUCTOR DEVICES WITH IMPROVED OVERCOAT ADHESION AND/OR PROTECTION - A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed. | 2022-05-05 |
20220139794 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - The present invention relates to a semiconductor device including: a semiconductor substrate having: an active region through which a main current flows; and a termination region around the active region; a polyimide film disposed in the active region and the termination region; and a passivation film disposed as a film underlying the polyimide film, wherein the termination region includes, in order from a side of the active region, a breakdown voltage holding region and an outermost peripheral region, the polyimide film is disposed except for a dicing remaining portion of the outermost peripheral region, and the passivation film is disposed, as the underlying film, at least in a region where the polyimide film is disposed. | 2022-05-05 |
20220139795 | SEMICONDUCTOR DEVICE - A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface; a dielectric film on the first main surface, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in a first outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion; a first electrode layer on the electrode layer disposing portion; a first protective layer covering a second outer peripheral end of the first electrode layer and at least a part of the protective layer covering portion; and a second protective layer covering the first protective layer, wherein the first protective layer has a relative permittivity lower than that of the second protective layer, and the second protective layer has moisture resistance higher than that of the first protective layer. | 2022-05-05 |
20220139796 | ON-DIE THERMAL MANAGEMENT FOR VLSI APPLICATIONS - Apparatus and methods are provided for managing operations of a semiconductor chip. In an exemplary embodiment, there is provided a semiconductor chip that may comprise a temperature sensor, a thermal heater, a processor and thermal control logic. The thermal control logic may be configured to: determine that a first temperature read-out from the temperature sensor reaches a first temperature threshold value, turn on the thermal heater, determine that a second temperature read-out from the temperature sensor reaches a second temperature threshold value that is lower than the first temperature threshold value, suspend functions of the processor, determine that a third temperature read-out from the temperature sensor reaches the first temperature threshold value, resume the functions of the processor, determine that a fourth temperature read-out from the temperature sensor reaches a third temperature threshold value that is higher than the first temperature threshold value and turn off the thermal heater. | 2022-05-05 |
20220139797 | SEMICONDUCTOR MODULE, POWER SEMICONDUCTOR MODULE, AND POWER ELECTRONIC EQUIPMENT USING THE SEMICONDUCTOR MODULE OR THE POWER SEMICONDUCTOR MODULE - The semiconductor module includes: a heat dissipation board including first to third wiring patterns; a first metal plate on the first wiring pattern, a second metal plate on the second wiring pattern, a first semiconductor chip and a first intermediate board which are on the first metal plate, a second semiconductor chip and a second intermediate board which are on the second metal plate. A first metal film on the first intermediate board is electrically connected to the first semiconductor chip and the second metal plate, and a second metal film on the second intermediate board is electrically connected to the second semiconductor chip and the third wiring pattern. | 2022-05-05 |
20220139798 | Method of Forming a Chip Package, Method of Forming a Semiconductor Arrangement, Chip Package, and Semiconductor Arrangement - A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material. | 2022-05-05 |
20220139799 | CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME - A chip-on-film package includes a base film including an upper surface and a lower surface that opposite from each other, a semiconductor chip mounted on the upper surface of the base film, a heat emission layer disposed on the lower surface of the base film to at least partially overlap the semiconductor chip in a thickness direction, an insulating layer disposed on a lower surface of the heat emission layer, and a protective layer surrounding side and lower surfaces of the insulating layer. Accordingly, thermal fatigue of the chip-on-film package may be reduced, and reliability may be increased. | 2022-05-05 |
20220139800 | HEAT DISSIPATION SHEET, MANUFACTURING METHOD OF HEAT DISSIPATION SHEET, AND ELECTRONIC APPARATUS - A heat dissipation sheet includes a first sheet composed of a plurality of first carbon nanotubes, and a second sheet composed of a plurality of second carbon nanotubes, wherein the first sheet and the second sheet are coupled in a stacked state, and the first carbon nanotubes and the second carbon nanotubes are different in an amount of deformation when pressure is applied. | 2022-05-05 |
20220139801 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. The semiconductor structure includes: a fin heat-dissipation region on a substrate; a fin channel part on the fin heat-dissipation region, and an isolation structure on the substrate. A width of the fin channel part is smaller than a width of the fin heat-dissipation region. A top surface of the isolation structure is coplanar with a top surface of the fin heat-dissipation region. | 2022-05-05 |
20220139802 | ADHESIVE AND THERMAL INTERFACE MATERIAL ON A PLURALITY OF DIES COVERED BY A LID - Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM. | 2022-05-05 |
20220139803 | SEMICONDUCTOR DEVICE - In this semiconductor device, a positioning protrusion is formed at a side surface of a sealing resin from which one end of a main electrode wire protrudes. Thus, the outer size of the sealing resin can be reduced as compared to a case where a positioning protrusion is formed at the bottom of the sealing resin. In addition, a thickness regulating protrusion is provided with a space from solder. Thus, it is possible to prevent interface separation or crack that would occur starting from a contact part between the thickness regulating protrusion and the solder, whereby the life of a joining part between a semiconductor module and a cooler can be ensured. Accordingly, a semiconductor device having enhanced heat dissipation property and reliability is obtained without increase in the outer size of the semiconductor module. | 2022-05-05 |
20220139804 | MOBILE PHONE AND OTHER COMPUTE DEVICE COOLING ARCHITECTURE - A system for cooling a mobile phone and method for using the system are described. The system includes an active piezoelectric cooling system, a controller and an interface. The active piezoelectric cooling system is configured to be disposed in a rear portion of the mobile phone distal from a front screen of the mobile phone. The controller is configured to activate the active piezoelectric cooling system in response to heat generated by heat-generating structures of the mobile phone. The interface is configured to receive power from a mobile phone power source when the active piezoelectric cooling system is activated. | 2022-05-05 |
20220139805 | SEMICONDUCTOR DEVICE WITH ETCH STOP LAYER HAVING GREATER THICKNESS AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with an etch stop layer having greater thickness and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor die including a first conductive layer, a first etch stop layer positioned on the first conductive layer, a second semiconductor die including a second conductive layer positioned above the first etch stop layer, a second etch stop layer positioned on the second conductive layer, a first through substrate via positioned along the second semiconductor die and the first etch stop layer, extended to the first semiconductor die, and positioned on the first conductive layer, and a second through substrate via extended to the second semiconductor die, positioned along the second etch stop layer, and positioned on the second conductive layer. A thickness of the second etch stop layer is greater than a thickness of the first etch stop layer. | 2022-05-05 |
20220139806 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads. | 2022-05-05 |
20220139807 | PACKAGE AND MANUFACTURING METHOD THEREOF - A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant. | 2022-05-05 |
20220139808 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF, AND THREE-DIMENSIONAL INTEGRATED CIRCUIT - A semiconductor apparatus includes a substrate and a through silicon via (TSV) structure; a groove is disposed on the substrate; the TSV structure is disposed on the substrate; and a first end of the TSV structure is exposed in the groove, and a distance between an end surface of the first end and a bottom wall of the groove is smaller than the depth of the groove. The first end of the TSV structure is exposed so as to facilitate heat dissipation; the distance between the end surface of the first end and the bottom wall of the groove is smaller than the depth of the groove, i.e., the first end of the TSV structure is sunken in the groove, and other structures will not be affected. | 2022-05-05 |
20220139809 | DEVICE TOPOLOGIES FOR HIGH CURRENT LATERAL POWER SEMICONDUCTOR DEVICES - A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die. | 2022-05-05 |
20220139810 | DEVICE TOPOLOGY FOR LATERAL POWER TRANSISTORS WITH LOW COMMON SOURCE INDUCTANCE - Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area. | 2022-05-05 |
20220139811 | Three Level Interconnect Clip - An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad. | 2022-05-05 |
20220139812 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer. | 2022-05-05 |
20220139813 | SEMICONDUCTOR DEVICE - A semiconductor device includes: first and second semiconductor elements, each of which has first and second electrodes; a first lead mounting the first semiconductor element; a second lead mounting the second semiconductor element; a sealing resin covering the first and second semiconductor elements; a third lead disposed apart from the first and second leads in a y direction, exposed from the sealing resin, and electrically connected to the first electrode of the first semiconductor element; a fifth lead disposed apart from the first and second leads on the opposite side to the third lead, exposed from the sealing resin, and electrically connected to the second electrode of the first semiconductor element; and a sixth lead disposed apart from the first and second leads on the same side as the fifth lead, exposed from the sealing resin, and electrically connected to the second electrode of the second semiconductor element. | 2022-05-05 |
20220139814 | ELECTRONIC PACKAGE WITH PASSIVE COMPONENT BETWEEN SUBSTRATES - An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component. | 2022-05-05 |
20220139815 | SEMICONDUCTOR DEVICE AND METHOD MANUFACTURING THEREOF - The present disclosure relates to a semiconductor device and a method manufacturing thereof. The object of the present disclosure is to simplify manufacturing steps of a semiconductor device. A semiconductor device of the present disclosure includes an organic film electrically insulative and penetrated by a through hole in a thickness direction, a conductive layer formed on the organic film and made of a copper (Cu)-based and titanium (Ti)-free alloy, a Cu wiring layer formed on the conductive layer, a semiconductor element mounted on the Cu wiring layer, a sealing resin sealing the semiconductor element, and an external terminal connected to the conductive layer. The conductive layer includes the exposed conductive portion exposed from the organic film by entering the through hole. The external terminal is in contact with the exposed conductive portion. | 2022-05-05 |
20220139816 | ORGANIC INTERPOSER INCLUDING INTRA-DIE STRUCTURAL REINFORCEMENT STRUCTURES AND METHODS OF FORMING THE SAME - An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level. | 2022-05-05 |
20220139817 | BALL GRID ARRAY PACKAGE AND PACKAGE SUBSTRATE THEREOF - A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes. | 2022-05-05 |
20220139818 | Process for Manufacturing a Chip-Card Module with Soldered Electronic Component - Process for manufacturing a chip-card module. It includes one or more operations in which a meltable solder is deposited on connection pads formed in a layer of electrically conductive material located on the back side of a dielectric substrate, and at least one electronic component is connected to these connection pads by reflowing the solder. Chip-card module obtained using this process. Chip card including such a module. | 2022-05-05 |
20220139819 | CAPACITOR STRUCTURE FOR INTEGRATED CIRCUIT AND RELATED METHODS - Embodiments of the disclosure provide a capacitor for an integrated circuit (IC). The capacitor may include a first vertical electrode on an upper surface of a first conductor within a first wiring layer. A capacitor dielectric may be on an upper surface of the first vertical electrode. A second vertical electrode may be on an upper surface of the capacitor dielectric. The second vertical electrode is vertically between the capacitor dielectric and a second conductor. An inter-level dielectric (ILD) layer is adjacent to each of the first vertical electrode, the capacitor dielectric, and the second vertical electrode. The ILD layer is vertically between the first conductor and the second conductor. | 2022-05-05 |
20220139820 | MIM CAPACITOR STRUCTURES - An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first area between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first area. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode. | 2022-05-05 |
20220139821 | SEMICONDUCTOR DEVICE AND MASSIVE DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel. | 2022-05-05 |
20220139822 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor fin, a gate structure, a capacitor structure, a conductive contact, and a hard mask layer. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer. The conductive contact is disposed on the capacitor structure. The hard mask layer laterally surrounds the conductive contact. The conductive contact protrudes from a top surface of the hard mask layer. | 2022-05-05 |
20220139823 | SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer. | 2022-05-05 |
20220139824 | WIRING PACKAGE AND METHOD OF MANUFACTURING THE SAME - At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer. | 2022-05-05 |
20220139825 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor. | 2022-05-05 |
20220139826 | FISHBONE STRUCTURE ENHANCING SPACING WITH ADJACENT CONDUCTIVE LINE IN POWER NETWORK - A method of generating a power network layout is provided. A first conductive line, generated by a processor, is in a first conductive layer along a first direction. A plurality of second conductive lines, generated by a processor, is in a second conductive layer along a second direction, substantially vertical to the first direction. The second conductive lines overlap with the first conductive line. A first plurality of interlayer vias, generated by a processor, is interposed between the first conductive layer and the second conductive layer at where the second conductive lines overlapping the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing. | 2022-05-05 |
20220139827 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor structure and a method of fabricating the same is disclosed. The semiconductor device includes a conductive structure that comprises: an upper conductive line arranged above and in electrical connection with a circuit component in a lower device layer through a via plug, wherein the upper conductive line extends laterally over the via plug; an interposing layer having a substantially uniform thickness arranged between the via plug and the upper conductive line, and extending laterally beyond a planar projection of the via plug, wherein the upper conductive line is in electrical connection with the via plug through the interposing layer; and an overlayer is disposed over the upper conductive line. | 2022-05-05 |
20220139828 | CONDUCTIVE FEATURES HAVING VARYING RESISTANCE - Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities. | 2022-05-05 |
20220139829 | INTEGRATED CIRCUIT DEVICE AND FORMATION METHOD THEREOF - Disclosed are an integrated circuit device and a formation method thereof. The formation method of an integrated circuit device comprises the following steps: providing a substrate, wherein a first plug and a second plug are disposed inside the substrate; forming a first covering layer covering the substrate; forming, in the first region, a first opening exposing the first plug; forming a first conductive layer in the first opening; forming an isolation layer covering the first conductive layer and the first covering layer; forming, in the first region, a contact hole exposing the first conductive layer and a trench located above the contact hole and connecting with the contact hole, and forming, in the second region, a second opening exposing the second plug; and forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse wire in the second opening. | 2022-05-05 |
20220139830 | ADJUSTMENT METHOD AND DEVICE FOR CHIP OUTPUT CHARACTERISTICS - An adjustment method for the chip output characteristics can include the following steps. When adjusting the output characteristics of the chip to be tested, first it is determined whether the output characteristics of the chip to be tested have been adjusted according to the state of each E-fuse. When determining that the output characteristics of the chip to be tested have not been adjusted, the target adjustment solution corresponding to the chip is determined among a plurality of adjustment solutions in a targeted manner according to the output performance of the chip to be tested. The E-fuse in the chip to be tested is subjected to blowing treatment according to the target adjustment solution, so as to adjust the output characteristics of the chip to be tested. | 2022-05-05 |
20220139831 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug. | 2022-05-05 |
20220139832 | WIRING STRUCTURES AND VERTICAL MEMORY DEVICES INCLUDING THE SAME - A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths. | 2022-05-05 |
20220139833 | INTERCONNECTION STRUCTURE LINED BY ISOLATION LAYER - A semiconductor device includes: a first conductive structure that comprises a first portion having sidewalls and a bottom surface, wherein the first conductive structure is embedded in a first dielectric layer; and an isolation layer comprising a first portion and a second portion, wherein the first portion of the isolation layer lines the sidewalls of the first portion of the first conductive structure, and the second portion of the isolation layer lines at least a portion of the bottom surface of the first portion of the first conductive structure. | 2022-05-05 |