19th week of 2009 patent applcation highlights part 19 |
Patent application number | Title | Published |
20090115392 | SWITCHING REGULATOR - A switching regulator includes a step-down-and-step-up unit to convert an input voltage to a low voltage or to a high voltage in accordance with a control signal, and a controller including a low-pass filter to receive a reference voltage generated in accordance with an external control signal. The controller causes the step-down-and-step-up unit to perform a step-down operation or a step-up operation in accordance with a voltage difference between a proportional voltage proportional to an output voltage of the step-down-and-step-up unit and the reference voltage. The controller further causes the step-down-and-step-up unit to perform a step-down operation or a step-up operation in accordance with a voltage difference between an output voltage of the low-pass filter and the proportional voltage, and changes a time constant of the low-pass filter in accordance with the operation being performed. | 2009-05-07 |
20090115393 | PHOTOVOLTAIC POWER GENERATION CONTROLLER AND POWER EVALUATION METHOD IN PHOTOVOLTAIC POWER GENERATION CONTROL - A photovoltaic power generation controller, in which minute power change is detected even with a low-resolution AD converter, thereby being capable of performing maximum power point tracking control with high accuracy, is provided. In the photovoltaic power generation controller of the invention, a control circuit | 2009-05-07 |
20090115394 | Semiconductor integrated circuit - A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other. | 2009-05-07 |
20090115395 | POWER SUPPLY SYSTEM - A power supply system includes a power supply unit, a conductive wire group and a voltage converter. The conductive wire group consists of a numbers of wires and extends from the power supply unit to electrically connect the voltage converter. The voltage converter can electrically connect at least a working element. Therefore, a first supply voltage is provided from the power supply unit to the voltage converter via the wires, the voltage converter converts the first supply voltage into a second supply voltage for the working element. | 2009-05-07 |
20090115396 | Communicating with an Implanted Wireless Sensor - The present invention determines the resonant frequency of a sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency or set of frequencies and a predetermined amplitude. The energizing signal is coupled to the sensor via magnetic coupling and induces a current in the sensor which oscillates at the resonant frequency of the sensor. The system receives the ring down response of the sensor via magnetic coupling and determines the resonant frequency of the sensor, which is used to calculate the measured physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal. | 2009-05-07 |
20090115397 | Preventing False Locks in a System That Communicates With an Implanted Wireless Sensor - The present invention determines the resonant frequency of a wireless sensor by adjusting the phase and frequency of an energizing signal until the frequency of the energizing signal matches the resonant frequency of the sensor. The system energizes the sensor with a low duty cycle, gated burst of RF energy having a predetermined frequency. The system receives the ring down response of the sensor and determines the resonant frequency of the sensor, which is used to calculate a physical parameter. The system uses a pair of phase locked loops to adjust the phase and the frequency of the energizing signal. The system identifies false locks by detecting an unwanted beat frequency in the coupled signal, as well as determining whether the coupled signal exhibits pulsatile characteristics that correspond to a periodic physiological characteristic, such as blood pressure. | 2009-05-07 |
20090115398 | Device And Method For Measuring A First Voltage And A Second Voltage By Means Of A Differential Voltmeter - The invention relates to a method and a device for measuring a first voltage and a second voltage by means of a differential voltmeter. The differential voltmeter comprises a first inlet and a second inlet and a known voltage potential is applied to the second inlet. The voltage measurement comprises the following; a first voltage is applied to a first inlet of the differential voltmeter, a first differential voltage is measured, the first voltage from the measured first differential voltmeter and the known voltage potential is determined, the second voltage is applied to the second inlet of the differential voltmeter, a second differential voltage is measured, and the second voltage from the measured second differential voltage and the previously determined first voltage is determined. | 2009-05-07 |
20090115399 | Shielded Current Sensor - A planar magnetic current sensor is described, incorporating a number of features designed to improve the efficiency and reliability of the basic sensor. The improvements comprise providing inner and outer conductive shields, an increased number of sensor elements for a given circuit board area, and distributing the resistance of the sensor circuitry. | 2009-05-07 |
20090115400 | Status indicator - The sensitivity and accuracy of a status indicator for sensing a current in an electrical circuit is improved by shifting the reference level of the transformer output to maximize the input signal to a precision voltage detector and by reducing the hysteresis of the status indicator by balancing the burden of the current transformer during the positive and negative alternations of the AC signal and by driving secondary loads with a voltage to current converter. | 2009-05-07 |
20090115401 | System comprising an automotive fuse and an A/D converter - The invention relates to a system which comprises an automotive fuse and an A/D converter. Conventional systems comprising an automotive fuse and an A/D converter are designed such that a measured value is generated at the automotive fuse, which value is then amplified and passed on to the A/D converter via a long signal line. The novel space-saving system is characterized in that the A/D converter is located in close vicinity to the automotive fuse. The automotive fuse supplies the non-amplified, analog measured value for the input of the A/D converter. Signal transmission is carried out digitally via a bus system. It is especially advantageous if all components are housing in a common housing. Signal transmission is then carried out digitally via a bus system. The inventive system is suitable for use in data bus systems of vehicles. | 2009-05-07 |
20090115402 | VOLTAGE DETECTING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A voltage detecting circuit detects a voltage between first and second wirings, and comprises at least first and second transistors connected in series between the first and second wirings, wherein a first reference voltage is supplied to a gate of the first transistor, a gate and a drain of the second transistor are short-circuited, and a detection signal is output from a connection point between a drain of the first transistor and a source of the second transistor. | 2009-05-07 |
20090115403 | Split core status indicator - The size of a status indicator for monitoring a current in a power cable is reduced by integrating a bobbin for the secondary winding with a current transformer core and integrating a circuit board including output terminals with a current transformer assembly. | 2009-05-07 |
20090115404 | HALL EFFECT METHODS AND SYSTEMS - A hall effect system in accordance with one embodiment is described herein. The hall effect system comprises a housing, an input element coupled to the housing, a magnetic element coupled to the input element and configured to have a detectable magnetic flux, a sensing element adjacent to the magnetic element, the sensing element being configured to sense the magnetic flux, and a processing element coupled to the sensing element and configured to determine a position of the magnetic element relative to the sensing element be determining changes in and/or the orientation of the magnetic flux upon movement of the interface element by a user. | 2009-05-07 |
20090115405 | Magnetic field angular sensor with a full angle detection - An integrated angular magnetic sensor apparatus for determining a magnetic field angle within two axes of a plane is formed on a substrate onto which two anisotropic magneto-resistive sensing elements and at least one magneto-resistive sensing element are fabricated. The two anisotropic magneto-resistive sensing elements are oriented such that the output voltages of a first and second of the anisotropic magneto-resistive sensing elements are a function of a first and second trigonometric function (a sine function) of the magnetic field angle to a reference axis. The at least one magneto-resistive sensing element on the substrate and having a fixed reference magnetization oriented with respect to the reference axis such that an output voltage of the at least one magneto-resistive sensing element provides a quadrant indicator for the magnetic field angle with respect to the reference axis. The quadrant indicator is a trigonometric function such as a sine or cosine function. | 2009-05-07 |
20090115406 | SYSTEM AND METHOD FOR MINIMIZING MUTUAL INDUCTANCE COUPLING BETWEEN COILS IN AN ELECTROMAGNETIC TRACKING SYSTEM - A system and method of minimizing the mutual inductance coupling between two or more coils of a coil array of an electromagnetic tracking system. The system involves a geometric arrangement of two or more coils, which significantly reduces any mutual inductance coupling between the two or more coils. The method involves characterization of two or more coils and compensating for mutual inductance coupling between the characterized two or more coils. | 2009-05-07 |
20090115407 | MOVABLE BODY POSITION DETECTING DEVICE - Disclosed is a technique for detecting the failure of a device without depending on A computer. | 2009-05-07 |
20090115408 | METHOD AND APPARATUS TO MONITOR POSITION OF A ROTATABLE SHAFT - A rotatable shaft is equipped with a measurement device that generates output signals corresponding to discrete angular positions of the shaft. Rotational angles of the shaft are measured for a complete rotational period. A true angular velocity of the shaft is determined. Angular velocity is calculated between contiguous pairs of the discrete angular positions. A velocity correction is determined, and a rotational angle error term is determined based upon the velocity correction. | 2009-05-07 |
20090115409 | MAGNETIC ENCODER - A high-precision magnet encoder in which high-order harmonic components can be suppressed without increasing the number of lead wires connecting magnetic field detecting elements to a signal processing circuit. Hall sensors of phase A | 2009-05-07 |
20090115410 | EDDY CURRENT PROBE AND METHODS OF ASSEMBLING THE SAME - A method of assembling an eddy current array probe to facilitate nondestructive testing of a sample is provided. The method includes positioning a plurality of differential side mount coils at least partially within a flexible material. The method also includes coupling the flexible material within a tip portion of the eddy current array probe, such that the flexible material has a contour that substantially conforms to a portion of a surface of the sample to be tested. | 2009-05-07 |
20090115411 | FLEXIBLE EDDY CURRENT ARRAY PROBE AND METHODS OF ASSEMBLING THE SAME - A method of assembling an eddy current probe for use in nondestructive testing of a sample is described. The method includes positioning at least one substantially planar spiral drive coil within the eddy current probe, such that the drive coil is at least one of adjacent to and at least partially within a flexible material. The method further includes coupling at least one unpackaged solid-state magnetic field sensor to the at least one drive coil. | 2009-05-07 |
20090115412 | Magnetic sensing device and electronic compass using the same - [Object] To provide a magnetic sensing device that can obtain the strength of an external magnetic field under circumstances where a relatively strong disturbance takes place, and an electronic compass using the same. | 2009-05-07 |
20090115413 | DEVICE AND METHOD FOR PARALLEL MAGNETIC RESONANCE IMAGING - The invention relates to a device ( | 2009-05-07 |
20090115414 | PHASE-SENSITIVELY DETECTED REDUCED DIMENSIONALITY NUCLEAR MAGNETIC RESONANCE SPECTROSCOPY FOR RAPID CHEMICAL SHIFT ASSIGNMENT AND SECONDARY STRUCTURE DETERMINATION OF PROTEINS - The present invention discloses eleven reduced dimensionality (RD) triple resonance nuclear magnetic resonance (NMR) experiments for measuring chemical shift values of certain nuclei in a protein molecule, where the chemical shift values encoded in a peak pair of an NMR spectrum are detected in a phase sensitive manner. The RD 3D | 2009-05-07 |
20090115415 | SYSTEM AND METHOD FOR USE OF NANOPARTICLES IN IMAGING AND TEMPERATURE MEASUREMENT - This invention provides a system and method that improves the sensitivity and localization capabilities of Magnetic Particle Imaging (MPI) by using combinations of time-varying and static magnetic fields. Combinations of magnetic fields can be used to distribute the signals coming from the magnetic particles among the harmonics and other frequencies in specific ways to improve sensitivity and to provide localization information to speed up or improve the signal-to-noise ratio (SNR) of imaging and/or eliminate the need for saturation fields currently used in MPI. In various embodiments, coils can be provided to extend the sub-saturation region in which nanoparticles reside; to provide a static field offset to bring nanoparticles nearer to saturation; to introduce even and odd harmonics that can be observed; and/or to introduce combinations of frequencies for more-defined observation of signals from nanoparticles. Further embodiments provide for reading of the signal produced by cyclically saturated magnetic nanoparticles in a sample so as to provide a measurement of the temperature of those nanoparticles. The spectral distribution of the signal generated provides estimates of the temperature of the nanoparticles. Related factors may also be estimated—binding energies of the nanoparticles, phase changes, bound fraction of the particles or stiffness of the materials in which the nanoparticles are imbedded. | 2009-05-07 |
20090115416 | Method of and apparatus for in-situ measurement of degradation of automotive fluids and the like by Micro-Electron Spin Resonance (ESR) spectrometry - A method of and miniaturized apparatus adapted for in-situ measurement of degradation of automotive fluids and the like by micro-electron spin resonance (ESR) spectrometry, wherein the use of a modulated constant magnetic field in an RF resonating variable frequency microwave cavity resonator through which a fluid sample is passed, enables direct detection of molecular changes in such fluid sample resulting from fluid degradation during use. | 2009-05-07 |
20090115417 | Three dimensional RF coil structures for field profiling - In one illustrative embodiment, a radio frequency (RF) coil is disclosed. The RF coil may include a plurality of transmission line elements, wherein at least one of the plurality of transmission line elements may have at least one dimension different than a dimension of another one of the plurality of transmission line elements. In some cases, each of the transmission line elements may include a signal line conductor and a ground plane conductor separated by a dielectric. | 2009-05-07 |
20090115418 | MAGNETIC RESONANCE COIL COMPOSED OF RELATIVELY MOVABLE CONSTITUENT ELEMENTS - A magnetic resonance coil has an antenna portion for accommodating a body part to be examined, the antenna portion is formed by a number of constituent units connected in series, the positions between various constituent units are relatively movable. By moving the positions between the constituent units, a portion of the area between at least two constituent units overlaps. By increasing or reducing the number of the constituent units, or by adjusting the overlapped area between the constituent units, one pair or a number of pairs of the constituent units are made to overlap completely, so as to achieve the adjustment of the size of the antenna portion to accommodate a body part to be examined, and to make said antenna portion as close as possible to the body part to be examined, so as to obtain a signal with a relatively high signal-to-noise ratio, and to obtain a relatively high imaging quality. | 2009-05-07 |
20090115419 | APPARATUS FOR ESTIMATING CHARGED STATE OF ON-VEHICLE BATTERY - An apparatus is provided to estimate a charged state of a vehicle provided with an internal combustion engine having a crankshaft, a starter that initially rotates the crankshaft when the engine is started, and a battery that powers the starter. The apparatus comprises a detection device and an acquisition device. The detection device detects a voltage of the battery and a discharge current from the battery for a period of time over time instants before and after starting the engine. The acquisition device acquires information indicative of an amount of the discharge current from the battery when the detected voltage of the battery becomes a minimum due to starting the engine. | 2009-05-07 |
20090115420 | METHOD AND SYSTEM FOR DETERMINING A STATE OF CHARGE OF A BATTERY - Methods and systems are provided for determining a state of charge of a battery. A magnetic force between the battery and a magnet is detected. The state of charge of the battery is determined based on the detected magnetic force. | 2009-05-07 |
20090115421 | Battery gauge for trolling motor - Battery Gauge for Trolling Motor is a gauge for measuring the amount of voltage remaining in a boat battery. The preferred embodiment of the invention utilizes a gauge having a scale, a battery level indicator, cables and cable terminals to connect to battery terminals. To use the preferred embodiment of Battery Gauge for Trolling Motor, an individual would attach the cable terminals to the battery terminals of a boat using the securing wingnut. The battery level indicator can then be monitored on the gauge to determine when the battery power is at a critical level. Ideally, the gauge would be placed on the trolling motor, near the boat battery housing or on the dash of the boat. | 2009-05-07 |
20090115422 | JIG FOR DETECTING POSITION - A transfer point of a transfer arm is detected accurately and stably by using a position detecting wafer having an electrostatic capacitance sensor. A position detecting wafer S is formed in a wafer shape transferable by a transfer arm | 2009-05-07 |
20090115423 | ELECTRODE CONTACT PELLET AND ASSOCIATED PHOTOIONISATION DETECTOR ASSEMBLY - A demountable pellet is disclosed for use as an electrode contact assembly. The pellet comprises a base | 2009-05-07 |
20090115424 | PRESSURE TANK FAULT DETECTOR AND METHOD - A pressure tank fault detector and method provides a system for detecting a fault in a pressure tank, such as a well water tank. The system includes a current transformer positioned adjacent a pump power wire. A circuit includes a timer, a data recorder, and a system status indicator. When the pump operates, the current transformer sends a signal to the circuit and the timer measures the signal duration. The data recorder logs a short cycle when the timer measures less than a selectable predetermined amount of time. When two or more short cycles are recorded, a signal indicates that a tank fault has been detected. Preferably, the system includes a test circuit and permits a user to select the number of short cycles before the alarm and whether to record only consecutive short cycles. Optionally, the system detects and signals pump cycles that exceed a predetermined excessive run time. | 2009-05-07 |
20090115425 | Drive System and Method for Final Testing of an Electronic Domestic Appliance and Electronic Domestic Appliance Having the Drive System - A drive system is provided for an electronic domestic appliance, for example a washing machine, a dryer or a dishwasher, having an electric motor and a motor controller for controlling operation of the electric motor. The motor controller is provided with a testing device which contains at least one apparatus for measuring motor currents of the electric motor, an apparatus for applying voltages to motor terminals of the electric motor, and an interface to an evaluation apparatus. The drive system can be tested without problems and at minimal cost during final testing of the domestic appliance if the drive system is fully integrated in the domestic appliance. A method for final testing of an electronic domestic appliance having a drive system and an electronic domestic appliance having the drive system, are also provided. | 2009-05-07 |
20090115426 | Faulted circuit indicator apparatus with transmission line state display and method of use thereof - The invention provides a faulted circuit indicator apparatus with transmission line state display, as well as methods for using the apparatus. The faulted circuit indicator has a sensor that can be electrically coupled to an electrical conductor for collecting data relating to a state of the electrical conductor. The faulted circuit indicator also has a controller that is logically coupled to the sensor for receiving data and determining whether a fault condition has occurred on the electrical conductor. The faulted circuit indicator also has one or more indicators that are logically coupled to the controller for indicating whether a fault condition has occurred as well as the state of the electrical conductor. The state of the conductor may be the voltage, the temperature, or the vibration present on the conductor. | 2009-05-07 |
20090115427 | System and Method For Determining The Impedance of a Medium Voltage Power Line - A system and method of detecting changes in the impedance of a segment of medium voltage power line is provided. In one embodiment, the method comprises receiving voltage data comprising data of the voltage of the power lines at locations at a plurality of different points in time, receiving current data that comprises data of the current flowing between adjacent locations at the plurality of points in time, intermittently determining an impedance of the power lines between adjacent locations based on the voltage data and current data, monitoring the impedance of the power lines between adjacent locations over time, and providing a notification of a change in the impedance of a power line between adjacent locations upon detection of a change in the impedance beyond a threshold change. | 2009-05-07 |
20090115428 | SINGLE PIN MULTI-STATE IDENTIFIER USING RC TIMING ELEMENT - In a circuit identifier, an electrical circuit includes an output node to output an electrical signal. A resistor device and a capacitor device, electrically in series with the resistor device, receive at least a portion of the electrical signal. A counter device determines a time for the capacitor device to reach a predetermined charge and assigns a value to the time for the capacitor device to reach the predetermined charge. A processor or other system reads the value assigned by the counter device and identifies the capacitor from a predetermined list of capacitors. The identification of the capacitor identifies a revision of the circuit. | 2009-05-07 |
20090115429 | Simultaneous Detection of In-Plane and Out-Of-Plane Position Displacement With Capacitive Sensors - An apparatus includes a first capacitive sensor connected to a first supply voltage, a second capacitive sensor connected to a second supply voltage, a sensing circuit for producing a sense voltage in response to current flowing in the first and second capacitive sensors, a first mixer for combining the sense voltage with a first reference voltage to produce a first signal representative of in-plane displacement between electrodes of the first and second capacitive sensors, and a second mixer for combining the sense voltage with a second reference voltage to produce a second signal representative of out-of-plane displacement between the electrodes of the first and second capacitive sensors. | 2009-05-07 |
20090115430 | SENSOR - A sensor including a carrier having two channels, a capacitive sensing element disposed on the carrier, and a cover is provided. The capacitive sensing element has a membrane, and a first chamber is formed between the membrane and the carrier. The cover is disposed on the carrier for covering the capacitive sensing element. A second chamber is formed between the membrane and the cover. The first chamber and the second chamber are located at two sides of the membrane, and the channels are respectively communicated with the first chamber and the second chamber. | 2009-05-07 |
20090115431 | Capacitive position sensor - A capacitive touch sensor is provided having sensing path for setting a color parameter to a desired value within a range, the color parameter being color hue, color saturation or color temperature. The sensor has a first mode of operation in which a parameter can be set approximately to a desired value and a second mode in which the value can be refined to the exact amount. In the first mode, the full range of possible values is mapped onto the sensing path and a user touch selects a value within the full range according to its position along the sensing path. In the second mode a finer adjustment is provided for, either by mapping a narrower sub-range of the full range onto the sensing path, or by allowing incremental adjustment of the parameter from the value initially set in the first mode, each incremental unit of adjustment being triggered by the object being displaced through a pre-determined threshold displacement along the sensing path. Switching from the first mode to the second mode is triggered if moving displacement of the object along the sensing path from the first point of touch exceeds a minimum threshold value. This provides an intuitive transition for the user from coarse to fine adjustment. | 2009-05-07 |
20090115432 | ELASTIC BODY, ELECTROSTATIC CAPACITANCE FORCE SENSOR AND ELECTROSTATIC CAPACITANCE ACCELERATION SENSOR - The invention provides an elastic body that reduces the cost of manufacture, has high deformation stability and excellent restoration capability, and is easy to be formed, a force sensor and an acceleration sensor equipped with said elastic body. | 2009-05-07 |
20090115433 | Method for Locating Leaks In Pipes - Method for establishing and possibly locating leaks in pipelines ( | 2009-05-07 |
20090115434 | Sample Cell for Hand-Held Impedance Spectroscopy Device - Disclosed herein is a sample cell for use in conjunction with an impedance spectroscopy analysis device having two electrodes extending therefrom. The sample cell is attachable to and detachable from the analysis device and includes a housing having an input port for receiving a fluid sample to be tested. The sample cell also includes two spaced apart parallel plates within the housing and in contact with the fluid sample, wherein when the sample cell is attached to the analysis device, each of the two electrodes contacts a respective one of the plates such that an excitation signal can be provided from the analysis device via the electrodes and the plates to excite the fluid sample, and a response signal indicative of the fluid sample can be communicated via the plates and the electrodes to the analysis device. | 2009-05-07 |
20090115435 | Processing System and Method for Hand-Held Impedance Spectroscopy Analysis Device for Determining Biofuel Properties - Disclosed herein is a hand-held impedance spectroscopy analysis device for analyzing fluids wherein the impedance spectroscopy device is in communication with a sample cell including a reservoir containing a fluid sample, the sample cell including a sample cell circuit and two metal plates in contact with the fluid sample and in contact with a pair of electrodes. The analysis device includes a processing system including a main processor which is responsive to commands from a user input device, and a data acquisition circuit which receives power and command signals from the processing system. The data acquisition circuit is operable to transmit excitation signals to the electrodes, wherein the excitation signals are applied at each frequency in a predetermnined set of frequencies, and the data acquisition circuit is further operable to receive response signals from the electrodes indicative of the fluid sample at each frequency in the predetermined set of frequencies and to convert the response signals into a magnitude and phase angle data set. The main processor is operable to receive the magnitude and phase angle data set from the data acquisition circuit and to receive at least one of calibration information and temperature information from the sample cell circuit and perform an impedance spectroscopy algorithm using the magnitude and phase angle data set and the information from the sample cell circuit to determine a fluid property. | 2009-05-07 |
20090115436 | Methods for Determining Fluid Properties - Disclosed herein is a method for determining two or more properties of a blended biofuel fluid sample, the method comprising measuring a complex impedance of the sample at each of a plurality of frequencies to produce a sample data set, determining a biofuel blend percentage of the sample using the sample data set; and determining at least one additional property of the sample based upon the determined biofuel blend percentage. In another aspect, a biofuel blend percentage of the sample can be determined using an algorithm developed using a data gathering and data mining technique relating measured impedance spectroscopy data from a plurality of samples to biofuel blend percentage values determined using a standard analytical measuring method for biofuel blend percentages. | 2009-05-07 |
20090115437 | HIGH TEMPERATURE RANGE ELECTRICAL CIRCUIT TESTING - An electrical circuit testing assembly that includes a mechanical reference that is relatively stationary as compared to a circuit under test. A probe support assembly is coupled to the mechanical reference and includes probes for contacting interconnect pads on the circuit under test. Optionally, the probe support structure is attached to the mechanical reference via a column that is thermally resistive. Also optionally, a testing circuitry support structure (e.g., a printed circuit board) is not rigidly attached to the mechanical reference or to the probe support structure, thereby permitting the testing circuitry support structure to float with respect to the probe support structure. | 2009-05-07 |
20090115438 | REMANUFACTURE OF ELECTRONIC ASSEMBLIES - A method for remanufacturing an electronic assembly allows the assembly to be disassembled, tested and reassembled despite certain components being permanently affixed to a housing of the assembly. The electronic assembly includes a circuit assembly within the housing. During remanufacture, a first portion of the housing is removed to expose a first side of the circuit assembly and a second portion of the housing is removed to expose a second side of the circuit assembly. When removing the second portion of the housing, one of the components of the circuit assembly may also be removed. During remanufacture a connector assembly including a replacement component substantially similar to the removed component, and including one or more pins connected to the replacement component and situated to mate with one or more empty sockets of the circuit assembly is used to facilitate testing of the assembly. | 2009-05-07 |
20090115439 | Methods for making contact device for making connection to an electronic circuit device and methods of using the same - Improved contact devices and methods for producing contact devices and using such contact devices to produce electronic devices are disclosed. A contact device having a plurality of nominally coplanar first contact elements makes electrical contact with corresponding nominally coplanar second contact elements of an electronic device such an integrated circuit or liquid crystal or other display when the contact device and the electronic device are positioned so that the plane of the first contact elements is substantially parallel to the plane of the second contact elements and relative displacement of the devices is effected in a direction substantially perpendicular to the plane of the first contact elements and the plane of the second contact elements. The contact device preferably consists of a stiff substrate having a major portion with fingers projecting therefrom in cantilever fashion, each finger having a proximal end at which it is connected to the major portion of the substrate and an opposite distal end and there being one or two contact elements on the distal end of each finger. | 2009-05-07 |
20090115440 | TESTING INTEGRATED CIRCUITS - A testing apparatus for a radiation sensing integrated circuit comprises a load board ( | 2009-05-07 |
20090115441 | PROBE CARD AND TEMPERATURE STABILIZER FOR TESTING SEMICONDUCTOR DEVICES - One aspect of the invention provides an apparatus that includes a probe card [ | 2009-05-07 |
20090115442 | Semiconductor integrated circuit and electronic device - A dummy wiring | 2009-05-07 |
20090115443 | SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUIT MODULES COMPRISING A PLURALITY OF INTEGRATED CIRCUIT DEVICES - Embodiments of a system and method for testing an integrated circuit module comprising multiple integrated circuit devices, such as a memory module comprising multiple memory devices for example, is disclosed. Embodiments of the method may be employed to test an integrated circuit device of the integrated circuit module that provides a data strobe signal associated with at least one data signal provided by the same integrated circuit device. A determination of a test outcome for the integrated circuit module may be made after identifying data valid windows for each integrated circuit device, without having to both identify a common sampling window defined by an intersection of the identified data valid windows and verify that such common sampling window meets specification requirements, as may be performed by conventional testers. | 2009-05-07 |
20090115444 | ANISOTROPIC CONDUCTIVE SHEET, ITS PRODUCTION METHOD, CONNECTION METHOD AND INSPECTION METHOD - Provided is an anisotropic conductive sheet ( | 2009-05-07 |
20090115445 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 2009-05-07 |
20090115446 | Measurement method of the current-voltage characteristics of photovoltaic device, a solar simulator for the measurement, and a module for setting irradiance and a part for adjusting irradiance used for the solar simulator - [Problem] In a solar simulator for measuring the current-voltage characteristics of photovoltaic devices, it is to provide a measurement method using a solar simulator in which locative unevenness of irradiance on the test plane of the test plane side is drastically improved, not in a light source side, and a means for adjusting irradiance and the like. | 2009-05-07 |
20090115447 | Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit - A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state. | 2009-05-07 |
20090115448 | Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver. | 2009-05-07 |
20090115449 | ON DIE TERMINATION DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes. | 2009-05-07 |
20090115450 | Circuit and method for controlling termination impedance - A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled. | 2009-05-07 |
20090115451 | CONFIGURABLE AND REUSABLE NAND SYSTEM - A configurable and reusable hardware-software NAND system adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics. A device identification signature is decoded from a NAND device in a NAND system; the device identification signature signal is analyzed to obtain a control phase sequence value descriptive of a characteristic of the NAND device; the control phase register is populated with the control phase sequence value; and control phase register provides the control phase sequence values to the command sequencer. The control phase register can be programmed by a low level driver for devices which NAND system cannot decode the device identification signature. | 2009-05-07 |
20090115452 | LOGIC BLOCK CONTROL SYSTEM AND LOGIC BLOCK CONTROL METHOD - The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the like is used. | 2009-05-07 |
20090115453 | IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER - An electronic integrated circuit includes a signal path connected between the functional logic ( | 2009-05-07 |
20090115454 | Method and System for Reducing Power Consumption with Configurable Latches and Registers - Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation. | 2009-05-07 |
20090115455 | VOLTAGE LEVEL TRANSLATION - A virtual zero delay unidirectional high voltage logic to low voltage CMOS logic voltage level translator can be achieved using a capacitive voltage divider coupled with the standard protection diodes commonly incorporated in low side logic (e.g. Xilinx Spartan-3E FPGA's). The complete voltage level translator will work equally well on frequencies from DC up to the rated operational frequency of the driver and receiver. Load side parasitic CMOS input capacitance in this case is ironically an asset rather than a liability since it can be used effectively as one element of the capacitive voltage divider. High voltage logic (e.g. 0 to 5V) can thus interface to lower voltage CMOS logic (e.g. 2.5V or 3.3V) with a minimum of additional external components and with virtually zero time delay. | 2009-05-07 |
20090115456 | Level shift circuit and method for the same - The present invention discloses a level shift circuit which comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of one of the second operational voltage levels according to a voltage level switching at the first node. | 2009-05-07 |
20090115457 | Apparatus and Methods for Self-Biasing Differential Signaling Circuitry Having Multimode Output Configurations for Low Voltage Applications - The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output. | 2009-05-07 |
20090115458 | CMOS COMPARATOR WITH HYSTERESIS - A complementary metal oxide semiconductor (CMOS) comparator circuit includes a plurality of p-type metal-oxide-semiconductor (PMOS) transistors receiving an input voltage signal, a plurality of n-type metal-oxide-semiconductor (NMOS) transistors operatively connected to the PMOS transistors and adapted to receive the input voltage signal, and an inverter adapted to invert the input voltage signal into an output voltage signal. An effective aspect ratio of the PMOS and NMOS transistors may be dependent on the level of the output voltage signal from the inverter. When a digital output of the inverter is “1”, the effective aspect ratio of the NMOS transistor is increased by turning on a second NMOS transistor, and a threshold voltage of the inverter is decreased. | 2009-05-07 |
20090115459 | Semiconductor device and operation method thereof - A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal. | 2009-05-07 |
20090115460 | VOLTAGE LEVEL CLAMPING CIRCUIT AND COMPARATOR MODULE - A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source. | 2009-05-07 |
20090115461 | CURRENT CONVERTING METHOD, TRANSCONDUCTANCE AMPLIFIER AND FILTER CIRCUIT USING THE SAME - The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output. | 2009-05-07 |
20090115462 | DRIVER CIRCUIT WITH EMI IMMUNITY - A driver circuit suitable for outputting a signal onto an output line affected by conducted EMI, has a slope control circuit and an output circuit, (op-amp, Mo, M | 2009-05-07 |
20090115463 | Buffer Circuit - A buffer circuit is provided, having an odd number of stages of inverting amplifiers, wherein the stages are capacitive coupled. A negative feedback path feeds back from an output terminal of the final stage of the inverting amplifiers to an input terminal of the initial stage. A reference current source is also provided. A first switch is provided between the adjacent stages of the inverting amplifiers and switched, depending upon a mode of operation. A second switch is provided for selectively driving at least a transistor(s) in the final stage to cause a current mirror circuit with the reference current source depending upon a mode of operation. | 2009-05-07 |
20090115464 | MULTIPLE-BRANCHING CONFIGURATION FOR OUTPUT DRIVER TO ACHIEVE FAST SETTLING TIME - A multiple branching configuration for output driver which achieves a fast settling time is provided. The multiple branching configuration comprises breaking down a typical output buffer stage into multiple branches; and utilizing multiple unit area sized transistors connected in parallel. | 2009-05-07 |
20090115465 | LOW POWER, HIGH SLEW RATE CCD DRIVER - A low power, high slew rate output driver circuit system is provided. The Circuit system comprises a cascade of two high-speed stages and a variable current biasing block. The combination of these two elements enables the realization of a high slew rate, yet low power output driver system. | 2009-05-07 |
20090115466 | SEMICONDUCTOR APPARATUS AND RADIO CIRCUIT APPARATUS USING THE SAME - A semiconductor apparatus includes a signal source 7 that outputs a signal of predetermined frequency, a frequency divider 15 that receives the output signal of the signal source and is capable of switching the output signal to two or more frequency division ratios, a delta-sigma modulator 16 that controls the frequency division ratio of the frequency divider, and a bandpass filter 17 that receives an output of the frequency divider. The frequency of the input signal of the frequency divider is divided by the frequency division ratio controlled by the delta-sigma modulator, and quantization noise appearing in the output of the frequency divider generated by the delta-sigma modulator is attenuated with the bandpass filter. The semiconductor apparatus easily can convert a signal output by a single signal source to a signal of predetermined frequency and supply a plurality of signals of predetermined frequency using a simple configuration with reduced chip size. | 2009-05-07 |
20090115467 | Semiconductor device and operation method thereof - A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference. | 2009-05-07 |
20090115468 | Integrated Circuit and Method for Operating an Integrated Circuit - An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time. | 2009-05-07 |
20090115469 | Variability-Aware Scheme for Asynchronous Circuit Initialization - A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained. | 2009-05-07 |
20090115470 | MEMORY RESET APPARATUS - A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories. | 2009-05-07 |
20090115471 | DELAY LOCKED LOOP AND OPERATING METHOD THEREOF - A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase difference between the first and second delay clocks to output a weight selection signal; a weight storage unit configured to store the weight selection signal obtained during a predetermined period from a point of time when the first and second delay clocks are delay locked; and a phase mixing unit configured to mix phases of the first and second delay clocks to output a DLL clock by applying a weight corresponding to the stored weight selection signal in the weight storage unit. | 2009-05-07 |
20090115472 | MULTIPLE REFERENCE PHASE LOCKED LOOP - A multi reference phase locked loop (MPLL) generates a high speed clock frequency and phase locks it to a lowest common reference frequency derived from a selected one of at least two reference clocks. One of the reference clocks is a system reference clock in a FBDIMM system, another may be a forwarded clock in an AMB | 2009-05-07 |
20090115473 | LOOP FILTER, PHASE-LOCKED LOOP, AND METHOD OF OPERATING THE LOOP FILTER - A loop filter capable of controlling a charge sharing point in time, a phase locked loop, and a method of operating the loop filter are provided. The loop filter includes a duty control unit and a variable capacitor unit. The duty control unit generates a duty control clock signal of which an activation section is shorter than an inactivation section, by controlling a duty of an input clock signal. The variable capacitor unit is charged by an input current and has a capacitance that varies according to the duty control clock signal. The variable capacitor unit may include a switch, a first capacitor, and a second capacitor. The switch is turned on or off in response to the duty control clock signal. The first capacitor is serially connected to the switch and charged by the input current when the switch is turned on. The second capacitor is connected in parallel to the switch and the first capacitor and charged by the input current. | 2009-05-07 |
20090115474 | CLOCK SYNCHRONIZATION CIRCUIT AND CLOCK SYNCHRONIZATION METHOD - A clock synchronization circuit and a clock synchronization method which generate an internal clock synchronized to an external clock is presented. The circuit and method include a clock enable control circuit generating a clock enable control signal controlled by a power supply voltage and a power-down signal. The circuit and method also include a clock generating circuit receiving an input clock which selectively generates an internal clock synchronized to an external clock using the input clock using the clock enable control signal. Whereupon, a locking failure can be prevented by performing a phase update operation selectively in accordance with whether the power supply voltage is varied or not in the power-down mode. Furthermore, current consumption can be reduced by controlling phase update time in accordance with a variable magnitude of the power supply voltage. | 2009-05-07 |
20090115475 | Semiconductor device and operating method thereof - A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit. | 2009-05-07 |
20090115476 | PROGRAMMABLE HIGH-RESOLUTION PHASE DELAY - A programmable delay lock loop system provides a delayed output signal having a programmed delay from an input signal. A phase detector provides a phase delay signal indicative of an actual phase difference between the input signal and the delayed output signal. An accumulator provides a delay command signal as a function of a difference between a commanded delay and the actual phase difference. A programmable phase delay circuit is configured to generate a ramp signal based upon the input signal, to adjust the ramp signal with respect to a threshold level in response to the delay command signal, to generate a trigger signal based upon a comparison of the ramp signal with the threshold level, and to clock the delayed output signal in response to the trigger signal. | 2009-05-07 |
20090115477 | Circuit Device and Related Method for Mitigating EMI - In order to mitigate electromagnetic interference (EMI), the present invention provides a circuit device for an electronic device including a signal generating unit, a phase adjusting unit and an output interface. The signal generating unit generates a plurality of in-phase signals. The phase adjusting unit is coupled to the signal generating unit and is used for adjusting the plurality of in-phase signals to generate a plurality of output signals, where all or some of the output signals have different phases. The output interface is coupled to the phase adjusting unit and is used for outputting the plurality of output signals to a plurality of signal processing units for image processing. | 2009-05-07 |
20090115478 | Data output controller - Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal. | 2009-05-07 |
20090115479 | METHODS AND APPARATUS FOR SYNCHRONIZING WITH A CLOCK SIGNAL - Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical. | 2009-05-07 |
20090115480 | Clock control circuit and data alignment circuit including the same - A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal. | 2009-05-07 |
20090115481 | PULSE OPERATED FLIP-FLOP CIRCUIT HAVING TEST-INPUT FUNCTION AND ASSOCIATED METHOD - The pulse generation circuit generates a first pulse signal and a complementary second pulse signal. The first and second pulse signals are activated simultaneously in a normal mode and activated selectively in response to a test input signal in a test mode. A multiplexing input circuit selects and outputs one of a data input signal and a test input signal as a latch input signal in response to the first pulse signal and the second pulse signal. The latch input signal corresponds to the data input signal in the normal mode and corresponds to the test input signal in the test mode. The latching circuit latches the latch input signal to generate data output signal. The length of data transfer path is reduced, and DtoQ delay can be decreased. | 2009-05-07 |
20090115482 | STORAGE ELEMENTS USING NANOTUBE SWITCHING ELEMENTS - Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements. | 2009-05-07 |
20090115483 | PHASE JUMP SEQUENCER ARCHITECTURE - A method for controlling an output phase of a phase interpolator, by forming an M bit control word, designating N bits of the control word as a fractional number portion, designating M-N bits of the control word as a whole number portion, adjusting a phase jump of the phase interpolator at a designated clock cycle by a first number of phases as designated by the whole number portion plus a second number of phases as designated by the fractional number portion. The designated clock cycle can be identified by numbering clock cycles with a count value from counter having a repeating period of 2 | 2009-05-07 |
20090115484 | DIGITALLY CONTROLLED DELAY ELEMENT - Techniques and corresponding circuits for achieving programmable delay with linear resolution are provided. The techniques provide for incremental delay with substantially equal increments. Linear resolution may be achieved through the use of a circuit arrangement that allows current to be controlled to linearly vary effective resistance of a delay circuit, without affecting the effective capacitance. | 2009-05-07 |
20090115485 | Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus - Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units. | 2009-05-07 |
20090115486 | Apparatus and method for generating multi-phase clocks - An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal. | 2009-05-07 |
20090115487 | Level Converter - A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal. | 2009-05-07 |
20090115488 | Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols Using a Gated Latch Enable Scheme - A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained. | 2009-05-07 |
20090115489 | SWITCH ARRANGEMENT, INTEGRATED CIRCUIT, ACTIVATION SYSTEM - A switch arrangement for providing a drive signal at an output comprises a drive switch coupled to the output of the switch arrangement and a regulating element coupled in series between the drive switch and a power supply input of the switch arrangement. The drive switch is operable to provide the drive signal at the output. The switch arrangement is characterised in that the regulating element is coupled in a cascode arrangement with the drive switch such that in operation the regulating element limits the voltage drop across the drive switch to a predetermined level. | 2009-05-07 |
20090115490 | OPTICAL SEMICONDUCTOR RELAY DEVICE - A transient voltage occurring between output terminals during ON/OFF operation is reduced. There are provided a pair of input terminals IN | 2009-05-07 |
20090115491 | PREDICTION STRATEGY FOR THERMAL MANAGEMENT AND PROTECTION OF POWER ELECTRONIC HARDWARE - A hybrid powertrain system includes an engine, an electric machine, a power electronics device including a plurality of electric circuit layers, and a cooling system. A method for managing thermal energy in the power electronics device includes monitoring a plurality of temperature sensors in the power electronics device, monitoring electric power into and out of the power electronics device, predicting temperatures for the plurality of electric circuit layers, and controlling the hybrid powertrain system based upon the predicted temperatures for the plurality of electric circuit layers. | 2009-05-07 |