19th week of 2015 patent applcation highlights part 30 |
Patent application number | Title | Published |
20150124501 | POWER CONVERSION SYSTEM - A power converter system suitable to provide a load with electrical power, the system comprising; an input voltage terminal; an output voltage terminal; a first power converter unit; a second power converter unit; an input relay unit; an output relay unit; a control unit; wherein the control unit is configured to control the input relay unit and the output relay unit such that the first and second power converter units are engaged alternating at subsequent power ups of the voltage input terminal. | 2015-05-07 |
20150124502 | DRIVING APPARATUS FOR DRIVING SWITCHING ELEMENTS OF POWER CONVERSION CIRCUIT - A driving apparatus for driving switching elements of a power conversion circuit. In the apparatus, a first determination unit determines whether or not a dead time that occurs immediately after a setting of discharge rate is changed is greater than the dead time assumed at the time of designing. When the dead time occurring immediately after the setting of discharge rate is changed is greater than the dead time assumed at the time of designing, a shift unit shifts in time at least one of transition to an OFF state of one of the upper-arm and lower-arm switching elements and transition to an ON state of the other of the upper-arm and lower-arm switching elements immediately after the transition to the OFF state so as to reduce a time difference between the transition to the OFF state and the transition to the ON state. | 2015-05-07 |
20150124503 | POWER CONVERTER AND POWER CONVERSION METHOD - A power converter according to an embodiment includes a power conversion unit and a controller. The power conversion unit includes a plurality of first bidirectional switches that are disposed between a plurality of DC side terminals and a plurality of AC side terminals, and a second bidirectional switch and a reactor that are disposed between the AC side terminals. The controller keeps the second bidirectional switch ON in any one or both of a free-wheeling mode in a step-down power conversion from DC power into AC power, and an energy storing mode in which electric energy is stored in the reactor in a step-up power conversion from the AC power to the DC power. | 2015-05-07 |
20150124504 | POWER CONVERSION APPARATUS - When switching control signals of self-excited semiconductor devices from OFF-control to ON-control, a control circuit controls the self-excited semiconductor device to be ON after a lapse of a turn-ON time from when a control voltage is applied to the self-excited semiconductor device. When switching the control signals of the self-excited semiconductor devices from ON-control to OFF-control, the control circuit controls the control signal of the self-excited semiconductor device to be OFF after a lapse of a turn-OFF time from when the control voltage is applied to the self-excited semiconductor device. | 2015-05-07 |
20150124505 | THREE-PHASE CURRENT SOURCE RECTIFIER FOR POWER SUPPLIES - A three-phase current source rectifier (CSR) with three AC inputs may include a controller, a free-wheeling diode with a cathode connected to a positive line and an anode connected to a negative line, three pairs of switches connected in parallel between the positive line and the negative line, and six pairs of diodes, each pair of the diodes connected in series. Each two pairs of the diodes may be connected in parallel with each other and in series with a respective pair of switches. Each AC input may be connected to between each of two pairs of the diodes. | 2015-05-07 |
20150124506 | MODULAR CONVERTER WITH MULTILEVEL SUBMODULES - One aspect of the disclosure includes a submodule topology for a modular multilevel converter. The submodule topology includes two electronic switches connected together with a first series connection terminal connecting the electronic switches in series, the series connected switches being connected in parallel with two capacitors connected together with a second series connection terminal connecting the capacitors in series. A bidirectional electronic switch connects the first series connection terminal with the second series connected terminal. An output voltage is obtained across the first series connected terminal and a common terminal formed by the parallel connection of the series connected switches with the series connected capacitors. | 2015-05-07 |
20150124507 | Circuit Arrangement for Actuating a Semiconductor Switching Element - A switching arrangement for triggering a semiconductor switching element with a first electrode, a second electrode and a control electrode includes: a pulse generator for generating a control voltage input signal; a bias voltage capacitor; a first electrical resistor electrically connected in series with the bias voltage capacitor between first and second terminals of the pulse generator, wherein the control electrode is electrically connected to the bias voltage capacitor and the first electrical resistor, and the first electrode is electrically connected to the pulse generator and the first electrical resistor; and an additional capacitor connected in series to the pulse generator, the first electrical resistor, and the bias voltage capacitor. | 2015-05-07 |
20150124508 | LOW-POWER POWER SUPPLY - A low-power power supply for an electronic circuit uses an existing current input and converts the current to a higher voltage sufficient for supplying an electronic circuit. The input current generates a defined input voltage, which input voltage is initially generated by voltage drop by the input current passing at least one diode in the open direction of the diode. The input voltage, through a transistor, charges a plurality of switched capacitor networks in a first mode of operation, and in a second mode of operation, the switched capacitor networks are coupled in series for multiplying the input voltage to second higher voltage that is supplied to a oscillating circuit. The oscillating circuit drives the input current via a transformer and half bridge driver to convert a low voltage current supply from a low voltage current into a low current and higher voltage useable for supplying a small electronic circuit. | 2015-05-07 |
20150124509 | THREE-PHASE/TWO-PHASE ROTARY TRANSFORMER - A three-phase/two-phase rotary transformer including a three-phase portion and a two-phase portion that are movable in rotation relative to each other about an axis A. The three-phase portion includes a first body made of ferromagnetic material and three-phase coils, the two-phase portion including a second body made of ferromagnetic material and two-phase coils. The second body defines a first annular slot of axis A and a second annular slot of axis A, the two-phase coils including a first toroidal coil of axis A in the first slot, a second toroidal coil of axis A in the first slot, a third toroidal coil of axis A in the second slot, and a fourth toroidal coil of axis A in the second slot, the first coil and the fourth coil being connected in series, the second coil and the third coil being connected in series. | 2015-05-07 |
20150124510 | SEMICONDUCTOR DEVICE WITH MORE THAN ONE TYPE OF MEMORY CELL - A semiconductor chip comprises a word line configured to be driven by a word line driver. The semiconductor chip also comprises a plurality of bit lines. Each bit line of the plurality of bit lines is configured to transmit a signal to a respective bit line amplifier. The semiconductor device further comprises a plurality of memory cells. At least one memory cell of the plurality of memory cells is at an intersection of the word line and a bit line of the plurality of bit lines. The at least one memory cell of the plurality of memory cells is a type selected from at least two memory cell types based on a distance of the intersection from an end of the word line. | 2015-05-07 |
20150124511 | SEMICONDUCTOR STORAGE APPARATUS - A semiconductor memory device, including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells coupled to the plurality of word lines and the plurality of pairs of bit lines, a plurality of sense amplifiers each coupled between a corresponding pair of bit lines, a plurality of first driver transistors coupled between the plurality of sense amplifiers and a first power supply line, a plurality of second driver transistors coupled between the plurality of sense amplifiers and a second power supply line, a pair of common data lines, and a plurality of column selection gates each coupled between the corresponding pair of bit lines and the pair of common data lines, wherein the number of the first driver transistors is more than the number of the second driver transistor. | 2015-05-07 |
20150124512 | MEMORY CELL AND MEMORY DEVICE - The memory cell of a memory device comprises a MOS capacitor having a n-type gate and a n-type well, a first switch to temporarily apply a breakthrough voltage across the n-type gate and the n-type well to generate a permanent conductive breakthrough structure between the n-type gate and the n-type well. | 2015-05-07 |
20150124513 | LIGHT INCIDENT ANGLE CONTROLLABLE ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a method of changing characteristics of an electronic device, including the steps of: applying light to an electronic device through a plurality of media having different refractive indexes from each other, the electrical characteristics of the electronic device being changed depending on the amount of incident light; and changing an incident angle of light applied the electronic device to adjust the amount of incident light. There is provided a method of providing light incident angle dependency by a simple procedure of accumulating additional media in various electronic devices. In the method, the light incident angle selectivity of the electronic device can be maintained even when the inclination angle of the device is changed depending on the axis parallel to the incident direction of light even though the incident direction thereof is fixed. This means that the performance of the device can be controlled only by changing the inclination angle of the device without greatly changing the dynamic state of the device. Further, since the movement speed of photons is higher than that of electrons and the signal interference of photons is lower than that of electrons, an additional effect of increasing the operating speed of the device or decreasing the size of the device can be expected. | 2015-05-07 |
20150124514 | Lifetime of Ferroelectric Devices - A method and apparatus for increasing the lifetime of ferroelectric devices is presented. The method includes applying a waveform to the input pulse to increase the rise or fall time of the pulse. The waveform may comprise a ramp, a step, or combinations of both. The waveform may be symmetrical with respect to the rising and falling edges of the pulses. A temperature control device may also be operatively connected to increase the temperature of the device to increase lifetime. In other embodiments, a resistance may be operatively connected in series with the ferroelectric device to increase lifetime. | 2015-05-07 |
20150124515 | NONVOLATILE MEMORY DEVICE AND METHOD FOR TESTING NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE MATERIAL - A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level. | 2015-05-07 |
20150124516 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on a side surface thereof: a first insulating film provided on a side surface of the current rectifier element and the variable resistance element and having a composition ratio of a non-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on a side surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value. | 2015-05-07 |
20150124517 | APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING - Apparatus and methods of forming a memory cell are described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring. | 2015-05-07 |
20150124518 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array. | 2015-05-07 |
20150124519 | CIRCUITRY INCLUDING RESISTIVE RANDOM ACCESS MEMORY STORAGE CELLS AND METHODS FOR FORMING SAME - A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells. | 2015-05-07 |
20150124520 | RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE WITH REDUCED PROGRAMMING VOLTAGE - A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface. | 2015-05-07 |
20150124521 | Semiconductor Devices Including Buried Channels - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an active region defined by a device isolation layer formed in a cell region, a transistor including a buried gate in the active region, a metal contact formed on the active region positioned at one side of the buried gate, a landing pad on the metal contact, a capacitor on the landing pad and electrically connected to the active region, and a metal oxide layer between the metal contact and the active region. | 2015-05-07 |
20150124522 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON. | 2015-05-07 |
20150124523 | INITIALIZATION METHOD OF A PERPENDICULAR MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICE - Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process. | 2015-05-07 |
20150124524 | MEMORY DEVICE WITH TIMING OVERLAP MODE - In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes. | 2015-05-07 |
20150124525 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device comprises a memory cell array comprising memory cells coupled to word lines and bit lines, a voltage generator suitable for generating a drive voltage to be applied to a selected word line, and a control logic suitable for detecting the number of pulses of a program voltage received from the memory cell array in a program operation, storing bias information corresponding to the detected number of pulses in a register, and controlling a level of the program voltage for a subsequent program operation based on the bias information. | 2015-05-07 |
20150124526 | NONVOLATILE MEMORY DEVICE, SYSTEM AND PROGRAMMING METHOD WITH DYNAMIC VERIFICATION MODE SELECTION - Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition. | 2015-05-07 |
20150124527 | Detecting Programmed Word Lines Based On NAND String Current - A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block. | 2015-05-07 |
20150124528 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor. | 2015-05-07 |
20150124529 | SEMICONDUCTOR DEVICE, METHOD FOR OPERATING THE SAME, AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a page buffer configured to read data out of a memory cell array in response to a bias enable signal, and a control logic configured to generate the bias enable signal and a bias precharge signal that are used to control the memory cell array. The control logic activates the bias enable signal and the precharge signal before a ready/busy signal activating a read operation of the memory cell array is enabled. | 2015-05-07 |
20150124530 | MEMORY STRING AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to k | 2015-05-07 |
20150124531 | IAS VOLTAGE GENERATOR FOR REFERENCE CELL AND BIAS VOLTAGE PROVIDING METHOD THEREFOR - A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and a sense amplifier latch signal. The cut-off signal generator delays the detection signal a delay time to generate a cut-off signal, wherein a start-up time of the cut-off signal is decided by the detection signal and the delay time. The output stage circuit starts or stops to provide a bias-voltage providing signal according to the cut-off signal. | 2015-05-07 |
20150124532 | DUMMY MEMORY ERASE OR PROGRAM METHOD PROTECTED AGAINST DETECTION - The invention relates to a method of programming or erasing memory cells of a nonvolatile memory, including a first erase or program cycle comprising i) applying at least one erase or program pulse to first memory cells, ii) determining the state, erased or programmed, of the memory cells, and repeating steps i) and ii) if the memory cells are not in the desired state, and a second erase or program cycle including applying a predetermined number of erase or program pulses to second memory cells. | 2015-05-07 |
20150124533 | SOLID STATE STORAGE DEVICE AND SENSING VOLTAGE SETTING METHOD THEREOF - A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values. | 2015-05-07 |
20150124534 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME - In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage. | 2015-05-07 |
20150124535 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data outputted from the memory block in response to a control signal; and a control circuit configured to generate a source signal separated into an odd order and an even order in response to a column access signal consecutively inputted to access the first region or the second region, and to generate the control signal in response to the source signal. | 2015-05-07 |
20150124536 | SEMICONDUCTOR DEVICES - The semiconductor device includes a comparator and a data output unit. The comparator compares a phase of a first pulse signal generated in a first memory region with a phase of a second pulse signal generated in a second memory region and responsively generates a detection signal. The data output unit outputs first data received from the first memory region as output data in synchronization with a first output strobe signal generated by defining a pulse width of a first strobe signal in response to the detection signal and outputs second data received from the second memory region as the output data in synchronization with a second output strobe signal generated by defining a pulse width of a second strobe signal in response to the detection signal. | 2015-05-07 |
20150124537 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment is provided with a memory, a register configured to store a first data group including test data and read/write instruction data to the memory, a first inversion portion having an inverting function of a value of the test data outputted from the register, a second inversion portion having the inverting function of a value of the read/write instruction data outputted from the register, first and second input portions configured to input a data inversion instruction to the first and second inversion portions, and a data switching portion configured to switch between a test data group obtained by applying predetermined processing to the first data group outputted from the register through the first and second inversion portions and a second data group used for reading/writing of data held in the memory during a system operation as input data into the memory. | 2015-05-07 |
20150124538 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of banks; a plurality of word lines; an advanced refresh operation mode where two or more word lines are selected in parallel in each bank; a pulse generation unit suitable for generating a single bank refresh pulse that toggles for a given time in response to a single bank refresh command of a single bank refresh operation mode; and an address generation unit suitable for generating an advanced single bank address for selecting at least two word lines in one of the banks in response to the single bank refresh pulse and an input address in an entry section of the advanced refresh operation mode. | 2015-05-07 |
20150124539 | SEMICONDUCTOR DEVICE - The problem was that the high-impedance state of the difference between signals DQS and DQSB cannot be prevented from being brought in. With this invention, a first comparator circuit outputs a signal DQSIN representing the difference between DQS and DQSB after the coupling of input terminals to a terminal potential and from before the start timing of a preamble of the two signals. A second comparator circuit compares the level of DQS or DQSB with a reference voltage Vref and outputs a signal ODT_DET representing the result of the comparison. A gate circuit masks the signal DQSIN with a signal EW in a masking state. A control circuit identifies the start timing of the preamble based on ODT_DET, and sets the signal EW to the masking state before the start of the preamble and to an unmasking state from the start timing of the preamble. | 2015-05-07 |
20150124540 | SEMICONDUCTOR INTEGRATED CIRCUIT - A system including a circuit integrated with a semiconductor is provided. The system includes a first data line, a second data line, and a first sense amp configured to sense and amplify data of the first data line. The first sense amp is also configured to transfer the amplified data to the second data line in response to a third control signal. The system also includes a control signal generation circuit configured to generate a first control signal for controlling a precharge of the first data line and a second control signal for controlling a reset of the second data line in response to a preparatory signal and a third control signal. The third control signal is generated in response to the first control signal and the second control signal. | 2015-05-07 |
20150124541 | MEMORY CARD AND SD CARD - According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory. | 2015-05-07 |
20150124542 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY MODULE AND OPERATION METHODS THEREOF - An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal. | 2015-05-07 |
20150124543 | SEMICONDUCTOR DEVICES - Semiconductor devices are provided. The semiconductor device includes a first pre-charge element and a second pre-charge element. The first pre-charge element receives a first pre-charge signal to pre-charge a first bit line to have a first pre-charge voltage signal. The second pre-charge element receives a second pre-charge signal to pre-charge a second bit line to have a second pre-charge voltage signal. The second pre-charge signal is enabled earlier than the first pre-charge signal in the event that a data stored in a memory cell of a first cell block is loaded on the first bit line. | 2015-05-07 |
20150124544 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including information on an internal temperature. The semiconductor device generates the temperature code signals according to a level combination of the offset signals. Further, the semiconductor device controls a refresh cycle time determined by the level combination of the offset signals. | 2015-05-07 |
20150124545 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal. | 2015-05-07 |
20150124546 | VOLTAGE REGULATOR AND APPARATUS FOR CONTROLLING BIAS CURRENT - A voltage regulator includes: a comparator configured to compare a feedback voltage with a reference voltage to output an enable signal and operate based on a bias current; a pass transistor turned on according to the enable signal and configured to output an external power voltage as an output voltage; a voltage distribution circuit configured to distribute and output the output voltage to an input terminal of the comparator; and a bias current control unit configured to control an amount of the bias current supplied to the comparator based on the output voltage. | 2015-05-07 |
20150124547 | SEMICONDUCTOR DEVICE - An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed. | 2015-05-07 |
20150124548 | SWITCHING CIRCUIT - A first transistor is turned on based on a first control signal provided to a first terminal of the first transistor. A second control signal is generated by a logic device based on a first input signal and a second input signal. The first input signal is controlled by a logical value stored by a keeper circuit and based on the first control signal, and the second input signal is generated by inverting the first control signal. A second transistor is turned on based on the second control signal provided to a first terminal of the second transistor. A second terminal of the first transistor is coupled with a second terminal of the second transistor. | 2015-05-07 |
20150124549 | SEMICONDUCTOR DEVICES - The semiconductor device includes a pulse width comparator suitable for generating an internal pulse signal having the same pulse width as an output pulse signal whose pulse width is controlled by first and second control signals during a predetermined period and suitable for generating first and second digital signals and a comparison pulse signal from the internal pulse signal according to a delay time which is set by the first and second control signals, an output pulse signal generator suitable for retarding the comparison pulse signal by the delay time determined by first and second control signals to generate the output pulse signal, and a control signal generator suitable for generating the first and second control signals which are sequentially enabled in response to pulses of the output pulse signal. | 2015-05-07 |
20150124550 | ATMOSPHERIC STORAGE MECHANICAL WEIGHT BATCH BLENDING PLANT - An atmospheric storage mechanical weigh batch blend plant is shown with atmospheric storage for providing a dry, pre-blend, oilfield cement ready for mixing at the wellhead for slurry injection into a well head upon adding the proper amount of water and other fluids. The batch blend plant has three separate weighing mechanisms for (a) larger or bulk quantity materials, (b) intermediate quantities of materials, and (c) small amounts of additives to be included to the mixture. The entire weigh batch blend plant can be disassembled and moved. A pneumatic system is used to move the materials and mixture. | 2015-05-07 |
20150124551 | GEAR BOX WITH VARIABLY COUPLED OSCILLATION AND ROTATION FOR KNEADING MACHINE - A gear box for a reciprocating kneader. A primary rotational gear is attached to a gear box primary shaft and rotates in concert therewith. A secondary rotational gear is engaged with the primary rotation gear and rotates therewith. A secondary shaft is attached to the secondary rotational gear and rotates therewith. A primary oscillation gear is attached to the gear box primary shaft and rotates therewith. A secondary oscillation gear is rotationally engaged with the primary oscillation gear and rotates on the secondary shaft. An eccentric is coupled to the secondary oscillation gear and rotates in concert therewith. A yoke is engaged with the eccentric and oscillates on an axis perpendicular to the secondary shaft in response to the lobe. The gearbox secondary shaft moves along its axis in concert with yoke oscillation. A housing is pivotally attached to the yoke and pivotally attached to a casing at a casing. | 2015-05-07 |
20150124552 | SYSTEM AND METHOD FOR MIXING A GAS AND A LIQUID - A system and method for mixing a gas and a liquid includes, receiving a liquid at a liquid inlet of a convergent nozzle and ejecting the liquid at a predetermined output velocity from a liquid outlet of the convergent nozzle into a mixing chamber, the mixing chamber comprising a cantilevered reed positioned within the mixing chamber. The ejection of the liquid from the liquid outlet causes the cantilevered reed to vibrate at an intrinsic frequency. The vibration of the cantilevered reed induces resonance between the liquid and the cantilevered reed and the resonance results in an ultrasound wave within the liquid. Upon the introduction of a gas into the liquid within the mixing chamber, the mixing of the gas into the liquid is effected by the ultrasound wave generated by the cantilevered reed. | 2015-05-07 |
20150124553 | METHOD AND APPARATUS FOR PRODUCING PAINT - The present invention is directed to a method and apparatus for producing an aqueous paint from a plurality of premixed compositions at the point of sale wherein the apparatus is cleaned during the paint production. The premixed compositions include a pigment composition, a dispersant-thickening agent composition, a high resin content binder, and a low resin content binder. The dispersant-thickening agent, when supplied in a cleaning amount, effectively cleans the nozzles and valves, used to supply the premixed compositions to a receiving reservoir for the desired aqueous paint. | 2015-05-07 |
20150124554 | APPARATUS AND METHOD FOR GENERATING SWIRLING FLOW - An apparatus and method for generating a swirl is disclosed that is used to induce an axi-symmetric swirling flow to an incoming flow. The disclosed subject matter induces a uniform and axi-symmetric swirl, circumferentially around a discharge location, thus imparting a more accurate, repeatable, continuous, and controllable swirl and mixing condition of interest. Moreover, the disclosed subject matter performs the swirl injection at a lower pressure drop in comparison to a more traditional methods and devices. | 2015-05-07 |
20150124555 | STIRRING DEVICE AND STIRRING METHOD - When a first electromagnetic valve of a first stirring tank is turned ON and a second electromagnetic valve of a second stirring tank is turned OFF, the air pressure inside the first stirring tank increases and the liquid in the first stirring tank is sent into the second stirring tank via piping. When the volume of the liquid inside the second stirring tank reaches an upper limit, the first electromagnetic valve of the first stirring tank is turned OFF and the second electromagnetic valve of the second stirring tank is turned ON. As a result, the liquid inside the second stirring tank is now sent into the first stirring tank via the piping. Ultimately, because the liquid is circulated between the first and second stirring tanks and the liquid is flowing at all times due to the repetition of said actions, separation does not occur. | 2015-05-07 |
20150124556 | Automated Mix In-Cup Apparatus and the Method of Operating the Same - The present disclosure describes an automated blend in-cup apparatus and the related method of operation. The disclosure relates generally to the field of mixing consumable material. More specifically, the disclosure relates to a mixer that is automatically operable to lower a mixing blade into a cup or vessel that contains material to be blended/mixed. A shield is automatically lowered to at least partially isolate the cup. The apparatus further comprises a well with an inlet manifold and a drain and a fixed but removable cup-receiving holder. The shield can include a magnetic portion that is detected by a first sensor on the apparatus. A safety interlock prevents the actuation of the mixing blade in the event that the magnetic portion is not proximate to the first sensor. Overall, the apparatus is effective, fast, easy to operate, safe, and clean. | 2015-05-07 |
20150124557 | Device for Stirring - A device for stirring a liquid or a granular material comprising a stirring agitator, a rotating drive shaft for rotating the stirring agitator, a rotating drive shaft for rotating the stirring agitator, a stationary axle extending in an essentially vertical direction about which the stirring agitator is adapted to rotate, and a transfer arrangement for contactless transfer of rotation of the drive shaft to the stirring agitator. The device has a centre axis around which the stirring agitator and the drive shaft are adapted to rotate, and means for generating a magnetic force exerting an upwardly directed force component on the stirring agitator. The means for generating a magnetic force comprises a first element arranged in a stirring agitator and a second element associated with the stationary axle. At least one of the first element and the second element comprises a permanent magnet. At least one of the first element and the second element is arranged such that the centre axis extends through the first element and/or the second element. | 2015-05-07 |
20150124558 | ACOUSTIC CAMERA - Apparatus for generating accurate 3-dimensional images of objects immersed in liquids including optically opaque liquids which may also have significant sound attenuation, is described. Sound pulses are caused to impinge on the object, and the time-of-flight of the reflected sound is used to create a 3-dimensional image of the object in almost real-time. The apparatus is capable of creating images of objects immersed in fluids that are optically opaque and have high sound attenuation at resolutions less than about 1 mm. The apparatus may include a piezoelectric transducer for generating the acoustic pulses; a high-density polyethylene compound acoustic lens, a 2-dimensional segmented piezoelectric detecting array positioned behind the lens for receiving acoustic pulses reflected by the object, the electric output of which is directed to digital signal processing electronics for generating the image. | 2015-05-07 |
20150124559 | Seismic Image Dip Decomposition Estimation and Recomposition - Method for optimal stacking of seismic images to remove noise and enhance signals in seismic images ( | 2015-05-07 |
20150124560 | COMPRESSIVE SENSING - Computer-implemented method for determining optimal sampling grid during seismic data reconstruction includes: a) constructing an optimization model, via a computing processor, given by min | 2015-05-07 |
20150124561 | Sound Velocity Profile Streamlining and Optimization Method Based on Maximum Offset of Velocity - The invention discloses a sound velocity profile (SVP) streamlining and optimization method based on maximum offset of velocity, and provides detailed comprehensive technical process so as to solve the problem that the work efficiency of multi-beam detection and data processing are seriously influenced because the original sound velocity profile has a large data quantity. An MOV method is provided and is used for deleting the redundant points automatically and quickly, and for evaluating the influence of the streamlined sound velocity profile on precision of multi-beam sounding through ray tracing and error analysis. The method has an important actual application value in the aspects of marine surveying and charting, multi-beam surveying, a marine geographic information system, computer graphics, submarine science research and the like, and can be popularized. | 2015-05-07 |
20150124562 | Wellbore Signal Monitor with Tangential Seismic Sensors for Tube-Wave Noise Reduction - A sensor array is positionable in a wellbore penetrating a subterranean formation. The sensor array includes a plurality of seismic sensors disposable about a perimeter of the wellbore and coupleable to a signal measurer with a configuration to provide three component seismic signal measurement within the wellbore. At least two of the seismic sensors are located at different azimuthal angles relative to one another and oriented tangentially to a longitudinal axis of the wellbore so as to receive tangential components of wellbore seismic signals to the exclusion of longitudinal and radial components of the wellbore seismic signals. | 2015-05-07 |
20150124563 | WIRELESS EXPLORATION SEISMIC SYSTEM - Systems and methods for seismic data acquisition employing a dynamic multiplexing technique. The dynamic multiplexing technique may include advancing one or more modules in a seismic array through a multiplexing signature sequence in successive transmission periods. The multiplexing signature sequence may be random or pseudo-random. A shared multiplexing signature sequence may be used at all the modules in the seismic array. As such, modules belonging to a common collision domain may operate out of phase with respect to the shared multiplexing signature sequence. | 2015-05-07 |
20150124564 | Ultrasonic Sensor And Device And Method For Measuring A Distance Between A Vehicle And An Obstacle - An ultrasonic sensor includes a housing having a peripheral side wall and a base surface, i.e., it is configured as essentially pot-shaped. The base surface is configured as a diaphragm. A transducer element, which is configured as a piezoelectric element, for example, and is used for generating and detecting ultrasonic oscillations, is situated on the base surface. At least one mass element is situated on the base surface so that the resistance of the mass element against an oscillation of the diaphragm increases with rising oscillation frequency. | 2015-05-07 |
20150124565 | DETERMINING POSITION OF UNDERWATER NODE - A method of determining the position of an underwater node. The positions of three or more transmitters are determined. Each transmitter transmits at least four pulses, wherein a time difference between each pulse and a previous one of the pulses is proportional to a respective co-ordinate of the position of the transmitter. The pulses are received at the underwater node and decoded by measuring the delays between them, thereby determining the co-ordinates of the transmitters. The range of each transmitter relative to the underwater node is also determined. Finally the position of the underwater node is determined in accordance with the co-ordinates and ranges. Any errors in the measurements of the delays between the pulses only translate into small errors in the determined position because of the proportionality between the delays and the coordinates. Therefore if there is a gradual decrease of signal-to-noise ratio then the accuracy of the position estimate also degrades gradually. Also, the use of pulse position modulation provides a low computation overhead in decoding and encoding. | 2015-05-07 |
20150124566 | SYSTEMS, ARTICLES AND METHODS FOR WEARABLE ELECTRONIC DEVICES EMPLOYING CONTACT SENSORS - Wearable electronic devices that employ one or more contact sensors (e.g., capacitive sensors and/or biometric sensors) are described. Contact sensors include electromyography sensors and/or capacitive touch sensors. Capacitive touch sensors include single-frequency capacitive touch sensors, recently-proposed swept frequency capacitive touch sensors, and a generalized version of swept frequency capacitive touch sensors referred to as multi-frequency capacitive touch sensors. The contact sensors are integrated into various devices, including generic watchstraps that may be substituted for the existing watchstrap in any wristwatch design, generic watch back-plates that may be substituted for the existing back-plate in any wristwatch design, and wearable electromyography devices that provide gesture-based control in a human-electronics interface. | 2015-05-07 |
20150124567 | MODULAR PORTABLE STACKABLE DEVICE - A portable modularized stack device includes a flexible wristband and an electronic module. The flexible wristband has a belt which is embedded with wires therein. The belt has a receiving portion formed thereon, a first connector connected at one end of the belt and a second connector connected at the other end of the belt. The first connector and the second connector are matched correspondingly. The flexible wristband further has a third connector. The electronic module has a fourth connector and is disposed on the receiving portion of the flexible wristband. The fourth connector is connected to the third connector. Thus, the present invention can be varied and expanded by stacking another electronic device thereon, and the flexible wristband can be used as a transmission line. | 2015-05-07 |
20150124568 | Digital Whistle - A method and apparatus to enable scoreboard time control system for referee(s) to accurately officiate a sporting event. The system includes a digital switch inside a whistle connected to a Communication Pack for one or more referees and a receiver at the Control Device for the official time clock of the sports event. This system allows the referee to control the clock starting and stopping at his command rather than putting that in the hands of a local official. The control device for the official time clock receives a signal to start the clock when the communication pack signals the control device and also stops the clock when the digital whistle is blown thereby transmitting a signal to the communications pack and then to the control device thereby stopping the official time clock. | 2015-05-07 |
20150124569 | TIMEPIECE WHEEL SET WITH A UNIDIRECTIONAL WHEEL - Timepiece wheel set with a unidirectional wheel including an arbor carrying a pinion and at least a first wheel that is coaxial with this pinion and pivotally mounted on this arbor, this first wheel being connected to the arbor by elastic rotational return means or at least a first spring constituting first means of uncoupling, which exert a friction force on this first wheel, and the wheel set including a second wheel pivotally mounted on this arbor, and connected to this arbor by second elastic rotational return means or at least a second spring constituting second uncoupling means, which exert a friction force on this second wheel. | 2015-05-07 |
20150124570 | TIMEPIECE PALLET LEVER WITH OPTIMISED HORNS - Pallet lever for an escapement mechanism including a balance with a pin of a given pin radius and oscillating over a given radius of gyration, this pallet lever including two horns for cooperation with a pin of this type. These horns are symmetrical to each other relative to a median plane passing through a pallet lever pivot axis, and each includes a concave inner profile over a first radius of curvature greater than or equal to the sum of this radius of gyration and this pin radius, this concave inner profile being adjacent to a convex outer profile over a second radius of curvature less than or equal to the difference between this radius of gyration and this pin radius. | 2015-05-07 |
20150124571 | MEASUREMENT INFORMATION MANAGEMENT SYSTEM, MEASUREMENT DEVICE, MEASUREMENT INFORMATION MANAGEMENT METHOD, AND MEASUREMENT INFORMATION MANAGEMENT PROGRAM - A measurement information management system includes: a measurement device; and a mobile information device, in which the measurement device includes a detail information generation unit which generates detail information including position information obtained by measuring position information, a title information transmission unit which transmits title information for identifying the detail information to the mobile information device, and a detail information transmission unit which transmits the detail information to the mobile information device according to a transmission request signal, and the mobile information device includes a detail information request unit which transmits the transmission request signal of the detail information of which the estimated transfer time necessary for transmitting the detail information corresponding to the title information transmitted from the measurement device from the measurement device to the mobile information device is determined to be shorter than a predetermined threshold value set in advance, to the measurement device. | 2015-05-07 |
20150124572 | WATCH WITH IMPROVED POWER RESERVE - Mechanical timepiece movement, including at least one energy storage means fed at the input by a ratchet driven by one winding mechanism and at the output powering a going train. | 2015-05-07 |
20150124573 | BRAZED BIMETAL EXTERNAL PART OF A TIMEPIECE - A method of manufacturing an external part of a timepiece, including: providing a metallic base made of a first material including titanium and/or a first titanium alloy; providing at least one metallic cover plate made of a second material, the second material including a second metal chosen from among gold or platinum, and/or a second alloy including at least gold or platinum, the at least one cover plate being of a thickness greater than or equal to 0.5 millimeters; brazing the cover plate onto the base with a braze material chosen for brazing titanium with gold or respectively platinum to form a bimetallic blank; and shaping the bimetallic blank to give the external part its final form. | 2015-05-07 |
20150124574 | EXTERIOR ELEMENT FOR A WRISTWATCH MIDDLE PART - Exterior element for a wristwatch middle part, wherein said exterior element takes the form of a separate cover plate which is fixed to the wristwatch middle part and at least partially covers a connection area between a bracelet strand and the watch middle part. | 2015-05-07 |
20150124575 | NEAR-FIELD LIGHT GENERATOR INCLUDING A WAVEGUIDE AND A PLASMON GENERATOR - A plasmon generator includes a first portion and a second portion that are adjacent in a first direction orthogonal to the direction of travel of light propagating through a core. The second portion includes a front end face located in a medium facing surface of a magnetic head. The core has a concave portion recessed from the top surface of the core. At least part of the first portion is received in the concave portion. The concave portion has a surface including an evanescent light generating portion. The first portion includes a plasmon exciting portion opposed to the evanescent light generating portion. The evanescent light generating portion is inclined relative to a first surface. | 2015-05-07 |
20150124576 | ENCODING DATA - Data can be encoded in physical medium and represented by shapes having many various physical attributes. In various examples, data points are encoded and represented by the physical shape, color, size, and/or structure of objects. In one embodiment, holes in memory surface substrates represent data. Various attributes of such holes, including depth, profile size, profile shape, and/or angle can represent data. | 2015-05-07 |
20150124577 | OPTICAL INFORMATION RECORDING MEDIUM AND OPTICAL INFORMATION RECORDING DEVICE | 2015-05-07 |
20150124578 | OBJECTIVE LENS AND OPTICAL PICKUP DEVICE - An objective lens capable of converging light of a used wavelength with a satisfactory aberration on a recording medium is provided. An objective lens for converging light of a predetermined wavelength λ on a recording medium satisfies the following condition: |CML|+|CMF|<0.03λ, where CML is an amount of a generated third-order coma aberration per 1 degree of tilt of the objective lens, and CMF is an amount of a generated third-order coma aberration per 1 degree of tilt of off-axis light. | 2015-05-07 |
20150124579 | System and Method for Transmitting a Synchronization Signal - A method for device-to-device (D2D) communications includes generating, by a synchronization source, a primary device-to-device synchronization signal that is different from a primary synchronization signal (PSS) sent by an Evolved NodeB (eNodeB) and an existing uplink (UL) signal sent by device-to-device communications devices, and transmitting, by the synchronization source, the primary device-to-device synchronization signal in a single carrier frequency division multiple access (SC-FDMA) waveform. | 2015-05-07 |
20150124580 | PARAMETER ADJUSTMENT METHOD AND APPARATUS - The application provides a parameter adjustment method and apparatus. The parameter adjustment method is applicable to a communication device including a SerDes link, and includes: acquiring, by the communication device, a current ambient temperature of the communication device; and if it is determined, according to a preset correspondence between a temperature range and a parameter, that the current ambient temperature does not match a SerDes parameter of the communication device, adjusting the SerDes parameter of the communication device according to the correspondence. In the application, the SerDes parameter of the communication device is adjusted in real time, thereby improving reliability of a SerDes link of the communication device, and reducing a bit error rate of the SerDes link. | 2015-05-07 |
20150124581 | METHODS AND APPARATUSES FOR DELIVERING USER-ASSISTED DATA USING PERIODIC MULTICAST - Disclosed herein are a method and apparatus for delivering user-assisted multimedia data using periodic multicast, which provide stable high-capacity Video-On-Demand (VOD) streaming service by proposing a user-assisted video transfer scheme capable of replacing a client-server configuration in providing high-capacity VOD streaming service. | 2015-05-07 |
20150124582 | SYSTEM AND METHOD OF RELEASING RESOURCES IN A TELECOMMUNCATIONS NETWORK - A system, method, and node for releasing resources in a telecommunications network. The method begins by a node assigning a resource-Identification (ID) to an internal resource within the node. At least one internal resource is allocated by the node for a specific Packet Data Network (PDN) connection. Next, a first message containing a resource-ID of the allocated internal resource is sent to one or more peer nodes. The peer nodes store the received resource-ID from the first message. When a node determines that a malfunction of the allocated internal resource of the node occurs, the node sends a second message containing the resource-ID of the malfunctioning internal resource to the peer nodes. The peer nodes then tear down the PDN connection. | 2015-05-07 |
20150124583 | NETWORK COMMUNICATION METHODS AND APPARATUS - The present invention includes various novel systems and methods for communication in a network. A System Environment Monitor is employed in some embodiments to extract from the network both real-time and historical Network Metrics at the Infrastructure Layer, as well as Application Metadata at the Application Layer. Network analytics facilitate decisions based upon the differing characteristics of Application Components and lower-level hardware components across multiple DTTs. In response, an SDN Controller generates modified sets of SDN Flows, and implements them in real time across a mixed technology (multi-DTT) network in a manner that avoids disrupting existing SDN Flows and other real-time network traffic. | 2015-05-07 |
20150124584 | METHOD AND APPARATUS FOR IMPROVED HANDLING OF IMS NODE BLACKLISTING - Accordingly, there is provided an IMS node, comprising a transmission module and a processor. The transmission module is arranged to send SIP messages to a plurality of other IMS nodes. The processor arranged to detect an error in a particular other IMS node, the error indicating that the particular other IMS node is not available to receive traffic. In response to detection of such an error, the processor causes the particular other IMS node not to be used for a period of time. The transmission module is further arranged to send at least one test message to the particular other IMS node when the period of time expires. The processor is further arranged to determine if the at least one test message is successfully processed by the particular other IMS node, and in response to a positive determination then returning the particular other IMS node to use. | 2015-05-07 |
20150124585 | METHODS AND APPARATUS FOR RELOCATING AND RESTORING CONNECTIONS THROUGH A FAILED SERVING GATEWAY AND TRAFFIC OFFLOADING - In a radio telecommunications network, a serving gateway support node controls connections between user equipment nodes and a packet-based network that pass through at least one serving gateway and at least one packet gateway. The serving gateway support node detects failure of communications to a first serving gateway. The serving gateway support node responds to the detected failure by initiating relocation of existing connections through the first serving gateway to instead pass through a second serving gateway. The serving gateway support node detects recovery of communications to the first serving gateway, and responds by ceasing relocation of at least some of the existing connections that have not yet been relocated to the second serving gateway. Related methods, serving gateways, and packet gateways are also disclosed. | 2015-05-07 |
20150124586 | N-WAY VIRTUAL PORT CHANNELS USING DYNAMIC ADDRESSING AND MODIFIED ROUTING - Systems, methods, and non-transitory computer-readable storage media for dynamic addressing of virtual port channels is described. In some implementations, a virtual IP address can be dynamically generated based on which links in a virtual port channel are active. If the numbers of active links in the virtual port channel changes, the virtual IP address can be dynamically changed. The virtual IP address can be dynamically adjusted by changing the values of individual bits in the virtual IP address that correspond to links in the virtual port channel. The virtual IP address can be used as a tunnel end point address in a VXLAN environment. | 2015-05-07 |
20150124587 | LOOP DETECTION AND REPAIR IN A MULTICAST TREE - Systems, methods and transitory computer-readable storage media for detecting one or more loops in a multicast tree. The method includes calculating a multicast tree radius for a first multicast tree, the multicast tree radius representing a maximum number of hops from a root node to a furthest edge node in the first multicast tree, forwarding, by the root node, a first packet to each edge node within the first multicast tree, the first packet having a time-to-live (TTL) value equal to twice the first multicast tree radius, receiving, at the root node, a copy of the forwarded first packet, and determining an existence of a loop in the first multicast tree based at least upon receiving the copy of the forwarded first packet. | 2015-05-07 |
20150124588 | METHOD AND APPARATUS FOR HANDLING P-CSCF FAILURE AND RESTORING CONNECTIVITY - A method for restoring connectivity between a node in an IP Multimedia Subsystem, IMS, network, and a User Equipment, UE. The UE is associated with a Proxy Call Session Control Function node, P-CSCF, of said IMS network, and with at least one control node of a packet access network, through which the UE connects to the IMS network. The method allows for restoring the connectivity of the UE to an IMS network node after said IMS node has failed to establish a communication to said UE via said P-CSCF node. | 2015-05-07 |
20150124589 | Automotive neural network - Network node modules within a vehicle are arranged to form a reconfigurable automotive neural network. Each network node module includes one or more subsystems for performing one or more operations and a local processing module for communicating with the one or more subsystems. A management system enables traffic from the one or more subsystems of a particular network node module to be re-routed to an external processing module upon failure of the local processing module of that particular network node module. | 2015-05-07 |
20150124590 | VIRTUAL PORT CHANNEL BOUNCE IN OVERLAY NETWORK - Aspects of the subject disclosure relate to methods for detecting a link failure between the first network device and a destination node, receiving a data packet addressed to the destination node, and rewriting encapsulation information of the first data packet. Subsequent to rewriting the encapsulation information of the first data packet, the first data packet is forwarded to a second network device (e.g., using updated address information in the packet header), wherein the second network device is paired with the first network device in the virtual port channel. In certain aspects, systems and computer readable media are also provided. | 2015-05-07 |
20150124591 | INFORMATION PROCESSING SYSTEM, SWITCHING DEVICE, AND METHOD FOR CONTROLLING INFORMATION PROCESSING SYSTEM - An information processing system includes a switching device group including a plurality of switching devices that include a switching device as a root node and switching devices as leaf nodes and are connected in a tree topology. The switching device includes: a controller that, when a failure that occurs in a communication path connected to the root node side of the switching device is detected, writes identification information indicating the communication path from which the failure is detected to a flow table which stores the identification information and output destination port information so as to be associated with each other, thereby switching a plurality of communication paths; and a notification unit that, when a failure that occurs in a communication path connected to the leaf node side of the switching device is detected, notifies another switching device connected to the switching device of a position where the failure occurs. | 2015-05-07 |
20150124592 | Restoring Aggregated Circuits with Circuit Integrity Checks in a Hierarchical Network - A system and method is disclosed that assures component circuits transported in aggregated circuits restore correctly after an aggregated circuit fault. The system and method implements component circuit tail segment integrity checks whenever an aggregated circuit is restored in a higher level of a network hierarchy. Switches at both ends of an aggregated circuit perform circuit integrity checks of the tail segments of every component circuit. A failure of the component circuit integrity check on any component circuit causes that component circuit to be released and restored end-to-end. | 2015-05-07 |
20150124593 | INTERFERENCE CONGESTION CONTROL - The present disclosure concerns interference congestion control in radio communication networks. Disclosed herein are methods as well radio network nodes. A radio network node may, for example, estimate a neighboring cell interference. The radio network node may also detect a sudden significant increase in the estimated neighboring cell interference. In response to detecting a sudden significant in the estimated neighboring cell interference, the radio network node may also transmit a message to at least one other radio network node. This message may include an indicator indicating to said at least one radio network node to initiate an interference congestion control procedure. Hereby it is made possible to allow for interference congestion control in radio communication networks. | 2015-05-07 |
20150124594 | METHOD AND APPARATUS FOR CONTROLLING NETWORK ACCESS IN A WIRELESS COMMUNICATION SYSTEM - The present invention is directed to a wireless communication system. Specifically, the present invention is directed to a method of controlling network access and an apparatus therefore, wherein the method comprises: receiving a first field for indicating network overload situation and a second field for indicating a network access priority; and receiving at least one of a N-bit field for indicating a first back-off window and a M-bit field for indicating a second back-off window, wherein if a configured priority is equal to or higher than the network access priority, a random access (RA) procedure is performed using the first back-off window, wherein if the configured priority is lower than the network access priority, the RA procedure is selectively barred or performed using at least one of the first back-off window and the second back-off window. | 2015-05-07 |
20150124595 | COMMUNICATION SYSTEM, ACCESS CONTROL APPARATUS, SWITCH, NETWORK CONTROL METHOD, AND PROGRAM - A communication system includes: a control apparatus setting control information in a forwarding node(s); a forwarding node(s); and an access control apparatus. The forwarding node(s) forwards packets by using first control information set by the control apparatus and second control information for forwarding packets that do not match a matching condition(s) in the first control information set by the control apparatus from a predetermined port of the forwarding node(s). The access control apparatus includes a determination unit determining whether to generate control information for the packets forwarded from the predetermined port of the forwarding node(s) and requesting the control apparatus to generate control information. | 2015-05-07 |
20150124596 | Method and system for adaptive bandwidth allocation - A method and system for adaptive bandwidth allocation are disclosed. The method includes evenly allocating the whole bandwidth to each user according to the number of the users currently connecting to a gateway, making statistics on the traffic usage of each user within a preset period, and dynamically allocating a bandwidth to each user according to the traffic usage and the theoretical traffic of the allocated bandwidth. According to the technical scheme of the disclosure, when there is a user connecting to or disconnecting from the gateway, the bandwidth can be evenly allocated according to the number of the users currently connecting to the gateway, the bandwidth of each user can be dynamically adjusted according to actual bandwidth utilization rates of the users, the bandwidths of the users with lower bandwidth utilization rates are reduced, and the bandwidths of the users with higher bandwidth utilization rates are increased, so that reasonable bandwidth allocation is fulfilled. | 2015-05-07 |
20150124597 | COMMUNICATION MANAGEMENT APPARATUS AND COMMUNICATION MANAGEMENT METHOD FOR VEHICLE NETWORK - A plurality of in-vehicle control apparatuses ( | 2015-05-07 |
20150124598 | METHOD AND DEVICE FOR PROCESSING BUFFER STATE REPORT IN WIRELESS COMMUNICATION SYSTEM USING INTER-ENB CARRIER AGGREGATION TECHNOLOGY - The present invention proposes a method of processing a buffer state report when a wireless communication system uses inter-eNB carrier aggregation technology. According to the present invention, a terminal may be provided with a proper amount of uplink resource allocations by notifying base stations of a buffer state. | 2015-05-07 |
20150124599 | WIRELESS COMMUNICATION APPARATUS AND TRANSMISSION FRAME CONTROL METHOD - A wireless communication apparatus which switches between plural wireless communication schemes that are different from each other in maximum transmission frame size includes a means for selecting one of the plural wireless communication schemes, a means for generating a transmission frame, a means for dividing the generated transmission frame if the size of the transmission frame is larger than a maximum transmission frame size of the selected wireless communication scheme, and a means for transmitting the transmission frame or divided transmission frames according to the selected wireless communication scheme. | 2015-05-07 |
20150124600 | METHOD FOR TRANSMITTING DATA IN A PACKET-ORIENTED COMMUNICATIONS NETWORK AND CORRESPONDINGLY CONFIGURED USER TERMINAL IN SAID COMMUNICATIONS NETWORK - A method for transmitting data in a packet-oriented communications network, in particular of a motor vehicle, with a guaranteed maximum transmission time for the data packets in the communications network, and to a user terminal in the communications network. In the method, a specific quality of service as a capacity of the communication link is reserved prior to a data transmission by a reservation request from the sender of the data to the receiver of the data and the requested quality of service as a capacity of the communication link between the sender and the receiver is guaranteed in the network for the data stream by the confirmation of the reservation request, or an indication is given by a rejection that transmission is not possible. In addition, the capacity of the communications network is determined cyclically prior to a reservation request, after a rejection and/or at predefinable time intervals. | 2015-05-07 |