19th week of 2013 patent applcation highlights part 41 |
Patent application number | Title | Published |
20130115693 | DEVICE FOR ISOLATION AND/OR PURIFICATION OF BIOMOLECULES - The present invention refers to a device, comprising a hollow body having at least one open end comprising at least one solid matrix binding, adsorbing, absorbing, chelating or retaining compounds which are not desired in a sample and preferably at least one barrier which is non-permeable for liquids and solids under ambience conditions, however, becomes liquid-permeable by applying an external force to said barrier, the use of such a device for isolating or purifying a biomolecule from a sample, a method for preparation of said device and a method for isolation or purification of any biomolecule using said device. | 2013-05-09 |
20130115694 | FORMATION OF NEUROMUSCULAR JUNCTIONS IN A DEFINED SYSTEM - A method for forming neuromuscular junctions includes forming functional neuromuscular junctions between motoneurons and muscle cells by co-culturing one or more human motoneurons and one or more human muscle cells in a substantially serum-free medium. A synthetic mammalian neuromuscular junction includes a human motoneuron functionally linked to a human muscle cell in a substantially serum-free medium. An artificial substrate may be used to support the one or more neuromuscular junctions. | 2013-05-09 |
20130115695 | SCALABLE PRIMATE PLURIPOTENT STEM CELL AGGREGATE SUSPENSION CULTURE AND DIFFERENTIATION THEREOF - The present invention relates to methods for production of undifferentiated or differentiated embryonic stem cell aggregate suspension cultures from undifferentiated or differentiated embryonic stem cell single cell suspensions and methods of differentiation thereof. | 2013-05-09 |
20130115696 | siRNA that Inhibits WT1 Gene Expression and Uses Thereof - The present inventors discovered that siRNAs targeting the 17AA site of the WT1 gene not only suppress the expression of the WT1 gene, but also demonstrate remarkable cell growth-suppressing effects and cell death-inducing effects in cancer cell lines. | 2013-05-09 |
20130115697 | METHODS AND APPARATUS FOR ENHANCED RECOVERY OF CELLS FROM TISSUE SAMPLES - This document describes methods and an apparatus for recovery of cells from a tissue sample. In some embodiments, at least two rounds of acceleration and deceleration are performed. | 2013-05-09 |
20130115698 | METHODS AND COMBINATION - A method and a combination for the cultivation of eukaryotic cells are provided, as well as a method for preparation of eukaryotic cells. The methods comprise providing a sample of eukaryotic cells to be cultured, applying said sample to a cell scaffold material; and maintaining said cell scaffold material having cells applied thereto under conditions suitable for cell culture. The combination comprises eukaryotic cells and a cell scaffold material. The cell scaffold material comprises a polymer of a spider silk protein. | 2013-05-09 |
20130115699 | POLYPLEX GENE DELIVERY VECTORS - Compositions comprising linear PNAI, cyclic PNAI, linear PEI, and/or cyclic PEI, useful for delivering compounds or substances into a cell, are provided, as well as methods of making linear PNAI, cyclic PNAI, linear PEI, and cyclic PEI. Also provided are methods of using compositions comprising linear PNAI, cyclic PNAI, linear PEI, and/or cyclic PEI for introducing substances into a cell. | 2013-05-09 |
20130115700 | METHOD FOR TRANSFECTING NUCLEIC ACID TO CELL AND NUCLEIC ACID COMPLEX - A method for transacting nucleic acid to cell comprising a step for forming a nucleic acid complex by bringing a double-stranded nucleic acid molecule into contact with a nucleic acid carrier having an amino acid sequence of alternating a basic amino acid and a hydrophobic amino acid, which has a peptide chain that forms a β-sheet structure in which a side chain of a positively charged basic amino acid is disposed on one surface side and a side chain of a hydrophobic amino acid is disposed on the opposite surface side in the presence of the double-stranded nucleic acid molecule having a double helix structure, and by binding the double-stranded nucleic acid molecule and the peptide chain through either one or both of the electrostatic interaction between the side chains of the basic amino acid and phosphate groups and hydrogen bonds between the double stranded-nucleic acid molecule and the peptide chain and a nucleic acid complex used for the same are disclosed. | 2013-05-09 |
20130115701 | TRANSGENIC PHOTOSYNTHETIC MICROORGANISMS - Provided herein is a transgenic bacteria engineered to accumulate carbohydrates, for example disaccharides. Also provided is a photobioreactor for cultivating photosynthetic microorganisms comprising a non-gelatinous, solid cultivation support suitable for providing nutrients and moisture to photosynthetic microorganisms and a physical barrier covering at least a portion of the surface of the cultivation support. Devices for the large scale and continuous cultivation of photosynthetic microorganisms incorporating photobioreactors and methods of use are disclosed. Also disclosed are methods of producing fermentable sugar from photosynthetic microorganisms using a photobioreactor of the invention. | 2013-05-09 |
20130115702 | TRANSGENIC PHOTOSYNTHETIC MICROORGANISMS - Provided herein is a transgenic bacteria engineered to accumulate carbohydrates, for example disaccharides. Also provided is a photobioreactor for cultivating photosynthetic microorganisms comprising a non-gelatinous, solid cultivation support suitable for providing nutrients and moisture to photosynthetic microorganisms and a physical barrier covering at least a portion of the surface of the cultivation support. Devices for the large scale and continuous cultivation of photosynthetic microorganisms incorporating photobioreactors and methods of use are disclosed. Also disclosed are methods of producing fermentable sugar from photosynthetic microorganisms using a photobioreactor of the invention. | 2013-05-09 |
20130115703 | DILUTION METHOD FOR DIGITAL MICROFLUIDIC BIOCHIPS - Systems and methods are provided for producing fluids with desired concentration factors. According to one embodiment, a sequence of mix steps comprises mixing a resultant solution of a preceding mix step with one of the input solutions of the preceding mix step depending on a concentration factor of the resultant solution. If the concentration factor of the resultant solution is higher than the target concentration factor, then the resultant solution is mixed with the input solution having the lower concentration factor. If the concentration factor of the resultant solution is lower than the target concentration factor, then the resultant solution is mixed with the input solution having the higher concentration factor. | 2013-05-09 |
20130115704 | SYSTEM AND METHOD FOR THE ANALYSIS OF BIODIESEL - Methods and devices are disclosed providing techniques for measuring the amount of biodiesel in a fuel sample. The methods may be used in the field without the use of laboratory equipment. The biodiesel in the sample is converted to the corresponding free acid which can be isolated and quantified to provide information regarding the amount of biodiesel in the original sample. | 2013-05-09 |
20130115705 | FUNCTIONALIZED NANOSTRUCTURES FOR DETECTING NITRO-CONTAINING COMPOUNDS - Devices, methods and systems for detecting nitro-containing compounds such as TNT, which utilize semiconductor nanostructures modified by a functional moiety that interacts with the nitro-containing compound, are disclosed. The functional moiety is attached to the nanostructures and is being such that upon contacting a sample that contains the nitro-containing compound, the nanostructure exhibits a detectable change in an electrical property, which is indicative of the presence and/or amount of the nitro-containing compound in the sample. Electronic noses for generating recognition patterns of various nitro-containing compounds, comprising a plurality of nanostructures modified by versatile functional moieties are also disclosed. The devices, methods and systems are suitable for detecting nitro-containing compounds in both liquid and gaseous states and for detecting a concentration of a nitro-containing compound such as TNT as low as attomolar concentrations. | 2013-05-09 |
20130115706 | SELECTIVE CHEMOSENSORS BASED ON THE FERROELECTRIC MATERIALS, MIXED OXIDES, OR TEMPERATURE MODULATION OF OXIDE POLYMORPH STABILITY - The present invention relates to gas sensors using doped ferroelectric materials. The sensors can be fabricated as an array where different portions of the array can operate at different independently controlled temperatures to detect different gas phase components of a gas sample. Preferred embodiments can be used for the diagnosis of conditions, such as, diabetes. | 2013-05-09 |
20130115707 | METHOD FOR REMOVING SULFUR-COMPRISING COMPOUNDS FROM A HYDROCARBONACEOUS GAS MIXTURE - A method for removing sulfur-comprising compounds from a hydrocarbonaceous gas mixture, in which an adsorber material is brought into contact with the hydrocarbonaceous gas mixture, wherein the adsorber material comprises a material that adsorbs sulfur-comprising compounds and, in addition, comprises at least one transition metal compound which changes color thereof by reaction with the sulfur-comprising compounds. | 2013-05-09 |
20130115708 | Systems and Methods for Measuring Particle Accumulation on Reactor Surfaces - Systems and methods for monitoring a particle/fluid mixture are provided. The method can include flowing a mixture comprising charged particles and a fluid past a particle accumulation probe. The method can also include measuring electrical signals detected by the probe as some charged particles pass the probe without contacting the probe while other charged particles contact the probe. The measured electrical signals can be manipulated to provide an output. The method can also include determining from the output if the charged particles contacting the probe have, on average, a different charge than the charged particles that pass the probe without contacting the probe. | 2013-05-09 |
20130115709 | CHROMATOGRAPHY METHOD AND MEDIA USED THEREFORE - The present invention relates to a method for running ion exchange chromatography on a media comprising shell beads having an inner porous core and an outer shell, wherein the inner core is provided with ligands whose charge changes with pH and the shell is provided with charged ion exchange ligands, the method comprising the following steps: a) adsorbing sample molecules on the shell ligands at a first pH; b) causing a discharge of the inner core ligands at a second pH by addition of a buffer substance that is able to increase its charge having the same sign/type as that of the core ligands, which at the same time causes release of ions from the inner core ligands and thereby an increase in ionic strength that displaces the sample molecules from the shell ligands i.e. causes an elution. | 2013-05-09 |
20130115710 | TUNING OF METAL ENHANCED EMISSIONS OF LONG-LIVED LUMINESCENT COMPOUNDS - The present invention provides for the surface plasmon-enhancement of long lived luminescent compounds, thereby providing for methods and systems having enhanced and controllable rates of the radiative emission of such relaxation of long lived luminescent compounds. The present invention achieves acceleration of the radiative processes by the interaction of the long lived luminescent compounds with surface plasmons of the metal surfaces. | 2013-05-09 |
20130115711 | REACTANTS FOR CHARGE TRANSFER REACTIONS IN MASS SPECTROMETERS - The invention relates to the use of substances for the production of anions suitable for charge transfer reactions in mass spectrometers, particularly for the fragmentation of multiply positively charged biopolymer ions by electron transfer or for charge reduction by proton transfer. Diketones, particularly α-diketones, are proposed as a newly found class of substances which can be used both for the production of radical anions for electron transfer dissociations (ETD) with a high yield of fragment ions and also for the production of non-radical anions for the charge reduction of multiply charged analyte ions by proton transfer reactions (PTR). These substances have favorable properties in terms of their handling and the associated analytical methods: they are largely nontoxic, cover a favorable range of molecular masses, and their volatility means that they can be stored in unheated containers outside of the vacuum system, which facilitates the refilling of the containers. | 2013-05-09 |
20130115712 | INSTRUMENT FOR CASSETTE FOR SAMPLE PREPARATION - A parallel processing system for processing samples is described. In one embodiment, the parallel processing system includes an instrument interface parallel controller to control a tray motor driving system, a close-loop heater control and detection system, a magnetic particle transfer system, a reagent release system, a reagent pre-mix pumping system and a wash buffer pumping system. | 2013-05-09 |
20130115713 | QUANTUM DOT-BASED OPTICAL SENSORS FOR RAPID DETECTION AND QUANTITATIVE ANALYSIS OF BIOMOLECULES AND BIOLOGICAL MATERIALS - The invention generally relates to detection and analysis of biological materials. In particular; the invention relates to quantum dot-based optical, sensors and methods for rapid detection and quantitative analysis of various biomolecules and biological materials, such as nucleic acids, proteins, cells, etc. | 2013-05-09 |
20130115714 | WESTERN BLOT ANALYTICAL TECHNIQUE - In accordance with an embodiment of the present invention, there is provided a method of performing the western blot analytical technique, wherein the method comprises carrying out the following steps in the following order: a), pre-staining the proteins within a sample; b). separating the proteins using gel electrophoresis; c). analysing the separated proteins to determine the total protein load and/or at least one housekeeping protein load; d). transferring the proteins onto at least one membrane; e). probing the separated proteins to detect a target protein; and f). analysing the probed proteins to determine the target protein's molecular weight and/or load. | 2013-05-09 |
20130115715 | METHOD OF SENSOR MEASUREMENT - The present invention provides a method of determining the amount of an optical probe species binding to or releasing from an optical sensor surface characterized in that the determination comprises the steps of determining at least one physical measurand (x | 2013-05-09 |
20130115716 | METHODS OF DETERMINING AMYLOID BETA TURNOVER IN BLOOD - A method for determining A.beta. turnover in blood includes the use of a labeled amino acid to assess the turnover rate. | 2013-05-09 |
20130115717 | ANALYZING CHEMICAL AND BIOLOGICAL SUBSTANCES USING NANO-STRUCTURE BASED SPECTRAL SENSING - An integrated chromatography-immunoassay system for integrated chromatography-immunoassay system includes a chromatographic unit that receives labeled nano-structured probes comprising nano particles and antibodies attached to the nano particles, and a test membrane comprising coating antigens. The chromatographic unit allows the labeled nano-structured probes to diffuse there through and into the test membrane, wherein the antibodies on the nano particles are bound to the coating antigens. A laser device emits a laser light to illuminate the labeled nano-structured probes having the antibodies bound to the coating antigens on the test membrane. A spectral analyzer obtains a Raman spectrum from light scattered from the labeled nano-structured probes having the antibodies bound to the coating antigens on the test membrane, and to identify a spectral signature in the Raman spectrum associated with the antibody-antigen pair, which enables detection and identification of the antibody. | 2013-05-09 |
20130115718 | Carrier Carrying Identifying Information for Identifying an Identification Subject and Use Thereof - Disclosed are a carrier that carries identifying information having favorable identification performance and a use thereof. The carrier carries identifying information for identifying an identification subject, and comprises one or more pieces of DNA having a thymine-rich base sequence and having, as the identifying information, an identifying base sequence pre-associated with the identification subject. | 2013-05-09 |
20130115719 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT STRUCTURE WITH MAGNETORESISTANCE COMPONENT - A method or manufacturing an integrated circuit structure with a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including a metal pad is formed on the substrate. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. An opening is formed in the dielectric layer so as to form a step-drop. A magnetoresistance material layer is formed on the dielectric layer after forming the metal damascene structure and the opening A photolithography process is applied to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure. | 2013-05-09 |
20130115720 | SURFACE MEASUREMENT - A method and apparatus for determining grain size of a surface. A light source is directed at the surface. Reflected light from the surface is detected. A peak surface grain wavelength is determined from the reflected light. The peak surface grain wavelength is converted to a grain size. Grain size of a semiconductor surface is used as a feedback input to control a manufacturing process. | 2013-05-09 |
20130115721 | EPITAXIAL FILM GROWTH IN RETROGRADE WELLS FOR SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized. | 2013-05-09 |
20130115722 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The manufacturing efficiency of semiconductor devices is improved. A plurality of external terminals (leads) electrically coupled with a semiconductor chip, and contact regions of a plurality of terminals (test terminals) are brought into contact with each other, respectively. This establishes an electrical coupling between the semiconductor chip and a test circuit. Thus, an electrical test is performed. Herein, the terminals are to be repeatedly used in the electrical test of a plurality of semiconductor devices. Whereas, the contact region of the terminal includes a core material formed of a first alloy, and a metal film covering the core material. Further, the metal film is formed of a second alloy higher in hardness than the first alloy. | 2013-05-09 |
20130115723 | Method of manufacturing semiconductor device and semiconductor manufacturing system - In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer. | 2013-05-09 |
20130115724 | METHOD OF FABRICATING AN INTEGRATED ORIFICE PLATE AND CAP STRUCTURE - In an embodiment, a method of fabricating an integrated orifice plate and cap structure includes forming an orifice bore on the front side of a product wafer, coating side walls of the orifice bore with a protective material, grinding the product wafer from its back side to a final thickness, forming a first hardmask for subsequent cavity formation, forming a second hardmask over the first hardmask for subsequent descender formation, forming a softmask over the second hardmask for subsequent convergent bore formation, etching a latent convergent bore using the softmask as an etch delineation feature, etching a descender using the second hardmask as an etch delineation feature, and anisotropic etching of convergent bore walls and cavities using the first hardmask as an etch delineation feature. | 2013-05-09 |
20130115725 | LIGHT EMITTING DIODE HAVING A TRANSPARENT SUBSTRATE - A light emitting diode having a transparent substrate and a method for manufacturing the same. The light emitting diode is formed by creating two semiconductor multilayers and bonding them. The first semiconductor multilayer is formed on a non-transparent substrate. The second semiconductor multilayer is created by forming an amorphous interface layer on a transparent substrate. The two semiconductor multilayers are bonded and the non-transparent substrate is removed, leaving a semiconductor multilayer with a transparent substrate. | 2013-05-09 |
20130115726 | CRYSTALLIZATION APPARATUS, CRYSTALLIZATION METHOD, ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A crystallization apparatus for crystallizing a semiconductor layer formed on a substrate, the crystallization apparatus including: a laser generator, which generates a laser beam, and a stage on which the substrate is mounted, where the semiconductor layer is divided into a plurality of crystallization areas and a plurality of non-crystallization areas, and the laser beam is radiated onto the crystallization areas a plurality of times to crystallize the crystallization areas, where the laser beam is radiated onto different positions of the same crystallization area a plurality of times. | 2013-05-09 |
20130115727 | ETCHING COMPOSITION AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SYSTEM - An etching composition and a method of manufacturing a display substrate using the etching composition are disclosed. The etching composition includes phosphoric acid (H | 2013-05-09 |
20130115728 | FUSING METHOD OF SUBSTRATE LAYER, MANUFACTURING METHOD OF MICROFLUIDIC CHIP AND FUSING APPARATUS OF SUBSTRATE LAYER - Provided is a fusing method of a substrate layer including: treating a joining surface of a substrate layer formed from a resin using an organic solvent having solubility with respect to the resin; and heating the treated substrate layer at less than a glass transition temperature or a softening point temperature of the resin and crimping the heated substrate layer. | 2013-05-09 |
20130115729 | Lithographic fabrication process for a pressure sensor - Lithographic fabrication of a pressure sensor ( | 2013-05-09 |
20130115730 | Low-Temperature Wafer Level Processing for MEMS Devices - It would be beneficial to integrate MEMS devices with silicon CMOS electronics, package them in controlled environments, e.g. vacuum for MEMS resonators, and provide industry standard electrical interconnections such as solder bumps. However, to do so requires through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and the stresses placed on metallization membranes are not present in conventional CMOS packaging. Accordingly there is provided a means of reinforcing through-wafer vias for integrated MEMS-CMOS circuits by in-filling the through-wafer electrical vias with low temperature deposited ceramic materials deposited with processes compatible with post-processing of CMOS electronics. Beneficially ceramics such as silicon carbide provide enhanced mechanical strength, enhanced expansion matching, and increased thermal conductivity in comparison to silicon and solder materials. The ceramic reinforcing may be further adapted to include micro-channels for the provisioning of liquid cooling through the structures. | 2013-05-09 |
20130115731 | METHOD OF MANUFACTURING RADIATION DETECTOR - Although Cl (chlorine) is no longer supplied in the course of a first process in which a detecting layer formed by a polycrystalline film or a polycrystalline lamination film by vapor deposition or sublimation is formed, an additional source (e.g., HCl of Cl-containing gas) other than a source is supplied at the start or in the course of the first process. Thus, the detecting layer as the polycrystalline film or the polycrystalline lamination film of CdTe, ZnTe, or CdZnTe can be doped with Cl uniformly in a thickness direction from the start until the end of the first process in film formation. As a result, uniform crystal particles and uniform detection characteristics can be achieved. | 2013-05-09 |
20130115732 | Method to Fabricate Multicrystal Solar Cell with Light Trapping Surface Using Nanopore Copolymer - Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm. | 2013-05-09 |
20130115733 | ETCHANT COMPOSITION AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR USING THE SAME - Provided is an etchant composition. The etchant composition according to an exemplary embodiment of the present invention includes ammonium persulfate ((NH | 2013-05-09 |
20130115734 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING FACE-TO-FACE SEMICONDUCTOR DICE - Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die. | 2013-05-09 |
20130115735 | Apparatus and Methods for Molded Underfills in Flip Chip Packaging - Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed. | 2013-05-09 |
20130115736 | METHOD FOR SEPARATING A PLURALITY OF DIES AND A PROCESSING DEVICE FOR SEPARATING A PLURALITY OF DIES - A method for separating a plurality of dies is provided. The method may include: selectively removing one or more portions from a carrier including a plurality of dies, for separating the plurality of dies along the selectively removed one or more portions, wherein the one or more portions are located between the dies; and subsequently forming over a back side of the dies, at least one metallization layer for packaging the dies | 2013-05-09 |
20130115737 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH OUTER LEADS HAVING A LEAD-FREE PLATING - A semiconductor device has a tab having a semiconductor chip fixed thereto, a plurality of inner leads, a plurality of outer leads formed integrally with the inner leads, a plurality of wires coupling the electrode pads of the semiconductor chip to the inner leads, and a molded body having the semiconductor chip molded therein. Over a surface of each of the outer leads protruding from the molded body, an outer plating including lead-free platings is formed. The outer plating has, in a thickness direction thereof, a first lead-free plating and a second lead-free plating, the first and second lead-free platings having the same composition and meeting at an interface. The first and second lead-free platings are formed under different conditions and may have different physical properties. | 2013-05-09 |
20130115738 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer. | 2013-05-09 |
20130115739 | Systems and Methods Integrating Trench-Gated Thyristor With Trench-Gated Rectifier - An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode. | 2013-05-09 |
20130115740 | MANUFACTURING METHOD OF THIN FILM TRANSITOR - Disclosed are a thin film transistor and a method of manufacturing the thin film transistor. An electrode layer of the thin film transistor includes a seed layer formed of a transparent conductive material doped with indium gallium zinc oxide (IGZO) and a main layer formed of a transparent conductive material. The thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulation film on the substrate to cover the gate electrode, a semiconductor layer disposed on the gate insulation film in a region corresponding to the gate electrode, an electrode layer having a double layer structure and disposed on the gate insulation film in a manner such that a topside portion of the semiconductor layer is exposed through the electrode layer, and a passivation layer on the gate insulation film to cover the semiconductor layer and the electrode layer. | 2013-05-09 |
20130115741 | PROCESS TO REMOVE Ni AND Pt RESIDUES FOR NiPtSi APPLICATIONS USING AQUA REGIA WITH MICROWAVE ASSISTED HEATING - The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate. | 2013-05-09 |
20130115742 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION TECHNIQUE - The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions. | 2013-05-09 |
20130115743 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device is provided, wherein a step of forming an S/D region comprises: determining an interface region comprising an active region of a partial width abutting an isolation region, and forming an auxiliary layer covering the interface region; removing a semiconductor substrate of a partial thickness in the active region using the auxiliary layer, a gate stack structure and the isolation region as a mask, so as to form a groove; and growing a semiconductor material in the groove for filling into the groove. A semiconductor device having a material of the semiconductor substrate sandwiched between an S/D region and an isolation region is further provided. The present invention is beneficial to reduce current leakage. | 2013-05-09 |
20130115744 | Vertical Gate LDMOS Device - A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material. | 2013-05-09 |
20130115745 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION TRENCHES SELF-ALIGNED TO GATE TRENCHES - Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer. | 2013-05-09 |
20130115746 | Method for Fabricating a Vertical LDMOS Device - A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body. | 2013-05-09 |
20130115747 | TRENCH GATE SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT. | 2013-05-09 |
20130115748 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer. | 2013-05-09 |
20130115749 | Semiconductor Package Having Passive Device and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced. | 2013-05-09 |
20130115750 | BLOCKING LAYERS FOR LEAKAGE CURRENT REDUCTION IN DRAM DEVICES - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer. | 2013-05-09 |
20130115751 | BORON-CONTAINING HYDROGEN SILSESQUIOXANE POLYMER, INTEGRATED CIRCUIT DEVICE FORMED USING THE SAME, AND ASSOCIATED METHODS - A composition includes a boron-containing hydrogen silsesquioxane polymer having a structure that includes: silicon-oxygen-silicon units, and oxygen-boron-oxygen linkages in which the boron is trivalent, wherein two silicon-oxygen-silicon units are covalently bound by an oxygen-boron-oxygen linkage therebetween. | 2013-05-09 |
20130115752 | Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops | 2013-05-09 |
20130115753 | METHOD OF MANUFACTURING THIN FILM-BONDED SUBSTRATE - A method of manufacturing a thin film-bonded substrate in which a high-quality gallium nitride (GaN) thin film can be transferred. The method includes implanting ions into a first | 2013-05-09 |
20130115754 | MICRO MACHINING METHOD FOR A SUBSTRATE ON AN UNDERLAY - A micro machining method includes utilizing a polymer as an intermediate adhesion layer, and bonding a underlay with a substrate by pressure bonding, thinning the substrate and deep-etching it to form through holes, backfilling the through holes and deep-etching the substrate again to form a plating hole, plating metal in the plating hole to form a support between the underlay and the substrate, and dissolving the through holes, and etching the polymer through the through holes to release structures. Alternatively, after forming the substrate on the underlay, the method can include thinning the substrate and deep-etching it to form a plating hole, plating metal in the plating hole to form a support between the underlay and the substrate, deep-etching the substrate again to form through holes, and etching the polymer through the through holes to release structures. | 2013-05-09 |
20130115755 | METHOD OF SEPARATING SEMICONDUCTOR DIE USING MATERIAL MODIFICATION - A method for separating semiconductor die includes forming a porous region on a semiconductor wafer and separating the die at the porous region using mechanical or other means. | 2013-05-09 |
20130115756 | PROCESSING METHOD FOR SEMICONDUCTOR WAFER HAVING PASSIVATION FILM ON THE FRONT SIDE THEREOF - A semiconductor wafer processing method forms a plurality of wafer dividing grooves respectively along a plurality of crossing streets formed on the front side of a semiconductor substrate of a semiconductor wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed. The semiconductor wafer has a passivation film formed on the front side of the semiconductor substrate so as to cover the devices and the streets. A first laser beam is applied to the passivation film along each street to thereby form a film dividing groove in the passivation film along each street. A second laser beam is applied to the semiconductor substrate along the film dividing groove formed in the passivation film, thereby forming the wafer dividing groove in the semiconductor substrate along each street. | 2013-05-09 |
20130115757 | METHOD FOR SEPARATING A PLURALITY OF DIES AND A PROCESSING DEVICE FOR SEPARATING A PLURALITY OF DIES - A method for separating a plurality of dies is provided, the method including: defining one or more portions to be removed from a carrier including a plurality of dies by chemically changing the properties of the one or more portions to be removed located between the dies; performing a front-end-of-line FEOL process on at least one die to form at least one semiconductor device; and selectively removing the one or more portions of the carrier whose properties were chemically changed for separating the dies along the removed one or more portions. | 2013-05-09 |
20130115758 | METHOD FOR MANUFACTURING SILICON CARBIDE SCHOTTKY BARRIER DIODE - The present invention provides a method for manufacturing a silicon carbide Schottky barrier diode. In the method, an n− epitaxial layer is deposited on an n+ substrate. A sacrificial oxide film is formed on the n− epitaxial layer by heat treatment, and then a portion where a composite oxide film is to be formed is exposed by etching. Nitrogen is implanted into the n− epitaxial layer and the sacrificial oxide film using nitrogen plasma. A silicon nitride is deposited on the n− epitaxial layer and the sacrificial oxide film. The silicon nitride is thermally oxidized to form a composite oxide film. An oxide film in a portion where a Schottky metal is to be deposited is etched, and then the Schottky metal is deposited, thereby forming a silicon carbide Schottky barrier diode. | 2013-05-09 |
20130115759 | Methods of Fabricating Semiconductor Devices - Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously. | 2013-05-09 |
20130115760 | METHOD OF FORMING A THIN LAYER STRUCTURE - A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets. | 2013-05-09 |
20130115761 | Methods of Forming a Semiconductor Device - Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern. | 2013-05-09 |
20130115762 | METHOD FOR DOPING A SEMICONDUCTOR MATERIAL - A feedstock of semiconductor material is placed in a crucible. A closed sacrificial recipient containing a dopant material is placed in the crucible. The content of the crucible is melted resulting in incorporation of the dopant in the molten material bath. The temperature increase is performed under a reduced pressure. | 2013-05-09 |
20130115763 | METHODS FOR FORMING DOPED SILICON OXIDE THIN FILMS - The present disclosure relates to the deposition of dopant films, such as doped silicon oxide films, by atomic layer deposition processes. In some embodiments, a substrate in a reaction space is contacted with pulses of a silicon precursor and a dopant precursor, such that the silicon precursor and dopant precursor adsorb on the substrate surface. Oxygen plasma is used to convert the adsorbed silicon precursor and dopant precursor to doped silicon oxide. | 2013-05-09 |
20130115764 | SUBSTRATE PROCESSING SYSTEM AND METHOD - A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head. | 2013-05-09 |
20130115765 | SEMICONDUCTOR DEVICE WITH BUFFER LAYER - A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region. | 2013-05-09 |
20130115766 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a tunnel insulating film and a first conductive film are formed on a semiconductor layer. A trench is formed. A first sacrifice film is buried in the trench. A second sacrifice film having density higher than that of the first sacrifice film is formed on the first sacrifice film in the trench. An insulating film is formed on the first conductive film and the second sacrifice film. A second conductive film is formed on the insulating film. The second sacrifice film is exposed. The first sacrifice film and the second sacrifice film are removed. | 2013-05-09 |
20130115767 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. | 2013-05-09 |
20130115768 | METHODS FOR DEPOSITING NICKEL FILMS AND FOR MAKING NICKEL SILICIDE AND NICKEL GERMANIDE - In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. Nickel thin films can be used directly in silicidation and germanidation processes. | 2013-05-09 |
20130115769 | METHOD FOR FORMING AN AIR GAP AROUND A THROUGH-SILICON VIA - Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first cavity with a sacrificial material, forming a second cavity in the substrate, through the sacrificial material, by removing a portion of the sacrificial material and a portion of the substrate below the sacrificial material, filling the second cavity with a conductive material, removing a remaining portion of the sacrificial material to form an air gap between the conductive material and the substrate, and forming a cap over the air gap. | 2013-05-09 |
20130115770 | ETCHING COMPOSITION, METHOD OF FORMING A METAL PATTERN AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE - An etching composition for a copper-containing layer includes about 0.1% to about 30% by weight of ammonium persulfate, about 0.1% to about 10% by weight of a sulfate, about 0.01% to about 5% by weight of an acetate and about 55% to about 99.79% by weight of water. The etching composition having improved stability during storage and an increased capacity for etching | 2013-05-09 |
20130115771 | Method of making semiconductor device - One or more embodiments may include a method of making a semiconductor structure, comprising: forming a first opening partially through a semiconductor substrate; forming a first dielectric layer over a sidewall surface of the first opening; and forming a second opening partially through a semiconductor substrate, the second opening being below the first opening. | 2013-05-09 |
20130115772 | Etching Method - The present invention relates to an etching method of capable of etching a silicon carbide substrate with a higher accuracy. A first etching step in which a silicon carbide substrate K is heated to a temperature equal to or higher than 200° C., SF6 gas is supplied into a processing chamber and plasma is generated from the SF6 gas, and a bias potential is applied to a platen, thereby isotropically etching the silicon carbide substrate K, and a second etching step in which the silicon carbide substrate K is heated to a temperature equal to or higher than 200° C., SF6 gas and O2 gas are supplied into the processing chamber and plasma is generated from the SF6 gas and the O2 gas, and a bias potential is applied to the platen on which the silicon carbide substrate K is placed, thereby etching the silicon carbide substrate K while forming a silicon oxide film as passivation film on the silicon carbide substrate K are alternately repeated. | 2013-05-09 |
20130115773 | Prevention of ILD Loss in Replacement Gate Technologies by Surface Treatmen - When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, pronounced loss of the interlayer dielectric material may be avoided by inserting at least one surface modification process, for instance in the form of a nitridation process. In this manner, leakage paths caused by metal residues formed in the interlayer dielectric material may be significantly reduced. | 2013-05-09 |
20130115774 | METHOD FOR CHEMICAL PLANARIZATION AND CHEMICAL PLANARIZATION APPARATUS - According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid. | 2013-05-09 |
20130115775 | METHOD OF FORMING WIDE TRENCHES USING A SACRIFICIAL SILICON SLAB - A method of forming an encapsulated wide trench includes providing a silicon on oxide insulator (SOI) wafer, defining a first side of a first sacrificial silicon slab by etching a first trench in a silicon layer of the SOI wafer, defining a second side of the first sacrificial silicon slab by etching a second trench in the silicon layer, forming a first sacrificial oxide portion in the first trench, forming a second sacrificial oxide portion in the second trench, forming a polysilicon layer above the first sacrificial oxide portion and the second sacrificial oxide portion, and etching the first sacrificial oxide portion and the second sacrificial oxide portion. | 2013-05-09 |
20130115776 | PRESSURE CONTROL VALVE ASSEMBLY OF PLASMA PROCESSING CHAMBER AND RAPID ALTERNATING PROCESS - A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber. | 2013-05-09 |
20130115777 | MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURES - A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate. | 2013-05-09 |
20130115778 | Dry Etch Processes - Provided methods of etching and/or patterning films. Certain methods comprise exposing at least part of a film on a substrate, the film comprising one or more of HfO | 2013-05-09 |
20130115779 | Conical Sleeves For Reactors - In some embodiments, the present invention discloses sealing mechanisms for generating site isolated regions on a substrate, allowing combinatorial processing without cross contamination between regions. The sealing mechanism can include a thin sharp edge ring for pressing on the substrate surface with small contact area. The small sealing area can concentrate the sealing force, generating higher contact pressure to guard against fluid leakage across the sealing surface, for example, eliminating fluid wicking at the seal interface through capillary action. The sealing mechanism can include multiple protrusions, which contacts the substrate leaving a small gap at the remaining portion of the sealing mechanism. The sealing mechanism can include minimal contact points with the substrate, which can significantly reduce the particle generation during processing. A pressure differential can be established across the sealing surface to prevent fluid leakage. | 2013-05-09 |
20130115780 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus has a circular chamber having an opening portion which serves as a plasma ejection port surrounded by a dielectric member, a gas supply pipe for introducing gas into the inside of the chamber, a coil provided in the vicinity of the chamber, a high-frequency power supply connected to the coil, and a base material mounting table. | 2013-05-09 |
20130115781 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes a flow splitter for dividing a common gas into two common gas streams of common gas branch lines. A central introduction portion connected to one of the common gas branch lines supplies a common gas to a central portion of a substrate to be processed. A peripheral introducing portion connected to the other one of the common gas branch lines supplies the common gas to a peripheral portion of the substrate. The peripheral introducing portion has peripheral inlets arranged about a circumferential region above the substrate. An additive gas line is connected to an additive gas source to add an additive gas to at least one of the common gas branch lines. In addition, an electron temperature of a plasma in a region where the peripheral inlets are disposed is lower than that in a region where the introduction portion is disposed. | 2013-05-09 |
20130115782 | PROCESS FOR REMOVING MATERIAL FROM SUBSTRATES - A method of removing materials, and preferably photoresist, from a substrate comprises dispensing a liquid sulfuric acid composition comprising sulfuric acid and/or its desiccating species and precursors and having a water/sulfuric acid molar ratio of no greater than 5:1 onto an material coated substrate in an amount effective to substantially uniformly coat the material coated substrate. The substrate is preferably heated to a temperature of at least about 90° C., either before, during or after dispensing of the liquid sulfuric acid composition. After the substrate is at a temperature of at least about 90° C., the liquid sulfuric acid composition is exposed to water vapor in an amount effective to increase the temperature of the liquid sulfuric acid composition above the temperature of the liquid sulfuric acid composition prior to exposure to the water vapor. The substrate is then preferably rinsed to remove the material. | 2013-05-09 |
20130115783 | METHOD FOR DEPOSITING CYCLIC THIN FILM - Provided is a method of depositing a cyclic thin film that can provide excellent film properties and step coverage. The method comprises the steps of forming a silicon thin film by repeating a silicon deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded and a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber; and forming the insulating film including silicon from the silicon thin film by forming a plasma atmosphere into the chamber. | 2013-05-09 |
20130115784 | ROTATABLE ELECTRICAL COUPLING DEVICE - A rotatable electrical coupling device incorporates a first connector having a first electrical contact member adapted to conduct or transmit a high-frequency and/or high-speed data signal, and a second connector having a second electrical contact member adapted to conduct or transmit a high-frequency and/or high-speed data signal. The second connector is configured to be coupled with the first connector for substantially free or unimpeded rotation about an axis (X) relative to the first connector, the first and second electrical contact members being configured to engage one another and to maintain uninterrupted electrical contact throughout a relative rotational movement between the first and second connectors in a coupled state. | 2013-05-09 |
20130115785 | ROTARY CONNECTOR DEVICE - A steering roll connector includes a rotator, a sleeve, and a fixed casing. The rotator includes a claw and an inner cylindrical part, and is mounted to a steering shaft such that the rotator is rotated integrally with the steering shaft inserted in the inner cylindrical part. The sleeve includes a projection connectable with the claw, and is mounted to the rotator such that the sleeve is rotated integrally with the rotator. The fixed casing includes an outer cylindrical part, and is mounted such that the fixed casing does not follow rotation of the steering shaft inserted in the outer cylindrical part and such that the fixed casing is in contact with the sleeve. A combination of materials of the claw and the projection is such that occurrence of a squeak caused when the claw and the projection are rubbed against each other is suppressed. | 2013-05-09 |
20130115786 | CONNECTOR MODULE - A connector module includes a single port connector and a circuit board capable of assembling with a multi-ports connector. The single port connector includes a receiving room and a number of first fixing pins formed at opposite sides of the receiving room along a longitudinal direction of the receiving room. The first fixing pins at each side of the receiving are arranged in a same way. The multi-ports connector includes at least two of the receiving room and the first fixing pins formed at opposite sides of each receiving room. The circuit board defines a group of first fixing holes corresponding to the first fixing pins formed at each side of the receiving rooms of the multi-ports connector. The single port connector is mounted on the circuit board by selectively inserting the first fixing pins into every two adjacent groups of the first fixing holes. | 2013-05-09 |
20130115787 | CONNECTOR - Impedance adjusting pieces are provided to properly obtain a shield operation over an entire length of an inner terminal. Thus, a matching of impedance is achieved so that a high frequency performance of an entire part of a connector for a circuit board may be improved. | 2013-05-09 |
20130115788 | ELECTRICAL HARNESS CONNECTOR - A connector is provided for joining two electrical harnesses. Each harness is formed from a flexible printed circuit board which provides a plurality of conductive tracks, and each harness has a substantially planar terminating region at which the conductive tracks of the harness fan out. One or more receiving holes are formed in each terminating region to extend to respective conductive tracks. Each receiving hole extends in a direction substantially perpendicularly to the plane of the respective terminating region. When in use, the connector includes a connection formation between respective terminating regions of the two electrical harnesses. The connector further includes a housing configured to hold the respective terminating regions of the two electrical harnesses in face-to-face relationship with the connection formation. The housing has one or more apertures through which the harnesses can exit the housing as they extend away from their terminating regions. | 2013-05-09 |
20130115789 | EARTH BUSBAR - A device for use with a printed circuit board, PCB, is provided. The device is arranged to electrically connect to a component on the PCB. The device comprises a first layer having a first hole therethrough and a second layer having a second hole therethrough. The second hole is arranged to receive a connector to connect the device to the PCB. Each of the first and second holes has a width in the plane of the respective first or second layer. The first and second holes are substantially coaxial. The width of the first hole is greater than the width of the second hole. Thus proper electrical clearance is provided between the component on the PCB an the device when the connector is not present. | 2013-05-09 |
20130115790 | BOARD TERMINAL AND PRINTED CIRCUIT BOARD PROVIDED WITH BOARD TERMINAL - A board terminal has a flat-plate shaped connection portion to be connected to an electric component at one end and an insertion portion to be inserted in and soldered to a through-hole of a printed circuit board at the other end and is formed in a crank shape by being provided with a support plate portion protruding in a plate thickness direction of the connection portion between the connection portion and the insertion portion. Also, the insertion portion is formed in a location on only one side in a width direction of the support plate portion. | 2013-05-09 |
20130115791 | MULTI-PIN BREAKAWAY CONNECTOR WITH FIXED AND RETRACTABLE PINS - A breakaway connector assembly which has first connector having a first housing, a plurality of retractable pins attached to the housing, and a plurality of fixed pins attached to the housing and circumscribing the plurality of retractable pins. A second connector is matable to the first connector, the second connector having a plurality of contacts adapted to engage the plurality of fixed pins. | 2013-05-09 |
20130115792 | PORTABLE ELECTRONIC DEVICE WITH COLLAPSIBLE PLUG - The present invention is to provide a portable electronic device, which includes a main body having one end concavely provided with a receiving groove, a pivot pin provided in the receiving groove, a pivot seat pivotally connected to the pivot pin, a transmission line having one end electrically connected to a circuit board provided in the main body and the other end extending into the receiving groove, and a plug having one end embedded in the pivot seat. Since the pivot pin has a hollow configuration, the other end of the transmission line is able to pass through the pivot pin and electrically connected to the plug, allowing the plug to be rotated and received in the receiving groove when the portable electronic device is not in use and ensuring the two ends of the transmission line not to be pulled or curled due to rotation of the plug. | 2013-05-09 |