19th week of 2019 patent applcation highlights part 69 |
Patent application number | Title | Published |
20190139840 | WAFER SCALE TESTING AND INITIALIZATION OF SMALL DIE CHIPS - A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region. | 2019-05-09 |
20190139841 | SEMICONDUCTOR TEST STRUCTURE AND METHOD FOR FORMING THE SAME - A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips. | 2019-05-09 |
20190139842 | SEMICONDUCTOR STRUCTURE - The present disclosure provides a semiconductor structure including a substrate, a first die vertically over the substrate, a second die vertically over the substrate and laterally separated from the first die with a gap, and an insulation material in the gap. The substrate is at least partially overlapped with the gap when viewed from a top view perspective, and a Young's modulus of the substrate is higher than that of the insulation material. | 2019-05-09 |
20190139843 | SEMICONDUCTOR CHIP PACKAGE - This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for supplying a voltage to the circuit part, a resin layer formed in a periphery of the semiconductor chip, a substrate that is disposed to face the first surface of the semiconductor chip and the resin layer, and a plurality of external terminals that are provided on the second surface of the semiconductor chip, each of the plurality of external terminals being electrically coupled to any of the plurality of electrodes. | 2019-05-09 |
20190139844 | METHOD FOR PROCESSING AN ELECTRICALLY INSULATING MATERIAL PROVIDING SAME WITH SELF-ADJUSTING ELECTRICAL FIELD GRADING PROPERTIES FOR ELECTRICAL COMPONENTS - A method for processing an electrically insulating protective material intended for covering at least one surface of an electrical component to be insulated, which includes first and second electrical contacts. The method includes: mixing an electrically insulating host matrix with a particulate filler having dielectric permittivity higher than that of the host matrix, so as to obtain a homogeneous composite mixture; depositing the solidifiable homogeneous composite mixture on the at least one surface of the electrical component to be insulated; applying an electrical field to the homogeneous composite mixture by using the first and second electrical contacts. | 2019-05-09 |
20190139845 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove. | 2019-05-09 |
20190139846 | SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME - At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a carrier, a first patterned conductive layer, an interconnection structure, a first semiconductor device, an encapsulant, a second patterned conductive layer, and a passivation layer. The carrier has a first surface and a second surface opposite to the first surface. The first patterned conductive layer is adjacent to the first surface of the carrier. The interconnection structure is disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer. The first semiconductor device is disposed on the interconnection structure and electrically connected to the interconnection structure. The encapsulant is disposed on the first patterned conductive layer and encapsulates the semiconductor device and the interconnection structure. The second patterned conductive layer is disposed on a top surface and a side surface of the encapsulant and electrically connected to the first patterned conductive layer. The passivation layer is disposed on the second patterned conductive layer and covers the side surface of the encapsulant. | 2019-05-09 |
20190139847 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure and a method of manufacturing the same are provided. The package structure includes a die, a first encapsulant, a second encapsulant, a protection layer, a RDL structure and a connector. The first encapsulant is aside a first sidewall of the die, at least encapsulating a portion of the first sidewall of the die. The second encapsulant is aside a second sidewall of the die, encapsulating the second sidewall of the die. The protection layer is aside the first sidewall of the die and on the first encapsulant. The RDL structure is on a first surface of the die. The connector is electrically connected to the die through the RDL structure. | 2019-05-09 |
20190139848 | Configuring a Sealing Structure Sealing a Component Embedded in a Component Carrier for Reducing Mechanical Stress - A component carrier including a stack of at least one electrically conductive layer structure and at least one electrically insulating layer structure, a component embedded in the stack, and a sealing structure sealing at least part of the component with regard to material of the stack, wherein the sealing structure is configured for reducing stress between the component and the stack. | 2019-05-09 |
20190139849 | SEMICONDUCTOR PACKAGE INCLUDING A DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 2019-05-09 |
20190139850 | Temporary Bonding Scheme - A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer. | 2019-05-09 |
20190139851 | SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER - A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips. | 2019-05-09 |
20190139852 | EMBEDDED THERMAL ENHANCEMENT STRUCTURES FOR MOLDED INTEGRATED CIRCUIT PACKAGES - A semiconductor package includes a substrate, a die coupled to the substrate, the die being smaller in size than the substrate and placed on top of the substrate, a mold formed around and over the die, the mold having a top surface and a mold volume, wherein the mold includes at least one of thermally conductive fin and pillar formed within the mold volume to enhance heat transfer within the package, and a film layer formed over the top surface of the mold volume. The mold includes a plurality of grooves and holes formed above and around the die, and a thermally conductive material is filled into the grooves and holes forming at least one of thermally conductive fin and pillar within the mold volume. | 2019-05-09 |
20190139853 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip, an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The heat dissipation member has a thickness greater than that of the semiconductor chip. | 2019-05-09 |
20190139854 | THERMAL-DISSIPATING SUBSTRATE STRUCTURE - A substrate structure is provided, including a substrate, an integrated circuit chip, a circuit structure, and a thermal-dissipating structure. The integrated circuit chip is disposed in the substrate. The circuit structure is electrically connected to the integrated circuit chip. The thermal-dissipating structure is disposed in the substrate and adjacent to the integrated circuit chip, and the thermal-dissipating structure is electrically isolated from the circuit structure. | 2019-05-09 |
20190139855 | ENHANCED SYSTEMS AND METHODS FOR IMPROVED HEAT TRANSFER FROM SEMICONDUCTOR PACKAGES - Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between an upper surface of a semiconductor package and a lower surface of a thermal member. The thermally conductive member is disposed above a first portion of the upper surface of the semiconductor package having a relatively higher thermal energy output when the semiconductor package is operating. A thermal interface material is disposed in the interstitial space and a force applied to the thermal member. The thermally conductive member forms a relatively higher pressure region above the first portion of the semiconductor package and a relatively lower pressure region in other portions of the semiconductor package remote from the thermally conductive member. The increased pressure region proximate the thermally conductive member beneficially enhances the flow of thermal energy from the first portion of the semiconductor package to the thermal member. | 2019-05-09 |
20190139856 | Ion-Implanted Thermal Barrier - Ion implantation can be used to define a thermal dissipation path that allows for better thermal isolation between devices in close proximity on a microelectronics chip, thus providing a means for higher device density combined with better performance. | 2019-05-09 |
20190139857 | SYNTHETIC DIAMOND HEAT SPREADERS - A synthetic diamond heat spreader that includes a first layer of synthetic diamond material forming a base support layer and a second layer of synthetic diamond material disposed on the first layer of synthetic diamond material and forming a diamond surface layer. The diamond surface layer has a thickness equal to or less than a thickness of the base support layer. The diamond surface layer has a nitrogen content less than that of the base support layer. The nitrogen content of the diamond surface layer and the diamond support layer is selected such that the thermal conductivity of the base support layer is in a range 1000 W/mK to 1800 W/mK and the thermal conductivity of the surface support layer is in a range 1900 W/mK to 2800 W/mK. | 2019-05-09 |
20190139858 | SEMICONDUCTOR DEVICE - A first inner heat conductor may include a plurality of first graphite layers. A second inner heat conductor may include a plurality of second graphite layers. The plurality of first graphite layers may be stacked in a first direction which is orthogonal to a direction in which a semiconductor element and a first heat radiator are arranged. The plurality of second graphite layers may be stacked in the direction in which the semiconductor element and the first heat radiator are arranged, or may be stacked in a second direction which is orthogonal to the direction in which the semiconductor element and the first heat radiator are arranged and orthogonal to the first direction. | 2019-05-09 |
20190139859 | POWER AND RF DEVICES IMPLEMENTED USING AN ENGINEERED SUBSTRATE STRUCTURE - An electronic device includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The electronic device also includes a buffer layer coupled to the support structure, a contact layer coupled to the buffer layer, and a field-effect transistor (FET) coupled to the contact layer. | 2019-05-09 |
20190139860 | PACKAGE STRUCTURE - A package structure is provided, including a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating layer is disposed on the first insulating layer, the chip is disposed in the second insulating layer, and the third insulating layer is disposed on the second insulating layer. The heat conductivity of the second insulating layer is lower than the heat conductivity of the first insulating layer, and the hardness of the second insulating layer is lower than the hardness of the first insulating layer. | 2019-05-09 |
20190139861 | STRUCTURE TO ENABLE HIGHER CURRENT DENSITY IN INTEGRATED CIRCUIT RESISTOR - An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate. | 2019-05-09 |
20190139862 | HEAT DISSIPATION APPARATUS AND METHOD FOR POWER SEMICONDUCTOR DEVICES - An improved heat dissipation apparatus for limiting the temperature of multiple power semiconductors featuring flow balancers to manipulate the hydrodynamic pressure of the coolant fluid to regulate the coolant fluid flow distribution across the heat exchange fins to either create uniform flow distribution or purposefully disproportionate or custom coolant fluid flow distribution for the purpose of achieving higher heat transfer efficiency. | 2019-05-09 |
20190139863 | COOLING APPARATUS - A cooling apparatus is provided with a casing having a top wall and a bottom wall and having a cooling fluid passage provided therein and a heat radiator disposed in the cooling fluid passage. The heat radiator is composed of a plurality of heat radiation units arranged in a vertically stacked manner and an intermediate plate arranged between adjacent heat radiation units. The heat radiation unit is composed of a substrate and a plurality of pin-like fins provided on the upper and lower surfaces of the substrate. The substrate of the heat radiation unit and the intermediate plate are separated in the vertical direction. The upper side pin-like fin of the upper end heat radiation unit is brazed to the top wall and the lower side pin-like fin of the lower end heat radiation unit is brazed to the bottom wall. To the intermediate plate between the adjacent heat radiation units, the pin-like fins of the heat radiation unit positioned on the upper and lower sides of the intermediate plate are brazed. | 2019-05-09 |
20190139864 | CAPPED THROUGH-SILICON-VIAs FOR 3D INTEGRATED CIRCUITS - The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits. | 2019-05-09 |
20190139865 | CHIP PACKAGE STRUCTURE - Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip package structure further includes a first photosensitive layer formed around sidewalls of the first chip and covering a top surface of the first chip and a second chip disposed over the first photosensitive layer. In addition, the first chip and the second chip are separated by the first photosensitive layer. | 2019-05-09 |
20190139866 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion. | 2019-05-09 |
20190139867 | CHIP ON FILM PACKAGE STRUCTURE - A chip on film (COF) package structure used to package a chip is disclosed. The COF package structure includes a flexible substrate, a conductive layer, a plating layer and a solder resist layer. A conductive layer is formed on the flexible substrate. A plating layer is formed on the conductive layer and has an opening area. A solder resist layer is formed on the plating layer and connected to the conductive layer through the opening area. The solder resist layer has a single layer structure. A bending area is defined in the COF package structure. The bending area is enclosed in the opening area and the bending area is smaller than or equal to the opening area. When the bending area of the COF package structure is bent, no plating layer exists in the bending area, so that the bending resistance of the bending area can be enhanced | 2019-05-09 |
20190139868 | SEMICONDUCTOR DEVICES AND METHODS AND APPARATUS TO PRODUCE SUCH SEMICONDUCTOR DEVICES - Semiconductor devices and methods and apparatus to produce such semiconductor devices are disclosed. An integrated circuit package includes a lead frame including a die attach pad and a plurality of leads; a die including a MEMs region defined by a plurality of trenches, the die electrically connected to the plurality of leads; and a mold compound covering portions of the die, the mold compound defining a cavity between a surface of the die and a surface of the mold compound, wherein the mold compound defines a vent. | 2019-05-09 |
20190139869 | Molded Semiconductor Package with C-Wing and Gull-Wing Leads - A semiconductor package includes a semiconductor die embedded in a molded package body, leads electrically connected to the die and protruding from a side face of the molded package body, and a recess extending inward from the side face and into a bottom main face of the molded package body to form a single groove. The recess begins below a region of the side face from which the leads protrude, so that this region of the side face is flat and each of the leads exits the molded package body in the same plane. A first subset of the leads is bent inward towards the molded package body and seated in the single groove, to form a first row of leads configured for surface mounting. A second subset of the leads extends outward from the molded package body, to form a second row of leads configured for surface mounting. | 2019-05-09 |
20190139870 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided, including: a package body; and a plurality of lead terminals exposed from each of at least three side surfaces of the package body, wherein the plurality of lead terminals include: a plurality of lead terminals exposed from a first side surface, half or more of which have tips pointing in a direction along the first side surface; a plurality of lead terminals exposed from a second side surface, all of which have tips pointing in a direction along a direction orthogonal to the second side surface; and a plurality of lead terminals exposed from a third side surface, half or more of which have tips pointing in a direction along the third side surface, or all of which have tips pointing in a direction along a direction orthogonal to the third side surface. | 2019-05-09 |
20190139871 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion. | 2019-05-09 |
20190139872 | PRESS-FIT PIN AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A press-fit pin increases contact area with the contact hole to provide appropriate contact pressure, reduce contact resistance, and increase heat transfer efficiency. The press-fit pin is of a semiconductor package including an end portion and a press unit extending from the end portion and is divided into a first press-fitting piece and a second press-fitting piece, the first press-fitting piece forming a convex portion in a first direction perpendicular to the direction of the press-fit pin and bending to a second direction perpendicular to the direction of the press-fit pin and forming 30-110 degrees with the first direction and the second press-fitting piece forming a convex portion in a third direction perpendicular to the direction of the press-fit pin and being 180 degrees with the first direction and bending to a fourth direction perpendicular to the direction of the press-fit pin and forming 250-330 degrees with the first direction. | 2019-05-09 |
20190139873 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part. | 2019-05-09 |
20190139874 | SEMICONDUCTOR DEVICE HAVING TWO SWITCHING ELEMENTS - A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a potential on a high potential side; a second terminal that has a potential on a low potential side; a third terminal that has a midpoint potential; and a resin part. A first potential part has potential equal to potential of the first terminal. A second potential part has potential equal to potential of the second terminal. A third potential part has potential equal to potential of the third terminal. A first creepage distance between the first potential part and the second potential part is longer than a minimum value of a second creepage distance between the first potential part and the third potential part and a third creepage distance between the second potential part and the third potential part. | 2019-05-09 |
20190139875 | FLAT NO-LEAD PACKAGE WITH SURFACE MOUNTED STRUCTURE - The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members. | 2019-05-09 |
20190139876 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps. | 2019-05-09 |
20190139877 | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD - A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on a first surface side of the laminate and second conductor pads on a second surface side of the laminate, and a solder resist layer interposed between the support plate and the laminate and having openings formed such that the openings are exposing the first conductor pads respectively. The laminate includes a resin insulating layer and has a first surface on the first surface side and a second surface on the second surface side on the opposite side with respect to the first surface of the laminate, the second conductor pads are embedded in the second surface of the laminate such that the second conductor pads have surfaces recessed from the second surface of the laminate respectively. | 2019-05-09 |
20190139878 | METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS - An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer. | 2019-05-09 |
20190139879 | MULTI-ROW WIRING MEMBER FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in the bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix. | 2019-05-09 |
20190139880 | Semiconductor Arrangement with Reliably Switching Controllable Semiconductor Elements - A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base section and first, second and third sections, the third section arranged between the first and second sections. The second conductor track has first and second sections. The first section of the second conductor track is arranged between the first and third sections of the first conductor track. The second section of the second conductor track is arranged between the second and third sections of the first conductor track. The third section of the first conductor track is arranged between the first and second sections of the second conductor track. First and second subsets of semiconductor chips are arranged on the first section of the second conductor track. Third and fourth subsets of semiconductor chips are arranged on the second section of the second conductor track. | 2019-05-09 |
20190139881 | SECURITY DEVICE SUCH THAT A SMART CARD - A security device includes a body and a contact interface including an external connection for external communication and an internal connection for internal communication. The body includes at least a first substrate and a second substrate lying in respective parallel planes. The contact interface is electrically connected to the first substrate and to the second substrate by the internal connection. The security device is a chip card, for example a bank card, or an identity document. | 2019-05-09 |
20190139882 | CIRCUIT ASSEMBLY AND MOUNTING UNIT - Each of busbars includes a bottom surface and a top surface. A holding member is made of resin and is formed integrally with the busbars. The bottom surface of each of the busbars includes exposed regions which are exposed downwards from the holding member. | 2019-05-09 |
20190139883 | PACKAGED SEMICONDUCTOR SYSTEM HAVING UNIDIRECTIONAL CONNECTIONS TO DISCRETE COMPONENTS - A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires. | 2019-05-09 |
20190139884 | COMBINED ELECTRODE AND THREE-LEVEL HIGH-POWER MODULE THEREOF - A combined electrode comprises a negative electrode, a first intermediate electrode, a positive electrode and a second intermediate electrode, wherein a main body portion of the negative electrode and a main body portion of the first intermediate electrode, a connection portion of the negative electrode and a connection portion of the first intermediate electrode, main body portions of the positive electrode and main body portions of the second intermediate electrode, and a connection portion of the positive electrode and a connection portion of the second intermediate electrode are arranged in parallel to and directly facing each other, thereby increasing a facing area between the negative electrode and the first intermediate electrode and between the positive electrode and the second intermediate electrode, reducing a current loop area between the negative electrode and the first intermediate electrode and between the positive electrode and the second intermediate electrode. | 2019-05-09 |
20190139885 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device includes a semiconductor substrate, a bottom insulating layer disposed on the semiconductor substrate, a first conductive layer which is a selective epitaxial growth layer disposed on the bottom insulating layer; a plurality insulating layers disposed over the bottom insulating layer; a plurality of second conductive layers alternatively stacked the insulating layers and insulated from the first conductive layer; a contact plug passing through the bottom insulating layer and electrically contacting the semiconductor substrate with the first conductive layer; a channel layer disposed on at least one sidewall of at least one first through opening and electrically contact the contact plug, wherein the first through opening passes through the insulating layers, the second conductive layers, so as to expose the contact plug; and a memory layer disposed between the channel layer and the second conductive layers. | 2019-05-09 |
20190139886 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein. | 2019-05-09 |
20190139887 | DIELECTRIC HELMET-BASED APPROACHES FOR BACK END OF LINE (BEOL) INTERCONNECT FABRICATION AND STRUCTURES RESULTING THEREFROM - Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types. | 2019-05-09 |
20190139888 | Package Structures and Method of Forming the Same - An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via. | 2019-05-09 |
20190139889 | LOSSY MIM CAPACITOR FOR ON-DIE NOISE REDUCTION - According to certain aspects of the present disclosure, a semiconductor die includes a decoupling capacitor between a first interconnect metal layer and a second interconnect metal layer of the die, a first supply rail formed from the second interconnect metal layer, and a resistive metal path coupled between the decoupling capacitor and the first supply rail. The decoupling capacitor may be a metal-insulator-metal (MIM) capacitor. In some embodiments, the resistive metal path includes a plurality of elongated segments, and one or more connecting segments, wherein each of the one or more connecting segments electrically couples a respective pair of the plurality of elongated segments. In some embodiments, the resistive metal path includes multiple vias coupled in series. | 2019-05-09 |
20190139890 | INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer. | 2019-05-09 |
20190139891 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE - A method includes etching a semiconductor substrate to form a fin. An isolation structure is formed over the semiconductor substrate and around the fin. The isolation structure and the semiconductor substrate are etched to form a recess. A barrier layer is deposited over a bottom surface and a sidewall of the recess. A conductive layer is deposited over the barrier layer. The conductive layer is recessed to form a conductive line, in which a top surface of the conductive line is lower than a top surface of the isolation structure. A dielectric cap layer is formed over the conductive line. The isolation structure and the dielectric cap layer are recessed, such that the fin protrudes from the recessed isolation structure. | 2019-05-09 |
20190139892 | VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE AND METHODS OF MAKING SAME - One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse. | 2019-05-09 |
20190139893 | Construction Of Integrated Circuitry And A Method Of Forming An Elevationally-Extending Conductor Laterally Between A Pair Of Structures - A method of forming an elevationally-extending conductor laterally between a pair of structures comprises forming a pair of structures individually comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line and the conductive via respectively have opposing sides in a vertical cross-section. Elevationally-extending-insulative material is formed along the opposing sides of the conductive via and the conductive line in the vertical cross-section. The forming of the insulative material comprises forming a laterally-inner-insulator material comprising silicon, oxygen, and carbon laterally-outward of the opposing sides of the conductive via and the conductive line in the vertical cross-section. A laterally-intervening-insulator material comprising silicon and oxygen is formed laterally-outward of opposing sides of the laterally-inner-insulator material in the vertical cross-section. The laterally-intervening-insulator material comprises less carbon, if any, than the laterally-inner-insulator material. A laterally-outer-insulator material comprising silicon, oxygen, and carbon is formed laterally-outward of opposing sides of the laterally-intervening-insulator material in the vertical cross-section. The laterally-outer-insulator material comprises more carbon than the laterally-inner-insulator material. Elevationally-extending-conductor material is formed laterally between and along the insulative material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed. | 2019-05-09 |
20190139894 | BICONVEX LOW RESISTANCE METAL WIRE - At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance. | 2019-05-09 |
20190139895 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE LINE - A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench. | 2019-05-09 |
20190139896 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection layer. The die includes a first surface and a second surface opposite to each other. The encapsulant is aside the die. The RDL structure is electrically connected to the die though a plurality of conductive bumps. The RDL structure is underlying the second surface of the die and the encapsulant. The protection layer is located over the first surface of the die and the encapsulant. The protection layer is used for controlling the warpage of the package structure. | 2019-05-09 |
20190139897 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film. | 2019-05-09 |
20190139898 | CHIP PACKAGE STRUCTURE AND CHIP PACKAGE STRUCTURE ARRAY - A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided. | 2019-05-09 |
20190139899 | SEMICONDUCTOR PACKAGES HAVING SEMICONDUCTOR CHIPS DISPOSED IN OPENING IN SHIELDING CORE PLATE - A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer. | 2019-05-09 |
20190139900 | SEMICONDUCTOR PACKAGES INCLUDING DIE OVER-SHIFT INDICATING PATTERNS - A semiconductor package includes a package substrate including a die attachment region, a semiconductor die attached to the die attachment region, and a die over-shift indicating pattern disposed on or in the package substrate and spaced apart from the die attachment region. The die over-shift indicating pattern is used as a reference pattern for obtaining a shifted distance of the semiconductor die. | 2019-05-09 |
20190139901 | SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT - A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge. | 2019-05-09 |
20190139902 | ULTRA-THIN THERMALLY ENHANCED ELECTRO-MAGNETIC INTERFERENCE SHIELD PACKAGE - A method to fabricate an electronic package is described and includes the steps of: connecting a plurality of semiconductor chips to at least one surface of a substrate using a connect pad; encapsulating the semiconductor chips with a non-conductive material; and forming an electro-magnetic interference shield layer over the encapsulated semiconductor chip. | 2019-05-09 |
20190139903 | FABRICATION METHOD OF SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a semiconductor strip in a seal ring area. The semiconductor structure further includes a dielectric structure extending into the semiconductor strip, wherein a plurality of metal structures and a plurality of via structures stack over the dielectric structure to form a seal ring structure. | 2019-05-09 |
20190139904 | DIELECTRIC CRACK STOP FOR ADVANCED INTERCONNECTS - An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material. | 2019-05-09 |
20190139905 | FLEXIBLE CIRCUIT BOARD, METHOD FOR MOUNTING THE SAME, AND DISPLAY DEVICE - A flexible circuit board, a display device and a method for mounting a flexible circuit board are disclosed. The flexible circuit board includes: a bendable portion, the flexible circuit board being bendable at the bendable portion to go into a bent state so as to be connected to a workpiece; and at least one opening in the bendable portion. In response to the bent state, a gap is formed between the bendable portion and the workpiece, and the at least one opening is in communication with the gap. | 2019-05-09 |
20190139906 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An object of the present invention is to obtain a semiconductor device having highly reliable bonding portions. The semiconductor device according to the present invention includes an insulating substrate on which a conductive pattern is formed, and an electrode terminal and a semiconductor element which are bonded to the conductive pattern, the electrode terminal and the conductive pattern are bonded by ultrasonic bonding on a bonding face, and the ultrasonic bonding is performed at a plurality of positions. | 2019-05-09 |
20190139907 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element. | 2019-05-09 |
20190139908 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove. | 2019-05-09 |
20190139909 | Physical Unclonable Functions in Integrated Circuit Chip Packaging for Security - In the invention described, magnetic field characteristics of randomly placed magnetized particles are exploited by using the magnetic field fluctuations produced by the particles as measured by a sensor. The magnetized particles generate a complex magnetic field near the surface of an integrated circuit chip that can be used as a “fingerprint.” The positioning and orientation of the magnetized particles is an uncontrolled process, and thus the interaction between the sensor and the particles is complex. The randomness of the magnetic field magnitude and direction near the surface of the material containing the magnetic particles can be used to obtain a unique identifier for an item such as an integrated circuit chip carrying the PUF. | 2019-05-09 |
20190139910 | ZERO CAPACITANCE ELECTROSTATIC DISCHARGE DEVICES - In some examples, an electrostatic discharge (ESD) device includes a substrate layer, a transition layer positioned on the substrate layer, a plurality of superlattice layers on the transition layer and including at least two doped superlattice layers. The ESD device further includes a plurality of doped contact structures extending from the transition layer to a surface of an outermost layer of the plurality of superlattice layers, where a first of the plurality of doped contact structures comprises an anode and a second of the plurality of doped contact structures comprises a cathode, where the plurality of doped contact structures are to generate a zero capacitance ESD device. | 2019-05-09 |
20190139911 | Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging - A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected. | 2019-05-09 |
20190139912 | ANTENNA MODULE - An antenna module includes a fan-out semiconductor package including an IC, an encapsulant encapsulating at least a portion of the IC, a core member having a first side surface facing the IC or the encapsulant, and a connection member including at least one wiring layer electrically connected to the IC and the core member and at least one insulating layer; and an antenna package including a plurality of first directional antenna members configured to transmit or receive a first RF signal. The fan-out semiconductor package further includes at least one second directional antenna member disposed on a second side surface of the core member opposing the first side surface of the core member, stood up from a position electrically connected to at least one wiring layer, and configured to transmit or receive a second RF signal. | 2019-05-09 |
20190139913 | ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic package and a method for fabricating the same are provided. The method includes disposing an antenna substrate on a package structure through a plurality of conductive elements. The antenna substrate has an antenna layer and the package structure has an electronic component. As such, an antenna length can be designed according to the requirement of antenna operation, without increasing the area of the package structure. | 2019-05-09 |
20190139914 | MICROWAVE IC WAVEGUIDE DEVICE MODULE - A microwave IC waveguide device module includes: a substrate having a throughhole; a microwave IC provided on or above the first face of the substrate; a waveguide member provided below the second face of the substrate opposite from the first face, the waveguide member having an electrically conductive waveguide face which opposes the throughhole; an electrically conductive member covering at least a portion of the second face that extends in a manner of following along the waveguide face; and an artificial magnetic conductor on both sides of the waveguide member. The substrate includes an inner-wall electrically conductive portion covering an inner wall of the throughhole and being electrically connected with the electrically conductive member. The signal terminal and the ground terminal of the IC are electrically connected respectively with two portions of the inner-wall electrically conductive portion opposing each other with the throughhole interposed therebetween. | 2019-05-09 |
20190139915 | WIRELESS MODULE WITH ANTENNA PACKAGE AND CAP PACKAGE - Wireless modules having a semiconductor package attached to an antenna package and cap package are disclosed. The semiconductor package may have one or more electronic components disposed thereon. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The cap package may also be attached to the semiconductor package on a side opposing the side on which the antenna package is disposed. The cap package may provide routing and/or additional antenna elements. The cap package may also allow for thermal grease to be dispensed therethrough. The antenna package, the cap package, and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct. | 2019-05-09 |
20190139916 | PACKAGE STRUCTURES - A package structure includes at least one semiconductor chip, an insulating encapsulation, and a redistribution circuit structure. The semiconductor chip has an active surface and connecting pads distributed thereon. The insulating encapsulation encapsulates the semiconductor chip. The redistribution circuit structure is disposed on and has at least one metallization layer with metal segments, wherein the redistribution circuit structure is electrically connected to the semiconductor chip through the at least one metallization layer and the connecting pads electrically connected thereto. A projection location of a first gap between any two most adjacent connecting pads of the connecting pads is partially overlapped with a projection location of a second gap between any two most adjacent metal segments of the metal segments of the at least one metallization layer in a vertical projection on the active surface of the at least one semiconductor chip. | 2019-05-09 |
20190139917 | MICRO-CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF - A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump. | 2019-05-09 |
20190139918 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: preparing a semiconductor substrate including an electrode; forming a wire connected to the electrode; forming a first insulating film including a first opening that partially exposes the wire; forming a base portion that is connected to a portion of the wire exposed via the first opening, and that comprises a conductor including a recess corresponding to the first opening; forming a solder film on a surface of the base portion; and fusing solder included in the solder film by a first heat treatment, and filling the recess with the fused solder. | 2019-05-09 |
20190139919 | CORROSION RESISTANT ALUMINUM BOND PAD STRUCTURE - A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer. | 2019-05-09 |
20190139920 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a first structure including a first semiconductor chip, a first encapsulant encapsulating at least portions of the first semiconductor chip, and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the first connection pads; and a second structure including a second semiconductor chip, a second encapsulant encapsulating at least portions of the second semiconductor chip, and a second connection member disposed on the semiconductor chip and including a second redistribution layer electrically connected to the second connection pads. The first and second structures are disposed so that first and second active surfaces face each other, and the first and second redistribution layers are connected to each other through a low melting point metal disposed between the first and second redistribution layers. | 2019-05-09 |
20190139921 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a contact pad arranged in the substrate, a bump arranged on the contact pad to be electrically connected with the contact pad, an insulating film arranged on the substrate to surround a side surface of the bump and to expose at least a portion of the contact pad to the bump, and a photosensitive film which is formed on the insulating film and comprises a polyimide, wherein the photosensitive film comprises a first region surrounding the side surface of the bump and having a first thickness measured in a vertical direction, and a second region arranged on the first region and having a second thickness thickermeasured in the vertical direction, wherein the second region is spaced apart from the bump in a horizontal direction, and wherein the second thickness is greater than a thickness two times thicker than a difference value between the second thickness and the first thickness. | 2019-05-09 |
20190139922 | Multi-Chip Package and Method of Formation - A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer. | 2019-05-09 |
20190139923 | STACKED RADIO FREQUENCY DEVICES - Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement. | 2019-05-09 |
20190139924 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars. | 2019-05-09 |
20190139925 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes an insulating encapsulation, at least one first chip, a redistribution layer and a bonding layer. The at least one first chip is encapsulated in the insulating encapsulation. The redistribution layer is located on the insulating encapsulation and the at least one first chip and electrically connected to the at least one first chip. The bonding layer mechanically connects the redistribution layer and the at least one first chip. | 2019-05-09 |
20190139926 | HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE - Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads. | 2019-05-09 |
20190139927 | ANISOTROPIC CONDUCTIVE FILM - An anisotropic conductive film which can be used as a standard product as long as no problems arise in anisotropic conductive connections, even in a case where omissions are present in a prescribed disposition of conductive particles, includes a regular disposition region in which conductive particles are disposed regularly in an insulating resin binder, and has a length of 5 m or greater. A standard region including no sections with more than a prescribed number of consecutive omissions in conductive particles is present in the regular disposition region over a prescribed width in a short-side direction of the anisotropic conductive film and at least a prescribed length in a long-side direction of the anisotropic conductive film. | 2019-05-09 |
20190139928 | DIE BONDING RESIN LAYER FORMING APPARATUS - A die bonding resin layer forming apparatus includes a liquid resin applying part including a chuck table that holds a wafer in such a manner that the back surface side is exposed and an applying unit that applies a liquid resin to the back surface side of the wafer held by the chuck table, a waiting part that holds the wafer to which the liquid resin has been applied by the liquid resin applying part and waits to dry the liquid resin applied to the wafer while enhancing flatness of the liquid resin, a curing part that gives an external stimulus to the liquid resin dried by the waiting part to cure the liquid resin and form the die bonding resin layer, and a conveying unit that conveys the wafer among the liquid resin applying part, the waiting part, and the curing part. | 2019-05-09 |
20190139929 | DETECTION OF FOREIGN PARTICLES DURING WIRE BONDING - A method of bonding wires onto surfaces, an apparatus and a computer program product are disclosed. The method of bonding wires onto surfaces, comprises the steps of: collecting operating characteristics of a bonding tool while forming a wire bond which bonds a wire to a surface; determining whether a possible bonding failure of the wire bond has occurred as indicated by the operating characteristics; and capturing an image of the wire bond to identify whether a foreign body is present on the surface if it is determined that a possible bonding failure has occurred. In this way, imaging of the wire bond is only necessary when the operating characteristics indicate a suspect bonding failure has occurred. This avoids the need to image every bond, while still imaging suspect bonds. This approach helps to significantly increase the throughput of the wire bonding apparatus whilst still identifying and classifying bonding defects due to the presence of a foreign body. | 2019-05-09 |
20190139930 | CONDUCTIVE PASTE AND DIE BONDING METHOD - Provided are: a conductive paste in which sinterability of silver particles the conductive paste can be easily controlled by using silver particles having predetermined crystal transformation characteristics defined by an XRD analysis, and after a sintering treatment, excellent electrical conductivity and thermal conductivity can be stably obtained; and a die bonding method using the conductive paste. | 2019-05-09 |
20190139931 | SENSOR, METHOD AND SENSOR ARRANGEMENT - A sensor including a system-in-package module, wherein electrical contacts can be contact-connected by way of a mating connector. An associated method and an associated sensor arrangement are also disclosed. | 2019-05-09 |
20190139932 | METHOD OF MASS TRANSFERRING ELECTRONIC DEVICE - A method of mass transferring electronic devices includes following steps. A wafer is provided. The wafer includes a substrate and a plurality of electronic devices. The electronic devices are arranged in a matrix on a surface of the substrate. The wafer is attached to a temporary fixing film. The wafer is cut so that the wafer is divided into a plurality of blocks. Each of the blocks includes at least a part of the electronic devices and a sub-substrate. The temporary fixing film is stretched so that the blocks on the temporary fixing film are separated from each other as the temporary fixing film is stretched. At least a part of the blocks is selected as a predetermined bonding portion, and each of the blocks in the predetermined bonding portion is transferred to a carrying substrate in sequence, so that the electronic devices in the predetermined bonding portion are bonded to the carrying substrate. The sub-substrates of the blocks are removed. Another method of mass transferring electronic devices is also provided. | 2019-05-09 |
20190139933 | 3D Chip-on-Wafer-on-Substrate Structure with Via Last Process - Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate. | 2019-05-09 |
20190139934 | SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE SHINGLED STACKS OF SEMICONDUCTOR DIES - A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack. | 2019-05-09 |
20190139935 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THE SAME - Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 μm. | 2019-05-09 |
20190139936 | MICROELECTRONIC DEVICE STACKS HAVING INTERIOR WINDOW WIREBONDING - A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or “window” formed therethrough. The first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or “window” in the first microelectronic die. | 2019-05-09 |
20190139937 | INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING AN INTEGRATED FAN-OUT PACKAGE - In accordance with some embodiments of the present disclosure, an integrated fan-out (INFO) package includes a substrate, a molding compound, a buffer layer, a first chip, a second chip, and a redistribution circuit structure layer. The molding compound is disposed on the substrate. The buffer layer is disposed on the substrate and includes a first buffer pattern and a second pattern separated from the first buffer pattern by a distance. A thickness of the first buffer pattern is greater than a thickness of the second buffer pattern. The first chip is attached to the substrate through the first buffer pattern and surrounded by the molding compound. The second chip is attached to the substrate through the second buffer pattern and surrounded by the molding compound. The redistribution circuit structure layer is disposed on the molding compound and electrically connected to the first chip and the second chip. | 2019-05-09 |
20190139938 | LARGE CHANNEL INTERCONNECTS WITH THROUGH SILICON VIAS (TSVS) AND METHOD FOR CONSTRUCTING THE SAME - An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure. | 2019-05-09 |
20190139939 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface. | 2019-05-09 |