19th week of 2012 patent applcation highlights part 67 |
Patent application number | Title | Published |
20120117324 | VIRTUAL CACHE WINDOW HEADERS FOR LONG TERM ACCESS HISTORY - A method of virtual cache window headers for long term access history is disclosed. The method may include steps (A) to (C). Step (A) may receive a request at a circuit from a host to access an address in a memory. The circuit generally controls the memory and a cache. Step (B) may update the access history in a first of the headers in response to the request. The headers may divide an address space of the memory into a plurality of windows. Each window generally includes a plurality of subwindows. Each subwindow may be sized to match one of a plurality of cache lines in the cache. A first of the subwindows in a first of the windows may correspond to the address. Step (C) may copy data from the memory to the cache in response to the access history. | 2012-05-10 |
20120117325 | METHOD AND DEVICE FOR PROCESSING DATA CACHING - The present invention discloses a method and device for processing data caching, wherein the method includes: storing cached data into a memory; after reading out the cached data from a memory space address for storing the cached data in the memory, judging whether the cached data that have been read out are the same as the cached data to be written before the storing, if so, then deciding that the memory space for storing the cached data in the memory is normal; if not, then deciding that the memory space for storing the cached data in the memory is abnormal; and when the cached data is stored during the subsequent data caching process, storing the cached data only into the memory spaces in normal state in the memory. | 2012-05-10 |
20120117326 | APPARATUS AND METHOD FOR ACCESSING CACHE MEMORY - The present invention relates to an apparatus and a method for accessing a cache memory. The cache memory comprises a level-one memory and a level-two memory. The apparatus for accessing the cache memory according to the present invention comprises a register unit and a control unit. The control unit receives a first read command and a reject datum of the level-one memory and stores the reject datum of the level-one memory to the register unit. Then the control unit reads and stores a stored datum of the level-two memory to the level-one memory according to the first read command. | 2012-05-10 |
20120117327 | Bimodal Branch Predictor Encoded in a Branch Instruction - Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes. | 2012-05-10 |
20120117328 | Managing a Storage Cache Utilizing Externally Assigned Cache Priority Tags - A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium. | 2012-05-10 |
20120117329 | COMBINATION BASED LRU CACHING - Combination based LRU caching employs a mapping mechanism in an LRU cache separate from a set of LRU caches for storing the values used in the combinations. The mapping mechanism is used to track the valid combinations of the values in the LRU caches storing the values resulting in any given value being stored at most once. Through the addition of a byte pointer significantly more combinations may be tracked in the same amount of cache memory with full LRU semantics on both the values and combinations. | 2012-05-10 |
20120117330 | METHOD AND APPARATUS FOR SELECTIVELY BYPASSING A CACHE FOR TRACE COLLECTION IN A PROCESSOR - A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed. | 2012-05-10 |
20120117331 | NOTIFICATION PROTOCOL BASED ENDPOINT CACHING OF HOST MEMORY - An endpoint device ( | 2012-05-10 |
20120117332 | SYNCHRONIZING COMMANDS FOR PREVENTING DATA CORRUPTION - A method and apparatus for synchronizing input/output commands is provided. An incoming command mask representing an incoming input/output command associated with a memory region is created. In response to a determination that a pending input/output command associated with the memory region is pending, a bitwise inversion operation is performed on the incoming command mask to form a modified incoming command mask. A bitwise AND operation is performed on the modified incoming command mask and the pending command mask to form a pending command locking mask associated with the pending input/output command. A bitwise OR operation is performed between an existing memory lock for a same type of commands and incoming command bit mask to form a new memory region lock. | 2012-05-10 |
20120117333 | CRITICAL SECTION DETECTION AND PREDICTION MECHANISM FOR HARDWARE LOCK ELISION - A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction. | 2012-05-10 |
20120117334 | READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS - A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item. | 2012-05-10 |
20120117335 | LOAD ORDERING QUEUE - A method and apparatus to utilize a strong ordering scheme to be performed on memory operations in a processor to prevent performance degradation caused by out-of-order memory operations is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing information associated with a first load operation in a load queue, the first load operation being executed out-of-order with respect to one or more second load operations. The method also includes detecting a snoop hit on the first load operation. The method further includes re-executing the first load operation in response to detecting the snoop hit. | 2012-05-10 |
20120117336 | CIRCUITS AND METHODS FOR PROVIDING DATA TO AND FROM ARRAYS OF MEMORY CELLS - A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals. | 2012-05-10 |
20120117337 | SEMICONDUCTOR INTEGRATED CIRCUIT AND EXPONENT CALCULATION METHOD - Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data. | 2012-05-10 |
20120117338 | METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES - A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time. | 2012-05-10 |
20120117339 | FLEXIBLE CONTENT STORAGE MANAGEMENT FOR DVRS - A media broker comprises a communication interface and a controller associated with the communication interface configured to receive a request from a user to record a requested media item. The media broker proceeds to query an aggregated stored content list (ASCL) including information indicative of each of the media items stored on one or more media storage device communicatively coupled to the media broker to determine if the requested media item is stored on the one or more media storage devices. If it is determined that the requested media item is stored on the one or more media storage devices the user that requested the media item is informed and the media item is stored on the one or more media storage devices. Conversely, if it is determined that the requested media item is not stored on the one or more media storage devices, the requested media item is recorded. | 2012-05-10 |
20120117340 | DATA ADMINISTRATION UNIT, DATA ACCESS UNIT, NETWORK ELEMENT, NETWORK, AND METHOD FOR UPDATING A DATA STRUCTURE - A data administration unit for updating a first data structure in a first memory may comprise a second memory, a data structure generator for setting up a second data structure in the second memory, a pointer generator for setting at least one of a dynamic change indicator and a pointer in the first data structure, a waiting unit for waiting for a finalization of a data access of a data access unit, and a data structure over-writer for overwriting the first data structure using data of the second data structure. An data access unit for accessing a first data structure in a first memory may comprise a data access driver, a first synchronization signal evaluator for reception and evaluation of a first synchronization signal, and a synchronization approval signal generator for generation and submission of a first synchronization signal. | 2012-05-10 |
20120117341 | METHOD AND SYSTEM FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - There are provided a method of transforming a non-transformed stored logical data object (LO) device into a transformed LO and system thereof. The method comprises: a) in response to a respective transformation request, logically dividing the non-transformed LO in a first segment and one or more non-transformed subsequent segments, the segments having predefined size; b) generating a header for the respective transformed LO; c) processing said first segment; d) overwriting said first segment by said generated header and said transformed first segment; e) indexing said first transformed segment and said one or more non-transformed subsequent segments as constituting a part of said transformed LO; f) generating at least one index section; and g) updating the indication in the header to point that the non-transformed LO has been transformed in the transformed LO comprising said generated header, said first transformed segment, said one or more subsequent segments comprising data in non-transformed form and said at least one index section. | 2012-05-10 |
20120117342 | RESTORE FROM BLOCK LEVEL BACKUP - A computer implemented method includes creating a child disk for a machine. A configuration of a backed up disk drive is derived from a storage container that includes a block level backup copy of the disk drive. The child disk is populated with selected data from blocks of data corresponding to selected files desired to be used on the machine. Drivers may be injected and registries modified to start with booting of the virtual. | 2012-05-10 |
20120117343 | MERGING DATA VOLUMES AND DERIVATIVE VERSIONS OF THE DATA VOLUMES - Responsive to an instruction to collapse a derivative version of an ancestor data volume into the ancestor data volume, it is determined if a characteristic of the derivative version of the ancestor data volume satisfies a criteria relative to a characteristic of the ancestor data volume. If the characteristic of the derivative version satisfies the criteria, the ancestor data volume is merged into the derivative version of the underlying data to form an updated derivative version. The updated derivative version is established as the ancestor data volume. | 2012-05-10 |
20120117344 | COMPUTING SYSTEM AND HIBERNATION METHOD THEREOF - A hibernation method of a computing system that includes generating backup data and write addresses according to at least a portion of data utilized by the computing system at a hibernation request, generating conversion addresses corresponding to a first non-volatile memory when the write addresses correspond to a second non-volatile memory, and storing the backup data in the first non-volatile memory according to either the write addresses or the conversion addresses. | 2012-05-10 |
20120117345 | METHOD AND APPARATUS FOR BACKUP AND RESTORE IN A DYNAMIC CHUNK ALLOCATION STORAGE SYSTEM - Backup and restore operations are made possible in a storage system that has dynamic chunk allocation (DCA) capability. In a DCA storage system, a chunk of physical storage area is not allocated to a segment of a volume until a write command is received targeting the segment of the volume. During a restore operation of the volume in the DCA storage system, the wasting of storage capacity when a backup image of the volume is restored is mitigated by preventing allocation of physical storage areas to segments of restore data that are only void data. | 2012-05-10 |
20120117346 | USER INTERFACE INDICATOR FOR MOBILE DEVICE BACKUP STATUS - Systems and methods are provided for performing data backup of a communication device. Data backup can occur automatically or manually. A data backup status indicator is displayed on the communication device indicating the current status of the data backup. The user can select the data backup status indicator to obtain additional information about the status of the data backup service. | 2012-05-10 |
20120117347 | INITIALIZING OF A MEMORY AREA - A method for initializing a memory area, the method includes: receiving a request to access a first memory sub area of a first memory area that comprises multiple memory sub areas; and initializing the first memory sub area if a first memory area initialization indicator differs from a first memory sub area initialization request indicator; wherein the first memory area initialization request indicator is a multiple bit variable indicative of a time of a last request to initialize the first memory area and the first memory sub area initialization indicator is a multiple bit variable indicative of a time of a request to initialize the first memory area that resulted in a last initialization of the first memory sub area. | 2012-05-10 |
20120117348 | TECHNIQUES FOR SECURITY MANAGEMENT PROVISIONING AT A DATA STORAGE DEVICE - Techniques for a data storage device to locally implement security management functionality. In an embodiment, a security management process of the data storage device is to determine whether an access to non-volatile media of the data storage device is authorized. In certain embodiments, the data storage device is to restrict access to a secure region of the non-volatile storage media, the secure region to store information used and/or generated by a security management process of the data storage device. | 2012-05-10 |
20120117349 | SPATIAL EXTENT MIGRATION FOR TIERED STORAGE ARCHITECTURE - Provided are techniques for migrating a first extent, determining a spatial distance between the first extent and a second extent, determining a ratio of a profiling score of the second extent to the spatial distance, and, in response to determining that the ratio exceeds a threshold, migrating the second extent. | 2012-05-10 |
20120117350 | POWER ECONOMIZING BY POWERING DOWN HUB PARTITIONS - An approach to power economization in a spoke and hub environment is presented. When a hub receives a data set from a first spoke, the hub writes the data set to a first partition that is associated with the first spoke. After the data transfer is complete, the hub powers down the first partition. If the first spoke sends additional data transfers to the hub while the first partition is powered down, the hub stores the additional data transfers in a second partition. When the first partition is powered up again, the hub moves the data intended for the first partition and that was stored in the second partition. The data is moved from the second partition to the first partition. The hub may monitor the size of the addition data transfers. If the data transfer is large, the hub may power up the first partition, write the data in the first partition, and move to the first partition any data that was intended for the first partition but written to the second partition while the first partition was powered down. | 2012-05-10 |
20120117351 | BALANCING MEMORY UTILIZATION IN A DISPERSED STORAGE NETWORK - A method begins by a processing module storing a plurality of encoded data slices in a plurality of memory devices of a dispersed storage (DS) unit of a dispersed storage network (DSN) memory using a quantity load balancing function to substantially balance a quantity of encoded data slices stored within each of the plurality of memory devices, wherein data size of at least some of the plurality of encoded data slices is different. The method continues with the processing module determining whether an available memory imbalance exists between a first memory device of the plurality of memory devices and a second memory device of the plurality of memory devices. The method continues with the processing module migrating one or more encoded data slices between the first and second memory devices to reduce the available memory imbalance when the available memory imbalance exists. | 2012-05-10 |
20120117352 | Docbase management system and implementing method thereof - The present invention discloses a docbase management system, including a first module, adapted to parse a received invocation from an application and generate an execution plan which comprises operations on physical storage; a second module, adapted to execute the execution plan to schedule a third module to execute the operations on physical storage in the execution plan; and the third module, adapted to execute the operations on physical storage in the execution plan under the scheduling of the second module. Since the implementation of the docbase management system is divided into hierarchies, and the hierarchies are independent of each other, the docbase management system is well extendable, scalable and maintainable. | 2012-05-10 |
20120117353 | CLIENT PARTITION SCHEDULING AND PRIORITIZATION OF SERVICE PARTITION WORK - A method in a data processing system is provided for processing a service request of a client partition. The method includes: obtaining by a service partition of the data processing system the service request from the client partition, wherein both the client and service partitions execute above a hypervisor of the data processing system; and processing the service request by the service partition utilizing a processor quantum assigned to the client partition and donated by the client partition to the service partition. The client partition controls scheduling of the service partition by queuing the service request at the client partition until the client partition decides to proceed with execution of the service request by the service partition. In one implementation, the service partition is a partition adjunct of the data processing system, which utilizes donated virtual address space of the client partition. | 2012-05-10 |
20120117354 | STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD - According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller. | 2012-05-10 |
20120117355 | Memory Management for a Dynamic Binary Translator - A dynamic binary translator apparatus, method and program for translating a first block of binary computer code intended for execution in a subject execution environment having a first memory of one page size into a second block for execution in a second execution environment having a second memory of another page size, comprising a redirection page mapper responsive to a page characteristic of the first memory for mapping an address of the first memory to an address of the second memory; a memory fault behaviour detector operable to detect memory faulting during execution of the second block and to accumulate a fault count to a trigger threshold; and a regeneration component responsive to the fault count reaching the trigger threshold to discard the second block and cause the first block to be retranslated with its memory references remapped by a page table walk. | 2012-05-10 |
20120117356 | Invalidating a Range of Two ro More Translation Table Entries and Instruction Therefore - An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 2012-05-10 |
20120117357 | ENERGY TILE PROCESSOR - An energy tile processor in which an internal structure of a single processor is divided into a part for supplying instructions and another part for executing the instructions in order for operating voltages and operating frequencies to be supplied independently. The processor includes an instruction supply unit storing instructions and issuing instructions to be executed, a first execution unit executing an integer operation and a memory operation according to an operation type of the instruction issued by the instruction supply unit, and a second execution unit executing a floating point operation according to an operation type of the instruction issued by the instruction supply unit. The instruction supply unit, the first execution unit, and the second execution unit are driven at operating voltages and operating frequencies which are independently controlled. | 2012-05-10 |
20120117358 | Software Selectable Adjustment of SIMD Parallelism - Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a mode of operation requiring a subset of the parallel processing capacity. At least one parallel processing element, that is not needed, can be shut down to conserve power. At a later time, when the added capacity is needed, execution of another software instruction sets the mode of operation to that of the wider data path, typically the full width, and the mode change reactivates the previously shut-down processing element. | 2012-05-10 |
20120117359 | NO-DELAY MICROSEQUENCER - An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit may be configured to (i) decode the instructions one at a time and (ii) present a sequence of the commands at an interface. The sequence (i) may be based on the decoding and (ii) may have no delays between consecutive the commands at the interface. | 2012-05-10 |
20120117360 | DEDICATED INSTRUCTIONS FOR VARIABLE LENGTH CODE INSERTION BY A DIGITAL SIGNAL PROCESSOR (DSP) - In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The DSP selectively uses a dedicated insert instruction to insert a variable number of bits into a register. | 2012-05-10 |
20120117361 | Processing Data Communications Events In A Parallel Active Messaging Interface Of A Parallel Computer - Processing data communications events in a parallel active messaging interface (‘PAMI’) of a parallel computer that includes compute nodes that execute a parallel application, with the PAMI including data communications endpoints, and the endpoints are coupled for data communications through the PAMI and through other data communications resources, including determining by an advance function that there are no actionable data communications events pending for its context, placing by the advance function its thread of execution into a wait state, waiting for a subsequent data communications event for the context; responsive to occurrence of a subsequent data communications event for the context, awakening by the thread from the wait state; and processing by the advance function the subsequent data communications event now pending for the context. | 2012-05-10 |
20120117362 | REPLAY OF DETECTED PATTERNS IN PREDICTED INSTRUCTIONS - Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued. | 2012-05-10 |
20120117363 | INTEGRATED CIRCUIT DESIGN AND OPERATION - Integrated circuit design and operation techniques are disclosed. In some embodiments, a data store stores, for each of a plurality of cores, a core image data comprising metadata about or otherwise associated with the core. A processor receives an indication of an application-related objective and uses core image data stored in the data store to identify programmatically a set of two or more cores from among the plurality of cores to help achieve the objective and to configure the two or more cores to help achieve the objective. | 2012-05-10 |
20120117364 | Method and System for Operating a Handheld Calculator - A method for operating a handheld calculator having a controllable power domain is provided. The method includes receiving, by the handheld calculator, a signal to power down the handheld calculator, storing context information of at least one component in the controllable domain in an external memory, setting a boot indicator to indicate a quick boot on power up, and removing power from the controllable power domain. | 2012-05-10 |
20120117365 | FIRMWARE UPDATE METHOD AND SYSTEM FOR MICRO-CONTROLLER UNIT IN POWER SUPPLY UNIT - Disclosed is a firmware update system for a micro-controller unit in a power supply unit. The micro-controller unit includes a central processing unit and a flash memory connected to the central processing unit. The flash memory includes a boot program sector, a main program sector, and a temporary data sector, where the boot program sector contains a boot program and the main program sector contains a main program to be executed by the central processing unit under a normal operating mode, and the temporary data sector is set to contain a downloaded firmware code to be copied to the main program sector to replace the main program, thereby updating the flash memory. The downloaded firmware code contains a sector checksum value and a firmware signature for allowing the boot program to validate if the downloaded firmware code is valid and authentic, and the boot program sector and the main program sector are accessed by a virtual address. | 2012-05-10 |
20120117366 | METHOD FOR CONTROLLING MULTI-PORT NETWORK INTERFACE CARD - A method for controlling a multi-port Network Interface Card (NIC) is provided. In a computer using the multi-port NIC with a plurality of NIC ports, a plurality of control options is set into a Basic Input/Output System (BIOS) setup menu, so that a user individually controls the NIC ports. Furthermore, due to the characteristic that after a reference code process in the BIOS restarts a system, the set of hardware becomes effective, an action of controlling the NIC ports is set before a reference code process restarts the system. | 2012-05-10 |
20120117367 | ELECTRONIC APPARATUS AND BOOTING METHOD THEREOF - An electronic apparatus and a booting method thereof are provided. First boot partition information of the electronic apparatus recorded at previous booting is obtained. Second boot partition information at current booting is obtained. Next, the first boot partition information and the second boot partition information are compared, so as to update the first boot partition information with a changed entry. Thereafter, a boot order is decided according to the updated first boot partition information. | 2012-05-10 |
20120117368 | Method for Rapidly Booting Up a Computer System - A method for booting up a computer is disclosed. Initially, a memory image of a boot program is stored in a main memory of a computer. The memory image includes a first initialization code and a second initialization code. During the booting process of the computer, first initialization code is executed. In response to the completion of the execution of the first initialization code, the boot program is shifted to an idle state. In response to an activation event, the second initialization code is executed. | 2012-05-10 |
20120117369 | PLATFORM BOOT WITH BRIDGE SUPPORT - A method for booting a processing device, the processing device comprising a first and a second processing unit, the method comprising: detecting by the first processing unit, whether at least one boot configuration parameter is accessible from a non-volatile storage medium of the processing device, the at least one configuration parameter being indicative of a boot interface; if said at least one configuration parameter is available, forwarding at least a part of the detected at least one configuration parameter by the first processing unit to the second processing unit; otherwise detecting by at least one of the first and second processing units whether a boot interface is available to the processing device; booting at least the second processing unit from the indicated or detected boot interface. | 2012-05-10 |
20120117370 | HARDWARE DIAGNOSTICS AND SOFTWARE RECOVERY ON HEADLESS SERVER APPLIANCES - Described is a headless server appliance configured with a secondary actuation mechanism that when actuated, enters the headless server appliance into a diagnostic mode. For example, the diagnostic mode may correspond to a secondary operating system booted from a BIOS component activated by the secondary actuation mechanism. In the diagnostic mode, primitives may be communicated between a client device coupled (e.g., via a network or USB connection) to the headless server appliance, such as to provide the client device with access to the headless server appliance's hard disk. Other primitives, such as communicated via APIs, may provide the client device with access to the BIOS. The secondary operating system and/or client device may perform diagnostics and recovery operations on the headless server appliance. For example, the client device or similar source may restore or update the primary operating system image to a storage medium of the headless server appliance. | 2012-05-10 |
20120117371 | DEVICE FOR CONFIGURING A PROGRAMMABLE COMPONENT, SYSTEM INCORPORATING SAID DEVICE, AND RELATED METHOD - This device includes a programmable component having an output able to send an inhibiting signal upon successful configuration of the programmable component and an input able to receive a reconfiguration signal; an automatic burn-in circuit for the configuration of the programmable component, having: selection means which, in a first state, connect the programmable component to a first configuration memory space and, in a second state, connect the programmable component to a second configuration memory space; and watchdog means having an input able to receive the inhibition signal and an output for sending, when no inhibition signal has been received for a predetermined period of time, a configuration signal intended for the programmable component to command the reconfiguration thereof and of the selection means to modify the state thereof. | 2012-05-10 |
20120117372 | Techniques and Graphical User Interfaces for Categorical Shuffle - Improved techniques and graphical user interfaces that enable users to shuffle a group of media items in accordance with categories associated with the media items are disclosed. According to one aspect, techniques can operate to categorically shuffle media items having categories associated therewith. According to another aspect, a user interface control can be graphically presented to a user to assist the user in selecting a shuffle setting. The shuffle setting provided by the user affects the nature of the shuffle. For example, the shuffle setting can impact the likelihood that two adjacent media items in the group of media items will be from the same one or more categories following the shuffle. | 2012-05-10 |
20120117373 | METHOD FOR CONTROLLING A SECOND MODALITY BASED ON A FIRST MODALITY - A method for controlling a second modality based on a first modality is provided. The method comprises the steps: providing a first modality comprising time-dependent characteristics and a second modality capable of changing its appearance over time; automatically determining changes in the appearance of the second modality based on the time-dependent characteristics of the first modality; adjusting a smoothing degree by means of a user input device; and adapting the determined changes in appearance of the second modality based on the smoothing degree and on boundaries present in the time-dependent characteristics of the first modality to arrive at resulting changes in the appearance of the second modality. | 2012-05-10 |
20120117374 | CENTRAL MANAGEMENT COMPUTING SYSTEM - Provided is a central management computing system. The central management computing system includes a plurality of terminals, and a rack system. The rack system is connected to the plurality of terminals. The rack system includes a rack power supply unit, a plurality of computers, and a switch. The rack power supply unit is mounted in a rack and converts an AC power into a plurality of DC powers to output to a plurality of DC output ports. The plurality of computers are mounted in the rack and receive the DC powers from the DC output ports. The switch is mounted in the rack and dynamically connects the computers to the terminals, respectively. | 2012-05-10 |
20120117375 | SYSTEMS AND METHODS FOR OPTIMIZING SSL HANDSHAKE PROCESSING - A method for buffering SSL handshake messages prior to computing a message digest for the SSL handshake includes: conducting, by an appliance with a client, an SSL handshake, the SSL handshake comprising a plurality of SSL handshake messages; storing, by the appliance, the plurality of SSL handshake messages; providing, by the appliance to a message digest computing device in response to receiving a client finish message corresponding to the SSL handshake, the plurality of SSL handshake messages; receiving, by the appliance from the message digest computing device, a message digest corresponding to the provided messages; determining by the appliance, the message digest matches a message digest included in the SSL client finish message; and completing, by the appliance with the client, the SSL handshake. Corresponding systems are also described. | 2012-05-10 |
20120117376 | METHOD AND APPARATUS FOR ANONYMOUS IP DATAGRAM EXCHANGE USING DYNAMIC NEWTORK ADDRESS TRANSLATION - Methods, apparatus, system and computer program are provided for concealing the identity of a network device transmitting a datagram having a network layer header. A unique local identifier and broadcast address are determined in accordance with a next-hop address. A partially encrypted network layer header is determined by encrypting a plurality of identifying portions of the network layer header, where one portion of the network layer header is the unique local identifier. The datagram is encapsulated with another network layer header whose address is set to the broadcast address. The encapsulated datagram can be received and detunneled, and an address of a recipient can be extracted from the network layer header. The datagram is then admitted into a network domain. | 2012-05-10 |
20120117377 | Mobile security protocol negotiation - A security gateway/home agent controller HAC is used to assign one home agent HA from a plurality of HAs and to identify at least one security protocol that is common between a mobile node MN and the assigned HA. Establishment of a security association between the MN and the assigned HA is enabled according to the identified security protocol and utilizing bootstrapping parameters provided over a secure connection between the security gateway/HAC and the MN. The bootstrapping parameters include at least a home address for the MN, an address of the assigned HA and security credentials and security parameters for the identified at least one security protocol. In an exemplary embodiment the home address for the MN may be an IPv6 home address and the MN may have certain capabilities with respect to security protocols and ciphering suites which the MN sends to the security gateway. | 2012-05-10 |
20120117378 | Multi-Network Cryptographic Device - A Personal Computer Memory Card International Association (PCMCIA) card is disclosed. The PCMCIA card may include a cryptographic module, a communications interface, and a processor. The cryptographic module may perform Type 1 encryption of data received from a computer into which the card is inserted. The cryptographic module may support High Assurance Internet Protocol Encryption (HAIPE). The communications interface may provide connectivity to a network adapter. The communications interface may include a Universal Serial Bus (USB) interface. The processor may detect whether a network adapter is coupled to the communications interface, identify a device driver that corresponds to the network adapter, and employ the device driver to provide operative communication between the cryptographic module and the network adapter. The PCMCIA card may contain a datastore that maintains a plurality device drivers. For example, the plurality of device drivers support any one of IEEE 802.x, Ethernet, V.90, or RS-232 network protocols. | 2012-05-10 |
20120117379 | METHODS FOR HANDLING REQUESTS BETWEEN DIFFERENT RESOURCE RECORD TYPES AND SYSTEMS THEREOF - A method, computer readable medium, and device for handling requests between different resource record types includes receiving at a traffic management device a first resource record type from one or more server devices in response to a request from a client device. The traffic management device validates the first resource record type, and creates a second resource record type corresponding to the first resource record type after the validating. Signing the second resource record type at the traffic management device is carried out for servicing the request from the client device. | 2012-05-10 |
20120117380 | Method for Granting Authorization to Access a Computer-Based Object in an Automation System, Computer Program, and Automation System - An identifier is determined for a control program, and the identifier is encrypted based on a private digital key associated with a control and monitoring unit of the automation system to grant authorization to access a computer-based object in an automation system. A first service of the automation system is provided based on the computer-based object, and a second service of the automation system is provided based on the control program. The encrypted identifier is decrypted when being transmitted to an authentication service and is verified by the authentication service. If the verification process has been successful, the authentication service transmits a temporarily valid token to the second service. When the control program requests access to the computer-based object, the token is transmitted to the first service for checking purposes. The control program is granted access to the computer-based object if the result of the checking process is positive. | 2012-05-10 |
20120117381 | System and Method for Component Authentication of a Secure Client Hosted Virtualization in an Information Handling System - A client hosted virtualization system (CHVS) includes a processor to execute code, a security processor, a component that includes a certificate, and a non-volatile memory. The non-volatile memory includes BIOS code for the CHVS and virtualization manager code to initialize the CHVS, launch a virtual machine on the CHVS, and authenticate the component with the security processor by determining that the certificate is valid. The CHVS is configurable to execute the first code and not the second code, or to execute the second code and not the first code. | 2012-05-10 |
20120117382 | SYSTEM AND METHOD EMPLOYING AN AGILE NETWORK PROTOCOL FOR SECURE COMMUNICATIONS USING SECURE DOMAIN NAMES - A method and system are used to transparently create an encrypted communications channel between a client device and a target device. Audio video communications between the client device and the target device are allowed over the encrypted communications channel once the encrypted communications channel is created. The method comprises: (1) receiving from the client device a request for a network address associated with the target device; (2) determining whether the request is requesting access to a device that accepts an encrypted channel connection with the client device; and (3) depending on the determination made in step (2) providing provisioning information required to initiate the creation of the encrypted communications channel between the client device and the target device such that the encrypted communications channel supports secure audio/video communications transmitted between the two devices. | 2012-05-10 |
20120117383 | System and Method for Secure Device Configuration Cloning - The subject application is directed to a system and method for secure device configuration cloning. Configuration data corresponding to software-settable configurations of a document processing device is received into a data storage. Schema data is generated on a processor in data communication with the data storage. The schema file includes segments and corresponds to a portion of the configuration data. At least one segment of the schema file is encrypted in accordance with a corresponding portion of the configuration data. Secure clone file data is then generated based upon the configuration data and the encrypted schema file and communicated to a second document processing device for configuration thereof. | 2012-05-10 |
20120117384 | METHOD AND SYSTEM FOR DELETING DATA - Methods, computer systems, and computer program products for deleting data in a computing environment are provided. A computer system having at least first and second documents, a plurality of decryption keys, and a plurality of data segments stored therein is provided. Each of the plurality of data segments is decryptable by a selected one of the decryption keys. The decryption keys include a first set of decryption keys associated with the first document and not associated with the second document, a second set of decryption keys associated with the second document and not associated with the first document, and a third set of decryption keys associated with the first document and the second document. The first document is deleted, and in response, the first set of decryption keys is rendered unusable, and the second set of decryption keys and the third set of decryption keys are not rendered unusable. | 2012-05-10 |
20120117385 | METHOD AND APPARATUS FOR DATA ENCRYPTION - Embodiments of the invention relate to message based encryption and authentication to support secure communication of a message. A time stamp embedded within the message is evaluated to ensure that a received message has not been subject to a significant time delay. More specifically, tools are employed to evaluate the authenticity of the message subject to the characteristics of the embedded time stamp. A message subject to a time delay is considered to be tainted and is not authenticated for receipt by a target device. | 2012-05-10 |
20120117386 | Methods for Identifying the Guarantor of an Application - Third-party applications for platforms are linked to identified individuals that guarantee the security of the applications. The linkage is achieved by acquiring one or more biometric records of the individual guarantor, storing those records as a signature in a database, assigning a unique identifier to the signature, and embedding that unique identifier in the executable file of the application. The signature of the guarantor can be compared to other stored signatures of other guarantors to check for individuals posing under multiple aliases. The signature of a guarantor linked to a malicious application can be flagged so that a subsequent application guaranteed by the same individual can be disapproved. | 2012-05-10 |
20120117387 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE MEDIUM - An information processing apparatus includes an accepting unit, a memory, an activating unit, and a controller. The accepting unit accepts first key information and second key information. The first key information includes performance information representing a performance and an identifier for identifying a device. The second key information includes the performance information and temporary use permission information. The memory stores the performance information in the first key information if the first key information is accepted and if the identifier is a predetermined identifier, and stores the temporary use permission information and the performance information in the second key information if the second key information is accepted. The activating unit activates the device with the performance represented by the performance information. The controller controls the activating unit to activate the device with the performance and then performs control to erase the performance information and the temporary use permission information. | 2012-05-10 |
20120117388 | SYSTEM FOR SELECTIVE ENCRYPTION WITHIN DOCUMENTS - A system for selective encryption within a document. A portion of the document selected and marked for encryption is detected, the selected portion of the document including plaintext. The detected portion of the document selected for encryption is encrypted as ciphertext. The document is displayed with the selected portion of the document encrypted. An attempt by an accessor to access the encrypted portion of document is detected. The encrypted portion of the document is decrypted with a proper decryption key, wherein the decrypting includes decrypting the encrypted portion of the document in response to presentation of required data by the accessor. The required data includes the proper decryption key, a name of the accessor, and an employee number of the accessor. The portion of the document is displayed as decrypted. | 2012-05-10 |
20120117389 | Methods and Apparatuses for Determining and Using a Configuration of a Composite Object - Methods and apparatuses are provided for determining and using a configuration of a composite object. A method may include receiving information emitted by one or more tags in one or more objects of a composite object. The method may further include determining, based at least in part on the received information, at least a partial configuration of the composite object. The method may additionally include using the determined at least a partial configuration of the composite object as an input to alter an application state. Corresponding apparatuses are also provided. | 2012-05-10 |
20120117390 | Energy Allocation to Groups of Virtual Machines - A method, data processing system, and computer program product for managing energy. A processor unit identifies a plurality of groups of virtual machines in a computer system. The processor unit allocates the energy in the computer system to the plurality of groups of virtual machines based on a policy. | 2012-05-10 |
20120117391 | Method and System for Managing the Power Supply of a Component - A method and system for managing the power supply of a component and of a memory cooperating with the component are disclosed. The component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory. When a voltage level of the first power supply source drops and reaches a threshold that is greater than or equal to the minimum operating voltage of the memory, the power supply of the memory is toggled to a second power supply source having a second voltage level that is greater than or equal to the minimum operating voltage of the memory. | 2012-05-10 |
20120117392 | POWER DISTRIBUTION UNIT-DEVICE CORRELATION - Apparatus, methods, and other embodiments associated with providing a correlation between a power distribution unit(s) and a device(s) are described. One example method includes storing first time series data that identifies, on a per power distribution unit (PDU) basis, current drawn from a set of PDUs. The example method may include storing second time series data that identifies, on a per device basis, power used by a set of related devices. With the two time series data available, the method may then provide a PDU-device correlation signal that identifies a correlation between current drawn from a PDU and power used by a device. | 2012-05-10 |
20120117393 | POWER MANAGEMENT SYSTEM - A power supply system includes at least one power supply module and at least one redundant power supply module. A power supply module may include a charging resistor in parallel with an OR-ing device to keep all filter capacitors charged as long as at least one power supply module remains operational. This may avoid current spikes at turn on and may enable the redundant module to turn on without using soft start. | 2012-05-10 |
20120117394 | SERVER SYSTEM AND METHOD FOR PROCESSING POWER OFF - A method for processing power-off suitable for a server system is provided. The server system includes a first node, a second node, and a power supply. The first and second nodes share the power supply. The method includes the following steps. A power-off process is performed by the first and second nodes respectively according to a power-off signal. An interception process is activated to intercept a completion signal generated in the power-off process, and an interrupt is triggered. The interrupt is performed by an interrupt handler, so as to detect whether the first and second nodes complete a power-off process. When the first and second nodes already complete the power-off process, the interception process is inactivated and the generated completion signal is recovered and transferred to the power supply for turning off a power. | 2012-05-10 |
20120117395 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus includes a power switch which is turned ON and OFF for supplying and cutting off power; a power supply portion which supplies power to each portion through the power switch; an operation control portion to which power is supplied from the power supply portion regardless of the ON or OFF state of the power switch, which controls power supply to a main storage device including a built-in cache memory based on software; a measurement portion which measures temperature of a measurement target; and a power control portion which is controlled by the operation control portion and controls power supply to the main storage device from the power supply portion. | 2012-05-10 |
20120117396 | POWER MANAGEMENT DEVICE WITH COMMUNICATIONS CAPABILITY AND METHOD OF USE - A power management device can include a housing, a power input associated with the housing, and a plurality of power outputs associated with the housing. At least certain power outputs can be connectable to one or more electrical loads external to the housing and to the power input. In some embodiments, a communications bus and one or more power control sections can be associated with the housing. In some embodiments, one or more power control sections can communicate with the communications bus and with one or more corresponding power outputs among the plurality of power outputs. In some embodiments, a power information display can communicate with the communications bus. If desired, a power information determining section can be associated with the housing and in communication with the communications bus. The power information determining section may communicate power-related information to the power information display. | 2012-05-10 |
20120117397 | DYNAMIC VOLTAGE ADJUSTMENT TO COMPUTER SYSTEM MEMORY - A system and method are provided wherein the voltage to a random access memory system may be automatically, dynamically adjusted without requiring an operating system to be restarted. In one embodiment, a target value of a voltage supplied to the memory system is dynamically selected. A system management mode is invoked in response to a change in the dynamically selected target value, including suspending a normal operation of the memory system. While in the system management mode, the voltage supplied to the memory system is adjusted according to the changed target voltage. A memory speed is adjusted according to the changed target value of the voltage. These steps are performed without restarting the computer system. The system management mode is exited and normal operation of the memory system may resume at the changed target voltage. | 2012-05-10 |
20120117398 | SYSTEM AND METHOD FOR CONTROL OF POWER CONSUMPTION OF INFORMATION HANDLING SYSTEM DEVICES - Systems and methods for controlling power usage of devices in information handling systems are provided. A device for use in an information handling system may include a connector and an auxiliary power connector. The connector may be configured to electrically couple to a device connector such that the device transmits and receives data via the device connector and receives electrical current from a power supply via the device connector. The auxiliary power connector may be configured to electrically couple the device to the power supply such that the device receives electrical current from the power supply via the device connector, the auxiliary power connector including at least one sense line, the at least one sense line configured to receive at least one power control signal. The device may be configured to establish its power usage in response to receiving the at least one power control signal. | 2012-05-10 |
20120117399 | SAVING POWER BY MANAGING THE STATE OF INACTIVE COMPUTING DEVICES - A system method and computer program product for managing readiness states of a plurality of computing devices. A programmed processor unit operates, upon receipt of a request, to either: provide one or more computing devices from an inactive pool to an active pool, or accept one or more active computing devices into the inactive pool. An Inactive Pool Manager proactively manages the inactive states of each computing device by: determining the desired number (and identities) of computing devices to be placed in each inactive state of readiness by solving a constraint optimization problem that describes a user-specified trade-off between expected readiness (estimated time to be able to activate computing devices when they are needed next) and conserving energy; generating a plan for changing the current set of inactive states to the desired set; and, executing the plan. Multiple alternative ways of quantifying the desired responsiveness to surges in demand are provided, and, in each case, the tradeoff between responsiveness and power savings is formulated as an objective function with constraints, and the desired number of devices in each inactive state emerges as the solution to a constraint optimization problem. | 2012-05-10 |
20120117400 | EFFICIENT SERVICE ADVERTISEMENT AND DISCOVERY IN A PEER-TO-PEER NETWORKING ENVIRONMENT - A local device broadcasts a service advertisement in a wireless network, where the service advertisement includes one or more service identifiers (IDs) identifying one or more services being advertised and an availability schedule of the local device. Optionally, the local device reduces power to at least a portion of the local device and wakes up at a time according to the availability schedule. The local device listens in the wireless network according to the availability schedule of the local device. In response to a service request received from a remote device during the availability window, the local device transmits a service response to the remote device. The service request includes one or more service IDs identifying one or more services being inquired by the remote device and the service response includes detailed information associated with one or more services identified by the one or more service IDs. | 2012-05-10 |
20120117401 | MAINTAINING CONNECTIVITY DURING LOW POWER OPERATION - Generally this disclosure describes methods and systems for conserving energy in a client platform by maintaining connectivity between the client platform and a remote resource when the client is in a low-power state. An example method may include receiving notification that the client platform is transitioning to the low-power state, receiving at least one payload from the client platform, the at least one payload being configured to maintain connectivity with a remote resource while the client platform is in the low-power state, transmitting a packet including the at least one payload and receiving a packet including an acknowledgement. | 2012-05-10 |
20120117402 | Memory Read Timing Margin Adjustment - An apparatus and method for changing the extra margin adjustment (EMA) for a memory is disclosed. A control unit may access a table responsive to an indication of a change of operating point. The table includes a number of different delay times, each of which corresponds to a particular operating point. The control unit may select the delay time that corresponds to the new operating point to which the memory operation is being changed. The control unit may further convey an indication of the selected delay time to the memory, thereby causing the memory to operate according thereto. | 2012-05-10 |
20120117403 | POWER MANAGEMENT FOR PROCESSING CAPACITY UPGRADE ON DEMAND - A method, computer program product, and apparatus for managing power in a data processing system are presented. A core is activated in the data processing system and configured to operate at a frequency in response to receiving a request to increase a processing capacity of a set of resources in the data processing system. A determination whether a use of power resulting from activating the core configured to operate at the frequency meets a policy for the use of the power in the data processing system is made. A set of parameters associated with devices in the set of resources are adjusted to meet the policy for the use of power in the data processing system in response to a determination that the use of power does not meet the policy. A determination whether a number of operations performed per unit of time by a set of cores associated with the set of resources increased after activating the core is made. An indication that the request to increase the processing capacity of the set of resources is unavailable is made in response to a determination that the number of operations performed per unit of time by the set of cores associated with the set of resources has not increased. | 2012-05-10 |
20120117404 | Decentralized Sleep Management - Techniques for employing a decentralized sleep management service are described herein. In some instances, each computing device of a group of computing devices periodically shares information about itself with each other computing device of the group. With this information, each computing device within the group that is awake and capable of managing other devices selects a subset of devices to probe. The devices then probe this subset to determine whether the probed devices are asleep. In response to identifying a sleeping device, the probing device takes over management of the sleeping device. Managing the sleeping device involves informing other devices of the group that the sleeping device is being managed, in addition to monitoring requests for services on the sleeping device. In response to receiving a valid request for a service hosted by the sleeping device, the managing device awakens the sleeping device and ceases managing the now-woken device. | 2012-05-10 |
20120117405 | Information Processing Device and Data Distribution Method - An information processing device that is connected to one or more other information processing devices and distributes hibernation data to another information processing device, includes: a storage unit that stores the hibernation data; a configuration information acquisition unit that acquires identification information and configuration information describing a device configuration of each information processing device from the other information processing device; a configuration evaluation unit that analyzes the acquired configuration information and determines if the configuration of the device is the same as the configuration of the other information processing device; and a data transmission unit that, when there is at least one information processing device with the same device configurationas itself among the other informationprocessing devices, sends the hibernation data to an information processing device with the same configuration using the identification information of that other device as the address. | 2012-05-10 |
20120117406 | METHOD AND APPARATUS FOR MEMORY MANAGEMENT IN MOBILE DEVICE - A method for memory management in a mobile device, and a mobile device for performing the method, are provided. The mobile device performs garbage collection in a flexible manner after transitioning from the sleep state to the wakeup state according to the paging cycle. This contributes to securing the sleep interval for the mobile device and reducing power consumption. The memory management method includes transitioning from a sleep state to a wakeup state, performing a paging procedure in the wakeup state, determining whether to initiate garbage collection after completion of the paging procedure, performing, when it is determined that garbage collection is to be initiated, garbage collection according to a paging cycle, and transitioning from the wakeup state to the sleep state after completion of garbage collection. | 2012-05-10 |
20120117407 | COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD - According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. | 2012-05-10 |
20120117408 | SWITCHING DEVICE, A SWITCHING DEVICE CONTROL METHOD AND A SWITCHING DEVICE CONTROL PROGRAM - A switching device is comprising connectors and switching part, which is connected via the connectors to a working power supply unit, a redundant power supply unit, a battery unit and a power supply output terminal, and, in an initial state, connects the power supply output terminal and the working power supply unit, and connects the battery unit and the redundant power supply unit is connected, and in a spare state, cuts a connection between the battery unit and the redundant power supply unit, and connects the power supply output terminal and the redundant power supply unit. | 2012-05-10 |
20120117409 | METHODS OF CHARGING AUXILIARY POWER SUPPLIES IN DATA STORAGE DEVICES AND RELATED DEVICES - A method of operating a data storage device can be provided by receiving first power and second power at a data storage device, that includes a semiconductor memory, upon powering on of the data storage device or hot-plugging of the data storage device. The first power can be applied to the data storage device and the second power can be applied after a delay to an auxiliary power supply included in the data storage device based on when an inrush current, generated from applying the first power, occurred. Related devices are also disclosed. | 2012-05-10 |
20120117410 | POWER ON RESET CIRCUIT - Embodiments may disclose a power on reset circuit, which includes: a current mirror connected to a power node, the power node receiving a variable power supply voltage, the current mirror being configured to supply a first current to a first line and a second current to a second line; a comparative voltage generator configured to generate a comparative voltage using the first current provided via the first line; a driver connected to the second line, the driver being configured to activate a reset signal in response to a voltage of the second line; and a ground selecting transistor configured to connect the second line and a ground node according to the comparative voltage. | 2012-05-10 |
20120117411 | ENERGY CAPTURE OF TIME-VARYING ENERGY SOURCES BY VARYING COMPUATIONAL WORKLOAD - A method and system for managing computational workload in a computerized system powered by an energy source. This invention relies first and foremost on adapting computational workload at the computerized system according to a time-varying property of the power supplied by the energy source, such that power generated at the source is optimized. A feedback mechanism is accordingly implemented which changes power available for computation, e.g., to track a more efficient energy generation efficiency point at the source. | 2012-05-10 |
20120117412 | LOWER ENERGY COMSUMPTION AND HIGH SPEED COMPUTER WITHOUT THE MEMORY BOTTLENECK - A computer system encompasses a processor ( | 2012-05-10 |
20120117413 | METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) - A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided. | 2012-05-10 |
20120117414 | PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS - A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop. | 2012-05-10 |
20120117415 | PROVIDING FAULT-TOLERANT SPREAD SPECTRUM CLOCK SIGNALS IN A SYSTEM - To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module. | 2012-05-10 |
20120117416 | METHOD AND SYSTEM FOR PROCESS CONTROL NETWORK MIGRATION - A method includes disconnecting a first component from a first network. The first component is redundant to a second component and operates in a secondary or passive redundancy mode. The second component operates in a primary or active redundancy mode and is coupled to the first network. The method also includes updating at least one of hardware and software on the first component to allow the first component to communicate on a second network. The method further includes connecting the updated first component to the second network and synchronizing data between the updated first component on the second network and the second component on the first network. In addition, the method includes switching the updated first component from the secondary redundancy mode to the primary redundancy mode. | 2012-05-10 |
20120117417 | Systems and Methods of High Availability Cluster Environment Failover Protection - A transparent high-availability solution utilizing virtualization technology is presented. A cluster environment and management thereof is implemented through an automated installation and setup procedure resulting in a cluster acting as a single system. The cluster is setup in an isolated virtual machine on each of a number of physical nodes of the system. Customer applications are run within separate application virtual machines on one physical node at a time and are run independently and unaware of their configuration as part of a high-availability cluster. Upon detection of a failure, traffic is rerouted through a redundant node and the application virtual machines are migrated from the failing node to another node using live migration techniques. | 2012-05-10 |
20120117418 | ERROR DETECTION IN A MIRRORED DATA STORAGE SYSTEM - A method and system for are provided for error detection in a mirrored data storage system. The method includes a first mirrored system applying a first error correction code (ECC) algorithm and a second mirrored system applying a second error correction code algorithm. The method reads recovered data in each of the first and second mirrored systems and processes the recovered data in each of the first and second mirrored systems by applying both first and second error correction code algorithms to produce four calculated error correction code values. The method uses the calculated error correction code values to determine the correct recovered data of the first and second mirrored systems. | 2012-05-10 |
20120117419 | SYSTEM, METHOD AND APPARATUS FOR ERROR CORRECTION IN MULTI-PROCESSOR SYSTEMS - This disclosure provides apparatus, methods and systems for error correction in multi processor systems. Some implementations include a plurality of computing modules, each computing module including a processor. Each processor may include processing state. In some other implementations, each computing module may also include a memory. Upon receiving a signal to perform a partial re-synchronization, a hash of each processor's state data may be performed. In some embodiments, a hash of at least a portion of each computing module's memory data may also be performed. The hashes for each processor are then compared to determine majority hashes and possible minority hashes. Upon identifying a minority hash, the computing module that produced the minority hash may receive new processing state data from one of the computing modules that produced a majority hash. | 2012-05-10 |
20120117420 | PROCESSOR AND METHOD IMPLEMENTED BY A PROCESSOR TO IMPLEMENT MASK LOAD AND STORE INSTRUCTIONS - A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits. | 2012-05-10 |
20120117421 | SYSTEM AND METHOD FOR REMOTE RECOVERY WITH CHECKPOINTS AND INTENTION LOGS - Accurate recovery of a primary server at a recovery server is accomplished with reduced network overhead by maintaining at the recovery server checkpoints taken over time of the primary server and an intention log of logical transactions pending and complete by the primary server. The recovery server is brought to the operational state of the primary server as of failure at the primary server by recovering the most recent checkpoint and then executing the transactions indicated by the intention log as received but not complete as of the time that the checkpoint was taken. | 2012-05-10 |
20120117422 | DISASTER RECOVERY IN A NETWORKED COMPUTING ENVIRONMENT - In general, embodiments of the present invention provide a DR solution for a networked computing environment such as a cloud computing environment. Specifically, a customer or the like can select a disaster recovery provider from a pool (at least one) of disaster recovery providers using a customer interface to a DR portal. Similarly, using the interface and DR portal, the customer can then submit a request for DR to be performed for a set (at least one) of applications. The customer will then also submit (via the interface and DR portal) DR information. This information can include, among other things, a set of application images, a set of application files, a set of recovery requirements, a designation of one or more specific (e.g., application) components for which DR is desired, dump file(s), database file(s), etc. Using the DR information, the DR provider will then generate and conduct a set of DR tests and provide the results to the customer via the DR portal and interface. In one embodiment, a temporary DR environment can be created (e.g., by the DR provider or the customer) in which the DR tests are conducted. | 2012-05-10 |
20120117423 | FAULT TOLERANCE IN DISTRIBUTED SYSTEMS - Fault tolerance is provided in a distributed system. The complexity of replicas and rollback requests are avoided; instead, a local failure in a component of a distributed system is tolerated. The local failure is tolerated by storing state related to a requested operation on the component, persisting that stored state in a data store, such as a relational database, asynchronously processing the operation request, and if a failure occurs, restarting the component using the stored state from the data store. | 2012-05-10 |