19th week of 2011 patent applcation highlights part 58 |
Patent application number | Title | Published |
20110113199 | PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS - An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced. Yet, if prefetch accuracy is low—miss rate is high—then more prefetch throttling is needed to save power, because the prefetch are not being utilized—performance is not being enhanced by the large number of prefetches. | 2011-05-12 |
20110113200 | METHODS AND APPARATUSES FOR CONTROLLING CACHE OCCUPANCY RATES - Embodiments of an apparatus for controlling cache occupancy rates are presented. In one embodiment, an apparatus comprises a controller and monitor logic. The monitor logic determines a monitored occupancy rate associated with a first program class. The first controller regulates a first allocation probability corresponding to the first program class, based at least on the difference between a requested occupancy rate and the first monitored occupancy rate. | 2011-05-12 |
20110113201 | GARBAGE COLLECTION IN A CACHE WITH REDUCED COMPLEXITY - Garbage collection associated with a cache with reduced complexity. In an embodiment, a relative rank is computed for each cache item based on relative frequency of access and relative non-idle time of cache entry compared to other entries. Each item having a relative rank less than a threshold is considered a suitable candidate for replacement. Thus, when a new item is to be stored in a cache, an entry corresponding to an identified item is used for storing the new item. | 2011-05-12 |
20110113202 | CACHE FLUSH BASED ON IDLE PREDICTION AND PROBE ACTIVITY LEVEL - A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. | 2011-05-12 |
20110113203 | Reservation Required Transactions - A method for performing a transaction including a transaction head and a transaction tail, includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered. | 2011-05-12 |
20110113204 | MEMORY CONTROLLER WITH EXTERNAL REFRESH MECHANISM - The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same. The effect is that the arbitration between the different requests is rendered less complex. In embodiments of the memory controller there is also an average latency reduction for the high-priority requests. The invention further relates to a System-on-Chip comprising the memory controller, to a method of a refresh request generator for use in such System-on-Chip. The invention also relates to a method of controlling access of a System-on-Chip to a volatile memory, wherein the System-on-Chip comprises a plurality of agents which need access to the volatile memory, and to a computer program product comprising instructions for causing a processor to perform such method. | 2011-05-12 |
20110113205 | DATA STORAGE DEVICE - A data storage device connectable to an electronic device and a remote storage serve, which comprises memory managing means configured to receive a request for a piece of information from the electronic device and if said piece of information is stored both in a local memory of the data storage device and in the remote server, retrieving the requested piece of information from the local memory to reduce latency. | 2011-05-12 |
20110113206 | METHOD FOR OBTAINING A SNAPSHOT IMAGE OF A DISK SHARED BY MULTIPLE VIRTUAL MACHINES - Methods for obtaining a snapshot of a shared virtual machine (VM) image are described herein. In response to a request for obtaining a snapshot of a first VM image stored in a storage disk accessed and shared by a plurality of VMs, a virtualization manager selects a VM from the plurality of VMs hosted within one or more hosts. First needs to notify others to prepare for the snapshot by pausing, etc. A process associated with the selected VM is configured to capture a snapshot from the first VM image, generating a second VM image to be stored in storage disk. Thereafter, the virtualization manager notifies the plurality of VMs to utilize the second image after the second VM image has been generated. | 2011-05-12 |
20110113207 | DATA PROCESSING SYSTEM WITH APPLICATION-CONTROLLED ALLOCATION OF FILE STORAGE SPACE - A data processing system stores data in a data file by first identifying the data file as a large file type known to require an amount of storage space substantially greater than a system allocation unit size. As data is to be written to the data file beginning at a location identified by a file pointer, the system determines whether it is necessary to allocate storage space of the data processing system to store the data to be written, and if so then commands are issued to the file system including (i) one or more first commands to set an end of file marker for the data file to a new value greater than a current value of the end of file marker by at least an application allocation unit size which is at least twice the system allocation unit size, and (ii) one or more second commands to mark a region of the data file extending between the current and new values of the end of file marker as holding valid data. Subsequently the data is written to the data file at the location identified by the file pointer. | 2011-05-12 |
20110113208 | STORING CHECKPOINT DATA IN NON-VOLATILE MEMORY - Methods and systems for storing checkpoint data in non-volatile memory are described. According to one embodiment, a data storage method includes executing an application using processing circuitry and during the execution, writing data generated by the execution of the application to volatile memory. An indication of a checkpoint is provided after writing the data. After the indication has been provided, the method includes copying the data from the volatile memory to non-volatile memory and, after the copying, continuing the execution of the application. The method may include suspending execution of the application. According to another embodiment, a data storage method includes receiving an indication of a checkpoint associated with execution of one or more applications and, responsive to the receipt, initiating copying of data resulting from execution of the one or more applications from volatile memory to non-volatile memory. In some embodiments, the non-volatile memory may be solid-state non-volatile memory. | 2011-05-12 |
20110113209 | Data Recovery Systems and Methods - Nearline disaster recovery (“nearline DR”) storage systems and methods that permit the use of previously restored stored data from a near time period by virtual applications operating off a backup storage location during the period of disaster recovery at a primary site. This is generally referred to as a “nearline DR storage process.” | 2011-05-12 |
20110113210 | CONCURRENT ACCESS TO A MEMORY POOL SHARED BETWEEN A BLOCK ACCESS DEVICE AND A GRAPH ACCESS DEVICE - A graph access device and block access device can simultaneously access a memory pool shared between the devices. The memory pool may include one or more memory arrays accessed as a single logical memory. The block access device accesses the memory pool as a flat array of memory blocks, and the graph access device accesses the memory pool as hierarchical file system. The simultaneous access is accomplished by monitoring one or more memory block access operations performed by the block access device, while it is accessing the memory pool. The block access operations are translated into a graph data structure including a plurality of pointers mapping the memory pool to the hierarchical file system. A processor regulates access to the memory pool, and is configured to permit the graph access device to access the memory pool concurrently with the block access device, in accordance with the graph data structure. | 2011-05-12 |
20110113211 | SYSTEMS AND METHODS OF QUOTA ACCOUNTING - Embodiments of the invention relate generally to incremental computing. Specifically, embodiments of the invention include systems and methods that provide for the concurrent processing of multiple, incremental changes to a data value while at the same time monitoring and/or enforcing threshold values for that data value. For example, a method is provided that implements domain quotas within a data storage system. | 2011-05-12 |
20110113212 | Systems for Accessing Memory Card and Methods for Accessing Memory Card by a Control Unit - A system for accessing a memory card is provided. The system includes a control unit having a control pin and a processor. The processor senses a card-insertion signal from a socket via the control pin for indicating whether the memory card has been inserted into the socket. The processor provides a power control signal via the control pin to supply an operating voltage to the memory card when the sensed card-insertion signal indicates that the memory card has been inserted into the socket. The processor detects whether a write protection function of the memory card is present via the control pin. | 2011-05-12 |
20110113213 | PACKED STORAGE COMMANDS AND STORAGE COMMAND STREAMS - A packed command can be received at a storage device. The packed command can include an indicator of a source data location in the storage device and an indicator of a destination data location in the storage device. In response to receiving the packed command, a storage map table in the storage device can be updated. Also, a storage processing guide can be sent to a storage device. The processing guide can include a stream indicator associating the processing guide with a storage command stream. A set of storage commands can also be sent to the storage device. One or more of the commands in the set can each include a stream indicator that matches the stream indicator in the processing guide and identifies the command with the stream. | 2011-05-12 |
20110113214 | INFORMATION HANDLING SYSTEM MEMORY MANAGEMENT - An information handling system (IHS) loads an application that may include startup code and steady state operation code. The IHS allocates one region of system memory to the startup code and another region of system memory to the steady state operation code. A programmer inserts a memory release call command at a location that marks the end of execution of the startup code. After executing the startup code, the operation system receives the memory release call command. In response to the memory release call command, the operating system releases or de-allocates the region of memory to which the IHS previously assigned to the startup code. This enables the released memory for use by code other than the startup code, such as other code pages, library pages and other code. | 2011-05-12 |
20110113215 | METHOD AND APPARATUS FOR DYNAMIC RESIZING OF CACHE PARTITIONS BASED ON THE EXECUTION PHASE OF TASKS - The present invention proposes a method and a system for dynamic cache partitioning for application tasks in a multiprocessor. An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided. The execution phases of the application tasks are identified and updated in a tabular form. Cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any given point of time. The cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically. Cache partitions are resized according to the execution phase of the task dynamically such that unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved. | 2011-05-12 |
20110113216 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes: a ROM for storing a program therein; a RAM for temporarily storing therein the program read from the ROM; a program execution unit that is adapted to read and execute the program from the ROM or the RAM; a memory management unit that translates a virtual address output by the program execution unit to a physical address of the ROM or the RAM; a page table storage unit for storing therein a page table which is referred to by the memory management unit, and in which mapping data of a virtual address with a physical address of the ROM or the RAM corresponding to the virtual address is stored; a detection unit that detects change of an event in the information processing apparatus; an operation switching unit that is adapted to instruct, when the detection unit detects the change of the event during a ROM-operation in which the program execution unit reads the program from the ROM, switching from the ROM-operation to a RAM-operation in which the program execution unit reads the program from the RAM; and a page table updating unit that updates the page table which is referred to by the memory management unit, depending on the instruction of the operation switching unit. | 2011-05-12 |
20110113217 | GENERATE PREDICTES INSTRUCTION FOR PROCESSING VECTORS - The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a first input vector, a second input vector, and optionally receiving a predicate vector (each of which includes N elements) as inputs. The processor then executes the vector instruction. Executing the vector instruction causes the processor to generate a result vector. When generating the result vector, if the predicate vector was received, for each element of the result vector for which the corresponding element of the predicate vector is active, otherwise, for each element of the result vector, the processor determines elements that are to be set in the result vector based on values in elements in the first input vector and the second input vector. The processor then sets the determined elements of the result vector to a first predetermined value. | 2011-05-12 |
20110113218 | CROSS FLOW PARALLEL PROCESSING METHOD AND SYSTEM - Provided is a cross flow parallel processing method and system that may process multiple data flows and increase a parallel processing rate in a multi-processor that processes multiple cross data flows. | 2011-05-12 |
20110113219 | Computer Architecture for a Mobile Communication Platform - A system includes first and second processors, first and second graphics processing units (GPUs), one or more peripheral devices, a switch matrix, and processor-readable memory. The switch matrix comprises programmable data paths between the processors, the GPUs, and the peripheral devices. Software encoded in the process-readable memory includes a first operating system (OS) executed by the first processor, a second OS executed by the second processor, a matrix scheduling engine, and a media interface switch (MIS) engine. The first OS boots faster than the second OS. The matrix scheduling engine runs on both OSs and configures the data paths in the switch matrix to couple the processors and the GPUs, and to couple the processors and the peripheral devices. The MIS engine runs on the operating systems, detects presence of the peripheral devices, and configures the data paths in the switch matrix to couple the processors and the peripheral devices. | 2011-05-12 |
20110113220 | MULTIPROCESSOR - Provided is a multiprocessor capable of executing a plurality of threads without decreasing execution efficiency. | 2011-05-12 |
20110113221 | Data Sharing in Chip Multi-Processor Systems - System, computer readable medium and method for providing transparent access to shared data ( | 2011-05-12 |
20110113222 | METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR OR THE LIKE - In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor. | 2011-05-12 |
20110113223 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 2011-05-12 |
20110113224 | EXECUTION TIME ESTIMATION METHOD, EXECUTION TIME ESTIMATION PROGRAM, AND EXECUTION TIME ESTIMATION DEVICE - An execution time estimation device includes a program partitioning section that extracts partial programs partitioned by a conditional branch instruction or a function call instruction from a target program, a partial program execution time estimation calculating section that calculates the execution time of each of the partial programs to associate the leading instruction and the end instruction of each of the partial programs, and the calculated execution time with one another, a branch history information generating section that generates a branch history bit sequence which is a sequence of the true-false of the conditional branch instruction of when the target program is executed, an execution trace reproducing section that generates the execution sequences of the partial programs based on the branch history bit sequence, and an execution time estimation calculating section that adds the execution time of the partial programs based on the execution sequences of the partial programs. | 2011-05-12 |
20110113225 | BASIC INPUT/OUTPUT SYSTEM CAPABLE OF SUPPORTING MULTI-PLATFORMS AND CONSTRUCTING METHOD THEREOF - A basic input/output system (BIOS) capable of supporting multi-platforms and a constructing method thereof are provided. In the method, a plurality of segment modules is provided, and each of the segment modules includes more than one BIOS module. A module header is established for each of the BIOS modules and records an application platform identifier (ID) of an applicable platform of the corresponding BIOS module and module type data of the corresponding BIOS module. The segment modules are then integrated according to a design structure of the BIOS. The segment modules are classified into a main system module, a plurality of slave segment modules, and a reset entry segment module. When the reset entry segment module obtains a platform ID of an electronic equipment currently configured with the BIOS, the main system module pre-stores an execution sequence according to the platform ID, and sequentially runs the BIOS modules matching with the platform ID. | 2011-05-12 |
20110113226 | Distribution Of Software Updates - Methods, apparatuses, and systems for distribution of software updates are described. A file representing a difference between a first software stack and a second software stack and a task sequence may be received at a computer. The task sequence may represent instructions for installing the second software stack on the computer using the file and a stored image that represents the first software stack. The computer then may execute the task sequence to use the file and the stored image to install the second software stack on the computer. In one example, a second file representing a difference between the first software stack and a third software stack may be received by the computer, and the task sequence may include further instructions for installing the second software stack based on the first file, the second file, and the stored image. | 2011-05-12 |
20110113227 | ELECTRONIC EQUIPMENT AND BOOT METHOD, STORAGE MEDIUM THEREOF - An electronic equipment is provided, which includes a plurality of boot devices and a basic input/output system (BIOS). The BIOS is electrically coupled to the boot devices and used for recording driving parameters of the boot devices and a driving sequence of the driving parameters. The BIOS drives the boot devices by using the driving parameters according to the driving sequence, so as to perform a system booting operation of the electronic equipment. When any one of the boot devices accomplishes the system booting operation, the BIOS adjusts a driving parameter corresponding to the boot device as a first order of the driving sequence, so that the boot device becomes a first selected system booting device. Furthermore, a boot method for an electronic equipment and a storage medium thereof are provided. | 2011-05-12 |
20110113228 | Rules-Based, Mode-Driven Manager for Timer Bounded Arbitration Protocol Based Resource Control - An example apparatus includes a processor, a memory, and an interface that connects the processor, the memory, and a set of components. The set of components includes a first component configured to acquire a mode from members of an HA cluster and a second component configured to enforce mode pairing rules for members of the HA cluster. Once the desired mode pairing has been determined, a third component takes actions configured to either achieve the mode pairing according to rules for members of the HA cluster or to selectively force a hardware reset of one or more members of the HA cluster upon determining that a split brain scenario is possible based, at least in part, on the mode of the members of the HA cluster. The example apparatus therefore implements a rules-based manager for timer bounded arbitration protocol based resource control. | 2011-05-12 |
20110113229 | Method for Shortening the Boot Time of a Computer System - A computer system having an operating environment configured for enabling boot up in a relatively short time is disclosed. A hard disk is utilized to store a boot file. A run process list registers a process to be run during boot up. When the computer system is being booted up, if the run process list registers a process to load the boot file, a process control unit does not control a process management unit, so that the process is run as usual. If the process is not registered, the process management unit suspends the process. When the suspended process is called by another process later, the process control unit makes the process resumed on demand. | 2011-05-12 |
20110113230 | APPARATUS AND METHOD FOR SECURING AND ISOLATING OPERATIONAL NODES IN A COMPUTER NETWORK - A system and method for securing firmware from malware in a computer processing system having a trusted node daughterboard connected to at least one operational node motherboard. The method includes the steps of sending a power on signal from the trusted node daughterboard to the operational node motherboard when it is desired to utilize the operational node motherboard for computer processing purposes. Pre-boot data is then requested from the operational node motherboard and is sent from the trusted node daughterboard to the operational node motherboard to enable operation of the operational node motherboard. | 2011-05-12 |
20110113231 | SYSTEM AND METHOD FOR PROVIDING SECURE RECEPTION AND VIEWING OF TRANSMITTED DATA OVER A NETWORK - A method and system for securely opening an e-mail attachment in a computer processing environment having a trusted node daughterboard connected to at least one operational node motherboard with an e-mail processing system operatively coupled to the trusted node daughterboard. The method includes the steps of when an e-mail attachment is to be opened, sending a power on signal from the trusted node daughterboard to the operational node motherboard when it is desired to utilize the operational node motherboard for opening an e-mail attachment. Pre-boot data is then requested from the operational node motherboard and is sent from the trusted node daughterboard to the operational node motherboard to enable operation of the operational node motherboard for securely opening an e-mail attachment. | 2011-05-12 |
20110113232 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR MEMORY MANAGEMENT IN DEVICES USING SOFTWARE DEFINED RADIOS - An apparatus may include a processor configured to maintain a profile comprising data about software defined radio usage. The processor may be further configured to determine a subset of the plurality of software defined radios. The processor may be additionally configured to determine computing resources required for loading an available software defined radio that is not currently loaded into the memory based at least in part upon the maintained profile and the determined subset. The processor may also be configured to determine based at least in part upon the determined required computing resources whether sufficient computing resources are available for loading the available software defined radio into the memory. The processor may further be configured to initiate a reboot of loaded software defined radios if sufficient computing resources are not available for loading the available software defined radio. Corresponding methods and computer program products are also provided. | 2011-05-12 |
20110113233 | SYSTEM, SERVER, METHOD, AND COMPUTER PROGRAM FOR RELAYING ELECTRONIC MAIL - A system, a server, a method, and a computer program are described for relaying an electronic mail without a leak of secret information included in a quoted electronic mail to an unintended recipient without impairing the usability of the electronic mail system. The server receives an electronic mail that is newly created by one of the clients with quotation from one or a plurality of electronic mails received in the past. The server determines, for each quoted electronic mail quoted in the received electronic mail, whether a destination designated in the received electronic mail is included in an originator and a destination set in each quoted electronic mail. The server edits the content of each quoted electronic mail that is determined not to include the destination designated in the received electronic mail. The server transfers the electronic mail including the edited quoted electronic mail to the designated destination. The server stores edition information for returning the edited quoted electronic mail to a state before the editing in association with information that identifies the received electronic mail. | 2011-05-12 |
20110113234 | User Device, Computer Program Product and Computer System for Secure Network Storage - A technique for providing secure network storage by a user device that includes one or multiple network interfaces, a driver configuration component comprising a volume mapping schema and a connection mapping schema, and a driver operable to map I/O requests for logical data blocks to one or multiple network storage volumes as specified by the volume mapping schema, the data transfer between the user device and the one or multiple network storage volumes being mapped to one or multiple network connections as specified by the connection mapping schema, the driver thereby being operable to provide the user device with a logical storage volume. | 2011-05-12 |
20110113235 | PC Security Lock Device Using Permanent ID and Hidden Keys - The invention is a method, system, and apparatus providing user control and security of a PC system. Using the hardware and associated installation software, the system is capable of uniquely securing a PC system without the need for name and password entry. The secure USB device contains a unique asymmetrical key pair, unique device ID, secure storage area, and the firmware to control all of this. In providing the security and control, one embodiment of the invention does not require biomechanical devices or name and password entry systems. There are no passwords and login names to be found, and the encryption/decryption keys are protected from exposure. This provides a more secure environment, as the keys are protected from exposure. The user is in control of the PC system and the data which is desired to be kept secure. | 2011-05-12 |
20110113236 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OFFLOADING INTERNET PROTOCOL SECURITY (IPSEC) PROCESSING USING AN IPSEC PROXY MECHANISM - Methods, systems, and computer readable media for offloading IPsec processing from application hosts using an IPsec proxy mechanism are disclosed. According to one method, at least one of unencrypted, IPsec, and Internet key exchange (IKE) packets transmitted between a first application host and a second application host are intercepted by a network gateway. The network gateway performs all IKE and IPsec-related processing for the at least one unencrypted, IPsec, and IKE packets on behalf of the first application host such that the second application host is unaware that IPsec processing is being performed by the network gateway. | 2011-05-12 |
20110113237 | KEY CAMOUFLAGING METHOD USING A MACHINE IDENTIFIER - A method is provided for generating a human readable passcode to an authorized user including providing a control access datum and a PIN, and generating a unique machine identifier for the user machine. The method further includes modifying the controlled access datum, encrypting the controlled access datum using the PIN and/or a unique machine identifier to camouflage the datum, and generating a passcode using the camouflaged datum and the PIN and/or the unique machine identifier. A mobile user device may be used to execute the method in one embodiment. The passcode may be used to obtain transaction authorization and/or access to a secured system or secured data. The unique machine identifier may be defined by a machine effective speed calibration derived from information collected from and unique to the user machine. | 2011-05-12 |
20110113238 | CERTIFICATE ENROLLMENT WITH PURCHASE TO LIMIT SYBIL ATTACKS IN PEER-TO-PEER NETWORK - A system may protect against Sybil attacks on a peer-to-peer (P2P) network based on each one the nodes in the P2P network being identified by a corresponding certificate. In particular, a node may receive a license key, where the license key is evidence of a purchased product license. The node may transmit a message included in the license key to a certificate authority. The node may receive a certificate from the certificate authority in response to authentication of the message. The node may be identified in the P2P network with a node identifier included in the certificate. | 2011-05-12 |
20110113239 | RENEWAL OF EXPIRED CERTIFICATES - A method and system for renewal of expired certificates is described. In one embodiment, a method, implemented by a computing system programmed to perform operations, includes receiving, at a certificate manager of a computing system from a requester, a certificate renewal request for an original digital certificate that has already expired, and renewing the expired certificate as a renewed certificate by the certificate manager when the certificate renewal request is approved. The renewed certificate comprises the same key pair as the original certificate, but includes a new expiration date, and wherein the renewed certificate is functionally identical to the original certificate. | 2011-05-12 |
20110113240 | CERTIFICATE RENEWAL USING ENROLLMENT PROFILE FRAMEWORK - A method and system for renewing digital certificates using an enrollment profile framework is described. | 2011-05-12 |
20110113241 | IC CARD, IC CARD SYSTEM, AND METHOD THEREOF - An IC card includes: a common key set upon issuance of a card by an IC card issuer; a public key certificate of a parent IC card issued by an authentication station; a signed public key which has been signed by using the parent IC card secret key; a key storage unit which stores the secret key; a data transmission/reception unit which receives at least the public key certificate and the signed public key from the parent IC card; an encryption calculation unit which decodes encrypted user biometric information received from the parent IC card; and a biometric information storage unit which stores first biometric information which has been decoded. The use of the IC card is limited depending on whether biometric information is correct. | 2011-05-12 |
20110113242 | PROTECTING MOBILE DEVICES USING DATA AND DEVICE CONTROL - A method for securing data on a mobile device includes establishing a remote connection between a server and a mobile device, receiving at the server a directory listing from the mobile device indicating files and folders stored on the mobile device, selecting one or more files or folders for securing on the mobile device, and transmitting from the server a secure command to the mobile device instructing the mobile device to secure the selected one or more files or folders. A system including a server and a mobile device can perform the method. | 2011-05-12 |
20110113243 | WIRELESS AD HOC NETWORK SECURITY - Providing network security includes detecting network traffic associated with an ad hoc network that includes a first station and a second station, and preventing data sent by the first station from reaching the second station. | 2011-05-12 |
20110113244 | STATELESS CRYPTOGRAPHIC PROTOCOL-BASED HARDWARE ACCELERATION - According to one embodiment of the invention, a network device comprises a first processing element and a second processing element. The first processing element is adapted to handle an authentication handshaking protocol, such as the SSL/TLS Handshake, and upon receipt of a Client Key Exchange message, passes control of the authentication handshaking protocol to the second processing element. The second processing element completes the authentication handshaking protocol. | 2011-05-12 |
20110113245 | ONE TIME PIN GENERATION - A method and system is provided for generating a one-time passcode (OTP) configured for use as a personal identification number (PIN) for a user account from a user device. The OTP may be generated using an OTP generator which may include an algorithm an user account-specific OTP key. The OTP key may be camouflaged by encryption, obfuscation or cryptographic camouflaging using a PIN or a unique machine identifier defined by the user device. Obtaining an OTP from the user device may require inputting a data element which may be one of a PIN, a character string, an image, a biometric parameter, a user device identifier such as an machine effective speed calibration (MESC), or other datum. The OTP may be used for any transaction requiring a user PIN input, including ATM and debit card transactions, secure access and online transactions. | 2011-05-12 |
20110113246 | SECURE DATA TRANSFER USING AN EMBEDDED SYSTEM - A method and device for securing data transmission via an embedded system that is operationally coupled to a local device and a remote computing system using a network is provided. The method includes, determining if data received from the remote computing system is secured, handshaking with the remote computing system if the data received is from a new connection; decrypting the secured data; and transmitting the decrypted data to the local device. The method also includes, determining if the data received from the local device is from a new connection, handshaking with the remote computing system if the data received is from a new connection; encrypting the data; and transmitting the encrypted data to the remote computing system. A receiving module determines whether input data needs to be encrypted or decrypted; a processing module for encrypting and/or decrypting input data; and an output module for transmitting encrypted and/decrypted data. | 2011-05-12 |
20110113247 | AUTOMATICALLY RECONNECTING A CLIENT ACROSS RELIABLE AND PERSISTENT COMMUNICATION SESSIONS - The invention relates to methods and systems for reconnecting a client and providing user authentication across a reliable and persistent communication session. The method includes providing a first connection between a client and first protocol service and a second connection between the first protocol service and a host service. The first protocol service detects a disruption in the first connection. The client re-establishes the first connection between the client and the first protocol service while maintaining the second connection between the first protocol service and the host service. The first protocol service receives a ticket associated with the client and validates the ticket. The first protocol service links the re-established first connection to the maintained second connection after the ticket is validated. | 2011-05-12 |
20110113248 | Leak-Resistant Cryptographic Token - Chip cards are used to secure credit and debit payment transaction. To prevent fraudulent transaction, the card must protect cryptographic keys used to authenticate transactions. In particular, cards should resist differential power analysis and/or other attacks. To address security risks posed by leakage of partial information about keys during cryptographic transactions, cards may be configured to perform periodic cryptographic key update operations. The key update transformation prevents adversaries from exploiting partial information that may have been leaked about the card's keys. Update operations based on a hierarchical structure can enable efficient transaction verification by allowing a verifying party (e.g., an issuer) to derive a card's current state from a transaction counter and its initial state by performing one operation per level in the hierarchy, instead of progressing through all update operations performed by the card. | 2011-05-12 |
20110113249 | METHOD AND SYSTEM FOR SHARING TRUSTED CONTACT INFORMATION - A method and system for sharing trusted contact information between trusted, known and unknown parties, without revealing the contact information itself, thus protecting the party defined in the contact from possible unsolicited messages known as “Spam”. Addresses of trusted senders are encrypted using a one-way encryption and stored in a whitelist repository that can be shared by different users. When a message is received, its senders address is extracted, encrypted using the same encryption method, and compared if it is found in the whitelist repository. | 2011-05-12 |
20110113250 | SECURITY INTEGRATION BETWEEN A WIRELESS AND A WIRED NETWORK USING A WIRELESS GATEWAY PROXY - A method, system and computer program product in a wireless gateway to provide secured communications over a wireless network and a wired network is provided herein. The method includes the steps of receiving a first authentication credential from a wireless device and mapping the first authentication credential to a second authentication credential. The method further includes transmitting the second authentication credential to an authentication server and receiving a first authentication response from the authentication server. The method also includes generating a first shared secret and a second shared secret if the first authentication response indicates that authentication is successful and transmitting a second authentication response to the wireless device. The first shared secret is used to setup a first secured channel for communications with a service provider over a wired network and the second shared secret is used to setup a second secured channel for communications with the wireless device. | 2011-05-12 |
20110113251 | METHOD FOR IMPROVING NETWORK APPLICATION SECURITY AND SYSTEM THEREOF - The invention, related to information security field, discloses a method for improving network application security and a system thereof. The method comprises that client terminal application generates protocol message and disassembles the protocol message to plural IP packets and sends the plural IP packets; network filter driver receives and caches the plural IP packets and assembles the plural IP packets to obtain the protocol message and determines whether critical information is in the protocol message; if so, the network filter driver sends the protocol message to a smart key device; the smart key device analyzes the protocol message to obtain the critical information and sends the critical information to the user for confirming, if the user confirms that the critical information is correct, the network smart key device signs the protocol message and returns the signature data, the network filter driver generates new protocol message according to the signature data and the protocol message and disassembles the new protocol message to plural IP packets and sends the plural IP packets to the server via network card driver; if the user confirms that the critical information is not correct or no confirmation is received from user in predetermined time period, the smart key device performs exceptional operation. The system comprises a smart key device and network filter driver of client terminal computer. With compatibility and usability, the invention enhances network application security without modifying the client terminal. | 2011-05-12 |
20110113252 | CONCIERGE REGISTRY AUTHENTICATION SERVICE - In an example embodiment described herein is an apparatus comprising a transceiver configured to send and receive data, and logic coupled to the transceiver. The logic is configured to determine from a beacon received by the wireless transceiver whether an associated wireless device sending the beacon supports a protocol for advertising available services from the associated wireless device. The logic is configured to send a request for available services from the associated wireless device via the wireless transceiver responsive to determining the associated wireless device supports the protocol. The logic is configured to receive a response to the request via the wireless transceiver, the response comprising a signature. The logic is configured to validate the response by confirming the signature comprises network data cryptographically bound with service data. | 2011-05-12 |
20110113253 | ENHANCED DIGITAL SIGNATURES ALGORITHM METHOD AND SYSTEM UTILIZING A SECRET GENERATOR - The present invention is a digital signatures scheme method and system that permits the generation of a digital signature in a manner whereby the generator is kept secret. The inclusion of a secret generator in the digital signatures scheme may reduce the potential for an attack upon the scheme to be successful. The present invention may incorporate a signing procedure and a verification procedure. The signing procedure may facilitate the determination of a group, and the identification of the generator from the group. The signing procedure may also keep the generator secret and may generate a digital signature of a message. The generator may be kept secret by one or more conditions, and one or more public keys may be utilized by the digital signatures scheme. The verification procedure may be a verification procedure operable to obtain the message and the digital signature and to verify the digital signature. Embodiments of the present invention may achieve processing of the signing procedure and/or verification procedure at a fast rate of speed, which may further diminish the chance of a successful attack upon the digital signatures scheme. Embodiments of the present invention may further generate variations of digital signatures. | 2011-05-12 |
20110113254 | MULTIPAD ENCRYPTION - A method for protecting a message or document. The method comprises encrypting the message using a first key associated with a first party; sending the encrypted message to a second party; encrypting the message using a second key associated with the second party, so that it is encrypted with two keys simultaneously; sending the encrypted message to the first party; decrypting the message using the first key; sending the message to the second party, the message being encrypted with the second key, and using the second key to decrypt the encrypted message, thereby exposing the original message. | 2011-05-12 |
20110113255 | SYSTEM AND METHOD FOR PROVIDING USER MEDIA - An identification system includes at least one user medium, which is equipped to store a derived key and authenticate itself using the same with respect to a write and/or read device. Furthermore, at least one key dispensing medium is present, which comprises a monolithic first integrated circuit having storage means and processor means, wherein the first integrated circuit is equipped to store a source key and derive therefrom the derived key and to pass it on for storage in the user medium, wherein the user medium is enabled neither directly nor by way of aids to read the source key from the key dispensing medium and/or the user medium is not enabled to calculate a derived key. | 2011-05-12 |
20110113256 | Secure Method for Processing a Content Stored Within a Component, and Corresponding Component - The component comprises a first memory (MM) comprising a first portion (P | 2011-05-12 |
20110113257 | SYSTEMS AND METHODS FOR MANIPULATING AND MANAGING COMPUTER ARCHIVE FILES - A computer program for managing and manipulating archive zip files of a computer. The program includes a system and method for opening, creating, and modifying, and extracting zip archive files. The program is fully integrated into Microsoft Windows Explorer and is accessed via Explorer menus, toolbars, and/or drag and drop operations. An important feature of the program is the archive manager which may be used to open a zip file, create a new zip file, extract zip files, modify zip files, etc. The program is integrated into Microsoft Windows Explorer using the shell name space extension application program interface developed by Microsoft. | 2011-05-12 |
20110113258 | INFORMATION PROCESSING DEVICE, INFORMATION RECORDING MEDIUM MANUFACTURING DEVICE, INFORMATION RECORDING MEDIUM, METHODS THEREOF, AND COMPUTER PROGRAM - An information processing device for executing reproduction processing of content recorded in an information recording medium that includes: a data processing unit for acquiring content codes including a program or application information to be applied to the recording content of the information recording medium, and executing data processing in accordance with the acquired content codes. The data processing unit executes the verification processing of a digital signature which allows tampering verification of the entire content codes included in a content code file storing the content codes, and as the verification result, executes data processing in accordance with the content codes on the condition that validity of the content code file has been confirmed. | 2011-05-12 |
20110113259 | RE-KEYING DURING ON-LINE DATA MIGRATION - A method of migrating data comprises migrating source encrypted data from a source storage device to a target storage device and re-keying while migrating the source encrypted data. The method further comprises while re-keying and migrating the source encrypted data, performing an access request to the source encrypted data apart from the migrating and re-keying. | 2011-05-12 |
20110113260 | Block Encryption Security for Integrated Microcontroller and External Memory System - A secure microcontroller system comprising an integrated cache sub-system, crypto-engine, buffer sub-system and external memory is described according to various embodiments of the invention. The secure microcontroller incorporates block encryption methods to ensure that content communicated between the integrated microcontroller and external memory is protected and real-time performance of the system is maintained. Additionally, the microcontroller system provides a user-configurable memory write policy in which memory write protocols may be selected to balance data coherency and system performance. | 2011-05-12 |
20110113261 | TAMPER RESISTANT APPARATUS FOR A STORAGE DEVICE - In various embodiments, an apparatus includes a processor, a read only memory communicatively coupled to the processor, and a visibility port associated with the apparatus. The visibility port provides information about the processor and the read only memory to the port, with the read only memory including at least a portion of cryptographic information. A visibility port disabler masks the visibility port during cryptographic operations of the processor. | 2011-05-12 |
20110113262 | Voltage sensor for high-current junction - A system includes a high-current junction, a voltage sensor, and a controller. Power connectors of two components are electrically connected at the high-current junction, where a high current passes between the two components at the high-current junction. The voltage sensor detects a voltage at the high-current junction. The controller performs a predetermined action in response to the voltage sensor detecting the voltage at the high-current junction being greater than a predetermined threshold voltage. The system may be a data center rack. The high-current junction may be the junction at which an alternating current (AC) input receives AC power from AC mains. The high-current junction may alternatively be the junction at which a power supply receives the AC power from the AC input to generate direct current (DC) power to provide to data center rack components insertable within the data center rack. | 2011-05-12 |
20110113263 | SERVER - The present invention provides a server including a plurality of power supplies independent from each other, a management backplane, a first embedded management board (first EMB) and a plurality of motherboards independent from each other. The power supplies are turned on or off according to a first control signal. The management backplane is coupled to the power supplies, the first EMB and the motherboards. The first EMB has a power-controlling unit and produces the first control signal and an acknowledgement signal according to the load status, the quantity of a plurality of turned on power supplies and a power-on demand command. The motherboards respectively send out the power-on demand command and decide whether or not to power on according to the acknowledgement signal, wherein when the first EMB works, a polling mode is used to sequentially switch the connections between the first EMB and the motherboards through the management backplane. | 2011-05-12 |
20110113264 | METHOD AND APPARATUS FOR NETWORK COMMUNICATIONS OVER HDMI IN STANDBY MODE - Provided are an apparatus and method thereof for providing standby power for Ethernet communications between a High-Definition Multimedia Interface (HDMI) device and an Ethernet device. The apparatus includes: an HDMI switch which is connected to the HDMI device; an Ethernet switch which is connected to the HDMI switch and the Ethernet device; a standby mode power switch operable to switch standby power to the Ethernet switch; and a primary power source operable to provide primary power to the Ethernet switch; a standby power source operable to provide the standby power to the Ethernet switch via the standby mode power switch; and a controller operable to receive the control signal from the HDMI device and to control to the standby mode power switch, wherein if the control signal is received, the controller controls the standby mode power switch to switch the standby power to the Ethernet switch. | 2011-05-12 |
20110113265 | CIRCUIT SYSTEM AND CONTROL METHOD THEREOF - A circuit system is provided, including a processing unit, a control unit electrically connected to the processing unit, and a plurality of PWM units electrically connected to the control unit. The processing unit transmits a control signal to the control unit according to a load current value of the circuit system, and the control unit enables at least one of the PWM units according to the control signal. | 2011-05-12 |
20110113266 | Electronic Device and Power Control Module Thereof - This invention provides an electronic device and a power control module thereof. The electronic device is used for being connected with an external power source, and the electronic device includes a system unit, a power supply unit, a power control module, and a control unit coupled with the system unit and the power control module. When the power supply unit is connected with the external power source, the power supply unit provides a first operating voltage for the power control module, the power control module provides a first control signal for the control unit, and the control unit receives the first control signal and provides a second control signal for the power supply unit according to the first control signal, allowing the power supply unit to sequentially provide a plurality of system working voltages for the system unit. | 2011-05-12 |
20110113267 | IMAGE FORMING APPARATUS AND POWER CONTROL METHOD THEREOF - An image forming apparatus includes a volatile memory and an SoC part. The SoC part includes an internal memory, a CPU for accessing the volatile memory in the normal mode; an interface part for receiving a external signal, and a control part for, when the interface part has no input during a first preset time, copying information stored to the volatile memory to the internal memory and converting to a first power saving mode to lower an operating frequency of the volatile memory and an operating frequency of the CPU, and when a normal mode switch signal is not input during a second preset time in the first power saving mode, controlling the CPU to access the information copied to the internal memory and converting to a second power saving mode to change the volatile memory to a self-refresh mode. | 2011-05-12 |
20110113268 | COMMUNICATION DEVICE - In one embodiment, a communication device includes: a relay module relaying communication of a signal between devices; a notification module giving a notice to recover from a standby state to the device via different communication from the communication; a function judgment module referring to information indicating a function of the device in the signal from the device to judge whether the device is to be recovered by the notice; a signal proxy response module sending a response indicating of receiving the signal as a proxy to the device from which the signal is transmitted when the signal indicates an instruction to recover, and the device to which the signal is transmitted is judged to recover by the notice; and a notification control module instructing the notification module to give the notice to the device to which the signal is transmitted and for which the proxy response is sent. | 2011-05-12 |
20110113269 | METHOD OF DYNAMICALLY SCALING A POWER LEVEL OF A MICROPROCESSOR - A method of dynamically scaling a power level of a microprocessor is provided. The method includes: calculating unit workload rates during unit periods in a first duration period; changing a length of the first duration period based on a variation of the unit workload rates; calculating a period workload rate by accumulating the unit workload rates in the first duration period; and changing the power level of the microprocessor based on the calculated period workload rate. | 2011-05-12 |
20110113270 | Dynamic Voltage and Frequency Scaling (DVFS) Control for Simultaneous Multi-Threading (SMT) Processors - A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors. | 2011-05-12 |
20110113271 | METHOD AND DEVICE FOR THE DYNAMIC MANAGEMENT OF CONSUMPTION IN A PROCESSOR - A method for managing the power consumed in a processor executing an application, the application including several processing phases, each of which is associated with a computational load. The method includes defining a first nominal mode of consumption, defining at least one second mode of low consumption, and formulating a decision function making it possible optionally to switch from the nominal mode of consumption to the mode of low consumption during the transition from one processing phase to another processing phase of the application. | 2011-05-12 |
20110113272 | PROJECTOR AND POWER CONTROL METHOD THEREOF - A projector and a power control method thereof are provided. The projector includes a battery supplying a battery power; an interface receiving and transmitting an external power; a selection unit receiving the battery power and the external power, and selecting and outputting one of the battery power and the external power to be served as the operation voltage of the projector; a lighting element; a driver receiving a driving signal and driving the lighting element accordingly; and a central processing unit (CPU) outputting a control signal with a first state to control the selection unit to select and output the external power when the capacity of the battery is not sufficient and the interface receives the external power, and regulating the intensity of the driving signal outputted from the CPU according to the capacity of the external power so as to make the projector continuously maintain in operation. | 2011-05-12 |
20110113273 | OPERATION MANAGEMENT METHOD OF INFORMATION PROCESSING SYSTEM - In a computer room including information processing devices and air conditioners, power saving of the computer room by means of optimization of workload allocation to the information processing devices is achieved in a short time. There, a coefficient of air conditioner performance with respect to the information processing device (device-specific COP) is calculated for each air conditioner. Further, a device-associated power consumption expression representing a total of device power and air conditioner power is created for each information processing device. Also, power consumption of the entire computer room is calculated from the device-associated power consumption expression of the information processing devices. Also, workload allocation is determined by using power saving performance evaluation indexes based on the device-associated power consumption expression of the information processing devices. Further, output of the air conditioner is controlled based on a result of the air conditioner power calculation. | 2011-05-12 |
20110113274 | ELECTRONIC DEVICE, A METHOD OF CONTROLLING AN ELECTRONIC DEVICE, AND SYSTEM ON-CHIP - An electronic device is provided, which comprises at least one processing unit (CPU) for processing at least one application, an operating system (OS) for controlling the at least one application performed by the at least one processing unit (CPU), at least one workload build-up detector (WBD) for detecting a build-up of the workload of the at least one processing unit (CPU), at least one workload decrease detector (WDD) for detecting a decrease of the workload of the at least one processing unit (CPU), and at least one power management unit (SPM) for controlling an operating frequency and/or an operating voltage of the at least one processing unit in dependence on the detected workload build-up or the detected workload decrease. | 2011-05-12 |
20110113275 | MICROCOMPUTER - IO buffers that operate with an IO power supply system and cut cells that isolate the IO buffers from each other are disposed on the periphery of an always-on power supply area and a power supply cut-off available area. A signal indicating the holding of an IO output(s) output from the always-on power supply area is wired so as to go round the IO buffers and the cut cells. The cut cell includes a level shifter that operates with an IO power supply system. The cut cell shifts the level of signal indicating the holding of IO output so that the signal level conforms to the power supply system of IO buffers, and outputs the resultant signal to the IO buffers. | 2011-05-12 |
20110113276 | Physical Separation and Recognition Mechanism for a Switch and a Power Supply for Power Over Ethernet (POE) in Enterprise Environments - A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In an enterprise environment, a table top network switch uses a power supply to provide power for PoE and data communications to one or more powered devices (e.g., personal or laptop computers). To reduce the amount of heat generated in the table top network switch, the power supply is located external to the table network switch. The table top network switch may also include enterprise equipment, such as a video projector, a monitor for a personal computing device, another personal computing device to provide some examples. The power supply for the enterprise equipment may be included within the table top network switch to provide additional integration. The power for PoE and data communications to a limited number of powered devices (e.g., personal or laptop computers) may be included within the table top network switch to provide even further integration. | 2011-05-12 |
20110113277 | PROCESSING UNIT, PROCESS CONTROL SYSTEM AND CONTROL METHOD - A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication. | 2011-05-12 |
20110113278 | TUNNEL MANAGEMENT METHOD, TUNNEL MANAGEMENT APPARATUS, AND COMMUNICATIONS SYSTEM - The present invention relates to communications technologies and discloses a tunnel management method, a tunnel management apparatus, and a communications system so that a node that causes failure of a tunnel management request can be determined. According to the present invention, a response returned by a tunnel management node to an initiating node includes not only a cause value of tunnel management request failure but also information of the node that causes failure of the tunnel management request, so that the initiating node can find the node that causes failure of the tunnel management request and determine the error checking direction. The present invention is applicable to network devices in a communications network. | 2011-05-12 |
20110113279 | Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk - A redundant and fault tolerant solid state disk (SSDC) includes a determination module configured to identify a first SSDC configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC. | 2011-05-12 |
20110113280 | CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR - A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed. | 2011-05-12 |
20110113281 | DATA STORAGE SYSTEM AND METHOD - A data storage system and method are disclosed. The data storage system includes a first memory, a controller, a counting module, and a checking and correcting module. Copyback operations are performed in the first memory. The controller couples the first memory to the counting module and the checking and correcting module. The counting module provides a counting operation for the copyback operations at different logic addresses of the first memory and, according to a counting result of the counting operation, determines whether a checking and correcting requirement has been satisfied by any of the logic addresses. The checking and correcting module receives data read out from the first memory, wherein the received data corresponds to a satisfying logic address, and checks, or checks and corrects the received data to correct the first memory accordingly. | 2011-05-12 |
20110113282 | METHOD OF STORING A DATA SET IN A DISTRIBUTED STORAGE SYSTEM, DISTRIBUTED STORAGE SYSTEM AND COMPUTER PROGRAM PRODUCT FOR USE WITH SAID METHOD - The present invention is directed to a method of storing a data set in a storage system. Said storage system comprises a plurality of storage entities. The method comprises the following steps. A step of forming at least one data set block from said data set using a fragmentation entity. A step of encoding said at least one data set block by means of an encoding entity, wherein said encoding entity provides a plurality of encoded blocks based on said at least one data set block at an output of said encoding entity. And a step of distributing said encoded blocks amongst at least two of said storage entities using a distribution entity for storage thereof by said storage entities. Said encoding entity uses a rateless erasure encoding algorithm based on rateless codes for encoding said at least one data set block. The invention is further directed to a storage system and a computer program product. | 2011-05-12 |
20110113283 | Apparatus and Method for Reloading Software Images - An apparatus and method are disclosed for reloading software images. A copy module copies application metadata for an application image to an application metadata copy. The application metadata and application image are stored on a writable memory of a data processing device. The application metadata copy is stored remotely from the data processing device. A detection module detects an operational anomaly. An erasure module erases at least the application image on the writeable memory in response to detecting the operational anomaly. An identification module identifies the application image from the application metadata copy. A reload module reloads the application image to the writable memory using the application metadata copy. | 2011-05-12 |
20110113284 | READ RETRY METHOD AND APPARATUSES CAPABLE OF PERFORMING THE READ RETRY METHOD - A read retry method performed in a hard disk drive, the read retry method may include performing a read operation; and ignoring a read error flag generated when a read error is generated, and continuing to perform the read operation. | 2011-05-12 |
20110113285 | SYSTEM AND METHOD FOR DEBUGGING MEMORY CONSISTENCY MODELS - A system and method for analyzing a test program with respect to a memory model includes preprocessing a test program into an intermediate form and translating the intermediate form of the test program into a relational logic representation. The relational logic representation is combined with a memory model to produce a legality formula. A set of bounds are computed on a space to be searched for the memory model or on a core of the legality formula. A relational satisfiability problem is solved, which is defined by the legality formula and the set of bounds to determine a legal trace of the test program or debug the memory model. | 2011-05-12 |
20110113286 | SCAN TEST CIRCUIT AND SCAN TEST METHOD - A scan test circuit for a memory with a first memory cell column, a second memory cell column that replaces a failed column of the first memory cell column, a first switching circuit that connects one of the memory cell columns to a first peripheral circuit disposed at an input side, and a second switching circuit that connects one of the memory cell columns to a second peripheral circuit disposed at an output side, comprises: a test priority control circuit that controls the switching circuits to establish at least two patterns of connections of the memory cell columns to the peripheral circuits; and a test point circuit that includes scan flip-flop circuits employed in a scan test for detecting a delay fault of the peripheral circuits, and is disposed between the memory cell columns and the first switching circuit. | 2011-05-12 |
20110113287 | System for Automated Generation of Computer Test Procedures - A system automatically generates a workflow report for computerized system testing and other uses. The system comprises at least one processing device including at least one log file including records identifying time stamped actions performed by a user of a computerized processing system and actions performed by the system. A repository includes stored predetermined data patterns associated with workflow tasks performed in a workflow by a user and a system. A parser automatically parses records of the at least one log file to identify workflow tasks performed during a time period using the predetermined data patterns. A report generator automatically generates a workflow report comprising the identified workflow tasks and associated time stamps indicating workflow tasks performed by the system and user during the time period. An output processor provides the generated workflow report to a destination device for access by a user. | 2011-05-12 |
20110113288 | Generating random sequences based on stochastic generative model having multiple random variates - Random sequences are generated based on a stochastic generative model having multiple random variates. Inputs representative of the stochastic generative model are received. The inputs include a first random variate having a finite set of alphabets, a second random variate having a set of alphabets, and a third random variate having a finite set of alphabets. Outputs representative of the random sequences are generated based on the stochastic generative model. The outputs include a first random sequence that is a finite-length random sequence of alphabets randomly selected from the first random variate, a second random sequence having a set of alphabets selected from the second random variate, and a third random sequence having a set of alphabets randomly selected from the third random variate. | 2011-05-12 |
20110113289 | UNIT FOR PREDICTING MALFUNCTION OF AN APPARATUS - According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result. | 2011-05-12 |
20110113290 | METHOD AND SYSTEM FOR TESTING CONFIGURATION OF ENVIRONMENTS - A method and system for testing configuration of environments are provided. A probe for connection to a network and/or devices interacts to launch a configuration analyser tool. The configuration analyser tool includes a test mechanism for running a set of tests for the probe relating to connectivity and configuration of attached networks and devices before connection and suggesting solutions to test results. The tests may be externalised and dynamically loaded at run time of the configuration analyser tool. | 2011-05-12 |
20110113291 | APPARATUS FOR COLLECTING TRACE INFORMATION AND PROCESSING TRACE INFORMATION, AND METHOD FOR COLLECTING AND PROCESSING TRACE INFORMATION - In the system, an apparatus for collecting trace information provided on a circuit executing a program includes a counter unit which increments a count value for each execution cycle of the program, and a collection unit outputs trace information at a fetching timing of the trace information outputted by the circuit and a count value of the counter unit at the fetching timing. Another apparatus for processing trace information includes a trace information acquisition unit which acquires the trace information added with a count value from a trace information collection apparatus, a sort processing unit which sorts the acquired trace information based on the count value, and a trace information storage unit which store the sorted trace information. | 2011-05-12 |
20110113292 | Method, Device, Computer Program Product and Data Processing Program For Handling Communication Link Problems Between A First Communication Means and A Second Communication Means - A method for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link. | 2011-05-12 |
20110113293 | DATA RECEPTION DEVICE, DATA RECEPTION METHOD, AND PROGRAM - A data reception device that receives scrambled and transmission data as received data and that descrambles and outputs the data after adjusting the timing with the transmitter has a descramble circuit | 2011-05-12 |
20110113294 | TUNABLE EARLY-STOPPING FOR DECODERS - A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computing a fidelity estimate and stopping decoding based on the fidelity estimate. | 2011-05-12 |
20110113295 | SUPPORT ELEMENT OFFICE MODE ARRAY REPAIR CODE VERIFICATION - A support element for verifying an array repair code solution includes a memory subsystem element including product data read from multichip modules utilized in a mainframe computing device, a wafer test repair algorithm, and a system test repair algorithm. The support element also includes a CPU emulator that causes the support element to perform an initial microcode load that includes a memory test, the memory test applying the wafer test repair algorithm to the product data to generate a wafer test repair solution and the system test repair algorithm to the product data to generate a system test repair solution and one or more repair rings for storing the wafer test repair solution and the system test repair solution. | 2011-05-12 |
20110113296 | Method of testing a memory module and hub of the memory module - Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals. | 2011-05-12 |
20110113297 | DISTRIBUTED JOINT TEST ACCESS GROUP TEST BUS CONTROLLER ARCHITECTURE - Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board. | 2011-05-12 |
20110113298 | METHOD OF AND AN ARRANGEMENT FOR TESTING CONNECTIONS ON A PRINTED CIRCUIT BOARD - A method of and an arrangement for testing connections on a printed circuit board between boundary-scan compliant circuit terminals of one or more boundary-scan compliant devices mounted at the printed circuit board and comprising a boundary-scan register of boundary-scan cells of the boundary-scan compliant circuit terminals. Under control of an electronic processing unit, boundary-scan properties of the or each boundary-scan compliant device are retrieved, a list comprising boundary-scan compliant circuit terminals is displayed, and a selection of at least a first and second boundary-scan compliant circuit terminal is received. Based on this selection, a boundary-scan cell of a first boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a driver and a boundary-scan cell of a second boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a sensor. The driver is controlled through data provided to the boundary-scan register. Data sensed by the sensor are latched in the boundary-scan register. The driver and sensor data are analyzed for a connection between the first and the second boundary-scan compliant circuit terminals and the result of the analyses is presented. | 2011-05-12 |