19th week of 2016 patent applcation highlights part 42 |
Patent application number | Title | Published |
20160132369 | MULTI-PROCESSOR DEVICE - An electronic device includes a first processor; and a second processor; and a third processor. The second processor is configured to detect an event, select one of the first and third processors to perform one or more operations associated with the event, and cause the selected processor to perform the one or more operations. | 2016-05-12 |
20160132370 | METHOD AND APPARATUS FOR PROVIDING APPLICATION NOTIFICATIONS - An approach is provided for distributing notifications from developers to installed applications via a notification enabler separate from the applications. The notification platform determines at least one application installed on at least one device. Then, the notification platform causes, at least in part, a subscription via at least one notification enabler to one or more notification channels associated with the at least one application, wherein the at least one notification enabler is a separate component from the at least one application. | 2016-05-12 |
20160132371 | MESSAGE-BASED MODEL VERIFICATION - A system and method may generate executable block diagrams having blocks that run in accordance with message-based execution semantics. A message may include an input data payload that does not change over time, and the message may persist for only a determined time interval during execution of block diagram. A verification engine may provide one or more tools for evaluating and verifying operation of message-based blocks. The verification engine may support one or more verification blocks that may be added to the block diagram and associated with the diagram's message-based blocks. The verification blocks may capture and present messages exchanged among the message-based blocks. The verification blocks may also specify an expected interaction of messages, and determine whether the actual messages are equivalent to the expected interaction. | 2016-05-12 |
20160132372 | Cognitive Analysis for Healing an IT System - A cognitive computing hardware system receives an error log from an IT system. The error log comprises a record of errors currently being detected by sensors in the IT system. The cognitive computing hardware system receives an error history log, which describes a history of past errors that have occurred in the IT system. The cognitive computing hardware system receives a listing of alternative IT systems that have been predetermined to have a same functionality as the IT system that is currently experiencing the errors. The cognitive computing hardware system receives a record of real-time events that are external to the IT system, and generates a prioritized set of solutions to heal the IT system, based on the error history log, the listing of alternative IT systems, and the record of real-time events. The cognitive computing hardware system transmits a highest prioritized solution to the IT system. | 2016-05-12 |
20160132373 | SYSTEM ANALYSIS DEVICE, SYSTEM ANALYSIS METHOD AND SYSTEM ANALYSIS PROGRAM - A system analysis device | 2016-05-12 |
20160132374 | DETECTION OF DATA CORRUPTION IN A DATA PROCESSING DEVICE - A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature. | 2016-05-12 |
20160132375 | METHOD FOR DETECTING THE IMPENDING ANALYTICAL FAILURE OF NETWORKED DIAGNOSTIC CLINICAL ANALYZERS - A method of detecting impending analytical failure in a networked diagnostic clinical analyzer is based upon detecting whether the operation of a particular analyzer is statistically distinguishable based on one or more thresholds. A failure occurs when one or more components or modules of the analyzer fails. A method to detect such an impending failure is disclosed. Baseline data on a pre-selected set of analyzer variables for a population of diagnostic clinical analyzers is used to generate an impending failure threshold. Subsequently, operational data comprising the same pre-selected set of analyzer variables allows generation of a time series of operational statistics. If the operational statistic exceeds the impeding failure threshold in a prescribed manner, an impending analytical failure is predicted. Such detection of impending analytical failures facilitates intelligent scheduling of service for the analyzer in question to maintain high assay throughput and accuracy. | 2016-05-12 |
20160132376 | DIAGNOSTC DATA SET COMPONENT - Various embodiments for retaining diagnostic information for data in a computing storage environment. In one such embodiment, a diagnostic component, apart from a volume table of contents (VTOC), associated with an integrated catalog facility (ICF) catalog and with a base data set from data sets via a catalog association record, is initialized. The diagnostic component is configured to retain base data set-specific diagnostic information retrievable by the computing storage environment to assist in error diagnosis. The base data set-specific diagnostic information is stored pursuant to at least one detected event associated with the base data set. | 2016-05-12 |
20160132377 | AUTOMATED DEFECT DIAGNOSIS FROM MACHINE DIAGNOSTIC DATA - Diagnosis of defect(s) in a system is disclosed. A defect signature-based query is performed against system diagnostic data stored in one or more structured records. It is determined that a defect signature is associated with a system based at least in part on the query. Remediation information generated based at least in part on the defect signature and the system diagnostic data may be output. | 2016-05-12 |
20160132378 | METHOD AND APPARATUS FOR CONTROLLING WATCHDOG - A method of controlling a watchdog and an apparatus for the same are provided. The method of controlling a watchdog within a controller includes determining, by a processor, whether to respond to a fault in the controller by comparing a watchdog count with a predetermined watchdog warning level when the fault is detected. Further, the method includes storing, by the processor, information regarding a program group related to the detected fault and a watchdog reset count that corresponds to the program group within a memory after increasing the watchdog reset count when the fault is to be responded to. In addition the processor is configured to reset the controller when the watchdog count exceeds a predetermined watchdog timeout level. Therefore, the present invention prevents occurrence of repeated resets that result from the same cause within the controller. | 2016-05-12 |
20160132379 | Storage Device Calibration Methods and Controlling Device Using the Same - A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful. | 2016-05-12 |
20160132380 | BUILDING AN INTELLIGENT, SCALABLE SYSTEM DUMP FACILITY - A computer program product and a computer system for building a scalable system dump facility is provided. The method includes loading a component into system memory. The component includes a plurality of program modules. A component text range table entry is created for each component, whereby the component text range table entry includes: an address range, a component identifier, a data collection function, and a link to one or more related components. Upon invoking a system dump facility, a failing function instruction is determined, based on an address of the failing instruction. The component text range table is searched for an address of a failing function that is in the address range. Memory regions that are associated with the address range are transferred to a storage device first. Memory regions that are associated with related components are transferred next. Remaining memory regions are then transferred. | 2016-05-12 |
20160132381 | BUILDING AN INTELLIGENT, SCALABLE SYSTEM DUMP FACILITY - A method for building a scalable system dump facility is provided. The method includes loading a component into system memory. The component includes a plurality of program modules. A component text range table entry is created for each component, whereby the component text range table entry includes: an address range, a component identifier, a data collection function, and a link to one or more related components. Upon invoking a system dump facility, a failing function instruction is determined, based on an address of the failing instruction. The component text range table is searched for an address of a failing function that is in the address range. Memory regions that are associated with the address range are transferred to a storage device first. Memory regions that are associated with related components are transferred next. Remaining memory regions are then transferred. | 2016-05-12 |
20160132382 | COMPUTING SYSTEM WITH DEBUG ASSERT MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: a volatile memory configured to: store a debug assert flag mask including bits; cores, coupled to the volatile memory, configured to: detect an error in at least one of the cores, set at least one of the bits corresponding to the cores with the error detected, collect debug information for each of the cores with the error detected, collect operating information for each of the cores without the error detected, generate assert dump information based on compiling the debug information; and a nonvolatile memory, coupled to at least one of the cores, configured to: store the assert dump information, the operating information, configured to by at least one of the cores. | 2016-05-12 |
20160132383 | Adjusting the Use of a Chip/Socket Having a Damaged Pin - An electronic system comprises: a pin sensor; and an integrated management module, wherein the integrated management module: identifies a location of a damaged connector between a semiconductor chip and a hardware socket, wherein the location of the damaged connector is described by one or more readings from the pin sensor, and wherein the damaged connector prevents a particular signal from being supplied to the semiconductor chip via the hardware socket; identifies the particular signal as an input for a particular semiconductor function; determines whether the semiconductor chip provides the particular semiconductor function; and adjusts a use of the semiconductor chip based on whether or not the semiconductor chip uses the particular signal to provide the particular semiconductor function. | 2016-05-12 |
20160132384 | DATA READING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A data reading method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first read command; setting a plurality of first read events in a multi trigger queue (MTQ) according to the first read command, wherein the first read events include a general read event and at least one cache read event; sending a first read command sequence according to at least one of the first read events and receiving first data from a rewritable non-volatile memory module; and if a decoding for the first data fails, resetting the MTQ, and sending at least one second read command sequence according to at least one second read event in the reset MTQ, wherein the at least one second read event includes at least one of the at least one cache reading event. | 2016-05-12 |
20160132385 | USING ERROR CORRECTING CODES FOR PARITY PURPOSES - Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block. | 2016-05-12 |
20160132386 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error. | 2016-05-12 |
20160132387 | DATA ACCESS METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data access method for a rewritable non-volatile memory module is provided. The method includes: filling dummy data to first data in order to generate second data, and writing the second data and an error checking and correcting code (ECC code) corresponding to the second data into a first physical programming unit. The method also includes: reading data stream from the first physical programming unit, wherein the data stream includes third data and the ECC code. The method further includes: adjusting the third data according to a pattern of the dummy data in order to generate fourth data when the third data cannot be corrected by using the ECC code, and using the ECC code to correct the fourth data in order to obtain corrected data, wherein the corrected data is identical to the second data. | 2016-05-12 |
20160132388 | SEMICONDUCTOR MEMORY DEVICE AND ECC METHOD THEREOF - A semiconductor memory device and ECC method thereof are provided which a first nonvolatile memory; a second nonvolatile memory having a type different from the first nonvolatile memory; a controller; a first error correction circuit configured to correct an error of first write data to be programmed at the first nonvolatile memory; and a second error correction circuit included in the controller and configured to correct an error of first write data or an error of second write data to be programmed at the second nonvolatile memory, based on an error correction algorithm different from that of the first error correction circuit. Error correction data for correcting an error of the first write data is generated using one of the first error correction circuit and the second error correction circuit according to an attribute of the first write data. | 2016-05-12 |
20160132389 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 2016-05-12 |
20160132390 | USING ERROR CORRECTING CODES FOR PARITY PURPOSES - Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block. | 2016-05-12 |
20160132391 | SLEEP MODE OPERATION FOR VOLATILE MEMORY CIRCUITS - Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data. | 2016-05-12 |
20160132392 | NON-VOLATILE MEMORY DATA STORAGE WITH LOW READ AMPLICATION - In one embodiment, an apparatus includes one or more memory devices, each memory device having non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices, the memory controller being configured to receive data to be stored to the one or more memory devices, store read-hot data within one error correction code (ECC) codeword as aligned data, and store read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. According to another embodiment, a method for storing data to non-volatile memory includes receiving data to store to one or more memory devices, each memory device including non-volatile memory configured to store data, storing read-hot data within one ECC codeword as aligned data, and storing read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. | 2016-05-12 |
20160132393 | System and Method for Improving Read Performance of a Distributed Parity RAID Solution - An information handling system includes a plurality of storage disks arranged as a redundant array of independent disks and a controller. The controller communicates with each of the storage disks. The controller determines a total amount of storage space utilized to store parity information within the storage disks based on a smallest disk size of the storage disks and a number of storage disks in the redundant array of independent disks, calculates an amount of storage space utilized to store parity information on each of the disks based on the total amount of storage space utilized to store parity information and the number of storage disks, and allocates a parity region of sectors within each of the storage disks to store the parity information. The parity region is an inner most region of a disk. | 2016-05-12 |
20160132394 | STORAGE DRIVE REMEDIATION IN A RAID SYSTEM - Techniques, systems, and devices are disclosed for remediating a failed drive in a set of drives, such as a RAID system, without having to physically replace the failed drive. After receiving a signal of an error indicating a specific physical portion on a storage drive in the set of storage drives has caused the drive to fail, the system can unmount the drive from the filesystem while other drives continue to operate. Next, the system can identify one or more files in the filesystem that have associations with the specific physical portion on the failed drive. Next, the system can remount the drive onto the filesystem and subsequently delete the identified files from the filesystem. The system can then perform a direct I/O write to the specific physical portion on the failed drive to force reallocation of the specific physical portion to a different area on the failed drive. The system can also power-cycle the drive before this remediation, e.g., to determine if this remediation can be avoided. | 2016-05-12 |
20160132395 | PERIPHERAL BUS ERROR CONTAINMENT AND RECOVERY - A peripheral bus error containment and recovery system enables a bus device to experience a fatal bus error and recover without stopping execution of an operating system. When a fatal bus error is detected at the bus device, a bus controller may deactivate a data link layer for a downstream port populated by the bus device, causing an operating system device driver to be uninstalled for the bus device. Then, the operating system device driver may be reinstalled without physically removing the bus device. | 2016-05-12 |
20160132396 | EXTENT METADATA UPDATE LOGGING AND CHECKPOINTING - In one embodiment, an extent store layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster manages efficient logging and checkpointing of metadata. The metadata managed by the extent store layer, i.e., the extent store metadata, resides in a memory (in-core) of each node and is illustratively organized as a key-value extent store embodied as one or more data structures, e.g., a set of hash tables. Changes to the set of hash tables are recorded as a continuous stream of changes to SSD embodied as an extent store layer log. A separate log stream structure (e.g., an in-core buffer) may be associated respectively with each hash table such that changed (i.e., dirtied) slots of the hash table are recorded as entries in the log stream structure. The hash tables are written to SSD using a fuzzy checkpointing technique. | 2016-05-12 |
20160132397 | PHASED NETWORK FORMATION FOR POWER RESTORATION - In one embodiment, a device receives a router advertisement message after a power outage event in a network. The device joins the network, in response to receiving the router advertisement message. The device sends a power restoration notification message via the network. The device selectively delays a disconnected node from joining the network. | 2016-05-12 |
20160132398 | IMPLEMENTING CHANGE DATA CAPTURE BY INTERPRETING PUBLISHED EVENTS AS A DATABASE RECOVERY LOG - A method for implementing a change capture system using an event publishing system as a database recovery log is provided. The method may include determining a set of data based on a description of events for which change capture is possible. The method may also include selecting at least one item of data from within the determined set of data, wherein the at least one item of data requires change capture to be performed. Additionally, the method may include identifying at least one published event, wherein the at least one published event is produced by the event publishing system. The method may include instructing the event publishing system to deliver the at least one identified published event to the change capture system. Furthermore, the method may include receiving the at least one identified published event. The method may also include processing the at least one published event. | 2016-05-12 |
20160132399 | IMPLEMENTING CHANGE DATA CAPTURE BY INTERPRETING PUBLISHED EVENTS AS A DATABASE RECOVERY LOG - A method for implementing a change capture system using an event publishing system as a database recovery log is provided. The method may include determining a set of data based on a description of events for which change capture is possible. The method may also include selecting at least one item of data from within the determined set of data, wherein the at least one item of data requires change capture to be performed. Additionally, the method may include identifying at least one published event, wherein the at least one published event is produced by the event publishing system. The method may include instructing the event publishing system to deliver the at least one identified published event to the change capture system. Furthermore, the method may include receiving the at least one identified published event. The method may also include processing the at least one published event. | 2016-05-12 |
20160132400 | CROSS-PLATFORM VIRTUAL MACHINE BACKUP AND REPLICATION - According to certain aspects, a method can include, at a first time, performing an incremental backup of first data associated with a virtual machine (VM) residing on a source client computing device from the source client computing device to one or more secondary storage devices to create a backup copy of the VM, where the VM is associated with a hypervisor of a first type; receiving an instruction to restore the first data associated with the VM from the one or more secondary storage devices; retrieving the first data from the one or more secondary storage devices; and applying the first data to second data associated with a replicated VM running on the destination client computing device, where the replicated VM is a replicated version of the VM, and where the second data corresponds to data of the VM at a time before the first time. | 2016-05-12 |
20160132401 | SYSTEMS AND METHODS FOR SECURE REMOTE STORAGE - Systems and methods are provided for transmitting data to at least one storage system. A request is received to store a data set in a storage location. In response, a first plurality of shares is generated, each containing a distribution of data from the data set, and at least one share is stored in a local memory configured for backup in at least one remote storage system. At least one share is transmitted to the at least one remote storage system. Systems and methods are also provided for improving data availability. In response to a restoration event, if insufficient shares of data are available to reconstruct a data set, a read instruction in a journaling message is transmitted to a remote storage system requesting an additional share. The additional share is received and stored in a local storage, and the data set is reconstructed. | 2016-05-12 |
20160132402 | TEST DEVICE AND METHOD FOR CONTROLLING THE SAME - A test device and a method for controlling the test device are disclosed. After a test is interrupted due to a malfunction of the test device, the test device continuously performs the interrupted testing. The test device for testing a biological material includes: a memory configured to store information which relates to progress of a test; and a controller which, if the test is interrupted due to a malfunction of the test device, is configured to continue performance of the test by using the information which relates to the test progress which is stored in the memory. | 2016-05-12 |
20160132403 | FAULT-TOLERANCE THROUGH SILICON VIA INTERFACE AND CONTROLLING METHOD THEREOF - A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, p data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<μ2016-05-12 | |
20160132404 | METHOD AND APPARATUS FOR REDUNDANCY IN AN ATM USING HOT SWAP HARDWARE UNDERLYING A VIRTUAL MACHINE - A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual environment such as a virtual machine and/or a virtual disk environment. Should a software component fail, the virtual environment will “crash” but the ATM hardware and operating system will remain intact. If the software is fatally flawed—e.g., due to a faulty “upgrade” the older version may be “rolled back” from a previously stored virtual environment. | 2016-05-12 |
20160132405 | METHOD AND APPARATUS FOR REDUNDANCY IN AN ATM USING HOT SWAP HARDWARE UNDERLYING A VIRTUAL MACHINE - A method and apparatus for providing redundancy in an Automatic Teller Machine (ATM) is provided. Application software may be run on top of a virtual environment such as a virtual machine and/or a virtual disk environment. Should a software component fail, the virtual environment will “crash” but the ATM hardware and operating system will remain intact. If the software is fatally flawed—e.g., due to a faulty “upgrade” the older version may be “rolled back” from a previously stored virtual environment. | 2016-05-12 |
20160132406 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super page by selecting main pages from the respective main regions, wherein when a main page of a main region in a memory device is a bad region, the processor forms a virtual super page by selecting a virtual page from a virtual region in the memory device instead of the main page. | 2016-05-12 |
20160132407 | FAILOVER SYSTEM AND METHOD OF DECIDING MASTER-SLAVE RELATIONSHIP THEREFOR - A failover system and a method of deciding master-slave relationship therefor are provided. The failover system includes a first electronic device, a second electronic device, a decision circuit and at least two isolation modules. The decision circuit is coupled to the first electronic device and the second electronic device and configured to determine operating states of the first electronic device and the second electronic device and output a first selecting signal and a second selecting signal. The at least two isolation modules are coupled to the first electronic device, the second electronic device, and the decision circuit and configured to switch a master-slave relationship between the first electronic device and the second electronic device according to the first selecting signal and the second selecting signal. | 2016-05-12 |
20160132408 | MIRRORING IN THREE-DIMENSIONAL STACKED MEMORY - A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips. | 2016-05-12 |
20160132409 | MIRRORING IN THREE-DIMENSIONAL STACKED MEMORY - A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips. | 2016-05-12 |
20160132410 | KERNEL STATE AND USER STATE DATA EXCHANGE METHOD FOR DISASTER RECOVERY OF VIRTUAL CONTAINER SYSTEM - The present invention relates to a kernel state and user state data exchange method for disaster recovery of a virtual container system. In one disaster recovery backup of a virtual container, data needs to be exchanged between a kernel state and a user state. The file system operation of the kernel state needs to be transmitted to a user state program for processing firstly, and the processing result is returned to the kernel state and then transmitted to an original application program. Low recovery speed of a data block is mainly caused by the need of multiple times of switching between the kernel state and the user state, and the communication efficiency of the kernel state and the user state is low. In the present invention, all recovery operations are completed by the user state by virtue of a FUSE. A FUSE file system is realized firstly, one of files therein is mapped to the /DEV/LOOP device, then the LOOP device is used as a shadow device of a disk to be recovered, and a virtual container manager enables a virtual container with the LOOP device. The access to the original hard disk is intercepted in the FUSE file system, and then the FUSE file system communicates with the server, so that efficient on-demand recovery of data is realized. | 2016-05-12 |
20160132411 | STORAGE CLUSTER FAILURE DETECTION - Direct monitoring of a plurality of storage nodes in a primary cluster is performed based on connectivity with the storage nodes. Indirect monitoring of a first storage node is performed, in response to direct monitoring of the first storage node indicating failure of the connectivity with the first storage node, wherein a second storage node of the plurality of nodes is a backup node for the first storage node. The indirect monitor of the first storage node indicates failure of the first storage node in response to performance of storage access operations by the second storage node that were previously performed by the first storage node. A cluster-switch operation is initiated to switch to from the primary cluster to a backup cluster based on an occurrence of at least one cluster-failure condition that comprises the indirect monitor of the first storage node indicating failure of the first storage node. | 2016-05-12 |
20160132412 | PERFORMANCE OPTIMIZATION OF READ FUNCTIONS IN A MEMORY SYSTEM - According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that minors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table. | 2016-05-12 |
20160132413 | RECOVERING STRANDED DATA - A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile memory (NVM) in a home node over a sideband interface and writing the data to a target memory region, wherein the target memory region is in a fail-over node. | 2016-05-12 |
20160132414 | SIMULATION DEVICE AND DISTRIBUTION SIMULATION SYSTEM - A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus. | 2016-05-12 |
20160132415 | TESTING INSECURE COMPUTING ENVIRONMENTS USING RANDOM DATA SETS GENERATED FROM CHARACTERIZATIONS OF REAL DATA SETS - The disclosed embodiments provide a system that facilitates testing of an insecure computing environment. During operation, the system obtains a real data set comprising a set of data strings. Next, the system determines a set of frequency distributions associated with the set of data strings. The system then generates a test data set from the real data set, wherein the test data set comprises a set of random data strings that conforms to the set of frequency distributions. Finally, the system tests the insecure computing environment using the test data set. | 2016-05-12 |
20160132416 | COMMUNICATION MONITORING SYSTEM - A communication monitoring system includes a plurality of detecting portions each provided at a connector at an end of a communication cable or at a relay connector to be connected to the connector to branch, extract and output a portion of a signal transmitted through the communication cable, and a monitoring unit configured to monitor an existence of information communication through each of the communication cables provided with the detecting portions based on an output from the plurality of detecting portions. | 2016-05-12 |
20160132417 | VERIFYING A GRAPH-BASED COHERENCY VERIFICATION TOOL - Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor caches, the graph-based coherency verification tool using trace files as input for verifying memory ordering rules of a given processor architecture for accesses to the caches, wherein nodes in a graph represent memory accesses and edges represent dependencies between them. The verifying includes (i) providing a specification of a test case for a self-checking tool, the test case comprising a sequence of statements in a high-level description language format, representing memory access events and system events; and (ii) generating trace files with the self-checking tool for the graph-based coherency verification tool by producing permutations of trace events, which are defined by the sequence of statements of the test case. | 2016-05-12 |
20160132418 | OPTIMIZED GENERATION OF DATA FOR SOFTWARE PROBLEM ANALYSIS - A computer optimizes the prospective generation of data used for analysis of a software problem. The computer generates data in accordance with data generation parameters and a software problem is analyzed with reference to the data so generated. The problem analysis produces a report that details specifics of the software problem, the data that was available for analysis, a flag to indicate success or failure of the analysis to identify a root cause, and information about whether the data supplied was insufficient, sufficient, or superfluous with respect to identifying a root cause of the software problem. The method then uses the analysis report to modify the data generation parameters, thereby iteratively optimizing the data that are generated for analysis of subsequent software problems. | 2016-05-12 |
20160132419 | OPTIMIZED GENERATION OF DATA FOR SOFTWARE PROBLEM ANALYSIS - A computer optimizes the prospective generation of data used for analysis of a software problem. The computer generates data in accordance with data generation parameters and a software problem is analyzed with reference to the data so generated. The problem analysis produces a report that details specifics of the software problem, the data that was available for analysis, a flag to indicate success or failure of the analysis to identify a root cause, and information about whether the data supplied was insufficient, sufficient, or superfluous with respect to identifying a root cause of the software problem. The method then uses the analysis report to modify the data generation parameters, thereby iteratively optimizing the data that are generated for analysis of subsequent software problems. | 2016-05-12 |
20160132420 | BACKUP METHOD, PRE-TESTING METHOD FOR ENVIRONMENT UPDATING AND SYSTEM THEREOF - A pre-testing method adapted for environment updating is illustrated. The pre-testing method comprises following steps: while detecting an environment updating process should be performed to an operating system environment, determining whether an environment test should be executed; while the environment test is executed, selecting a plurality of pieces of system and software information of the operating system environment, wherein the system and software information of the operating system environment is extracted from the operating system environment; generating a virtual machine having a first clone environment according to the system and software information; performing the environment updating process to the first clone environment so as to cause the first clone environment to become a second clone environment of the virtual machine; and executing the environment test for the second clone environment. | 2016-05-12 |
20160132421 | ADAPTATION OF AUTOMATED TEST SCRIPTS - Embodiments provide a computerized method for adapting automating test scripts, said method including: utilizing at least one processor to execute computer code that performs the steps of: receiving, at an input device, an original test script created to test an application; utilizing the original test script to test, using the processor, a variant of the application; identifying, using the processor, failures in the original test script when the variant of the application is being tested; and modifying, using the processor, the original test script to overcome the identified failures. | 2016-05-12 |
20160132422 | SYSTEM AND METHOD FOR DETERMINING REQUIREMENTS FOR TESTING SOFTWARE - A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a method may include inspecting contents of a test case, including source code of the test case. The method may also include identifying at least one of: at least one characteristic of a test machine and at least one characteristic of a resource required to execute the test case correctly. The method may further include compiling a list of requirements for the test case to execute correctly based upon, at least in part, the at least one of the at least one characteristic of the test machine and the at least one characteristic of the resource. | 2016-05-12 |
20160132423 | SYSTEM AND METHOD FOR DETERMINING REQUIREMENTS FOR TESTING SOFTWARE - A computer-implemented method, computer program product, and system is provided for determining requirements for testing software. In an implementation, a method may include inspecting contents of a test case, including source code of the test case. The method may also include identifying at least one of: at least one characteristic of a test machine and at least one characteristic of a resource required to execute the test case correctly. The method may further include compiling a list of requirements for the test case to execute correctly based upon, at least in part, the at least one of the at least one characteristic of the test machine and the at least one characteristic of the resource. | 2016-05-12 |
20160132424 | SIMULATING SENSORS - Simulating sensors can include hooking an application associated with sensory data and associating the sensory data with an automation instruction. Simulating sensors can include providing the sensory data to a support device having an ability to modify the application and automatically causing the support device to simulate a sensory input using the sensory data by executing the automation instruction. | 2016-05-12 |
20160132425 | SYSTEM AND METHOD FOR EFFICIENT CREATION AND RECONCILIATION OF MACRO AND MICRO LEVEL TEST PLANS - A method includes creating a macro plan for a test project, creating a micro plan for the test project, wherein the micro plan and the macro plan are based on at least one common parameter, and reconciling the macro plan and the micro plan by identifying deviations between the macro plan and the micro plan based on the at least one common parameter. | 2016-05-12 |
20160132426 | AUTOMATED GENERATION OF SCRIPTED AND MANUAL TEST CASES - Systems and methods that provide manual test cases and scripted test cases automatically based on metadata included in a software application. In an embodiment, an application may include elements that generate an output file containing information corresponding to one or more forms with one or more fields in an application. The information may be utilized by a test device or application to automatically generate manual test cases, automated scripted test cases, or a combination of manual and automated test cases based on the information. In an embodiment, a manual test case may include a sequence of instructions in a natural language format. In an embodiment, an automated test case may be in a script language configured to interact with the application or an appropriate application emulator. | 2016-05-12 |
20160132427 | USER INTERFACE CONFORMANCE - Verifying user interface conformance can include deriving a conformance rule set based on desired user interface characteristics identified through an examination of mockup data for the user interface. That mockup data includes a visual representation of the desired characteristics. Conformance data can then be generated based on differences between the desired characteristics and actual characteristics. Those differences are identified by processing the conformance rule set against screen capture data of the user interface as produced by an application under test. The screen capture data includes a visual representation of the actual characteristics of the user interface. | 2016-05-12 |
20160132428 | ASSIGNING HOME MEMORY ADDRESSES TO FUNCTION CALL PARAMETERS - Embodiments are directed to assigning a home memory location for a function call parameter. A method may include determining whether a caller is configured to allocate a memory location for a parameter passed to a callee. The caller is a module that includes a function call to the callee and the callee is a function. The method may include inserting instructions in the callee to allocate a home memory location for the parameter in response to determining that the caller is not configured to allocate a memory location for the parameter. In addition, the method may include inserting instructions in the callee to set the memory location as a home location for the parameter in response to determining that the caller is configured to allocate a memory location for the parameter. | 2016-05-12 |
20160132429 | Method and Storage Device for Collecting Garbage Data - A method and a storage device for collecting garbage data, where the method includes separately recording a data volume of first data in each segment of a storage device at a current time and a variation of the first data in each segment of the storage device in a preset period of time before the current time; obtaining, by means of calculation, a predicted value of the first data according to the data volume of the first data in each segment and the variation of the first data in each segment; and determining, according to the predicted value of the first data in each segment, a segment whose garbage data needs to be collected. A segment that has more garbage data and whose garbage creating rate is lower is reclaimed preferentially. | 2016-05-12 |
20160132430 | Memory Control Circuit and Processor - A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry. | 2016-05-12 |
20160132431 | STORE CACHE FOR TRANSACTIONAL MEMORY - A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping. | 2016-05-12 |
20160132432 | Methods for Caching and Reading Data to be Programmed into a Storage Unit and Apparatuses Using the Same - A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected. | 2016-05-12 |
20160132433 | COMPUTER SYSTEM AND CONTROL METHOD - A computer system according to the present invention is composed of a server | 2016-05-12 |
20160132434 | STORE CACHE FOR TRANSACTIONAL MEMORY - A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping. | 2016-05-12 |
20160132435 | SPINLOCK RESOURCES PROCESSING - According to an example, in a spinlock processing method, a value of a spinlock cache variable may be read from a cache and the value of the spinlock cache variable may be written into a register. A determination may be made as to whether the value of the spinlock cache variable is an initial value. If yes, the value of the spinlock cache variable in the register may be updated. A determination may also be made as to whether the spinlock cache variable is accessed by a core after the value of the spinlock cache variable is written into the register. If yes, a value of a spinlock cache variable may be obtained from the cache. If no, the updated value of the spinlock cache variable may be written into the cache. Moreover, an access speed of the cache may be larger than an access speed of an L2 cache. | 2016-05-12 |
20160132436 | SYSTEM SUPPORTING MULTIPLE PARTITIONS WITH DIFFERING TRANSLATION FORMATS - A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor. | 2016-05-12 |
20160132437 | PROCESSOR EXTENSIONS FOR EXECUTION OF SECURE EMBEDDED CONTAINERS - Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for manageability function is provided, e.g., for UMPC environments or otherwise where utilizing a dedicated processor or microcontroller for manageability is inappropriate or impractical. For example, in an embodiment, an OS (Operating System) or VMM (Virtual Machine Manager) Independent (generally referred to herein as “OI”) architecture involves creating one or more containers on a processor by dynamically partitioning resources (such as processor cycles, memory, devices) between the HOST OS/VMM and the OI container. Other embodiments are also described and claimed. | 2016-05-12 |
20160132438 | PROCESSING DEVICE, PROCESSING METHOD, STORAGE MEDIUM, AND ELECTRONIC MUSICAL INSTRUMENT - A processing device includes: a plurality of processing units that perform processes in accordance with data items read from a memory; a bus that connects the memory to the plurality of processing units; and a traffic monitor that monitors traffic on the bus with respect to the plurality of processing units, and when the traffic for one of the processing units that has been assigned access rights to the memory exceeds or reaches a prescribed upper limit, outputs a signal to the one of the processing units so as to reduce or suspend the traffic for the one of the processing units. | 2016-05-12 |
20160132439 | EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM - An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket. | 2016-05-12 |
20160132440 | MULTI-CHANNEL I2S TRANSMIT CONTROL SYSTEM AND METHOD - A serial peripheral interface is configurable to operate in a I | 2016-05-12 |
20160132441 | HETEROGENEOUS MULTIPROCESSOR PLATFORM TARGETING PROGRAMMABLE INTEGRATED CIRCUITS - An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller. | 2016-05-12 |
20160132442 | DATA WRITING SYSTEM AND METHOD FOR DMA - A data writing system is provided. A processing unit includes at least one core processor. The dynamic random access memory (DRAM) includes a user buffer storing data to be written to a storage device, a buffer cache and a direct memory access (DMA) buffer. The processing unit executes a plurality of write transactions for moving a portion of the data from the user buffer of the DRAM to the storage device via a first write path, and the remainder of the data from the user buffer of the DRAM to the storage device via a second write path. The first write path passes through the buffer cache of the DRAM, and the second write path does not pass through the buffer cache of the DRAM. | 2016-05-12 |
20160132443 | TRACKING VIRTUAL MACHINE MEMORY MODIFIED BY A SINGLE ROOT I/O VIRTUALIZATION (SR-IOV) DEVICE - Techniques for tracking, by a host system, virtual machine (VM) memory modified by a physical input/output (I/O) device that supports I/O virtualization are provided. In one embodiment, a hypervisor of the host system can receive a hardware interrupt from the physical I/O device, where the hardware interrupt indicates that a virtual function (VF) of the physical I/O device has completed a direct memory access (DMA) write to a guest memory space of a VM running on the host system. In response to the hardware interrupt, the hypervisor can invoke a function implemented by a physical function (PF) driver of the physical I/O device, where the function is configured to inspect the VF's state in order to identify memory portions modified by the DMA write. The hypervisor can then mark, in a hypervisor-level page table, one or more memory pages corresponding to the identified memory portions as dirty pages. | 2016-05-12 |
20160132444 | UNIVERSAL ETHERNET SOLUTION - A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, providing a single hardware platform usable to build different automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc. The monolithic integrated circuit includes: one application processor core operable to execute an industrial application and Ethernet connectivity/management code, including standard Ethernet connectivity/management code and industrial Ethernet connectivity/management code; a real time processor configured to support a plurality of industrial Ethernet data link layers; an interface configured to be coupled to an external non volatile memory from which the at least one application processor is configured for execute in place processing; and an on-chip RAM having a capacity sufficient to eliminate the need for external RAM in execution by the at least one application processor core of an operating system, the industrial application, and the Ethernet connectivity/management code. | 2016-05-12 |
20160132445 | PERIPHERAL REGISTER PARAMETER REFRESHING - Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register. | 2016-05-12 |
20160132446 | NETWORK SUBSCRIBER - A network subscriber comprises a plurality of individual functional units, each individual functional unit comprising an application interface. The network subscriber further comprises a network subscriber comprises at least a shared functional unit, a first interface for establishing a physical connection and a second interface for establishing a further physical connection. | 2016-05-12 |
20160132447 | AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE - In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed. | 2016-05-12 |
20160132448 | HUB MODULE WITH A SINGLE BRIDGE SHARED AMONG MULTIPLE CONNECTION PORTS TO SUPPORT ROLE REVERSAL - An apparatus includes a multiport hub, a single bridge configured to communicatively couple together a plurality of hosts and to emulate a slave device to each such host, and a plurality of connection port. The apparatus further includes a configurable data path network coupled to the multiport hub, the single bridge, and the plurality of connection ports. The configurable data path network is configured to selectively provide for a connection port for which a host is detected, data communications through the single bridge between the multiport hub and the connection port, and for a connection port for which no host is detected, data communications between the multiport hub and the connection port that bypass the single bridge. Corresponding methods are also so disclosed. | 2016-05-12 |
20160132449 | NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER - A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller. | 2016-05-12 |
20160132450 | NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER - A network interface controller includes a media access controller connected to receive an in-band packet and further connected to receive a sideband packet. The network interface controller includes a host adapter that includes a receive route connected to receive the in-band packet and the sideband packet from the media access controller, and further connected to transmit the in-band packet to a host. The network interface controller includes a sideband port controller comprising a sideband receive buffer. The host adapter further includes a first receive buffer to store the in-band packet and to store the sideband packet. The host adapter further includes an arbiter connected to allow, at a time, the in-band packet to advance from the first receive buffer along the receive route towards the host and further connected to allow, at a different time, the sideband packet to advance to the sideband receive buffer of the sideband port controller. | 2016-05-12 |
20160132451 | SYSTEM ON CHIP HAVING SEMAPHORE FUNCTION AND METHOD FOR IMPLEMENTING SEMAPHORE FUNCTION - A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result. | 2016-05-12 |
20160132452 | PCI EXPRESS FABRIC ROUTING FOR A FULLY-CONNECTED MESH TOPOLOGY - A PCIe Fabric that includes an IO tier switch, hub tier switches, and a target device connected to one of the hub tier switches. The IO tier switch is configured to receive a TLP from a client, make a determination that an address in the TLP is not associated with any multicast address range in the first IO tier switch and is not associated with any downstream port in the first IO tier switch, and, based on the determinations, route the TLP to the first hub tier switch via a upstream port on the IO tier switch. The hub tier switch is configured to make a determination that the TLP is associated with a multicast group, and, based on the determination, generate a rewritten TLP and route the rewritten TLP to a target device via a downstream port on the hub tier switch. | 2016-05-12 |
20160132453 | Selectively Transparent Bridge for Peripheral Component Interconnect Express Bus System - A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers. | 2016-05-12 |
20160132454 | ADAPTER CARD FOR THIN COMPUTING DEVICES - A system and method for facilitating communication. The system includes an adapter card and a first motherboard interface for coupling the adapter card to a motherboard. In some embodiments, the first motherboard interface is configured to transmit data between the adapter card and the motherboard. In some embodiments, the first motherboard interface is configured to supply power from the motherboard to the adapter card. The system further includes a second motherboard interface configured for communicative coupling of a component. In some embodiments, the adapter card comprises a portion configured for structurally coupling of the adapter card to the second motherboard interface. The system further includes an external interface for coupling the adapter card to an external environment of the system associated with the motherboard, where the external interface is configured to transmit data between the external environment of the system and the adapter card. | 2016-05-12 |
20160132455 | CONTROL METHOD APPLIED TO OPERATING-MODE FINITE-STATE-MACHINE AND COMPUTER READABLE MEDIA - A control method applied to an Operating-Mode Finite-State-Machine (OPFSM) arranged for deciding a behavior of a first port of an apparatus includes: controlling the OPFSM to enter a second local state from a first local state and controlling the first port to send a signal with a wakeup pattern to a link partner of the first port when the state of the OPFSM is the first local state, and a wakeup request bit is a first local value. | 2016-05-12 |
20160132456 | INTEGRATED ADAPTER FOR THIN COMPUTING DEVICES - A system and method for facilitating communication. The system includes an adapter card and a motherboard interface for coupling the adapter card to a motherboard. In some embodiments, the adapter card comprises an optical transmitter. In some embodiments, the motherboard interface is configured to transmit data between the adapter card and the motherboard. In some embodiments, the motherboard interface is configured to supply power from the motherboard to the adapter card. In some embodiments, the motherboard interface is a mini PCI express interface. The system may further comprise an external interface for coupling the adapter card to an external environment of a system associated with the motherboard. In some embodiments, the external interface is configured to transmit data between the external environment of the system and the adapter card. | 2016-05-12 |
20160132457 | INTERCONNECT ASSEMBLY - An interconnect assembly is disclosed herein. An example includes a cable including a first end and a cable head at the first end of the cable. The example also includes a wireless data transceiver disposed in the cable head to wirelessly communicate data to and from a device and a wireless power coupler disposed in the cable head to wirelessly supply power from the device to the wireless data transceiver. | 2016-05-12 |
20160132458 | APPLICATION MODULE PROVIDED WITH STATIONARY INTERFACE - Provided is an application module provided with a stationary interface, and more particularly, an application module performing functions of a battery management system (BMS), which transceives data from an application module data control device or calls a service module included in a basic program (basic software (BSW) to increase compatibility regarding function execution among one or more modules. | 2016-05-12 |
20160132459 | In-Situ Die-to-Die Impedance Estimation for High-Speed Serial Links - A receiver includes an analog-to-digital converter (ADC) module that receives a test signal via a transmission channel and provides a time domain representation of the test signal as received by the receiver, and a processor that determines a time domain representation of an impedance of the transmission channel based on the time domain representation of the test signal. | 2016-05-12 |
20160132460 | EXTERNAL MEMORY CONTROLLER NODE - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 2016-05-12 |
20160132461 | HIGH PERFORMANCE IMPLEMENTATION OF THE FFT BUTTERFLY COMPUTATION - This invention is a FFT butterfly circuit. This circuit includes four temporary data registers connected to three memories. The three memories include read/write X and Y memories and a read only twiddle coefficient memory. A multiplier-accumulator forms a product and accumulates the product with one of two accumulator registers. A register file with plural registers is loaded from one of the accumulator registers or the fourth temporary data register. An adder/subtracter forms a selected one of a sum of registers or a difference of registers. A write buffer with two buffers temporarily stores data from the adder/subtracter before storage in the first or second memory. The X and Y memories must be read/write but the twiddle memory may be read only. | 2016-05-12 |
20160132462 | Methods And Systems For Calculating Uncertainty - Disclosed are methods and systems for performing uncertainty calculations. For example, a first numeric value and an error range associated with the first numeric value is converted by a processor into a dual number, which is then converted into an input chordal, where the input chordal is both a numeric and a geometric form of the dual number. A chordal calculation is performed using the input chordal to create an output chordal, and the processor then converts the output chordal to an output numeric value that comprises both a number and an error range associated with that number. | 2016-05-12 |
20160132463 | COMPUTING APPARATUS, COMPUTING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a computing apparatus includes a memory, and a processor. The memory stores N first vectors in a d-dimensional binary vector space consisting of binary values. The processor acquires a second vector in the d-dimensional binary vector space. The processor extracts M first vectors having a distance from the second vector satisfying a first condition out of the N first vectors, and calculate a distribution of distances of the M first vectors from the second vector. The processor acquires a first kernel function per a first distance between the M first vectors and the second vector in a first range. The processor generates a second kernel function based on the distribution and the first kernel functions. The processor calculates an occurrence probability of the second vector in the N first vectors based on the second kernel function. | 2016-05-12 |
20160132464 | SYSTEM AND METHOD FOR RE-MARGINATING DISPLAY CONTENT - A method and system for re-marginating content displayed on a display screen of a computing device when upon receiving indication of an object superposed on the display screen content, a “handedness” preference of the reader/observer can be determined. In one embodiment, the content comprises display of one page in a series of digitally constructed pages. A keep out margin is calculated based on position of the object. Content is then re-flowed or line-wrapped about that keep out margin, to counteract any obscuration of displayed content. The line-wrapping of the content around the keep out margin is accomplished while maintaining a plurality of text attributes of the content. The line-wrapping forces reconstruction of a next one of the series of pages for display. | 2016-05-12 |
20160132465 | METHOD AND APPARATUS FOR SELECTIVE VISUAL FORMATTING OF AN ELECTRONIC DOCUMENT - A method for managing display of electronic documents is described. A user interface is generated for a visual style set of visual styles that affect display of electronic document content. A visual style of the visual style set comprises a style element set of style elements. A lock status for a style element of the style element set is received via the user interface. The lock status indicates whether the style element is editable or non-editable by a user of an electronic document associated with the visual style set. The visual style set is stored with the lock status for the style element. | 2016-05-12 |
20160132466 | Organizational Chart Exporting with Layout Preview and Customization - Techniques are described for exporting organizational charts being presented inside a browser window. The system can present an export canvas that identifies the portion of the organizational chart that is to be exported. In some embodiments, the export canvas can be automatically adjusted to prevent collisions with tiles within the organizational chart. In some examples, the export canvas can be presented on a different layer than the organizational chart, thus allowing the export canvas to move around freely without disrupting the underlying organizational chart. | 2016-05-12 |
20160132467 | DETERMINATION OF ENCODING BASED ON PERCEIVED CODE POINT CLASSES - A method, a computer program product, and a computer system for determination of encoding based on received code point classes are provided. The computer implemented method includes transferring data in a text form. The computer implemented method includes, in response to determining that decoding the data in text form passes, transferring some or all of the data in a binary form. The computer implemented method includes calculating code point class proportions for the data in the text form and the data in the binary form and determining a best form for transferring the data, based on comparison of the code point class proportions. | 2016-05-12 |
20160132468 | USER-INTERFACE REVIEW METHOD, DEVICE, AND PROGRAM - A user-interface review method includes: acquiring information regarding the content of an operation performed on a screen by a user and a change in the screen caused in response to the operation; and reviewing whether or not the information regarding the content of the operation and the change in the screen caused in response to the operation conforms to a review rule that contains a user-interface review criterion. | 2016-05-12 |