19th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100117080 | SEMICONDUCTOR TEST PAD STRUCTURES - A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer. | 2010-05-13 |
20100117081 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit device for driving an LCD, COG chip packaging is performed. To achieve this, an elongate and relatively thick gold bump electrode is formed over an aluminum-based pad having a relatively small area. In a wafer probe test performed after formation of the gold bump electrode, a cantilever type probe needle having gold as a main component and having an almost perpendicularly bent tip portion is used. The diameter of this probe needle in the vicinity of its tip is usually almost the same as the width of the gold bump electrode. This makes it difficult to perform the wafer probe test stably. To counteract this, a plurality of bump electrode rows for outputting a display device drive signal are formed such that the width of inner bump electrodes is made greater than the width of outer bump electrodes. | 2010-05-13 |
20100117082 | SEMICONDUCTOR DEVICE CAPABLE OF COMPENSATING FOR ELECTRICAL CHARACTERISTIC VARIATION OF TRANSISTOR ARRAY - A semiconductor device capable of compensating for an electrical characteristic variation of a transistor array is provided. The semiconductor device includes an N-well region and a transistor array spaced from the N-well region and including a plurality of transistors. A characteristic of each of the transistors is adjusted to enable the transistors to have a same electrical characteristic. | 2010-05-13 |
20100117083 | SEMICONDUCTOR DEVICE - Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex. | 2010-05-13 |
20100117084 | METHOD FOR SORTING AND ACQUIRING SEMICONDUCTOR ELEMENT, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for sorting and acquiring a semiconductor element, including: disposing a plurality of semiconductor elements in an effective section in a semiconductor substrate; disposing a standard semiconductor element outside of the effective section in the semiconductor substrate; forming a bump in each of the plurality of the semiconductor elements and in the standard semiconductor element; performing a test on the plurality of the semiconductor elements in the effective section; forming a location map using the standard semiconductor element as a base point; and picking up the semiconductor elements determined as non-defective in the test from the plurality of the semiconductor elements based on the location map. | 2010-05-13 |
20100117085 | THIN FILM TRANSISTOR AND METHOD FOR PREPARING THE SAME - The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide (ZnO series) electrode having one or more of Si, Mo, and W as a source electrode and a drain electrode, and a method of manufacturing the same. | 2010-05-13 |
20100117086 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer. | 2010-05-13 |
20100117087 | THIN FILM TRANSISTOR MATRIX DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a thin film transistor matrix device which includes forming a transparent insulating substrate, arranging a plurality of thin film transistors on the substrate in a matrix, arranging a plurality of picture element electrodes on the substrate in a matrix and connecting the picture element electrodes to sources of the thin film transistors. The method also includes forming a plurality of bus lines for commonly connecting gates or drains of the thin film transistors, forming a plurality of bus line terminals on the ends of the bus lines, respectively, with each bus line terminal being provided for each bus line, and forming one connection line on the substrate in a region outer of plurality of the bus line terminals and commonly connecting the plurality of bus lines. The method further includes the step of electrically disconnecting the bus lines from the connection line by laser melting. | 2010-05-13 |
20100117088 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor (TFT) substrate having an improved wire structure without an under-cut phenomenon that may occur during formation of a gate wire having a double-layered structure and a method of manufacturing the same are provided, where the method includes forming a first metal layer made of at least one low resistance material selected from the group consisting of Al, AlNd, Cu, and Ag, forming a second metal layer made of at least one heat-resistant, etch-resistant material selected from the group consisting of Cr, CrNx, Ti, Mo, and MoW on the first metal layer, forming an etch mask on the second metal layer, sequentially etching the second metal layer and the first metal layer using the etch mask, and forming a second metal layer pattern and a first metal layer pattern, respectively, and selectively re-etching the second metal layer pattern using the etch mask to make a width of the second metal layer pattern smaller than or substantially equal to a width of the first metal layer pattern, and completing a gate wire. | 2010-05-13 |
20100117089 | LIQUID CRYSTAL DISPLAY DEVICE HAVING DRIVE CIRCUIT AND FABRICATING METHOD THEREOF - A fabricating method of an array substrate for a liquid crystal display device including forming a polycrystalline silicon film on a substrate having a display region and a peripheral region, the polycrystalline silicon film having grains of square shape, forming a first active layer in the display region and a second active layer in the peripheral region by etching the polycrystalline silicon film, forming a first gate electrode over the first active layer, a second gate electrode over the second active layer and a gate line connected to the first gate electrode, and forming first source and drain electrodes connected to the first active layer, second source and drain electrodes connected to the second active layer and data line connected to the first source electrode. Further, the second gate electrode overlaps the first active layer to form a first channel region, and the first channel region is formed inside one of the grains. | 2010-05-13 |
20100117090 | ARRAY SUBSTRATE INCLUDING THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole. | 2010-05-13 |
20100117091 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device having thin film transistors which can acquire an appropriate ON current and an appropriate OFF current and a manufacturing method thereof are provided. A display device includes: a transparent substrate; and a plurality of thin film transistors which are formed on the transparent substrate. Each thin film transistor includes a gate electrode which is stacked on the transparent substrate, a source electrode and a drain electrode which are stacked over the gate electrode, a first semiconductor film which is stacked between the gate electrode, and the source electrode and the drain electrode so as to control an electric current which flows between the source electrode and the drain electrode, an insulation film which is stacked on the first semiconductor film in a contacting manner in a state where a source-electrode-side edge portion and a drain-electrode-side edge portion of the first semiconductor film are exposed, and a second semiconductor film and a third semiconductor film which are stacked between the source-electrode-side edge portion and the source electrode T as well as between the drain-electrode-side edge portion and the drain electrode. The third semiconductor film is connected with the source electrode and the drain electrode by an ohmic contact. The second semiconductor film is formed below the third semiconductor film with resistance higher than resistance of the third semiconductor film. | 2010-05-13 |
20100117092 | SEMICONDUCTOR DEVICE - In a conventional analog buffer circuit composed of polycrystalline semiconductor TFTs, a variation in the output is large. Thus, a measure such as to provide a correction circuit has been taken. However, there has been such a problem that a circuit and driver operation are complicated. Therefore, a gate length and a gate width of a TFT composing an analog buffer circuit is set to be larger. Also, a multi-gate structure is adopted thereto. In addition, the arrangement of channel regions is devised. Thus, the analog buffer circuit having a small variation is obtained without using a correction circuit, and a semiconductor device having a small variation can be provided. | 2010-05-13 |
20100117093 | LASER IRRADIATION DEVICE, PATTERNING METHOD AND METHOD OF FABRICATING ORGANIC LIGHT EMITTING DISPLAY (OLED) USING THE PATTERNING METHOD - In a laser irradiation device, a patterning method and a method of fabricating an Organic Light Emitting Display (OLED) using the same. The laser irradiation device includes a light source, a mask, a projection lens, and a Fresnel lens formed at a predetermined portion of the mask to change an optical path. When an organic layer pattern is formed using the laser irradiation device, laser radiation is irradiated onto a region of an organic layer, which is to be cut, and the laser radiation is appropriately irradiated onto a region of the organic layer, which is to be separated from a donor substrate. The laser radiation irradiated onto an edge of the organic layer pattern has a laser energy density greater than that of the laser radiation irradiated onto other portions of the organic layer pattern. As a result, it is possible to form a uniform organic layer pattern and reduce damage of the organic layer. | 2010-05-13 |
20100117094 | GALLIUM NITRIDE EPITAXIAL CRYSTAL, METHOD FOR PRODUCTION THEREOF, AND FIELD EFFECT TRANSISTOR - The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer. | 2010-05-13 |
20100117095 | GaN-Based Device Cascoded with an Integrated FET/Schottky Diode Device - A power semiconductor device is provided that includes a depletion mode (normally ON) main switching device cascoded with a higher speed switching device, resulting in an enhancement mode (normally OFF) FET device for switching power applications. The main switching device comprises a depletion mode GaN-based HEMT (High Electron Mobility Transistor) FET that does not include an intrinsic body diode. In one or more embodiments, the higher speed switching device comprises a high speed FET semiconductor switch arranged or connected in parallel with a Schottky diode. The high speed FET semiconductor switch may comprise a Si FET, GaN FET or any other type of FET which possesses higher speed switching capabilities and a lower voltage than that of the GaN-based HEMT FET. In some embodiments, the GaN-based HEMT FET and the higher speed switching device (i.e., the FET and Schottky diode) may be monolithically integrated on the same substrate. | 2010-05-13 |
20100117096 | VERTICAL STRUCTURE SEMICONDUCTOR DEVICES WITH IMPROVED LIGHT OUTPUT - The invention provides a reliable technique to fabricate a new vertical structure compound semiconductor devices with highly improved light output. An exemplary embodiment of a method of fabricating light emitting semiconductor devices comprising the steps of forming a light emitting layer, and forming an undulated surface over light emitting layer to improve light output. In one embodiment, the method further comprises the step of forming a lens over the undulated surface of each of the semiconductor devices. In one embodiment, the method of claim further comprises the steps of forming a contact pad over the semiconductor structure to contact with the light emitting layer, and packaging each of the semiconductor devices in a package including an upper lead frame and lower lead frame. Advantages of the invention include an improved technique for fabricating semiconductor devices with great yield, reliability and light output. | 2010-05-13 |
20100117097 | SILICON CARBIDE SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device ( | 2010-05-13 |
20100117098 | SCHOTTKY ELECTRODE FOR DIAMOND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a Schottky electrode in a diamond semiconductor, which has a good adhesion properties to diamonds, has a contacting surface which does not become peeled due to an irregularity in an external mechanical pressure, does not cause a reduction in yield in a diode forming process and does not cause deterioration in current-voltage characteristics, and a method of manufacturing the Schottky electrode. | 2010-05-13 |
20100117099 | Multi-chip light emitting diode modules - A multi-chip lighting module is disclosed for maximizing luminous flux output and thermal management. In one embodiment, a multi-chip module device comprises a substantially thermally dissipative substrate with a dark insulating layer deposited on a surface of the substrate. A plurality of light emitting devices is also provided. An electrically conductive layer is applied to a surface of the substrate, with the conductive layer comprising a plurality of chip carrier parts each having a surface for carrying at least one of the light emitting devices. Each light emitting device has a first and a second electrical terminal. A reflective layer is also provided that at least partially covers the conductive layer. | 2010-05-13 |
20100117100 | LIGHT-EMITTING MODULE AND ILLUMINATION DEVICE - There is provided a light-emitting module which makes it difficult to sense glare and which suppresses the temperature rise of light-emitting diode chips and has a cost advantage. The light-emitting module is provided with a base body formed with a non-metallic member having a thermal conductivity of 1 W/mk or less. In the base body, a plurality of LED chips are spaced 10 to 30 mm apart from each other, and their junction temperature when they are normally lit is preferably set at 90° C. or less. A translucent sealing member covering an area between the adjacent light-emitting diode chips is provided. | 2010-05-13 |
20100117101 | AC LIGHT EMITTING DIODE - Disclosed herein is an AC light emitting diode. The light emitting diode comprises a plurality of light emitting cells two-dimensionally arranged on a single substrate. Wires electrically connect the light emitting cells to one another to thereby form a serial array of the light emitting cells. Further, the light emitting cells are spaced apart from one another by distances within a range of 10 to 30 μm, and the serial array is operated while connected to an AC power source. Accordingly, the excellent operating characteristics and light output power can be secured in an AC light emitting diode with a limited size. | 2010-05-13 |
20100117102 | LIGHT EMITTING DIODES AND BACKLIGHT UNIT HAVING THE SAME - The LED assembly has an LED chip, 2 via holes and 2 metal electrodes. The LED chip is attached to a front surface of the substrate. 2 via holes penetrate the front surface and a rear surface of the substrate opposite to the front surface, and 2 metal electrodes extend from the front surface to the rear surface through the via holes, respectively. The LED chip has an N-electrode and a P-electrode. The N-electrode and the P-electrode are electrically connected to the metal electrodes via wires, respectively, and the metal electrodes have exposed portions on the rear surface, respectively. | 2010-05-13 |
20100117103 | Light-Emitting Module and Method of Manufacture for a Light-Emitting Module - A light-emitting module includes a supporting element, a number of optoelectronic semiconductor components mounted on the supporting element for the generation of electromagnetic radiation, and a metallic connecting layer by means of which the optoelectronic semiconductor components are supplied with operating voltage. An insulation layer is arranged in a region of the optoelectronic semiconductor components between the supporting element and the metallic connecting layer. The metallic connecting layer forms a light shade for the optoelectronic semiconductor components, so that the electromagnetic radiation is only emitted in a specified direction. | 2010-05-13 |
20100117104 | INTEGRATED SEMICONDUCTOR OPTICAL DEVICE AND OPTICAL APPARATUS USING THE SAME - In an integrated semiconductor optical device, a first cladding layer is made of a first conductivity type semiconductor. A first active layer for forming a first semiconductor optical device is provided on the first cladding layer in a first area of a principal surface of a substrate. A second active layer for forming a second semiconductor optical device is provided on the first cladding layer in a second area of the principal surface. A second cladding layer made of a second conductivity type semiconductor is provided on the second active layer. A third cladding layer made of a first conductivity type semiconductor is provided on the first active layer. A tunnel junction region is provided between the first active layer and the third cladding layer. The first active layer is coupled to the second active layer by butt joint. The second and third cladding layers form a p-n junction. | 2010-05-13 |
20100117105 | LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a light-emitting diode and a method for fabricating the same. The ternary or quaternary Group III-V nitride semiconductor light-emitting diode comprises a buffer layer doped with conductive impurities and developed with an orientation inclined toward the axis [1122] at an angle of 40° to 70° with respect to the axis [0001] on a [0001]-oriented substrate, a light-emitting layer arranged on the buffer layer, a first electrode arranged under the buffer layer, and a second electrode arranged on the light-emitting layer, wherein the light-emitting layer includes a first clad layer arranged on the buffer layer, an activation layer arranged on the first clad layer and a second clad layer arranged on the activation layer. According to the semiconductor light-emitting diode, the light-emitting layer is formed on the substrate with an orientation inclined toward the axis [1122] at an angle of 40° to 70° with respect to the axis [0001], and compositions of Group III-V and Group II-VI compounds constituting the first and second clad layers are controlled. As a result, it is possible to offset the stresses applied to the activation layer and prevent spontaneous polarization. As a result, the light-emitting diode can exhibit improved light efficiency. | 2010-05-13 |
20100117106 | LED WITH LIGHT-CONVERSION LAYER - A lighting apparatus includes a light-emitting diode (LED). A light-conversion layer having multiple non-overlapping regions overlies the light-emitting diode. The light-conversion layer includes at least one first region and at least one second region. In the lighting apparatus, the light-emitting diode is configured to emit light of a first color, the at least one first region is substantially transparent to light of the first color, and the at least one second region converts light of the first color to light of a second color. In an embodiment, the light-conversion layer is configured such that the lighting apparatus provides substantially uniform light of a third color. In some embodiments, the second region includes a phosphor-containing material, and the first region includes silicone or epoxy. In an example, the lighting apparatus uses a blue LED in conjunction with a yellow phosphor material to produce white light. | 2010-05-13 |
20100117107 | ELECTRICAL CURRENT DISTRIBUTION IN LIGHT EMITTING DEVICES - A light emitting device is disclosed that has a plurality of epitaxial layers including an active layer, at least one of a reflective layer and an ohmic contact on a first side of the epitaxial layers; and a layer of a conductive metal on a second side of the epitaxial layers and having a light emitting surface. A terminal is on the light emitting surface, the terminal comprising an array for diffusing electrical current and minimizing its effect on light output. The array may have a bonding pad, an outer portion, and a joining portion connecting the bonding pad and the outer portion; the outer portion and the joining portion being for current dissipation. | 2010-05-13 |
20100117108 | USES OF SELF-ORGANIZED NEEDLE-TYPE NANOSTRUCTURES - The invention relates to processes for the production and elements (components) with a nanostructure ( | 2010-05-13 |
20100117109 | Light emitting element - A light emitting element includes a semiconductor stacked structure including a first semiconductor layer of first conductivity type, a second semiconductor layer of second conductivity type different from the first conductivity type and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer. The light emitting element further includes a plurality of convex portions formed on one surface of the semiconductor stacked structure, and an embedded part for transmitting a light emitted from the active layer and reducing stress generated in the plurality of convex portions, the embedded part being formed between two adjacent convex portions of the plurality of convex portions. | 2010-05-13 |
20100117110 | Photosensitive Quantum Dot, Composition Comprising the Same and Method of Forming Quantum Dot-Containing Pattern Using the Composition - A photosensitive quantum dot including a quantum dot, and a plurality of photosensitive moieties that are bound to a surface of the quantum dot, wherein each of the photosensitive moieties includes silicon (Si) and a photosensitive functional group. Also disclosed are a composition for forming a quantum dot-containing pattern, where the composition includes the photosensitive quantum dot, and a method of forming a quantum dot-containing pattern using the composition. | 2010-05-13 |
20100117111 | Optoelectronic Component and Method for the Manufacture of a Plurality of Optoelectronic Components - An optoelectronic component with a semiconductor body includes an active region suitable for generating radiation, and two electrical contacts arranged on the semiconductor body. The contacts are electrically connected to the active region. The contacts each have a connecting face that faces away from the semiconductor body. The contact faces are located on a connection side of the component and a side of the component that is different from the connection side is mirror-coated. A method for the manufacture of multiple components of this sort is also disclosed. | 2010-05-13 |
20100117112 | LIGHT-EMITTING ELEMENT AND DEVICE - A light-emitting element used for display devices and illuminating devices has been formed on a flat substrate, and therefore, when the size of such devices is increased, manufacturing apparatuses also have to be enlarged. Also, a problem involved has been that even a failure of one light-emitting element causes the entire device to fail, making improvement of production yield difficult. To solve the above problems, in the present invention, light-emitting elements are formed as linear elements, and the linear elements are combined to form a plane light-emitting device. This enables the light-emitting device to be produced by selecting only linear light-emitting elements of good quality, and enlargement of apparatuses and enhancement of production yield can be expected. | 2010-05-13 |
20100117113 | LIGHT EMITTING DIODE AND LIGHT SOURCE MODULE HAVING SAME - An exemplary light emitting diode includes a substrate, a metal material and a light emitting diode chip. The substrate has a first surface and a first through hole defined in the first surface. The first through hole is filled with the metal material. The light emitting diode chip is mounted on the first surface contacting the metal material in the first through hole. | 2010-05-13 |
20100117114 | SEMICONDUCTOR LIGHT-EMITTING APPARATUS AND METHOD OF FABRICATING THE SAME - A light-emitting apparatus has a light-emitting device and a supporting board. The light-emitting device has a pair of n-electrodes with a p-electrode therebetween, on the same plane. The supporting board includes an insulating substrate on which positive and negative electrodes are formed, opposing to the p- and n-electrodes of the light-emitting device, respectively. Bonding members bond the p- and n-electrodes with the positive and negative electrodes, respectively. The positive electrode on the supporting board is formed within the width region of the p-electrode and narrower in width than the width of the p-electrode, in a cross-section along a line extending through the pair of n-electrodes. The negative electrodes oppose to the n-electrodes, respectively, with the same widths, or with that side face of each of the negative electrodes which faces the positive electrode being retracted outwardly from that side face of each of the n-electrodes which faces the p-electrode. | 2010-05-13 |
20100117115 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND SEMICONDUCTOR LIGHT EMITTING ELEMENT - A method includes steps of: sequentially growing a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type on a growth substrate to form a layered structure; separating the substrate from the layered structure to expose the first layer; performing wet etching on an exposed surface to form defect depressions; forming an insulating layer on the exposed surface; polishing the insulating layer and the first layer to flatten the surface of the first layer; and performing wet etching on the surface of the first layer to form protrusions deriving from a crystal structure. | 2010-05-13 |
20100117116 | INTEGRATED CIRCUIT ARRANGEMENT WITH SHOCKLEY DIODE OR THYRISTOR AND METHOD FOR PRODUCTION AND USE OF A THYRISTOR - An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element. | 2010-05-13 |
20100117117 | Vertical IGBT Device - According to one embodiment, a power semiconductor device comprises a semiconductor substrate. A transistor gate structure is arranged in a trench formed in the semiconductor substrate. A body region of a first conductivity type is arranged adjacent the transistor gate structure and a first highly-doped region of a second conductivity type is arranged in an upper portion of the body region. A drift zone of the second conductivity type is arranged below the body region and a second highly-doped region of the second conductivity type is arranged below the drift zone. An end-of-range irradiation region is arranged adjacent the transistor gate structure and has a plurality of vacancies. In some embodiments, at least some of the vacancies are occupied by metals. | 2010-05-13 |
20100117118 | High electron mobility heterojunction device - A method for providing a periodic table group III nitrides materials based heterojunction device comprising growing all layers therein by molecular beam epitaxy to result having a crystal defects concentration sufficiently small to allow electron mobilities in the sheet charge region to exceed 1100 cm2/volt-second. The invention includes the heterojunction device provided by this method. | 2010-05-13 |
20100117119 | SEMICONDUCTOR DEVICE HAVING HETERO JUNCTION - A semiconductor device | 2010-05-13 |
20100117120 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first well region | 2010-05-13 |
20100117121 | MIRRORED-GATE CELL FOR NON-VOLATILE MEMORY - A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate. | 2010-05-13 |
20100117122 | Optimized Device Isolation - A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions. | 2010-05-13 |
20100117123 | IMAGE SENSOR PIXEL HAVING A LATERAL DOPING PROFILE FORMED WITH INDIUM DOPING - An active pixel using a transfer gate that has a polysilicon gate doped with indium. The pixel includes a photosensitive element formed in a semiconductor substrate and an n-type floating node formed in the semiconductor substrate. An n-channel transfer transistor having a transfer gate is formed between the floating node and the photosensitive element. The pixel substrate has a laterally doping gradient doped with an indium dopant. | 2010-05-13 |
20100117124 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a semiconductor substrate; a source region formed in a top layer portion of the semiconductor substrate; a drain region formed in the top layer portion of the semiconductor substrate and spaced apart from the source region; a gate electrode formed on the semiconductor substrate and opposing to an interval between the source region and the drain region; a wiring formed on the semiconductor substrate and connected to the source region, the drain region, or the gate electrode; and a MEMS sensor disposed on the semiconductor substrate. The MEMS sensor includes: a thin film first electrode made of the same material as the gate electrode and formed in the same layer as the gate electrode; and a second electrode made of the same material as the wiring, formed in the same layer as the wiring, and spaced apart from the first electrode at a side opposite to the semiconductor substrate side of the first electrode. | 2010-05-13 |
20100117125 | SEMICONDUCTOR STRUCTURES INCORPORATING MULTIPLE CRYSTALLOGRAPHIC PLANES AND METHODS FOR FABRICATION THEREOF - A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure. | 2010-05-13 |
20100117126 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a substrate, a plurality of photodiodes arranged in the substrate in a depth direction of the substrate, a vertical readout gate electrode for reading signal charges in the photodiodes, the vertical readout gate electrode being embedded in the substrate such that the readout gate electrode extends in the depth direction of the substrate, a dark-current suppressing area which covers a bottom portion and a side surface of the readout gate electrode, the dark-current suppressing area including a first-conductivity-type semiconductor area having a uniform thickness on the side surface of the readout gate electrode, and a reading channel area disposed between the first-conductivity-type semiconductor area and the photodiodes, the reading channel area including a second-conductivity-type semiconductor area. | 2010-05-13 |
20100117127 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes a memory cell having a ferroelectric capacitor and a cell transistor connected in parallel. The memory cell includes: a first conductive layer provided above a substrate; a ferroelectric layer formed on a top surface of the first conductive layer; a second conductive layer formed on a top surface of the ferroelectric layer; and a stopper layer formed in the same layer as the ferroelectric layer. A selection ratio of the stopper layer under CMP is higher than that of the ferroelectric layer under CMP. | 2010-05-13 |
20100117128 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, an impurity diffusion layer that is formed at a surface portion of the semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate, a contact plug that penetrates the interlayer insulating film, has a top surface formed higher than a top surface of the interlayer insulating film, a region having a convex shape formed higher than the top surface of the interlayer insulating film, and contacts the impurity diffusion layer, a lower capacitor electrode film that is formed on the contact plug and a predetermined region of the interlayer insulating film, a ferroelectric film that is formed on the lower capacitor electrode film, and an upper capacitor electrode film that is formed on the ferroelectric film. | 2010-05-13 |
20100117129 | Scratch protection for direct contact sensors - In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed. The selected conductive material is employed for each metallization level between the surface and the active regions, including contacts and vias, landing pads, interconnects, capacitive electrodes, and electrostatic discharge protection lines. Tungsten is a suitable conductive material, for which existing processes may be substituted in place of aluminum metallization processes. | 2010-05-13 |
20100117130 | HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS - A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate. | 2010-05-13 |
20100117131 | Transistor for Preventing or Reducing Short Channel Effect and Method for Manufacturing the Same - A transistor for preventing or reducing short channel effect includes a substrate; a gate stack disposed over the substrate; a first junction region disposed on the substrate at a first side surface of the gate stack, said first junction layer being formed of an epitaxial layer; a trench formed within the substrate at a second side surface of the gate stack; and a second junction region disposed below the trench, said second junction layer being lower than the first junction region. | 2010-05-13 |
20100117132 | MEMORY DEVICE AND FABRICATION METHOD THEREOF - A memory device is disclosed, comprising a substrate, and a capacitor with a specific shape along an orientation parallel to a surface of the substrate, wherein the specific shape includes a curved outer edge, a curved inner edge having a positive curvature, a first line and a second line connecting the curved outer edge with the curved inner edge. A word line is coupled to the capacitor. In an embodiment of the invention, the capacitor is a deep trench capacitor with a vertical transistor. In another embodiment of the invention, the capacitor is a stacked capacitor. | 2010-05-13 |
20100117133 | MOS VARACTORS WITH LARGE TUNING RANGE - A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device. In depletion mode, a depletion region under the gate structure in the channel region merges with a depletion region of the shallow PN junction. | 2010-05-13 |
20100117134 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A dielectric film is formed on a silicon substrate made of single crystal silicon, an opening is formed in the dielectric film, an amorphous silicon film is formed on the dielectric film, the amorphous silicon film being in contact with the silicon substrate through the opening, solid-phase epitaxial growth of this amorphous silicon film is caused to start at the silicon substrate, and thereafter patterning is performed. Thereby, a seed layer made of the single crystal silicon is formed in part of a region deviated from immediately above the opening. Next, the amorphous silicon film is deposited so as to cover the seed layer, forming a single crystal silicon film by solid-phase epitaxial growth of the amorphous silicon film starting at the seed layer. The silicon pillar is formed by patterning the single crystal silicon film. | 2010-05-13 |
20100117135 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer. | 2010-05-13 |
20100117136 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film. | 2010-05-13 |
20100117137 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Each of memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate; a charge storage layer formed to surround a side surface of the columnar portions; and a first conductive layer formed to surround the charge storage layer. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; a gate insulating layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the gate insulating layer. An effective impurity concentration of the second semiconductor layer is less than or equal to an effective impurity concentration of the first semiconductor layer. | 2010-05-13 |
20100117138 | NONVOLATILE MEMORY CELL COMPRISING A NONWIRE AND MANUFACTURING METHOD THEREOF - A memory cell ( | 2010-05-13 |
20100117139 | Methods of Operating Non-Volatile Memory Devices - Methods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above the channel region. A charge storage layer is disposed above the tunneling dielectric layer. An upper insulating layer is disposed above the charge storage layer, and a gate is disposed above the upper insulating multi-layer structure. A positive bias is applied to a word line of the memory device in a selected memory cell and a negative bias is applied to a bit line in the selected cell. In another memory device, opposite polarity voltages are applied to the bit line and the word line. | 2010-05-13 |
20100117140 | NON-VOLATILE MEMORY DEVICE FOR 2-BIT OPERATION AND METHOD OF FABRICATING THE SAME - A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern. | 2010-05-13 |
20100117141 | Memory cell transistors having limited charge spreading, non-volatile memory devices including such transistors, and methods of formation thereof - In one aspect, a transistor comprises: a substrate body; a tunnel oxide layer on the body; a charge trapping layer on the tunnel oxide layer; a blocking layer on the charge trapping layer; a control gate on the blocking layer, the control gate having first and second sidewalls, the first and second sidewalls being spaced apart from each other by a first distance; and charge confinement features on the body, the charge confinement features being spaced apart from each other by a second distance that is greater than or substantially equal to the first distance, the charge confinement features suppressing or preventing migration of charge present in the charge trapping layer. | 2010-05-13 |
20100117142 | Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter - A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region. | 2010-05-13 |
20100117143 | Vertical type semiconductor device - A vertical type semiconductor device including a first vertical semiconductor device on a semiconductor substrate, a second vertical semiconductor device on the first vertical semiconductor device, and an interconnection between the first and second vertical semiconductor devices. | 2010-05-13 |
20100117144 | SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR DEVICE - In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material. | 2010-05-13 |
20100117145 | Configuration of trenched semiconductor power device to reduce masked process - A semiconductor power device formed on a semiconductor substrate of a first conductivity type wherein the semiconductor power device includes trench gates surrounded by body regions of a second conductivity type encompassing source regions of the first conductivity type therein. The semiconductor power device further includes trench contact structure having a plurality of trench contacts with trenches extended into the body regions for as source-body contacts and extended into the trench gates as gate contact. The semiconductor power device further includes a termination area wherein a plurality of the trench gate contacts are electrically connected to the source-body contacts. | 2010-05-13 |
20100117146 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode. | 2010-05-13 |
20100117147 | Capacitor-Less DRAM Device - Provided is a capacitor-less DRAM device including: an insulating layer formed on a semiconductor substrate; a silicon layer formed on the insulating layer, wherein a trench is formed inside the silicon layer; and an offset spacer formed on both sidewalls of the trench and protruded upward through the silicon layer. A gate insulating layer is formed on a bottom of the trench, and a gate electrode is formed to be buried in the gate insulating layer and in the trench and the offset spacer. A source region and a drain region are formed in the silicon layer on both sides of the offset spacer so as not to overlap with the gate electrode. A channel region is formed in the silicon layer below the gate insulating layer to be self-aligned with the gate electrode. | 2010-05-13 |
20100117148 | SEMICONDUCTOR DEVICES HAVING A RECESSED ACTIVE EDGE AND METHODS OF FABRICATING THE SAME - A semiconductor device having a recessed active edge is provided. The semiconductor devices include an isolation layer disposed in a substrate to define an active region. A gate electrode is disposed to cross over the active region. A source region and a drain region are disposed in the active region on both sides of the gate electrode. A recessed region is disposed under the gate electrode and on an edge of the active region adjacent to the isolation layer. A bottom of the recessed region may be sloped down toward the isolation layer. The gate electrode may further extend into and fill the recessed region. That is, a gate extension may be disposed in the recessed region. A method of fabricating the semiconductor device is also provided. | 2010-05-13 |
20100117149 | SEMICONDUCTOR DEVICE HAVING A RECESS CHANNEL TRANSISTOR - The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region. | 2010-05-13 |
20100117150 | METHODS OF MANUFACTURING TRENCH ISOLATED DRAIN EXTENDED MOS (DEMOS) TRANSISTORS AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate having a semiconductor surface, the semiconductor surface including at least a first surface region that provides a first dopant type. A patterned masking layer is formed on the first surface region, wherein at least one aperture in the masking layer is defined. The first surface region is etched to form at least one trench region corresponding to a position of the aperture. A dopant of a first dopant type is implanted to raise a concentration of the first dopant type in a first dopant type drift region located below the trench region. After the implanting, the trench region is filled with a dielectric fill material. A body region is then formed having a second dopant type in a portion of the first surface region. A gate dielectric is then formed over a surface of the body region and the first surface region. A patterned gate electrode layer is formed over the gate dielectric, a source region in the body region and a drain region in the first surface region on a side of the trench region opposite to the source are formed, and fabrication of the IC is completed. | 2010-05-13 |
20100117151 | SEMICONDUCTOR DEVICE WITH PI-SHAPED SEMICONDUCTOR CONDUCTIVE LAYER AND METHOD FOR MAKING THE SAME - The semiconductor device with a π-shaped semiconductor conductive layer manufactured by the manufacturing method thereof utilizes two pathways of the π-shaped semiconductor conductive layer connected to the silicon layer of a silicon-on-insulator (SOI) substrate for heat dissipation, so as to reduce the self-heating effects (SHEs). Furthermore, the semiconductor device of the invention utilizes the self-aligned technique to form a self-aligned structure with a gate unit and the silicon layer, so that the process is simple, the production cost is reduced, the compacted ability and the yield are improved, the off current and short-channel effects (SCEs) are still similar to a conventional UTSOI MOSFET, and the stability and the reliability are therefore superior. | 2010-05-13 |
20100117152 | SEMICONDUCTOR DEVICES - Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern. | 2010-05-13 |
20100117153 | HIGH VOLTAGE SOI CMOS DEVICE AND METHOD OF MANUFACTURE - A high voltage FET and process for fabricating such an FET are provided. An extended drain and thick gate oxide device design is implemented in a basic CMOS structure to enable higher operating voltages. The basic concept of the invention is well suited for the body-tie architecture often utilized in this technology and is also applicable to other SOI processes using similar isolation schemes. | 2010-05-13 |
20100117154 | HIGHLY N-TYPE AND P-TYPE CO-DOPING SILICON FOR STRAIN SILICON APPLICATION - A semiconductor device includes a gate, a source region and a drain region that are co-doped to produce a strain in the channel region of a transistor. The co-doping can include having a source and drain region having silicon that includes boron and phosphorous or arsenic and gallium. The source and drain regions can include co-dopant levels of more than 10 | 2010-05-13 |
20100117155 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - The present invention provides a semiconductor device including thin film transistors that have different characteristics on the same substrate and that have high performance and high reliability and a production method thereof. | 2010-05-13 |
20100117156 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor, a second transistor, a first interconnect, a second interconnect, and a first gate electrode. The first gate electrode is a gate electrode of the first and second transistors and extends linearly over first and second channel regions. In addition, a first source of the first transistor is located at the opposite side of a second source of the second transistor with the first gate electrode interposed therebetween, and a first drain of the first transistor is located at the opposite side of a second drain of the second transistor with the first gate electrode interposed therebetween. | 2010-05-13 |
20100117157 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an element isolation layer provided in a semiconductor layer; an element region divided by the element isolation layer; a gate interconnect which extends over the element region and the element isolation layer; a sidewall formed at a sidewall of the gate interconnect; and a contact connected to the gate interconnect located over the element isolation layer. The sidewall of the gate interconnect has a region, which is in contact with the contact, in at least an upper portion. | 2010-05-13 |
20100117158 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique capable of improving the reliability of a semiconductor device even if the downsizing thereof is advanced. | 2010-05-13 |
20100117159 | Strained Semiconductor Device and Method of Making Same - A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface. | 2010-05-13 |
20100117160 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material. | 2010-05-13 |
20100117161 | SEMICONDUCTOR DEVICE THAT DEGRADES LEAK CURRENT OF A TRANSISTOR - A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential. | 2010-05-13 |
20100117162 | Semiconductor Body and Method for the Design of a Semiconductor Body with a Connecting Line - A semiconductor body ( | 2010-05-13 |
20100117163 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; first and second spacers respectively formed on two side faces of the gate electrode; a gate sidewall formed on a side face of the first spacer; a channel region formed in the semiconductor substrate under the gate insulating film; first and second impurity diffused layers respectively formed on the first spacer side and the second spacer side of the channel region, the first impurity diffused layer including a first extension region in the gate electrode side thereon, the second impurity diffused layer including a second extension region in the gate electrode side thereon; a first silicide layer formed on the first impurity diffused layer; and a second silicide layer formed on the second impurity diffused layer, the channel region being closer to the second silicide layer than the first silicide layer. | 2010-05-13 |
20100117164 | SEMICONDUCTOR DEVICE WITH A LOW JFET REGION RESISTANCE - A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region. | 2010-05-13 |
20100117165 | DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM - The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The deposition process does not interfere with and/or alter the correct functioning of the electronic devices (diodes, bipolar junction transistors, field effect transistors and electronic amplifiers in general) already integrated on the support to be coated on which said deposition is effected. The process according to the invention can be applied to electronic devices and permits their unaltered correct functioning. | 2010-05-13 |
20100117166 | METHOD FOR THE PRODUCTION OF A COMPONENT, AND COMPONENT - A method for producing a component, especially a micromechanical, micro-electro-mechanical or micro-opto-electro-mechanical component, as well as such a component which has an active structure that is embedded in a layer structure. Strip conductor bridges are formed by etching first and second depressions having a first and second, different etching depth into a covering layer of a first layer combination that additionally encompasses a substrate and an insulation layer. The deeper depression is used for insulating the strip conductor bridge while the shallower depression provides a moving space for the active structure with the moving space being bridged by the strip conductor bridge. | 2010-05-13 |
20100117167 | Semiconductor dymamic quantity sensor and method of producing the same - A semiconductor dynamic quantity sensor includes a sensor part and a cap connected to the sensor part. Dynamic quantity is detected based on a capacitance of a capacitor defined between a movable electrode and a fixed electrode of the sensor part. A float portion of the sensor part is separated from a support board of the sensor part to define a predetermined interval. At least one of the cap and the support board has a displacing portion displacing the float portion in a direction perpendicular to the support board so as to change the predetermined interval. The movable electrode has a displacement in accordance with the displaced float portion. | 2010-05-13 |
20100117168 | MEMS Microphone with Single Polysilicon Film - An integrated circuit structure includes a capacitor, which further includes a first capacitor plate formed of polysilicon, and a second capacitor plate substantially encircling the first capacitor plate. The first capacitor plate has a portion configured to vibrate in response to an acoustic wave. The second capacitor plate is fixed and has slanted edges facing the first capacitor plate. | 2010-05-13 |
20100117169 | MEMORY CELL WITH RADIAL BARRIER - Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization. | 2010-05-13 |
20100117170 | MAGNETIC MEMORY WITH POROUS NON-CONDUCTIVE CURRENT CONFINEMENT LAYER - A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer. | 2010-05-13 |
20100117171 | SENSOR PACKAGE - Sensor package | 2010-05-13 |
20100117172 | THIN FILM SEMICONDUCTOR ALLOY MATERIAL PREPARED BY A VHF ENERGIZED PLASMA DEPOSITION PROCESS - A thin film, hydrogenated, silicon based semiconductor alloy material is produced by a VHF energized plasma deposition process wherein a process gas is decomposed in a plasma so as to deposit the thin film material onto a substrate. The process is carried out at process gas pressures which are in the range of 0.5-2.0 torr, with substrate temperatures that do not exceed 300° C., and substrate-cathode spacings in the range of 10-50 millimeters. Deposition rates are at least 5 angstroms per second. Also disclosed are photovoltaic devices which include the semiconductor material. | 2010-05-13 |
20100117173 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a method of manufacturing an image sensor. A method of manufacturing an image sensor may include forming an interconnection and/or an interlayer dielectric over a semiconductor substrate including circuitry connected to an interconnection. A method of manufacturing an image sensor may include forming a photodiode having a first doping layer and/or a second doping layer over an interlayer dielectric, and forming a via hole through a photodiode, which may expose a portion of a surface of an interconnection. A method of manufacturing an image sensor may include forming a barrier pattern over a via hole which may cover an exposed surface of a second doping layer, and a contact plug on and/or over a via hole, which may connect an interconnection and a first doping layer. An upper portion of a contact plug may be etched. An insulating layer may be formed over a contact plug. | 2010-05-13 |
20100117174 | METHOD OF MANUFACTURING IMAGE SENSOR - A method of manufacturing an image sensor and devices thereof. A method of manufacturing an image sensor may include forming an interlayer dielectric layer, which may include a metal line, on and/or over a semiconductor substrate. A method of manufacturing an image sensor may include forming an image sensing part, including a stacked structure having a first doped layer and/or a second doped layer, on and/or over a interlayer dielectric layer. A method of manufacturing an image sensor may include forming a via hole, which may expose a metal line by perforating a image sensing part and/or a interlayer dielectric layer. A method of manufacturing an image sensor may include performing a cleaning process. An undercut may be formed on and/or over a image sensing part when a via hole is formed, and/or a native oxide layer may be substantially removed from a undercut through a cleaning process. | 2010-05-13 |
20100117175 | Semiconductor module - A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and a light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The light permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance. | 2010-05-13 |
20100117176 | Camera module and manufacturing method thereof - A manufacturing method of a camera module includes steps of: forming a wafer assembly of a semiconductor wafer and a light transmissible optical wafer which are fixed to each other, wherein the semiconductor wafer has an array of plural sensor units each having a light receiving unit of a photoelectric conversion element, and wherein the light transmissible optical wafer has an array of plural lens units, the lens units being opposite to the respective sensor units while each pair of the lens unit and the sensor unit faces each other across a space, so that the semiconductor wafer and the light transmissible optical wafer are adhered at circumferences of the respective pair of the lens unit and the sensor unit with a spacer unit, cutting the wafer assembly at the spacer unit to individually divide the wafer assembly into a plurality of camera modules each comprising a sensor chip and a lens chip bonded to each other by a spacer, forming a light shieldable mask film to determine a lens aperture of each of the plural lens units on the light transmissible optical wafer; forming a groove in the light transmissible optical wafer of the wafer assembly such that the groove reaches the spacer unit and filling the groove with a light shieldable resin to form a light shieldable resin layer; and cutting the light shieldable resin layer at a width less than the groove to individually divide the camera modules in each of which the light shieldable resin layer is provided at a side of the lens chip. | 2010-05-13 |
20100117177 | Image Sensor and Method of Manufacturing the Same - An image sensor and a method of manufacturing the same are disclosed. A passivation layer on an interlayer dielectric layer has different thicknesses for neighboring pixels. Consequently, a phase of light incident on a pixel is out of phase with light incident on an adjacent pixel before it reaches a photodiode. As a result, diffraction of the incident light results in destructive interference between the pixels. Thus, cross talk between adjacent pixels can be prevented. | 2010-05-13 |
20100117178 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor is disclosed that includes a first substrate including an electric junction region, a transistor, and a metal line connected to the electric junction region or the transistor; and a photodiode formed on the first substrate. The first substrate is formed at an upper portion thereof with a reflective layer to reflect light back to the photodiode. | 2010-05-13 |
20100117179 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a substrate, a bonding silicon, an interlayer dielectric, a first contact plug, a second contact plug, a second metal interconnection, and a color filter layer and a microlens. The substrate comprises a first metal interconnection. The bonding silicon is formed on the substrate, and comprises a plurality of impurity regions. The interlayer dielectric is formed on the bonding silicon. The first contact plug penetrates the bonding silicon and is electrically connected to the first metal interconnection. The second contact plug penetrates the interlayer dielectric and is connected to a surface of the bonding silicon. The second metal interconnection is formed on the interlayer dielectric, and is connected to the second contact plug. The color filter layer and a microlens are formed over the second metal interconnection. | 2010-05-13 |