19th week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100117180 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a method of manufacturing the same. An image sensor may include a first interlayer dielectric layer having a first metal wiring and/or a bonding silicon including impurity regions on and/or over a first interlayer dielectric layer. An image sensor may include a second interlayer dielectric layer formed on and/or over a bonding silicon, and/or a first contact plug connected to a first metal wiring. An image sensor may include a third interlayer dielectric layer on and/or over a second interlayer dielectric layer, a second contact plug connected to a first impurity region and/or a second metal wiring on and/or over a second interlayer dielectric layer. An image sensor may include and a color filter layer and/or a microlens. A dielectric layer may be between a first contact plug and a first impurity region. A dielectric layer may be on and/or over a second interlayer dielectric layer. | 2010-05-13 |
20100117181 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip, a transparent substrate, an adhesive pattern, and at least one dew-proofer. The semiconductor includes a pixel area. The transparent substrate is disposed on the semiconductor chip. The adhesive pattern is disposed between the semiconductor chip and the transparent substrate and provides a space on the pixel area. At least one dew-proofer is disposed between the semiconductor chip and the transparent substrate and spaced from the adhesive pattern. | 2010-05-13 |
20100117182 | IMAGE PICKUP DEVICE - An image pickup device includes a plurality of photoelectric transducers. The plurality of photoelectric transducers includes color filters provided thereon. A diffusion-reflection layer is provided in front of the plurality of photoelectric transducers, includes a microstructure which is finer than each light receiving element of the image pickup device and is provided on surfaces of the color filters so as to diffuse and reflect a part of incident light. A part of incident light on the diffusion-reflection layer is reflected and dispersed therefrom, and a remainder of the incident light is transmitted through the diffusion-reflection layer so as to be incident on the plurality of photoelectric transducers. | 2010-05-13 |
20100117183 | PHOTODETECTOR WITH INTERNAL GAIN AND DETECTOR COMPRISING AN ARRAY OF SUCH PHOTODETECTORS - A photodetector with internal gain comprising a semiconductor structure in which impact ionization events are produced mostly by minority charge carriers; a first biasing contact and a second biasing contact located in the semiconductor structure; a means of defining, in the semiconductor structure, a photon collection region close to first biasing contact; a P-N type junction formed in the semiconductor structure between the two biasing contacts and close to the second biasing contact; and a collector contact which is located in the P-N junction and used to collect current in the P-N junction. | 2010-05-13 |
20100117184 | METHOD OF MANUFACTURING IMAGE SENSOR - A method of manufacturing an image sensor and an image sensor. A method of manufacturing an image sensor may include forming an interlayer dielectric including a metal line on and/or over a semiconductor substrate, forming an image sensing part on and/or over an interlayer dielectric, and/or forming a hard mask in which an opening corresponding to a metal line may be defined on and/or over an image sensing part. A method of manufacturing an image sensor may include performing an etch process to form an auxiliary via hole exposing an inside of an image sensing part, and/or forming a spacer within a auxiliary via hole by an etch byproduct of a hard mask. A method of manufacturing an image sensor may include performing an etch process including a chemical to remove a spacer, and/or etching an image sensing part and/or an interlayer dielectric to form a deep via hole. | 2010-05-13 |
20100117185 | Temperature sensor with buffer layer - A temperature sensor with a bandgap circuit is provided. The bandgap circuit is covered by a buffer layer of photoresist. The device is packaged in a housing. By providing the buffer layer, mechanical stress in the bandgap circuit, as it is e.g. caused by different thermal expansion coefficients of the packaging and the chip, can be reduced. This improves the accuracy of the device. | 2010-05-13 |
20100117186 | Semiconductor device and method of producing the same - The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film. | 2010-05-13 |
20100117187 | METHOD FOR FORMING GATE IN FABRICATING SEMICONDUCTOR DEVICE - In fabricating a semiconductor device, by forming gate electrode lines to meet a design rule with additional simple processes such as a masking process, an etching process and the like for securing an isolation space between the gate electrode lines according to the design rule, the method of embodiments can overcome a problem in the related gate forming process so that a chip size is increased and high mask quality is required since the process has to proceed in consideration of additional design guide rules B | 2010-05-13 |
20100117188 | METHOD FOR PRODUCING TRENCH ISOLATION IN SILICON CARBIDE AND GALLIUM NITRIDE AND ARTICLES MADE THEREBY - A method for fabricating a trench in a SiC or GaN semiconductor wafer is provided. The method may include filling the trench with a conformal layer of electrically and/or optically isolating material. A device is also provided. | 2010-05-13 |
20100117189 | DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH - A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region. | 2010-05-13 |
20100117190 | FUSE STRUCTURE FOR INTERGRATED CIRCUIT DEVICES - A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure. | 2010-05-13 |
20100117191 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device that shows excellent manufacturing stability and has lower contact resistance, and a method for manufacturing the semiconductor device. | 2010-05-13 |
20100117192 | SEMICONDUCTOR INTEGRATED CIRCUIT CHIP, MULTILAYER CHIP CAPACITOR AND SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGE - Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip. | 2010-05-13 |
20100117193 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of capacitor cells having respective lower electrodes to which signals are applied and respective upper electrodes arranged to face the respective lower electrodes, wherein each interconnect connected to a corresponding one of the lower electrodes includes a shield interconnect section enclosing a corresponding one of the upper electrodes. | 2010-05-13 |
20100117194 | METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE - A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed. | 2010-05-13 |
20100117195 | CAPACITOR INTEGRATION AT TOP-METAL LEVEL WITH A PROTECTIVE CLADDING FOR COPPER SURFACE PROTECTION - An on-chip decoupling capacitor ( | 2010-05-13 |
20100117196 | Support For Vertically-Oriented Capacitors During The Formation of a Semiconductor Device - A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described. | 2010-05-13 |
20100117197 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor. | 2010-05-13 |
20100117198 | INTEGRATED PROCESS FOR THIN FILM RESISTORS WITH SILICIDES - The formation of devices in semiconductor material is provided using an HF/HCL cleaning process. In one embodiment, the method includes forming at least one hard mask overlaying at least one layer of resistive material, forming at least one opening to a working surface of a silicon substrate of the semiconductor device, and cleaning the semiconductor device with a diluted HF/HCL process. The HF/HCL process includes applying a dilute of HF for a select amount of time and applying a dilute of HCL for a specific amount of time. After cleaning with the diluted HF/HCL process, a silicide contact junction is formed in the at least one opening to the working surface of the silicon substrate, and interconnect metal layers are formed. | 2010-05-13 |
20100117199 | METHOD AND APPARATUS FOR THE PRODUCTION OF THIN DISKS OR FILMS FROM SEMICONDUCTOR BODIES - The invention relates to a method and an apparatus for the production of thin disks or films ( | 2010-05-13 |
20100117200 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING A REINFORCING MEMBER THAT PREVENTS DISTORTIONS AND METHOD FOR FABRICATING THE SAME - A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body. | 2010-05-13 |
20100117201 | Cooling Channels in 3DIC Stacks - An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through. | 2010-05-13 |
20100117202 | MOLD AND SUBSTRATE FOR USE WITH MOLD | 2010-05-13 |
20100117203 | OXIDE-CONTAINING FILM FORMED FROM SILICON - A process for forming an oxide-containing film from silicon is provided that includes heating the silicon substrates to a process temperature of between 250° C. and 1100° C. with admission into the process chamber of diatomic reductant source gas Z-Z′ where Z and Z′ are each H, D and T and a stable source of oxide ion. Multiple exhaust ports exist along the vertical extent of the process chamber to create reactant across flow. A batch of silicon substrates is provided having multiple silicon base layers, each of the silicon base layers having exposed <110> and <100> planes and a film residual stress associated with the film being formed at a temperature of less than 600° C. and having a <110> film thickness that exceeds a <100> film thickness on the <100> crystallographic plane by less than 20%, or a film characterized by thickness anisotropy less than 18% and an electrical breakdown field of greater than 10.5 MV/cm. | 2010-05-13 |
20100117204 | FILM FORMING METHOD FOR A SEMICONDUCTOR - The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention, the SiCN film that is highly fluorine-resistant near the interface with the CFx film and has a low dielectric constant as a whole can be formed as a hard mask. | 2010-05-13 |
20100117205 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes forming a paddle having a paddle top surface, the paddle top surface having a depression provided therein, forming an external interconnect having a lead tip and a lead body with the lead body having a first recess segment along a length-wise dimension of the lead body, connecting a device over the paddle top surface and the external interconnect, and filling a substantially electrically nonconductive material in the depression. | 2010-05-13 |
20100117206 | MICROARRAY PACKAGE WITH PLATED CONTACT PEDESTALS - A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm. | 2010-05-13 |
20100117207 | BOND PAD ARRAY FOR COMPLEX IC - An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers. | 2010-05-13 |
20100117208 | SEMICONDUCTOR PACKAGE FOR IMPROVING CHARACTERISTICS FOR TRANSMITTING SIGNALS AND POWER - A semiconductor package includes a semiconductor chip having a first region and a second region. Bonding pads are formed and through-holes are defined in the first and second regions. Insulation layers are formed on sidewalls of the through-holes, and through-electrodes formed in the through-holes and connected with corresponding bonding pads. The insulation layers formed in the first and second regions have different thicknesses or dielectric constants. | 2010-05-13 |
20100117209 | MULTIPLE CHIPS ON A SEMICONDUCTOR CHIP WITH COOLING MEANS - The present invention is directed to a method of packaging multiple semiconductor chips on a second semiconductor chips with a built-in efficient cooling means. One embodiment is to place two multiple chip stacks on opposing sides of a vapor chamber for transferring heat away from the semiconductor chips. Another embodiment is to construct a vapor chamber with a substrate such that at least one multiple chip stack is embedded inside the vapor chamber. | 2010-05-13 |
20100117210 | Semiconductor device - A semiconductor device including: a substrate formed with a concave portion at one surface thereof; and a first semiconductor chip provided in the concave portion of the substrate and is adhered to the substrate by an underfill in the concave portion, wherein the concave portion includes a chip arrangement region in which the first semiconductor chip is arranged, and an adjustment region which protrudes from at least a portion of the periphery of the chip arrangement region when seen in a plan view at a height of at least a portion of a region where the first semiconductor chip is placed in a stacked direction of the substrate, and has different shapes from the chip arrangement region is provided. | 2010-05-13 |
20100117211 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package includes a cover plate disposed on a substrate mounted with an integrated circuit chip thereon. The chip is formed with first solder pads coupled respectively and wiredly to pin terminals on the substrate, and second solder pads coupled respectively and wiredly to pinhole terminals in the cover plate, and includes a main circuit unit, a pin transmission unit interconnecting electrically first ports of a main circuit unit and the first solder pads, a pinhole transmission unit interconnecting electrically second ports of the main circuit unit, and a control unit coupled to the pin and pinhole transmission units, and operable to control operation of the pin and pinhole transmission units such that each first port is coupled to a selected first solder pad through the pin transmission unit and that each second port is coupled to a selected second solder pad through the pinhole transmission unit. | 2010-05-13 |
20100117212 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES - Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads. | 2010-05-13 |
20100117213 | COIL AND SEMICONDUCTOR APPARATUS HAVING THE SAME - An apparatus to package a semiconductor chip includes a coil configured to use induction heating to reflow a solder ball of the semiconductor chip. The coil includes a first body, a second body parallel to the first body, a third body extending from the first body to the second body. The first and second bodies are symmetrical with respect to a vertical plane disposed therebetween. The first and second bodies have inclined surfaces facing each other, and the inclined surfaces are distant from each other downward. | 2010-05-13 |
20100117214 | IMAGE FORMING APPARATUS, CHIP, AND CHIP PACKAGE - An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals. | 2010-05-13 |
20100117215 | PLANAR MULTI SEMICONDUCTOR CHIP PACKAGE - Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate. | 2010-05-13 |
20100117216 | CHIP PACKAGE STRUCTURE - A chip package structure including a substrate, at least one chip, a heat dissipation device, at least one first conductive bar, a molding compound, and at least one second conductive bar is provided. The chip and the heat dissipation device are respectively disposed on a first and a second surface of the substrate. The first conductive bar has two opposite end surfaces, wherein one end surface is disposed on the first surface of the substrate, the other end surface is extended away from the substrate, and a fastening slot is disposed between the two end surfaces and passes through the other end surface. The molding compound encapsulates the substrate, the chip, part of the heat dissipation device, and the first conductive bar. The second conductive bar is disposed on one surface of the molding compound and has a protrusion portion fastened to the fastening slot of the first conductive bar. | 2010-05-13 |
20100117217 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package. | 2010-05-13 |
20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 2010-05-13 |
20100117219 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device in which transfer molding resin seals: a metallic circuit substrate; a power semiconductor element joined to a wiring pattern; and a side surface of a cylindrical external terminal communication section provided on the wiring pattern and to which an external terminal can be inserted and connected. The cylindrical external terminal communication section is substantially perpendicular to a surface on which the wiring pattern is formed. An outer surface of a metal plate of the metallic circuit substrate and a top portion of the cylindrical external terminal communication section are exposed from the transfer molding resin. The transfer molding resin is not present within the cylindrical external terminal communication section. | 2010-05-13 |
20100117220 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor package includes at least: a workpiece at least one surface of which is equipped with a device; a wall portion provided along an outer circumference of the device and is spaced apart from the device; and a cover member that is arranged above the device so as to form a first space and is supported by the workpiece via the wall portion, in which the first space includes at least one second space that communicates with an external space. | 2010-05-13 |
20100117221 | Capped Wafer Method and Apparatus - A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die. Removing excess cap wafer material involves making a first cut in the cap wafer near a first row of bond pads and a second cut near the adjacent row of bond pads, such that a strip of wafer cap material is suspended from portions of an underlying supporting member near the edge of the capped wafer, and then removing the wafer cap material suspended from the portions of the supporting glass frit using an adhesive tape. | 2010-05-13 |
20100117222 | Void Reduction in Indium Thermal Interface Material - Thermal interface materials and method of using the same in packaging are provided. In one aspect, a thermal interface material is provided that includes an indium preform that has a first surface and a second surface opposite to the first surface, an interior portion and a peripheral boundary. The indium preform has a channel extending from the peripheral boundary towards the interior portion. The channel enables flux to liberate during thermal cycling. | 2010-05-13 |
20100117223 | SEMICONDUCTOR MODULE - A semiconductor module includes a base plate, at least one semiconductor chip mounted on the base plate, a case fixed to the base plate and surrounding the at least one semiconductor chip, an electrically insulating gel layer covering the at least one semiconductor chip, a thermosetting resin layer formed on top of the gel layer, and a lid formed on top of the thermosetting resin layer. The lid comprises a lid-extension, which defines a lid-opening. The lid-opening extends through the thermosetting resin layer to the gel layer and allows gel of the gel layer to expand into the lid-opening. | 2010-05-13 |
20100117224 | Sensor - A sensor die in a sensor device includes a conformal dielectric coating over at least a die sidewall adjacent an interconnect edge and, in some devices, a conformal dielectric coating over at least part of the active area of the front side of the die. The sensor die can be connected to circuitry in a support by an electrically conductive material that is applicable in a flowable form, such as a curable electrically conductive polymer, which is applied onto or adjacent the dielectric coating on the die sidewall, and which is cured to complete connection between interconnect pads on the die and exposed sites on the support circuitry. In some devices, a coating over the active area of the sensor die provides mechanical and chemical protection for underlying structures in and on the die. In an image sensor device, for example, the coating over the image sensor array on the die is substantially optically transparent. Also, a package contains such a sensor die mounted on and electrically connected to a support; and assemblies include such a sensor die and additional die mounted on and electrically connected to opposite sides of a support. Also, methods are disclosed for making the sensor die, devices, packages, and assemblies. | 2010-05-13 |
20100117225 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them. | 2010-05-13 |
20100117226 | STRUCTURE AND METHOD FOR STACKED WAFER FABRICATION - A method for fabricating stacked wafers is provided. In one embodiment, the method comprises providing a wafer having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies is provided, each of the die bonded to one of the plurality of semiconductor chips. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material. The non-chip side of the wafer is thinned to an intended thickness. The wafer is then diced to separate the wafer into individual semiconductor packages. | 2010-05-13 |
20100117227 | METHOD OF PREPARING DETECTORS FOR OXIDE BONDING TO READOUT INTEGRATED CHIPS - In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip. | 2010-05-13 |
20100117228 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has an element interconnection | 2010-05-13 |
20100117229 | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same - The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device. | 2010-05-13 |
20100117230 | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof - A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump. | 2010-05-13 |
20100117231 | RELIABLE WAFER-LEVEL CHIP-SCALE SOLDER BUMP STRUCTURE - A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions. | 2010-05-13 |
20100117232 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of Mn | 2010-05-13 |
20100117233 | METAL LINE IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method includes forming a buffer lower metal line over a semiconductor substrate for absorbing an external impact, forming a pre-metal-dielectric layer which covers the buffer lower metal line, the pre-metal-dielectric layer having a via hole formed therein to expose a portion of the buffer lower metal line, forming a seed layer over a surface of the pre-metal-dielectric layer having the via hole formed therein, forming polyimide which exposes the via hole and the seed layer formed over the pre-metal-dielectric layer in the vicinity of the via hole, growing an upper metal line over the exposed seed layer, subjecting the semiconductor substrate having the upper metal line formed thereon to a thermal process, removing the polyimide by dry etching, and bonding a bonding portion onto the upper metal line. | 2010-05-13 |
20100117234 | Semiconductor device and method of manufacturing the same - A method includes burying a conductive pattern in an insulating film made of SiOH, SiCOH or organic polymer, treating surfaces of the insulating film and the conductive pattern with plasma which includes a hydrocarbon gas as a treatment gas, and forming a diffusion barrier film, which is formed of an SiCH film, an SiCHN film, an SiCHO film or an SiCHON film, over the insulating film and the conductive pattern with performing a plasma CVD by adding an Si-containing gas to the treatment gas while increasing an addition amount gradually or in a step by step manner. | 2010-05-13 |
20100117235 | METAL LINE IN SEMICONDUCTOR DEVICE - A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer. | 2010-05-13 |
20100117236 | TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist define electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill. | 2010-05-13 |
20100117237 | Silicided Trench Contact to Buried Conductive Layer - A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers. | 2010-05-13 |
20100117238 | METHOD FOR PREPARING A LAYER COMPRISING NICKEL MONOSILICIDE NISI ON A SUBSTRATE COMPRISING SILICON - The invention relates to a method for fabricating a layer comprising nickel monosilicide NiSi on a substrate comprising silicon successively comprising the following steps:
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20100117239 | INTERCONNECTION STRUCTURE OF ELECTRONIC DEVICE AND METHOD OF MANUFACTURING PACKAGE THEREOF - An interconnection is formed on an object having a step by a screen printing method. The interconnection is formed by printing it on a substrate having an upper stage surface and a lower stage surface. A multilayer interconnection structure having a plurality of layers which are stacked is formed by repeatedly performing a process of printing and drying an interconnection pattern on the lower stage surface. Then, when the height of the multilayer interconnection structure approaches the height of the upper stage surface, an interconnection pattern of the uppermost layer is printed on the multilayer interconnection structure to extend onto the upper stage surface. Because the interconnection pattern of the uppermost layer is printed in a smaller step, the print characteristic is good. Thus, by the printing, the interconnection structure is formed which has a narrow interconnection width and surely connects the upper surface and the lower surface in a larger step than the interconnection width. | 2010-05-13 |
20100117240 | PROCESS FOR WET PASSIVATION OF BOND PADS FOR PROTECTION AGAINST SUBSEQUENT TMAH-BASED PROCESSING - A process for forming a protective layer at a surface of an aluminum bond pad. The aluminum bond pad is exposed to a solution containing silicon, ammonium persulfate and tetramethylammonium hydroxide, which results in the formation of the protective layer. This protective layer protects the bond pad surface from corrosion during processing of an imager, such as during formation of a color filter array or a micro-lens array. | 2010-05-13 |
20100117241 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device includes: a plurality of semiconductor substrates each having a pad-formed surface and being mutually laminated; a connection electrode pad formed on the pad-formed surface; a wire connecting the connection electrode pads of the plurality of semiconductor substrates so as to electrically connect the semiconductor substrates; a relay electrode pad that is provided on the pad-formed surface of a lower one of the laminated semiconductor substrates so as to be exposed by an upper one of the laminated semiconductor substrates, and that is connected to the connection electrode pad by a relay wire included in the wire; and a mounting electrode pad that is formed on a mounting surface on which the laminated semiconductor substrates are mounted, and that is connected to the relay electrode pad of the lower semiconductor substrate by the wire. In the device, the wire electrically connects the connection electrode pad of the upper semiconductor substrate to the relay electrode pad of the lower semiconductor substrate. | 2010-05-13 |
20100117242 | TECHNIQUE FOR PACKAGING MULTIPLE INTEGRATED CIRCUITS - A semiconductor device includes an intermediate substrate having a first surface and a second surface, a first die attached to the first surface of the intermediate substrate. The first die has a first active surface, and the first active surface faces the intermediate substrate. A second die is attached to the second surface of the intermediate substrate, has a second active surface, faces the intermediate substrate, and is coupled to the first die through an electrically conductive material in the intermediate substrate. An organic material encapsulates at least an edge of the intermediate substrate. There is also a method of forming the semiconductor device. | 2010-05-13 |
20100117243 | METHOD AND APPARATUS FOR STACKED DIE PACKAGE WITH INSULATED WIRE BONDS - A semiconductor package has a substrate with a plurality of contact pads. A first semiconductor die is mounted to the substrate. First wire bonds are formed between each of the center-row contact pads of the first semiconductor die and the substrate contact pads. The first wire bonds include an electrically insulative coating formed over the shaft that covers a portion of a surface of a bumped end of the first wire bonds. An epoxy material is deposited over the first semiconductor die. A second semiconductor die is mounted to the epoxy material. Second wire bonds are formed between each of the center-row contact pads of the second semiconductor die and the substrate contact pads. The second wire bonds include an electrically insulative coating formed over the shaft of the second wire bonds that covers a portion of a surface of a bumped end of the second wire bonds. | 2010-05-13 |
20100117244 | Semiconductor device and manufacturing method therefor - The present invention can avoid spaces not filled with resin by using simplified procedures and configuration even when multiple semiconductor chips are stacked, creating an overhanging portion. A semiconductor device | 2010-05-13 |
20100117245 | INTEGRATED CIRCUIT PACKAGE SUBSTRATE HAVING CONFIGURABLE BOND PADS - Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate. | 2010-05-13 |
20100117246 | REAGENT DISPENSING APPARATUSES AND DELIVERY METHODS - This invention relates to a vapor or liquid phase reagent dispensing apparatus that may be used for dispensing vapor or liquid phase reagents such as precursors for deposition of materials in the manufacture of semiconductor materials and devices. The vapor phase reagent dispensing apparatus has a single port capable of receiving a carrier gas and dispensing a vapor phase reagent. The liquid phase reagent dispensing apparatus has a single port capable of receiving an inert gas and dispensing a liquid phase reagent. | 2010-05-13 |
20100117247 | METHOD FOR PRODUCING NITRATE GRANULES - An apparatus for producing nitrate granules includes a first fluidized bed which is supplied with air that has been conditioned to a relative humidity of less than 30% at 40° C. and heated to a temperature of 40° C. to 100° C. One or more spray nozzles are provided for spraying a nitrate melt into the first fluidized bed to form nitrate granules. The apparatus also includes a second fluidized bed which is in direct communication with the first fluidized bed. Nitrate granules formed in the first fluidized bed flow directly to the second fluidized bed where they are cooled to a temperature of less than 60° C. The nitrate granules produced by the apparatus and process of the invention are spherical in shape, hard and dry and do not break down easily during handling. The apparatus according to the invention is compact, capable of very high product rates, and can be operated by one operator. | 2010-05-13 |
20100117248 | Amorphous Formwork - The invention disclose a method and formwork for casting concrete or concrete like elements where said elements may have an amorphous shape, wherein the method comprises the following steps: —in a block of formable material having a size larger than the element to be cast, a model of the element is cut out, thereby creating an inner formwork; —an outer load bearing support structure having an inner size corresponding to the outer dimensions of the block is created; —the parts of the block not representing the model are arranged in the interior of the load bearing support structure, thereby creating a cavity corresponding to the model; —optionally reinforcement is arranged in the cavity; fresh concrete or other concrete like material is poured into the cavity and allowed to cure; —the outer load bearing support structure and the inner formwork are removed. | 2010-05-13 |
20100117249 | METHOD FOR PRODUCTION OF CONCRETE DOUBLE-WALL PANELS - Method of production of concrete double-wall panels, wherein a layer of concrete is poured into the bottom of a mould, covering a welded wire fabric and the lower end portion of vertical structures of rods; subsequently a second layer of concrete is poured into the upper part of the mould, over a plate of insulating material arranged at a height on the vertical structures, said concrete covering a third welded wire fabric fitted to the upper end portion of the vertical structures; after which the two layers of concrete are left to cure simultaneously. | 2010-05-13 |
20100117250 | METHOD FOR INSPECTING DEFECT OF HOLLOW FIBER POROUS MEMBRANE, DEFECT INSPECTION EQUIPMENT AND PRODUCTION METHOD - A method for inspecting a defect of a hollow fiber porous membrane having substantially uniform, continuous inner hollow portions comprises steps for introducing a part of the hollow fiber porous membrane into an irradiation chamber, for irradiating the hollow fiber porous membrane with light from the outside in the irradiation chamber, and for detecting light exiting the hollow fiber porous membrane on the outside of the irradiation chamber. | 2010-05-13 |
20100117251 | NATURAL TOURMALINE ANION FIBER AND FILTER AND PRODUCING METHOD - The present invention provides to a method of producing fiber from tourmaline anion fiber; of which, polypropylene or polyethylene chip, TPE and submicrometer tourmaline particle are prepared and then rolled into submicrometer tourmaline agglomerate through granulation by double screw; then, take submicrometer tourmaline agglomerate and polypropylene or polyethylene chip, of which the content of tourmaline agglomerate accounts for 1˜10% of gross weight, and TPE for 1˜40% of gross weight; tourmaline agglomerate and polypropylene or polyethylene are melted into composite fiber or filter material via spinning, such that the fiber or filter material can yield anion and present outstanding gas permeability and mechanical property. | 2010-05-13 |
20100117252 | SOLID COMPOSITION HAVING ENHANCED PHYSICAL AND ELECTRICAL PROPERTIES - A method of making a treating wash includes mixing brass granules with acetone, mixing carbon nanotube material, silver granules, iron pyrite granules and copper granules in the acetone brass mixture, and straining the liquid from the remaining solid material. Methods of treating materials such as brass granules, silver granules, iron pyrite granules, carbon nanotube material, and brass granules comprises washing the materials in the treating wash, followed by straining and drying the materials. | 2010-05-13 |
20100117253 | SOLID COMPOSITION HAVING ENHANCED PHYSICAL AND ELECTRICAL PROPERTIES - A method of making a treating wash includes mixing brass granules with acetone, mixing carbon nanotube material, iron pyrite granules and copper granules in the acetone brass mixture, and straining the liquid from the remaining solid material. Methods of treating materials such as brass granules, iron pyrite granules, carbon nanotube material, and brass granules comprises washing the materials in the treating wash, followed by straining and drying the materials. | 2010-05-13 |
20100117254 | Micro-Extrusion System With Airjet Assisted Bead Deflection - A gas jet source is used in conjunction with a micro-extrusion printhead assembly in a micro-extrusion system to bias extruded material onto a target substrate. The micro-extrusion system includes a material feed system for pushing/drawing materials out of extrusion nozzles defined in the printhead assembly as the printhead assembly is moved over the substrate. The gas jet source is positioned near the nozzle outlets, and directs a gas jet against the extruded material as it exits the extrusion nozzles such that the extruded material is reliably directed (biased) toward the target substrate. In some embodiments the gas jet causes slumping (flattening) of the extruded material against the substrate, producing low aspect ratio lines that may be merged to form a connected structure. | 2010-05-13 |
20100117255 | COATING METHOD AND COATING APPARATUS - A first coating rod placed on an upper-surface side of a resin film is pressed onto the resin film in a state where the first coating rod is circumscribed and supported by support members each comprising a pair of rollers and spaced with intervals therebetween in a length direction of the first coating rod so that the first coating rod is rotated in a forward direction at a speed substantially equal to that of the resin film, and a lower surface of the resin film is supported by a guide roll or a second coating rod placed on a downstream side of the first coating rod and an upstream side of a tenter so that the coating liquid continuously measured and supplied to an upper surface of the resin film is smoothened by the first coating rod. | 2010-05-13 |
20100117256 | SELF-RELEASING RESIST MATERIAL FOR NANO-IMPRINT PROCESSES - Nanoimprint lithography using resist material with the addition of a surfactant is described. A template release layer is formed on a pattern of a template. A non-ionic surfactant is added to a resist material to form a mixed resist material. The resist material may comprise a hydrocarbon material having an unsaturated bond, such as an acrylate material. The surfactant may comprise polyakylene glycol or an organically modified polysiloxane. A resist layer is then formed on a substrate from the mixed resist material. The surfactant added to the resist material forms a resist release layer on the surface of the resist layer. The template is then pressed into the resist layer, where the template release layer and the resist release layer are between the pattern of the template and the resist layer. | 2010-05-13 |
20100117257 | Reinforced extrusion and method for making same - A reinforced extrusion for attachment to a motor vehicle component edge or flange. The reinforced extrusion includes a reinforcement core having at least one flexible wire and at least one threaded cord. A thermoplastic overmold is formed on at least one side of the reinforcement core and at least partly fills any gaps formed in the reinforcement core. An extruded layer is selectively formed around the thermoplastic overmold and reinforcement core and has a flange extending flange portion extending from a channel portion for engaging a motor vehicle component. The thermoplastic overmold helps prevent the reinforcement core from showing through to any visible show surface of the reinforced extrusion. | 2010-05-13 |
20100117258 | APPARATUS AND METHOD - A method and apparatus of production of tubes comprising, on an extruder, extruding molten plastics through die formations of a die head so as to extrude tubes each including at least one internal longitudinal web, and subsequently cooling the extruded tubes. In addition, when advancing molten plastics through a die hole ( | 2010-05-13 |
20100117259 | FABRICATION OF SMALL DIAMETER CONTINUOUS FIBERS - Methods of fabricating continuous nanofibers include the steps providing a column, flowing an extrusion liquid through the column, and flowing a precursor liquid through the extrusion liquid, wherein the flowing precursor liquid has a viscosity less than the viscosity of the extrusion liquid. The method further includes reducing the diameter of the flowing precursor liquid by extruding the precursor liquid through the extrusion liquid, wherein the diameter of the precursor liquid is reduced by a factor of at least 5, and forming a continuous nanofiber by solidifying the extruded precursor liquid. | 2010-05-13 |
20100117260 | Block press equipment having translating fluid injection apparatus and method of forming building blocks using same - A block press apparatus provides operations for forming a building block. An operation is performed for depositing a quantity of article-forming media within a media receiving cavity of article forming equipment. After depositing at least a portion of the article-forming media within the media receiving cavity, an operation performed for depositing a volume of a prescribed fluid into the media receiving cavity. Depositing the prescribed fluid includes moving a first fluid delivery device through the quantity of the article-forming media while injecting the prescribed fluid through the first fluid delivery device into the quantity of the article-forming media. | 2010-05-13 |
20100117261 | Method of making a plastic bench top - The method of making a plastic bench top is a method for manufacturing bench tops having a U-shaped channel formed by flanges depending from opposite sides of an elongated planar member. The bench top is mounted on pedestals, legs or the like. In general, the method includes forming a fold line by machining or by heating along the lateral edges of the elongated planar member to define flanges, folding the flanges so that the flanges are orthogonal to the planar member, and welding or fusing the joint, if necessary. Alternatively, discrete flange members may be heated simultaneously with the elongated lateral edges of the planar member, the heating element is withdrawn from between the flange and the planar member, and the flange is butted against the longitudinal edge to form a butt weld. | 2010-05-13 |
20100117262 | METHOD OF DUAL MOLDING PRODUCTS WITH LOGOS AND OTHER INDICIA - A method of dual injection molding is provided herewith. Generally, the method comprises the steps of providing a first mold to produce an inner portion of a product; forming the inner portion from a first plastic material such as polypropylene; providing an insert in the form of a logo or other indicia; combining the insert with the inner portion of the product; providing a second mold to receive the inner portion and insert combination; and injecting a second plastic material such as Santoprene® into the second mold around the core-insert combination, thereby forming a cover around the core and leaving at least one surface of the insert exposed so that it is visible. | 2010-05-13 |
20100117263 | MODULAR HANDRAIL CONSTRUCTION FOR A PASSENGER CONVEYOR HANDRAIL - A method of making a passenger conveyor handrail includes forming a drive member having a plurality of longitudinally spaced drive surfaces. The drive member has a longitudinal stiffness for maintaining a desired spacing between the drive surfaces. The drive member is inserted into a molding device. A gripping surface portion of the handrail is formed using the molding device such that the gripping surface portion and the drive member are secured together. Another method includes forming a belt drive member having a plurality of teeth that establish a plurality of longitudinally spaced drive surfaces. The belt has a longitudinal stiffness for maintaining a desired spacing between the drive surfaces. Each of the teeth extends across an entire width of the belt. The belt is secured to a gripping surface portion of the handrail. | 2010-05-13 |
20100117264 | COMPRESSION MOULDING METHOD FOR COMPOSITES, AND MOULD DEVICE FOR IMPLEMENTATION THEREOF - Compression molding method for composites including the step of forming a dough under pressure, including an amalgam of non-woven fibers randomly mixed and associated, in a defined proportion, with a thermosetting or thermoplastic material. The preparation of the dough includes mixing the fibers and the thermosetting or thermoplastic material, in a vacuum, while the forming operation is carried out by introducing the dough into a mould shaped and dimensioned to withstand high pressures. There is a molding cavity in the form of a part to be produced and provided with at least one well configured so as to accommodate, tightly, a plunger piston, which, by sliding, can pressurize the dough in the cavity, and therefore form the latter in the mould. | 2010-05-13 |
20100117265 | SIZING COMPOSITION FOR FIBERS, SIZED FIBERS AND METHOD OF USING TO MAKE MOLDING COMPOUNDS AND FRP MOLDED PRODUCTS - Disclosed are aqueous size compositions for reinforcing fibers containing very little or no polymer film formers, but comprising one or more coupling agents, one or more lubricants and optionally one or more other functional ingredients that do not include a resin polymer film former. Also disclosed are reinforcing fiber strands having such a sizing thereon, molding compounds containing these reinforcing fiber strands and methods of making the molding compounds and reinforced polymer composite products. | 2010-05-13 |
20100117266 | METHOD OF PROCESSING PLANT - One embodiment of the present invention includes: a step of setting a piece of a plant containing moisture inside a pressurizing apparatus and hermetically closing the internal space of the pressurizing apparatus; a step of applying a heat and a pressure to the piece of the plant; and a step of (i) enabling ventilation between the inside of the pressurizing apparatus and outside thereof after the piece of the plant reaches a predetermined molding temperature, (ii) retaining the pressure and the temperature for a predetermined period, (iii) cooling a molded article, and (iv) taking out the molded article from the pressurizing apparatus. This realizes a method for processing a plant which method makes it possible to mold a piece of a plant into a desired shape without reducing the piece of the plant into powder and without using an adhesive. | 2010-05-13 |
20100117267 | PROCESS FOR PELLETIZING PET - A pelletizing system and a method for pelletizing a polymer are disclosed. The method comprises the steps of compressing a quantity of polymer flake of a predetermined size to produce a pellet and heating at least one of the polymer flake and the pellet to remove contaminants therefrom. | 2010-05-13 |
20100117268 | FINE MOLD AND METHOD FOR REGENERATING FINE MOLD - A fine mold comprises a regeneration target film forming a convex part of a formation surface, and a light shielding unit that is configured deeper than a bottom of the formation surface and that regenerates the regeneration target film. A manufacturing cost of a product having a three-dimensional structure can be reduced. | 2010-05-13 |
20100117269 | COLLECTION TUBES APPRATUS, SYSTEMS, AND METHODS - Methods of producing collection tubes are presented. The methods include providing a separator substance that can rapidly polymerize in a short time to a desired hardness and disposing the separator substance within the lumen of the tube. The separator substance is formulated to have a density between an average density of a serum fraction of whole blood and a cell-containing fraction of whole blood, and to be flowable with whole blood. Upon centrifugation of a tube having blood, the separator substance forms a barrier between the whole blood fractions. The barrier rapidly hardens forming a solid barrier when triggered by a suitable energy source. | 2010-05-13 |
20100117270 | Extrusion molding technique and synthetic stopper produced therefrom - Exemplary embodiments of the invention provide an extrusion molding method and system that may be utilized to produce one or more objects having a desired shape, such as a shape suitable for a synthetic wine cork, for example. In one exemplary embodiment, a method includes: extruding a material including a blowing agent through a die; cutting the extruded material to obtain at least one piece; placing the at least one piece in a mold; and allowing the at least one piece to expand and cool within the mold in order to form a produced object, where the produced object has a predefined shape based on the mold. | 2010-05-13 |
20100117271 | Process for producing zinc oxide varistor - A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism. | 2010-05-13 |
20100117272 | Method Of Increasing Ceramic Paste Stiffening/Gelation Temperature By Using Organic Additive Urea - The present invention provides a ceramic precursor batch composition comprising inorganic ceramic-forming ingredients, a binder, an aqueous solvent and a chaotropic agent. The chaotropic agent can be urea, methylurea, ethylurea, n-butylurea, 1,3-dimethylurea, ethyleneurea, 1,1-dimethylurea, tetramethylurea, thiourea or mixtures thereof. The presence of the chaotropic agent provides a composition with a lower viscosity and/or a greater batch stiffening temperature allowing for increased rates of extrusion. Methods for producing a ceramic honeycomb body using the ceramic precursor batch composition of the present invention are also provided. | 2010-05-13 |
20100117273 | PROCESS FOR HOT-FORGING SYNTHETIC CERAMIC - The embodiments of the invention are directed to a synthetic ceramic comprising pyroxene-containing crystalline phase, a clast, and a glass phase, wherein at least a portion of the synthetic ceramic is plastically deformable in a certain temperature range. Other embodiments of the invention relate to a method of making a synthetic ceramic, comprising heating a green ceramic material to 900-1400° C., to a temperature sufficient to initiate partial melting of at least a portion of the green ceramic material, transferring the heated green ceramic material to a press, pressing the heated green ceramic material in a die at 1,000 to 10,000 psi, and transferring the heated, pressed green ceramic material to a furnace for cooling to form the synthetic ceramic. | 2010-05-13 |
20100117274 | AIR SPRINGS AND VULCANIZABLE COMPOSITIONS FOR PREPARING THE SAME - An air spring having an airsleeve, wherein at least one layer of said airsleeve includes the vulcanization product of a vulcanizable composition including an elastomer and a non-ionic surfactant. | 2010-05-13 |
20100117275 | DAMPING DEVICE - A vibration isolator includes layered rubbers interposed between a support body and a movable body, and a pair of dampers attached to the support body at one ends and to the movable body at the other ends. The layered rubbers are arranged to be spaced apart in an anterior and posterior direction and in a left and right direction, with reference to a direction in which an operator faces when seated. One of the dampers is arranged at a position corresponding to a middle of the left and right direction between the layered rubbers arranged in the left and right direction, and aligned in the anterior and posterior direction. The other one of the dampers is arranged closer to an anterior side than a middle of the anterior and posterior direction between the layered rubbers arranged in the anterior and posterior direction, and aligned in the lift and right direction. | 2010-05-13 |
20100117276 | BUMP STOPPER - To provide a bump stopper ( | 2010-05-13 |
20100117277 | SUSPENSION DEVICE - A suspension device S interposed between a sprung member B and an unsprung member W of a vehicle, comprising an actuator A, a hydraulic damper D, and a direction changing mechanism T for changing a linear motion of the actuator A into a linear motion in an opposite direction and transmitting the opposite linear motion to the hydraulic damper D. When a high-frequency vibration acts on the unsprung member, the drawback that the vibration is apt to be transmitted to the sprung member B under the influence of moment of inertia of the actuator A is remedied and it is possible to improve the ride comfort in the vehicle. | 2010-05-13 |
20100117278 | Vacuum sucker for workpiece having through holes - A vacuum sucker for workpiece having through holes comprises a vacuum cup and a vacuum accessory. The vacuum cup is provided with a combining section and a vacuum chamber. The vacuum accessory is provided with an assembling section and a suction head having an abutting surface. The vacuum accessory is defined with a passage, the assembling section of the vacuum accessory is screwed with the combining section of the vacuum cup, so that the suction head of the vacuum accessory is located in the vacuum chamber of the vacuum cup. Thereby, the abutting surface of the vacuum accessory can seal the through holes of the workpiece so as to prevent air from outside from entering the vacuum sucker, and the passage of the vacuum accessory is used to vacuum the vacuum chamber of the vacuum cup, thus sucking the workpiece successfully. | 2010-05-13 |
20100117279 | SUPPORTING SYSTEM AND A METHOD FOR SUPPORTING AN OBJECT - A supporting system, the system includes a vertically movable chuck and a stationary chuck; wherein the vertically movable chuck and the stationary chuck are concentric; wherein the vertically movable chuck vertically moves between an upper position and a lower position; wherein when the vertically movable chuck is positioned at the upper position an upper surface of the vertically movable chuck is higher than an upper surface of the stationary chuck and when the vertically movable chuck is positioned at the lower position the upper surface of the vertically movable chuck is lower than the upper surface of the stationary chuck. | 2010-05-13 |