20th week of 2009 patent applcation highlights part 43 |
Patent application number | Title | Published |
20090124030 | Nitride-Based Light-Emitting Device and Method of Manufacturing the Same - A nitride-based light-emitting device and a method of manufacturing the same. The light-emitting device includes a substrate, and an n-cladding layer, an active layer, a p-cladding layer, a grid cell layer and an ohmic contact layer sequentially formed on the substrate. The grid cell layer has separated, conducting particle type cells with a size of less than 30 micrometers buried in the ohmic contact layer. The nitride-based light-emitting device and the method of manufacturing the same improve the characteristics of ohmic contact on the p-cladding layer, thereby increasing luminous efficiency and life span of the device while simplifying a manufacturing process by omitting an activation process after wafer growth. | 2009-05-14 |
20090124031 | Flip-Chip Packaging Structure For Light Emitting Diode And Method Thereof - A packaging structure and method for a light emitting diode is provided. The present invention uses flip-chip and eutectic bonding technology to attach a LED to a thermal and electrical conducting substrate. The flip-chip packaging structure comprises a thermal and electrical conducting substrate having an insulating layer formed in an appropriate area on the top surface of the substrate and a bonding pad formed on top of the insulating layer; and a LED reversed in a flip-chip style and joined to the substrate by eutectic bonding. A first electrode of the LED is eutectically bonded to an appropriate area on the top surface of the substrate via a eutectic layer, while a second electrode of the LED is electrically connected to the bonding pad. | 2009-05-14 |
20090124032 | Penetrating hole type LED chip package structure using a ceramic material as a substrate and method for manufacturing the same - An LED chip package structure includes a ceramic substrate, a conductive unit, a hollow ceramic casing, many LED chips, and a package colloid. The ceramic substrate has a main body, many protrusions extended from the main body, many penetrating holes respectively penetrating through the protrusions, and many half through holes formed on a lateral side of the main body and respectively formed between each two protrusions. The conductive unit has many first conductive layers respectively formed on the protrusions, many second conductive layers respectively formed on inner surfaces of the half through holes and a bottom face of the main body, and many third conductive layers respectively filled in the penetrating holes. The hollow ceramic casing is fixed on the main body to form a receiving space. The LED chips is received in the receiving space. The package colloid is filled in the receiving space for covering the LED chips. | 2009-05-14 |
20090124033 | PROCESS FOR PRODUCING ORGANICLIGHT-EMITTING DISPLAY DEVICE - A position displacement between a substrate and a mask which is caused when the substrate and the mask are brought into close contact with each other is suppressed by a magnetic force. In a step of forming an organic compound layer (organic EL element film) included in an organic light-emitting display device on the substrate ( | 2009-05-14 |
20090124034 | Nanostructured Thin Films and Their Uses - The present invention generally discloses the use of a nanostructured non-silicon thin film (such as an alumina or aluminum thin film) on a supporting substrate which is subsequently coated with an active layer of a material such as silicon or tungsten. The base, underlying non-silicon material generates enhanced surface area while the active layer assists in incorporating and transferring energy to one or more analytes adsorbed on the active layer when irradiated with a laser during laser desorption of the analyte(s). The present invention provides substrate surfaces that can be produced by relatively straightforward and inexpensive manufacturing processes and which can be used for a variety of applications such as mass spectrometry, hydrophobic or hydrophilic coatings, medical device applications, electronics, catalysis, protection, data storage, optics, and sensors. | 2009-05-14 |
20090124035 | METHOD OF PRODUCING A SUSPENDED MEMBRANE DEVICE - A method for producing a device with at least one suspended membrane, comprising at least the following steps:
| 2009-05-14 |
20090124036 | METHOD OF PRODUCTION OF SEMICONDUCTOR DEVICE AND METHOD OF PRODUCTION OF SOLID-STATE IMAGING DEVICE - A method of production of a semiconductor device includes: forming a pattern having open element isolation regions on a first insulating film situated on a semiconductor substrate; forming trenches at the element isolation regions on the semiconductor substrate; forming a second insulating film on the first insulating film and inside the trenches; forming holes in the second insulating film in active regions sectioned by the element isolation regions; and leaving the second insulating film inside the trenches only. An interval between an outer perimeter of each the active regions and an outer perimeter of each of the holes in each of the active regions is set such that the interval in the first circuit region, in which a total area of the active regions is relatively large, is smaller than the interval in the second circuit region, in which the total area of the active regions is relatively small. | 2009-05-14 |
20090124037 | METHOD OF PREVENTING COLOR STRIATION IN FABRICATING PROCESS OF IMAGE SENSOR AND FABRICATING PROCESS OF IMAGE SENSOR - A fabricating process of an image sensor is provided. A substrate having thereon a circuit of the image sensor and an insulating layer is provided, wherein the insulating layer has therein a pad opening exposing a metal pad of the circuit. A filling layer is formed in the pad opening, and a color filter array is formed over the insulating layer. A planarization layer is formed over the substrate covering the color filter array, and a microlens array is formed on the planarization layer. The filling layer is then removed. | 2009-05-14 |
20090124038 | IMAGER DEVICE, CAMERA, AND METHOD OF MANUFACTURING A BACK SIDE ILLUMINATED IMAGER - A method of manufacturing a back side illuminated imager device comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a defect layer in the substrate; defining an image array proximate the front side after creating the defect layer; and cleaving proximate the defect layer after defining the image array. Other methods and apparatus are also provided. | 2009-05-14 |
20090124039 | LOW TEMPERATURE DEPOSITION OF PHASE CHANGE MEMORY MATERIALS - A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C. with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates. | 2009-05-14 |
20090124040 | FIELD EFFECT TRANSISTOR, METHOD OF PRODUCING THE SAME, AND METHOD OF PRODUCING LAMINATED MEMBER - There is provided a field effect transistor having an organic semiconductor layer, including: an organic semiconductor layer containing at least porphyrin; and a layer composed of at least a polysiloxane compound, the layer being laminated on the organic semiconductor layer so as to be in intimate contact with the organic semiconductor layer. As a result, there can be provided a field effect transistor which enables an organic semiconductor layer having high crystallinity and high orientation to be formed and which exhibits a high mobility. | 2009-05-14 |
20090124041 | RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. | 2009-05-14 |
20090124042 | ZnO BASED SEMICONDUCTOR DEVICE MANUFACTURE METHOD - A manufacture method for a ZnO based semiconductor device includes the steps of: (a) preparing a ZnO based semiconductor wafer including a ZnO based semiconductor substrate having a wurzeit structure with a +C plane on one surface and a −C plane on an opposite surface, a first ZnO based semiconductor layer having a first conductivity type epitaxially grown above the +C plane of the ZnO based semiconductor substrate, and a second ZnO based semiconductor layer having a second conductivity type opposite to the first conductivity type epitaxially grown above the first semiconductor layer; and (b) wet-etching the ZnO based semiconductor wafer with acid etching liquid to etch the −C plane of the ZnO based semiconductor substrate | 2009-05-14 |
20090124043 | Method of manufacturing a package board - A method of manufacturing a package board is disclosed. The method is for manufacturing a package board that has a pad electrically connected with a component, and includes: forming an indentation, which is in correspondence with the pad, in one side of a first insulating layer; filling a metal paste in the indentation; mounting the component on the first insulating layer in correspondence with a location of the indentation; and hardening the metal paste. Using this method, damage to the component can be prevented during the forming of vias, as the component is mounted after filling paste in an indentation formed in an insulating layer. | 2009-05-14 |
20090124044 | Method for removing bubbles from adhesive layer of semiconductor chip package - In a method for removing bubbles from adhesive layer of semiconductor chip package, one or more semiconductor chips are attached to or stacked on a base plate using an adhesive material. The base plate is selected from a substrate, a lead frame, and other carrier for carrying the semiconductor chips thereon. Before the adhesive material starts curing or becomes fully cured, the base plate with the semiconductor chips is placed in a processing tank which is preset to heat at a predetermined heating rising rate to a predetermined temperature and to apply a predetermined pressure for a predetermined period of time, so that bubbles presented in the adhesive material, at an interface between the adhesive material and the base, and at an interface between the adhesive material and the semiconductor chip are expelled from the adhesive material under the temperature and pressure in the processing tank. | 2009-05-14 |
20090124045 | Low Profile Stacking System and Method - The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile. | 2009-05-14 |
20090124046 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in which a functional element is disposed; a step C that removes the first transforming portion that is disposed on the first substrate by etching; and a step D that forms a conductive portion in the first substrate by filling a conductive material in a portion where the first transforming portion has been removed. | 2009-05-14 |
20090124047 | STACKED IMAGE METHOD - An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light. | 2009-05-14 |
20090124048 | Semiconductor device and method of manufacturing semiconductor device - A semiconductor device is configured of a semiconductor chip which is sandwiched by first and second resin films having a wiring pattern. Plural semiconductor chips can be fabricated collectively by sandwiching the semiconductor chips by the first and second resin films, and productivity can be improved. | 2009-05-14 |
20090124049 | Deletable nanotube circuit - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. | 2009-05-14 |
20090124050 | METHOD OF MANUFACTURING NANOWIRES PARALLEL TO THE SUPPORTING SUBSTRATE - A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method comprising:
| 2009-05-14 |
20090124051 | THIN-FILMED FIELD EFFECT TRANSISTOR AND MAKING METHOD - In a thin-film field effect transistor with a MIS structure, the materials of which the semiconductor and insulating layers are made are polymers which are dissolvable in organic solvents and have a weight average molecular weight of more than 2,000 to 1,000,000. Use of polymers for both the semiconductor layer and insulating layer of TFT eliminates such treatments as patterning and etching using photoresists in the prior art circuit-forming technology, reduces the probability of TFT defects and achieves a reduction of TFT manufacture cost. | 2009-05-14 |
20090124052 | METHOD OF FABRICATING MEMORY CELL - A method of fabricating a memory cell includes following steps. First, a substrate is provided, and a control gate is formed on the substrate. Then, a dielectric layer is formed to cover the control gate and the substrate. Afterward, an α-SiGe layer is formed on the dielectric layer. After that, a laser annealing process is performed to oxidize the α-SiGe layer into a silicon oxide layer, so as to separate out Ge atoms from the α-SiGe layer to form a Ge quantum dot layer between the silicon oxide layer and the dielectric layer. A poly-Si island is then formed on the silicon oxide layer, wherein the poly-Si island includes a source doped region, a drain doped region, and a channel region located therebetween. | 2009-05-14 |
20090124053 | FABRICATION OF NANOWIRES AND NANODEVICES - Methods of fabricating nanowire structures and nanodevices are provided. The methods involve photolithographically depositing a nucleation center on a crystalline surface of a substrate, generating a nanoscale seed from the nucleation center, and epitaxially growing a nanowire across at least a portion of the crystalline surface starting at a nucleation site where the nanoscale seed is located. | 2009-05-14 |
20090124054 | METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING - A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications. | 2009-05-14 |
20090124055 | Transistor structure and method for making same - A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure. | 2009-05-14 |
20090124056 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure. | 2009-05-14 |
20090124057 | DAMASCENE GATE FIELD EFFECT TRANSISTOR WITH AN INTERNAL SPACER STRUCTURE - A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure. | 2009-05-14 |
20090124058 | Method of Providing Electrical Separation in Integrated Devices and Related Devices - An integrated device includes two sections (A, B), such as a DFB laser (A) and an EAM modulator (B), having a semi-insulating (SI) separation region therebetween. The separation region ( | 2009-05-14 |
20090124059 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer. | 2009-05-14 |
20090124060 | Method for manufacturing silicon carbide semiconductor apparatus - A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished. | 2009-05-14 |
20090124061 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprises forming an isolation trench on a semiconductor substrate, exposing a silicon surface of the isolation trench formed on the semiconductor substrate, filling a first insulating film into the semiconductor substrate by means of TEOS/O | 2009-05-14 |
20090124062 | DISPLAY DEVICE HAVING A CURVED SURFACE - The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed. | 2009-05-14 |
20090124063 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device by which a wafer with devices formed in a plurality of regions demarcated by a plurality of streets formed in a grid pattern in the face-side surface of the wafer is divided along the streets into individual devices, and an adhesive film for die bonding is attached to the back-side surface of each of the devices. The adhesive film is attached to the back-side surface of the wafer divided into individual devices by exposing cut grooves formed along the streets by a dicing-before-grinding method, and thereafter the adhesive film is irradiated with a laser beam along the cut grooves through the cut grooves from the side of a protective tape adhered to the face-side surface of the wafer, so as to fusion-cut the adhesive film along the cut grooves. | 2009-05-14 |
20090124064 | PARTICLE BEAM ASSISTED MODIFICATION OF THIN FILM MATERIALS - Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase. | 2009-05-14 |
20090124065 | PARTICLE BEAM ASSISTED MODIFICATION OF THIN FILM MATERIALS - Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase. | 2009-05-14 |
20090124066 | PARTICLE BEAM ASSISTED MODIFICATION OF THIN FILM MATERIALS - Several examples of a method for processing a substrate are disclosed. In a particular embodiment, the method may include: disposing a substrate having an upper surface and a lower surface on a platen contained in a chamber; generating a plasma containing a plurality of charged particles above the upper surface of the substrate, the plasma having a cross sectional area equal to or greater than a surface area of the upper surface of the substrate; applying a first bias voltage to the substrate to attract the charged particles toward the upper surface of the substrate; introducing the charged particles to a region extending under entire upper surface of the substrate; and initiating, concurrently, a first phase transformation in the region from the amorphous phase to a crystalline phase. | 2009-05-14 |
20090124067 | METHOD TO DECREASE THIN FILM TENSILE STRESSES RESULTING FROM PHYSICAL VAPOR DEPOSITION - A method and apparatus for a backside metallization of a wafer is provided. The wafer comprised of a first substance is bent by creating tension on a backside and creating compression on a front side prior to deposition of a thin film of a second substance. After deposition, the wafer is released and the thin film deposited on the wafer exhibits less tensile stress than if the thin film was deposited on a flat wafer. | 2009-05-14 |
20090124068 | Non-Uniformly Doped High Voltage Drain-Extended Transistor and Method of Manufacture Thereof - The present invention provides, in one embodiment, a transistor ( | 2009-05-14 |
20090124069 | METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION - A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction. | 2009-05-14 |
20090124070 | Methods of Manufacturing Semiconductor Devices Including Metal Oxide Layers - Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature. | 2009-05-14 |
20090124071 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer. | 2009-05-14 |
20090124072 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 2009-05-14 |
20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 2009-05-14 |
20090124074 | WAFER LEVEL SENSING PACKAGE AND MANUFACTURING PROCESS THEREOF - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 2009-05-14 |
20090124075 | Method of manufacturing a wafer level package - A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved. | 2009-05-14 |
20090124076 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure. | 2009-05-14 |
20090124077 | Method for forming poly-silicon film - A poly-silicon film formation method for forming a poly-silicon film doped with phosphorous or boron includes heating a target substrate placed in a vacuum atmosphere inside a reaction container, and supplying into the reaction container a silicon film formation gas, a doping gas for doping a film with phosphorous or boron, and a grain size adjusting gas containing a component to retard columnar crystal formation from a poly-silicon crystal and to promote miniaturization of the poly-silicon crystal, thereby depositing a silicon film doped with phosphorous or boron on the target substrate. | 2009-05-14 |
20090124078 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH THROUGH HOLE - A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate. | 2009-05-14 |
20090124079 | METHOD FOR FABRICATING A CONDUCTIVE PLUG - A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure. | 2009-05-14 |
20090124080 | SEMICONDUCTOR DEVICE THAT IS ADVANTAGEOUS IN MICROFABRICATION AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes. | 2009-05-14 |
20090124081 | Techniques to Improve Characteristics of Processed Semiconductor Substrates - Techniques to improve characteristics of processed semiconductor substrates are described, including cleaning a substrate using a preclean process, the substrate comprising a dielectric region and a conductive region, introducing a hydroquinone to the substrate after cleaning the substrate using the preclean operation, and forming a capping layer over the conductive region of the substrate after introducing the hydroquinone. | 2009-05-14 |
20090124082 | SLURRY FOR POLISHING RUTHENIUM AND METHOD FOR POLISHING USING THE SAME - A slurry for polishing a ruthenium layer comprises distilled water, sodium periodate (NaIO | 2009-05-14 |
20090124083 | Film formation apparatus and method for using same - A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate while supplying a film formation reactive gas from a first nozzle inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited inside the reaction chamber and the first nozzle, in a state where the reaction chamber does not accommodate the target substrate. The cleaning process includes, in order, an etching step of supplying a cleaning reactive gas for etching the by-product film into the reaction chamber, and activating the cleaning reactive gas, thereby etching the by-product film, and an exhaust step of stopping supply of the cleaning reactive gas and exhausting gas from inside the reaction chamber. The etching step is arranged to use conditions that cause the cleaning reactive gas supplied in the reaction chamber to flow into the first nozzle. | 2009-05-14 |
20090124084 | FABRICATION OF SUB-RESOLUTION FEATURES FOR AN INTEGRATED CIRCUIT - A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set. | 2009-05-14 |
20090124085 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAS A LENGTHENED CHANNEL LENGTH - The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate. | 2009-05-14 |
20090124086 | METHOD OF FABRICATING A FLASH MEMORY DEVICE - A method of fabricating a flash memory device, in which a pre-metal dielectric layer, a hard mask layer, and a first etch mask pattern are sequentially formed over a semiconductor substrate; an auxiliary layer is formed along a surface of the first etch mask pattern and the hard mask layer; and an etch mask layer is formed on the auxiliary layer to gap-fill between adjacent first etch mask pattern elements. The etch mask layer is etched to form a second etch mask pattern between adjacent first etch mask pattern elements. The auxiliary layer between the first and second etch mask patterns is removed; and a hard mask pattern is formed by etching the hard mask layer between the first etch mask pattern and the second etch mask pattern. The pre-metal dielectric layer is etched process using the hard mask pattern as a mask to form contact holes. | 2009-05-14 |
20090124087 | Vertical plasma processing apparatus and method for using same - A vertical plasma processing apparatus for a semiconductor process for performing a plasma process on target substrates all together includes an exciting mechanism configured to turn at least part of a process gas into plasma. The exciting mechanism includes first and second electrodes provided to a plasma generation box and facing each other with a plasma generation area interposed therebetween, and an RF power supply configured to supply an RF power for plasma generation to the first and second electrodes and including first and second output terminals serving as grounded and non-grounded terminals, respectively. A switching mechanism is configured to switch between a first state where the first and second electrodes are connected to the first and second output terminals, respectively, and a second state where the first and second electrodes are connected to the second and first output terminals, respectively. | 2009-05-14 |
20090124088 | METHOD FOR ETCHING A SACRIFICIAL LAYER FOR A MICRO-MACHINED STRUCTURE - A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species. | 2009-05-14 |
20090124089 | Device and Method for Stopping an Etching Process - A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being different from the second etchant. | 2009-05-14 |
20090124090 | CONDUCTIVE POLYMER ELECTRODES - A known method of forming organic semiconductor devices employs the deposition of a conductive polymer onto a substrate to form electrodes or conductive tracks and then to apply an electrical material such as an organic semiconductor on top of these tracks. Although the conductive polymer serves as a highly efficient injector of electrons into the semiconductor, it is not a good conductor. This introduces undesirable inefficient in the supply of current to and from the semiconductor. Worse still the conductivity may deteriorate with time. A solution to this problem has been found by printing the polymer ( | 2009-05-14 |
20090124091 | ETCHING SOLUTION COMPOSITION FOR METAL FILMS - The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof. | 2009-05-14 |
20090124092 | METHODS OF SELECTIVE DEPOSITION OF FINE PARTICLES ONTO SELECTED REGIONS OF A SUBSTRATE - A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst. | 2009-05-14 |
20090124093 | Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities - A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors. | 2009-05-14 |
20090124094 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE TO PREVENT DEFECTS DUE TO INSULATION LAYER VOLUME CHANGE - A semiconductor device is made by forming patterns on a semiconductor substrate. After forming the patterns, sequentially forming a spacer layer, an oxidation promotion layer and a buffer layer on the semiconductor substrate including the surfaces of the patterns previously formed. An insulation layer is then formed on the buffer layer to fill the patterns. The semiconductor substrate including the insulation layer is subsequently annealed such that the buffer layer is oxidized and the insulation layer is baked. | 2009-05-14 |
20090124095 | METHOD FOR FORMING PATTERNED PHOTORESIST LAYER - A method for forming a patterned photoresist is provided, which is applicable to a substrate. The method includes: performing an implantation process over the substrate; next, performing a surface treatment process; then, forming a photoresist layer over the substrate; and thereafter, patterning the photoresist layer. | 2009-05-14 |
20090124096 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present invention relates to a method of fabricating a flash memory device, the method of the present invention comprises the steps of forming a tunnel insulating layer on a semiconductor substrate through a plasma oxidation process and performing a nitridation treatment to a surface of the tunnel insulating layer. | 2009-05-14 |
20090124097 | METHOD OF FORMING NARROW FINS IN FINFET DEVICES WITH REDUCED SPACING THEREBETWEEN - A method of forming narrow fins in a substrate includes forming a sacrificial mandrel layer over the substrate; using a photolithographic process to pattern the mandrel layer so as to perform a plurality of mandrel features having an initial width greater than or equal to F and spacing therebetween of greater than or equal to F, wherein F corresponds to a minimum feature size associated with the photolithographic process; performing a thermal oxidation of sidewall surfaces of the mandrel features so as to form a plurality of oxide pillars, wherein the thermal oxidation consumes a portion of the mandrel material, and wherein the plurality of oxide pillars have both a width and a spacing therebetween that is less than F; removing remaining portions of the material; and transferring a pattern defined by the oxide pillars into the semiconductor substrate so as to form a plurality of fins having both a width and a spacing therebetween that is less than F. | 2009-05-14 |
20090124098 | COMBINATION TYPE SLIP RING - A combination type slip ring includes a base, a plurality of conductive members, conductive rings, and insulating rings. Each of the conductive members has a slot for connection of the conductive members respectively. Each of the insulating rings has an axial hole at a center thereof, and a plurality of bores and a slot around the axial hole. The conductive rings are fitted to the insulating rings in sequence with the conductive members received in the slots and the insulating rings passing through the corresponding bores of other insulating rings that the conductive members have distal ends thereof out of said insulating ring. | 2009-05-14 |
20090124099 | PCB with improved soldering holes and a battery set with the same - A printed circuit board (PCB), which can be implemented on a battery set, having a plurality of soldering holes thereon. A soldering portion and a non-soldering portion are separately arranged around each of the soldering holes on both surfaces of the PCB. Each corresponding conductive stick can respectively pierce each soldering hole and be fixed to each soldering portion of the PCB with the fused solder or move from the soldering portion to the non-soldering portion in the soldering hole. Thus, this invention provides a convenient and efficient way for assembling the PCB on the battery set or disassembling the PCB apart from the battery set. | 2009-05-14 |
20090124100 | SHIELDED ELECTRICAL INTERCONNECT - An electrical interconnect includes a contact array having an insulator holding a plurality of contacts. Each of the contacts include a conductive polymer column having first and second opposite contact tips for interconnecting first and second electronic packages, wherein each of the contacts are individually shielded from adjacent ones of the contacts. Optionally, a frame may be provided on the insulator and positioned between each of the contacts, wherein the frame defines a shield concentrically surrounding each of the contacts. The frame may be conductive and non-coplanar with, and parallel to, the insulator, wherein the frame is electrically isolated from the contacts and provides shielding between adjacent ones of the contacts. | 2009-05-14 |
20090124101 | ELECTRICAL CONNECTOR SYSTEM WITH JOGGED CONTACT TAILS - Connector systems include electrical connectors orthogonally connected to each other through shared through-holes in a midplane. An orthogonal vertical connector includes jogged contacts to offset for or equalize the different length contacts in the right-angle connector to which the vertical connector is connected. A first contact in the right angle connector may mate with a first contact in the vertical connector. A second contact in the right angle connector may mate with a second contact in the vertical connector. The first contact in the right angle connector may be greater in length than the adjacent second contact of the right angle connector. Thus, the second contact of the vertical connector may be jogged by the distance to increase the length of the second contact by the distance. | 2009-05-14 |
20090124102 | Electrical connector with reduced stress between contacts and housing - A conductive contact ( | 2009-05-14 |
20090124103 | Method and apparatus for providing symmetrical signal return path in differential systems - A circuit board and connector for use in an electrical connector has been provided. The circuit board comprises first and second signal contacts associated as a differential pair. A ground contact is located immediately adjacent the first signal contact and is joined directly to a ground plane provided within the circuit board. A floated contact is located immediately adjacent the second signal contact. A component interconnects the floated contact to the ground plane, forming an open circuit when a DC signal is impressed on the floated contact and a closed circuit when AC interference is impressed on the floated contact. | 2009-05-14 |
20090124104 | Flash memory device with a retractable plug - A flash memory device ( | 2009-05-14 |
20090124105 | Self-Aligning Electrical Contact And Related Methods - The present invention generally relates to self-aligning electrical coupling devices and related methods. For example, one embodiment can include an aligning means for aligning a central axis of a male connector component with a central axis of a female connector component. The embodiment can also include a rotationally-aligning means for rotationally aligning a male connector component with a female connector component so as to achieve a predetermined rotational orientation. Some embodiments can also an electrically-communicating means for electrically communicating between the male connector component and the female connector component. Some embodiments relate to processes for assembling self-aligning electrical coupling device. | 2009-05-14 |
20090124106 | FLAT CIRCUIT CONNECTOR - An electrical connector is provided for terminating a flat electrical circuit. The connector includes a dielectric housing having an opening at a front portion thereof for receiving an end of the flat circuit, along with a rear terminating portion. A plurality of terminals are mounted on the housing in a side-by-side array spaced along the opening. An actuator is movably mounted relative to the housing for movement between an open position allowing the end of the flat circuit to be inserted into the opening and a closed position to relatively bias the flat circuit against the terminals. The actuator has a dust cover portion for covering the rear terminating portion of the housing when the actuator is in its closed position. | 2009-05-14 |
20090124107 | Electrical connector having matched impedance by contacts having node arrangement - An electrical connector includes an insulative housing and a number of conductive contacts received in the insulative housing. Each conductive contact has a contacting portion, an engaging portion and an extension portion electrically connecting with the contacting portion and the engaging portion. A node is disposed in the extension portion for matching characteristic impedance of the conductive contact, and a positioning portion is disposed in the insulative housing corresponding to the node for cooperating with the node to restrict movement of the node. The electrical connector in accordance with the present invention can match characteristic impedance of the conductive contact to realize impedance match and can assure precise positioning of the conductive contact. | 2009-05-14 |
20090124108 | Insertable card format - A housing and memory card, usable to store data, and where the operation connects directly to contacts on the memory devices that are housed within the card. The pinouts can be usb pinouts. | 2009-05-14 |
20090124109 | Conductor with Simplified Assembly for Multi-Conductor Cable - The invention concerns a connector designed to be fitted to a multi-conductor cable and which comprises at least one socket, a cable grip formed by a portion connected to the socket and a free portion articulated on the connected portion, and assembly means. The assembly means comprise a lever articulated around an articulation axis, held by the socket and distant from the articulation axis of the grip, wherein this lever has a curved end that may exert on the external surface of the free portion of the grip a thrust force which solicits the grip when closing in response to the application, on the lever, of a rotational torque around the articulation axis. | 2009-05-14 |
20090124110 | RESTRICTION MECHANISM FOR CARD - A restriction mechanism for a card is provided. The card includes at least one electronic component mounted thereon. The restriction mechanism includes a substrate, a slot, a latch, and a restriction member. The slot allows the card to be inserted in the slot. The latch is pivotally connected to one side of the slot. The latch is rotatable between a first position in which the card is locked in the slot by the latch, and a second position in which the card is allowed to disengage from the slot. The restriction member is used to prevent the latch from being rotated to the second position. | 2009-05-14 |
20090124111 | Plug-In Unit For Supplying And Controlling An Electric Motor - A plug-in unit to be inserted in a housing carrying comb connectors of an electric motor, includes motor connectors ( | 2009-05-14 |
20090124112 | Transparent Insulating Enclosure - An enclosure formed from a first compartment and an identical second compartment to house an electrical connector. Each compartment has a main body that is defined by a first wall, a second wall and ends. The first wall of each compartment has an outer tab with at least one projection that extends inwards and an inner tab positioned adjacent to the outer tab. The second wall of each compartment has an aperture. When the compartments are mounted to each other to form the enclosure, the projection of the first wall of the first compartment is disposed in the aperture in the second wall of the second compartment and the projection of the first wall of the second compartment is disposed in the aperture in the second wall of the first compartment. The enclosure also includes a label and label cover that are disposed inside the enclosure to identify the connector. | 2009-05-14 |
20090124113 | FLAT WIRE EXTENSION CORDS AND EXTENSION CORD DEVICES - Flat wire extension cords and extension cord devices are provided. A flat wire extension cord includes an elongated cord, a first connected attached to a first end of the elongated cord, and a second connected attached to an opposite end of the elongated cord. The elongated cord includes at least one electrifiable conductor for delivering electrical power, first and second insulating layers formed on opposing sides of the at least one electrifiable conductor, and first and second return conductors formed on the first and second insulating layers, respectively, such that said at least one electrifiable conductor is at least substantially entrapped by said first and second return conductors. The first connector is operable to connect the conductors of the elongated cord to a line side input, and the second connector is operable to connect the conductors of the elongated cord to a load. | 2009-05-14 |
20090124114 | CONNECTOR - A locking projection ( | 2009-05-14 |
20090124115 | Strain Relief Collar for Accessories Associated with Mobile Device and Method of Making - The present invention discloses a strain relief collar for use with an accessory associated with a mobile device and its method of making. The first step is the making of an outer molded body. The second step is inserting a cord into the outer molded body. The third step is the forming of an inner molded body. The present invention also discloses another strain relief collar for use with another accessory associated with a mobile device and its method of making. The first step is connecting the cord to an electrical component associated with the accessory. The second step is the forming of an inner molded body. The third step is the forming of an outer molded body. | 2009-05-14 |
20090124116 | Wire containment cap with an integral strain relief clip - A wire containment cap for reducing horizontal strain on a cable terminated at a communication jack. The wire containment cap is part of the communication jack and includes a strain relief clip that may be actuated to apply pressure to the cable. The applied pressure holds the cable in place and helps prevent wire pairs of the cable from pulling out of terminals in the communication jack. | 2009-05-14 |
20090124117 | PLUG CONNECTOR - The invention relates to a plug connector ( | 2009-05-14 |
20090124118 | BATTERY TERMINAL CONNECTOR - A cable connector having a one-piece body with a termination end for terminating an electrical cable and a clamping end for clamping to a terminal post is provided. The cable connector's clamping end may include a pair of spaced apart deformably movable clamping arms for supporting the terminal post therebetween. A lever attached to the movable arms may also be provided where the lever may be actuable between a first position urging the arms towards one another to clamp the clamping end to the terminal post and a second position urging the arms apart so as to unclamp the arms from the terminal post to permit removal of the connector body from the terminal post. | 2009-05-14 |
20090124119 | Watt Hour Meter Socket Adapter with Current Transformer Housing Structure - A meter socket adapter includes an insulating housing that is connected to a power circuit on one side by bus bars and connected to a watt-hour meter on the other side by jaw contacts. The housing includes insulating compartments for current transformers through which the bus bars extend. Current transformers extend around the bus bars and are housed in individual compartments in the current transformer housing. Transformed current is directed to the jaw contacts for metering with the watt-hour meter. The bus bars include an insulating layer there on, reducing the need for insulation around the secondary of the current transformers. The current transformers are then significantly smaller and fit within a K-Base meter socket. The adapter housings define a cavity with separate dielectric plates between the bus bars and the jaw contacts. The adapter conveniently allows for self-contained meters to be used in high current installations. | 2009-05-14 |
20090124120 | STACKABLE CONNECTOR ASSEMBLY - This invention discloses a stackable connector assembly, which includes a first connector, a second connector, a shielding member, a contact member, and a ground member. The second connector is placed above the first connector. The shielding member is covered on the first connector. The contact member is used for connecting the shielding member and the ground member. This structure can reduce the electromagnetic radiation from the first connector. | 2009-05-14 |
20090124121 | CONNECTOR FOR A DEVICE - A connector for device is for supplying power to a device accommodated in a metallic casing (C) and provided with a housing ( | 2009-05-14 |
20090124122 | Apparatus for Applying A Load - An apparatus for the application of a test load apparatus | 2009-05-14 |
20090124123 | WATERPROOF PLUG FOR CONNECTOR, WATERPROOF CONNECTOR COMPRISING THE SAME AND METHOD OF ATTACHING THE SAME - A waterproof plug for a connector, includes an elastically deformable seal member for sealing a housing which houses terminals fixed at edges of electric cables in the inside thereof. The seal member is housed inside the housing by press-fitting, and has at least two elements holding the electric cables by sandwiching from both sides and tightly contacting with outer peripheral surfaces thereof. | 2009-05-14 |
20090124124 | Electrical connector with shell interferentially engaged with portion of the connector - An electrical connector ( | 2009-05-14 |
20090124125 | AUGMENTED SMALL FORM-FACTOR CONNECTOR - A connector that is structured to electrically and physically connect with (i) a first connector type using a first set of electrical contacts, and (ii) a second connector type that uses the first set of electrical contacts and a second augmenting set of electrical contacts. | 2009-05-14 |
20090124126 | SIM CARD CONNECTOR APPARATUS OF PORTABLE WIRELESS TERMINAL - A SIM card connector of a portable wireless terminal has a structure that forms a space thereunder using its lower edges to place electronic parts of a printed circuit board (PCB) within the space, so that the PCB can increase its space efficiency. The SIM card connector further forms an electromagnetic wave shield around the space, so that the electromagnetic wave shield can block electromagnetic waves generated from the electronic parts. | 2009-05-14 |
20090124127 | Conductive cage - A conductive cage ( | 2009-05-14 |
20090124128 | Edge card connector assembly with high-speed terminals - A surface mount connector for high speed data transfer application has an insulative housing with a vertically-oriented circuit card-receiving slot disposed along a front face thereof. A plurality of conductive terminals are supported by the housing so that contact portions of the terminals extend into the card slot. The terminals are formed with a thin configuration to reduce the overall capacitance of the terminals as a group as a means of regulating the impedance thereof. The terminals are supported on opposing sidewalls of the connector housing and each of the terminals includes a tail portion, a contact portion and a retention portion that engages the connector housing so that the contact portions are cantilevered in their extent within the housing. | 2009-05-14 |
20090124129 | REMOVABLE STORAGE DEVICE - An adapter for removable memory cards including a housing configured to receive a memory card, a connector for connection to a host system, an interface circuit interconnecting the memory card and connector and adapted to allow communication therebetween and at least one movable cover pivotably engaged with the housing and which, in a closed position, with the housing, defines a substantially enclosed cavity configured to retain the memory card. The adapter has a generally rounded and smooth outer contour and is relatively small and light weight to provide convenient carry on the person. The adapter is made of strong materials and by fully enclosing the memory card provides a physically robust removable storage device. | 2009-05-14 |