20th week of 2015 patent applcation highlights part 31 |
Patent application number | Title | Published |
20150131326 | LED Light With Special Effects - An LED light device with special effects utilizes persistence of vision theory to cause an LED(s) or LED array to change faster than the human eye response time of 1/16 to 1/24 second to display a special message, time, drawing, light patterns, or color changes. In addition, the light device may be provided with a sealed-unit arranged to receive a variety of eye-catching shades. | 2015-05-14 |
20150131327 | Solid State Lamp Using Modular Light Emitting Elements - A solid state lamp, such as one that can replace an incandescent light bulb, has a base portion having an electrical connector for connection to a source of power, such as an Edison-type connector for connection to the mains voltage. An AC/DC converter in the base converts the mains voltage to a suitable light emitting diode (LED) drive voltage. A plurality of receptacles on the base connects to electrodes of plug-in modules. Each plug-in module supports a plurality of low power LEDs connected in series. The strings of LEDs on different modules are connected in parallel when connected to the receptacles. The modules and base are configured to allow a user to operate the lamp with different combinations of modules to generate a desired light output from the lamp. For example, the user can recreate the lumens equivalent of a 20W, 40W, or 60W bulb by using one, two, or three modules. | 2015-05-14 |
20150131328 | SYSTEM AND METHOD FOR POWER CONVERSION - A power conversion system is presented. The system includes a power source coupled to a power converter and a controller. The controller is configured to determine a value of at least one parameter corresponding to the power source. Additionally, the controller is configured to provide a first portion of the at least one parameter to the power converter and modify an operating frequency of the power converter, duty ratio of the power converter, or a combination thereof. Furthermore, the controller is configured to obtain an electrical quantity at an output of the power converter based on the modified operating frequency, the modified duty ratio, or a combination thereof. Also, the controller is configured to deliver a combination of the electrical quantity obtained at the output of the power converter and a second portion of the at least one parameter to a load. Method for converting power is also presented. | 2015-05-14 |
20150131329 | Gate Drive Apparatus for Resonant Converters - An apparatus comprises a bridge coupled between a bias voltage and ground, wherein the bridge comprises a first switch and a second switch connected in series and coupled between the bias voltage and ground and a third switch and a fourth switch connected in series and coupled between the bias voltage and ground, a resonant device coupled to the bridge, wherein the resonant device comprises a fixed capacitance, a gate capacitance and a magnetizing inductance, a transformer coupled to the resonant device, wherein the transformer comprises a primary winding and a plurality of secondary windings. | 2015-05-14 |
20150131330 | BIDIRECTIONAL DC-DC CONVERTER SYSTEM AND CIRCUIT THEREOF - The invention discloses a bidirectional dc-dc converter system and circuit thereof. In boost mode, topology is combined with interleaved two-phase boost converter for providing a higher step-up voltage gain. In buck mode, topology is combined with interleaved two-phase buck converter in order to get a higher step-down conversion ratio. The main objectives of the invention are aimed to both store energy in the blocking capacitors (C | 2015-05-14 |
20150131331 | APPARATUS AND METHOD FOR SUPPLYING POWER - Disclosed is an apparatus for supplying power to a device. The apparatus includes a transformer configured to output a predetermined voltage to a device varying in load; a switch configured to switch on and off the voltage output from the transformer in accordance with pulse width modulation (PWM) signals; a PWM signal supplier configured to supply the PWM signal to the switch; a feedback circuit which detects the output from the transformer and applies a control signal to the PWM signal supplier; and an output voltage controller which detects a load current of the device, and adjusts the control signal of the feedback circuit by adjusting the output detected by the feedback circuit in accordance with the detected load current. | 2015-05-14 |
20150131332 | ELECTRONIC APPARATUS AND POWER CONTROLLING METHOD THEREOF - Disclosed are an electronic apparatus and a power controlling method thereof, the electronic apparatus including a system portion configured to operate with a received voltage, and a power supply including a pulse width modulation (PWM) generator to generate a PWM signal, a converter to transfer voltage from a primary side to a secondary side in accordance with an output voltage of the PWM generator, and an output portion to supply voltage at the secondary side as standby voltage to the system portion, the PWM generator receives feedback on the standby voltage at the secondary side of the converter, the PWM signal is turned on/off in accordance with levels of the standby voltage at the secondary side, and voltage being supplied to components, except, when the PWM signal is turned off, voltage at the secondary side is only supplied to a component that monitors the feedback of the standby voltage. | 2015-05-14 |
20150131333 | DC-DC CONVERTER WITH MULTIPLE OUTPUTS - A multiple output DC-DC converter comprises a transformer, a primary circuit, a plurality of secondary circuits, and a controller. The transformer has a primary and at least one secondary winding. The primary circuit connects to a DC power supply source and includes the primary winding of the transformer and a primary switch connected in series. The plurality of secondary circuits includes the at least one secondary winding of the transformer, wherein each secondary circuit provides a DC power supply output, and at least one of the secondary circuits has a secondary switch. The controller monitors an output signal of each secondary circuit and controls operation of the primary and secondary switches based on the monitored signals. The controller co-ordinates operation of the secondary switch with the primary switch, such that the primary switch and the secondary switch are switched on simultaneously, or with a controlled offset. | 2015-05-14 |
20150131334 | SWITCHING POWER SUPPLY APPARATUS AND SEMICONDUCTOR DEVICE - Provided is a switching power supply apparatus that shifts to an OFF mode when electronic equipment is on standby, and includes: an OFF mode delay circuit that delays shifting to the OFF mode; and an electric storage unit and a power supply circuit that function as a power supply source of an OFF mode control circuit. With the configuration, the power consumption can almost be eliminated, and the switching power supply apparatus can start without any charge in an electricity storage component such as a primary battery or a secondary battery. | 2015-05-14 |
20150131335 | POWER SUPPLY CIRCUIT, ELECTRONIC PROCESSING APPARATUS, AND POWER SUPPLY METHOD - A power supply circuit includes: an environment detecting circuit which detects an installation environment; and a voltage control circuit which makes a report of a power supply capability by performing fluctuation control of an output voltage in response to detection information of the environment detecting circuit. | 2015-05-14 |
20150131336 | DUAL-EDGE TRACKING SYNCHRONOUS RECTIFIER CONTROL TECHNIQUES FOR A RESONANT CONVERTER - This disclosure provides control techniques for a resonant converter. In one control technique, for switching speeds that are below the resonant frequency of the primary stage of the converter, the switches of the synchronous rectifier (SR) portion (SR switches) of the resonant converter are controlled based on a rising edge of the corresponding primary side switch and the turn off time of a corresponding SR switch. In general, for below resonance operation, each corresponding SR switch will be turned off prior to the falling edge of each corresponding primary side switch, while each corresponding SR switch will be turned on at the rising edge of the each corresponding primary side switch. The conduction time of respective SR switches is generally constant for below resonance operation. In another control technique, for switching speeds that are above the resonant frequency of the primary stage of the converter, the SR switches are controlled based on the falling and rising edges of the voltage across the each corresponding SR switch. In general, for above resonance operation, each corresponding SR switch will be turned off after the falling edge of each corresponding primary side switch, while each corresponding SR switch will be turned on after the rising edge of the each corresponding primary side switch. | 2015-05-14 |
20150131337 | Resonant Isolated Active PFC Rectifier - A method of driving an isolated converter includes opening a first bi-directional switch on an input side of a transformer, accepting current into a resonant capacitor connected across the first bi-directional switch to reduce voltage across the first bi-directional switch in response to said opening the first bi-directional switch, reversing current out of the resonant capacitor, and closing the first bi-directional switch as voltage across the first bi-directional switch is approximately zero volts. | 2015-05-14 |
20150131338 | POWER CONVERSION APPARATUS - An isolated power conversion apparatus has an isolation transformer, a series circuit including a load and an inductor connected in series with each other, the series circuit being disposed on a secondary side of the isolation transformer, and one or a plurality of switching means disposed between the series circuit and the secondary side of the isolation transformer, the switching means being bidirectional. This apparatus sends out power from a DC power supply of a primary side of the isolation transformer toward the load as DC power or AC power of an arbitrary polarity, or regenerates and supplies the DC power or AC power from the load to the DC power supply. | 2015-05-14 |
20150131339 | POWER CONVERSION APPARATUS - An isolated power conversion apparatus has an isolation transformer, a series circuit including a load and an inductor connected in series with each other, the series circuit being disposed on a secondary side of the isolation transformer, and one or a plurality of switching means disposed between the series circuit and the secondary side of the isolation transformer, the switching means being bidirectional. This apparatus sends out power from a DC power supply of a primary side of the isolation transformer toward the load as DC power or AC power of an arbitrary polarity, or regenerates and supplies the DC power or AC power from the load to the DC power supply. | 2015-05-14 |
20150131340 | POWER SUPPLY DEVICE - A power supply device may include a transformer having a primary winding receiving a rectified alternating current (AC) input power and a secondary winding electromagnetically coupled to the primary winding to supply power to a load, an auxiliary switch selectively providing the rectified AC input power to the primary winding, and a limitation controlling unit controlling the auxiliary switch based on a voltage level of the AC input power. | 2015-05-14 |
20150131341 | CONVERTER AND DRIVING METHOD THEREOF - A converter and a driving method thereof are disclosed. The converter includes a transformer, a main switch, a clamp switch, and a switching controller. Here, the switching controller controls a turn-on time of the main switch and a turn-off time of the clamp switch corresponding to an output load. | 2015-05-14 |
20150131342 | MULTI TERMINAL HVDC CONTROL - An exemplary Multi-Terminal High Voltage Direct Current (MTDC) system includes at least three terminals, where each terminal including a Voltage Source Converter (VSC) controlled by a VSC controller. A method for controlling the MTDC system includes providing a converter schedule including at least one of a desired power flow value and a DC voltage; determining, by a MTDC master controller, a present state of the MTDC system including a dynamic topology of the MTDC system; determining, by the MTDC master controller, based on the present state of the MTDC system, based on the schedule and based on MTDC system constraints, VSC controller parameters including droop settings for local control by the VSC controllers; and transmitting the VSC controller parameters to the VSC controllers. | 2015-05-14 |
20150131343 | RESISTORLESS PRECHARGING - A boost PFC converter includes a rectifier, a converter and an output stage comprising an output capacitor where the DC output voltage is provided across the output capacitor. The rectifier includes four rectifying elements connected in a full bridge configuration where the upper two of these four rectifying elements are thyristors and where the lower two are diodes. In that the thyristors are controlled such as to be open for only a part of each half period of the input voltage, the amount of current per half period that is passed to the output capacitor is controllable and can be made very small. Accordingly, the charge current for precharging the output capacitor can be controllably limited such that a bulky precharge resistor is not required anymore to avoid high inrush currents. | 2015-05-14 |
20150131344 | Boost Circuit - A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level. | 2015-05-14 |
20150131345 | METHOD AND APPARATUS FOR MINIMISING A CIRCULATING CURRENT OR A COMMON-MODE VOLTAGE OF AN INVERTER - The present disclosure discloses a method and an apparatus implementing the method for minimising a circulating current of parallel-connected inverters. The method can include, for at least one parallel-connected inverter, measuring a common-mode voltage of the inverter, and controlling a cycle length of the switching cycle on the basis of the common-mode voltage. | 2015-05-14 |
20150131346 | METHOD FOR DESIGNING POWER CONTROLLER, POWER CONTROLLER, AND POWER CONTROL DEVICE - A method including: setting a weighting function based on an amount of change in impedance of a control target; and determining, for a power controller, a transfer function composed of a transfer function of an internal model obtainable by performing Laplace transform on the voltage reference value and a transfer function of a partial controller, the transfer function of the partial controller being for outputting the control output after receiving, as an input, an output of the transfer function of the internal model, wherein the determining includes determining the transfer function of the partial controller using an H∞control theory so as to reduce (i) a first amount of control obtainable by multiplying the control output and the weighting function and (ii) a second amount of control that is an output of the transfer function of the internal model. | 2015-05-14 |
20150131347 | Method for controlling an H-bridge inverter - The invention relates to a H-bridge inverter and a method for controlling a H-bridge converter. The H-bridge inverter ( | 2015-05-14 |
20150131348 | REVERSIBLE MATRIX CONVERTER CIRCUIT - A reversible matrix converter circuit is provided with n levels per phase including n conversion arms exhibiting on one side n ends for generating or receiving respectively n intermediate DC voltage levels, and exhibiting on another side n ends linked at a common point of AC signal input or output. The circuit includes: —two external arms linked respectively to the highest level of positive voltage and to the lowest level of negative voltage, these two external arms each having a single IGBT transistor or two power transistors, linked by their emitter, —two IGBT power transistors, linked in series by their emitter on each of the n-1 internal arms, —filtering capacitors disposed respectively between the n intermediate voltage levels. | 2015-05-14 |
20150131349 | SYSTEM AND METHOD FOR BALANCING MULTILEVEL POWER CONVERTERS - A system including a multi-level power converter is provided. The system also includes a plurality of DC link capacitors and a balancing circuit coupled to the multi-level power converter. The balancing circuit further includes two sets of interface branches. Each set includes a plurality of interface branches and a plurality of switching elements. The balancing circuit also includes a battery coupled to one or more inductors across the two sets of interface branches and a controller for controlling switching operations of the plurality of switching elements for modifying a voltage of the battery to balance voltages of the plurality of DC link capacitors. | 2015-05-14 |
20150131350 | ELECTRICAL POWER CONVERTER - This description relates to an electrical power converter including a series connection of two transistors, and provides a technology for suppressing increase in electrical current flowing through the transistors when the two transistors are turned on at the same time for some defective reason. An electrical power converter disclosed herein includes a series connection of a first transistor and a second transistor. The electrical power converter includes a clamp circuit configured to inhibit an abnormal rise in gate voltage, which is provided in at least either the first transistor or the second transistor. The clamp circuit includes a diode and a capacitor. The diode has an anode connected with a gate of the transistor. The capacitor has one electrode connected with a cathode of the diode and the other electrode connected with an emitter of the transistor. | 2015-05-14 |
20150131351 | Modulation Of Switching Signals In Power Converters - A method comprises: applying control signals to an inverter switching network according to a selected switching sequence, wherein a switching sequence is applied corresponding to a desired sector of a switching scheme in which a demand vector is currently located, the switching scheme corresponding to the demand vector in a space vector modulation scheme having stationary active vectors around the periphery and a stationary zero vector at an origin; storing a plurality of simultaneous switching schemes in which, for a single switching cycle, a switch in each of at least two phases of the inverter switching network is switched simultaneously from a first state to a second state with a corresponding switch in at least one other phase of the inverter switching network being in a given state and in which the switch in each of the at least two phases is switched simultaneously from the second state to the first state with the switch in the at least one other phase being in the given state; and applying a simultaneous switching sequence by applying a first of the simultaneous switching schemes in dependence on the position of the demand vector in relation to the stationary active vectors. | 2015-05-14 |
20150131352 | Multi-Level Converter Control - A method is disclosed for controlling at least four switching components of a multi-level converter. The method comprises receiving first and second control signals for controlling a dual-level inverter having two switching components, and processing the first and second received control signals to produce at least four switching component control signals for controlling the switching components of a multi-level converter. Also disclosed are a control logic system, a multi-level converter system and a computer readable medium. | 2015-05-14 |
20150131353 | POWER SUPPLY DEVICE - According to one embodiment, a power supply device includes a main circuit board including a switching circuit, a transformer board opposite the main circuit board and including a transformer, and an intermediate cooling plate between the main circuit board and the transformer board and configured to cool at least one of a heat-producing element of the switching circuit and the transformer. | 2015-05-14 |
20150131354 | AC-DC CONVERTER - According to one embodiment, an AC-DC converter includes a first printed wiring board, a planar transformer, a plurality of primary members, and a plurality of secondary members. The planar transformer has a primary coil, a secondary coil, a second printed wiring board and a core. The primary members are mounted on the first printed wiring board, and are electrically connected to the primary coil. The secondary members are mounted on the second printed wiring board, and are electrically connected to the secondary coil. | 2015-05-14 |
20150131355 | ASSOCIATIVE MEMORY CIRCUIT - An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage. | 2015-05-14 |
20150131356 | DATA PROCESSING DEVICE AND MANUFACTURING METHOD THEREOF - A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M word lines and (N+K) bit lines. K of the bit lines are spares (i.e., redundant bit lines). Programmable switches in a switch array are programmed so that the switch array connects a driver that drives the bit lines to N bit lines that are not connected to defective memory cells. The memory cell array is tested by a test circuit connected to the bit lines in such a manner that the test circuit transmits and receives a signal to and from the bit lines via the switch array. The test circuit may be formed using a reconfigurable circuit. Other embodiments may be claimed. | 2015-05-14 |
20150131357 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; amounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory. | 2015-05-14 |
20150131358 | SEMICONDUCTOR DEVICE AND PROGRAMING METHOD - This semiconductor device is provided with: a variable resistance first switch ( | 2015-05-14 |
20150131359 | CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS - A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals. | 2015-05-14 |
20150131360 | VERTICAL 1T-1R MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME - Vertical 1T-1R memory cells, memory arrays of vertical 1T-1R memory calls, and methods of forming such memory cells and memory arrays are described. The memory cells each include a vertical transistor and a resistivity-switching element coupled in series with and disposed above or below the vertical transistor. The vertical transistor includes a controlling electrode coupled to a word line that is above or below the vertical transistor. The controlling electrode is disposed on a sidewall of the vertical transistor. Each vertical transistor includes a first terminal coupled to a bit line, a second terminal comprising the controlling electrode coupled to a word line, and a third terminal coupled to the resistivity-switching element. | 2015-05-14 |
20150131361 | MEMORY DEVICE - A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells. | 2015-05-14 |
20150131362 | MEMORY CELLS WITH RECTIFYING DEVICE - Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor. | 2015-05-14 |
20150131363 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING VARIABLE RESISTANCE ELEMENT - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections. | 2015-05-14 |
20150131364 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 2015-05-14 |
20150131365 | SPSRAM WRAPPER - Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density. | 2015-05-14 |
20150131366 | VOLTAGE CONTROLLER - A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is configured to inhibit a second voltage of a second signal at a second node of the voltage inducing circuit from exceeding a first specified voltage threshold so that a fifth voltage of a fifth signal at a fifth node of the voltage inducing circuit is inhibited from exceeding a second specified voltage threshold. The pull up circuit is configured to maintain the second voltage substantially equal to a specified pull up voltage. The fifth node is connected to the SRAM cell, and a voltage to which the SRAM cell is exposed is thereby controlled. | 2015-05-14 |
20150131367 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased. | 2015-05-14 |
20150131368 | IMPLEMENTING SENSE AMPLIFIER FOR SENSING LOCAL WRITE DRIVER WITH BOOTSTRAP WRITE ASSIST FOR SRAM ARRAYS - A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability. | 2015-05-14 |
20150131369 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 2015-05-14 |
20150131370 | MULTI-LEVEL CELLS AND METHOD FOR USING THE SAME - The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention. | 2015-05-14 |
20150131371 | MAGNETIC RESISTANCE STRUCTURE, METHOD OF MANUFACTURING THE MAGNETIC RESISTANCE STRUCTURE, AND ELECTRONIC DEVICE INCLUDING THE MAGNETIC RESISTANCE STRUCTURE - Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first magnetic material layer between the boron nitride layer and the graphene layer according to an intercalation process; and forming a second magnetic material layer on the graphene layer. | 2015-05-14 |
20150131372 | MEMORY CONTROLLER, MEMORY DEVICE AND METHOD OF OPERATING - A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell. | 2015-05-14 |
20150131373 | Incremental Programming Pulse Optimization to Reduce Write Errors - In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed. | 2015-05-14 |
20150131374 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - The present invention relates to a semiconductor device, including memory blocks suitable for storing data, peripheral circuits suitable for refreshing the memory blocks, and a control circuit suitable for controlling the peripheral circuits to change data stored in a first memory block among the memory blocks and refresh the first memory block with changed data, and an operating method thereof. | 2015-05-14 |
20150131375 | METHOD OF DRIVING NONVOLATILE MEMORY DEVICES - A method of driving a nonvolatile memory device, includes; forward shifting threshold voltages of nonvolatile memory cells by executing a first program loop with respect to the nonvolatile memory cells, and thereafter, reverse shifting the threshold voltages of the nonvolatile memory cells, and again forward shifting the threshold voltages of the nonvolatile memory cells by executing a second program loop with respect to the nonvolatile memory cells. | 2015-05-14 |
20150131376 | THRESHOLD ESTIMATION USING BIT FLIP COUNTS AND MINIMUMS - A bit flip count is determined for each bin in a plurality of bins, including by: (1) performing a first read on a group of solid state storage cells at a first threshold that corresponds to a lower bound for a given bin and (2) performing a second read on the group of solid state storage cells at a second threshold that corresponds to an upper bound for the given bin. A minimum is determined using the bit flip counts corresponding to the plurality of bins and the minimum is used to estimate an optimal threshold. | 2015-05-14 |
20150131377 | METHOD AND DEVICE FOR PROTECTING DATA OF FLASH MEMORY - A method of protecting data of a flash memory is provided. The method includes detecting primary power applied to the flash memory, and applying secondary power converted from the primary power to the flash memory. The primary power is compared to first and second values, and a writing-protection pin of the flash memory is enabled when the detected primary power reaches a predetermined value. | 2015-05-14 |
20150131378 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected to a gate electrode of the selection transistor, a driver, or a node that supplies an unselected voltage, or is set to be in a floating state. | 2015-05-14 |
20150131379 | BAD BLOCK COMPENSATION FOR SOLID STATE STORAGE DEVICES - Technologies and implementations for reusing bad blocks in a solid state drive are generally disclosed. | 2015-05-14 |
20150131380 | ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY - When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines. | 2015-05-14 |
20150131381 | Three Dimensional Nonvolatile Memory Cell Structure with Upper Body Connection - A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines. | 2015-05-14 |
20150131382 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device including a memory cell array including a memory cell and a circuit element including first wirings and a selection element, the first wirings having a wiring width smaller than a resolution limit of an exposure apparatus. The first wirings extend in a first direction and are aligned in a second direction crossing with the first direction. A second wiring, being one of the first wirings, is cut by at least one cut region. The first wiring adjacent to the second wiring in the second direction extends continuously in the first direction in a portion adjacent to the cut region in the second direction. | 2015-05-14 |
20150131383 | NON-VOLATILE IN-MEMORY COMPUTING DEVICE - Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array. | 2015-05-14 |
20150131384 | SEMICONDUCTOR DEVICE - In a nonvolatile memory device ( | 2015-05-14 |
20150131385 | FLASH MEMORY DEVICE HAVING EFFICIENT REFRESH OPERATION - Provided is a flash memory device capable of efficiently performing a refresh operation. The flash memory device includes a normal memory array including a plurality of normal memory cells arranged in a matrix of word lines and bit lines, wherein the plurality of normal memory cells are divided into a plurality of memory blocks and are programmable and erasable; a refresh address generation unit configured to generate a refresh block address, wherein the refresh block address is sequentially increased in response to activation of a refresh driving signal; and a refresh driving unit driven to refresh a memory block specified by the refresh block address among the memory blocks of the normal memory array in a unit refresh frame, and generate the refresh driving signal. In the flash memory device, a refresh operation may be efficiently performed to fix a data disturbance. | 2015-05-14 |
20150131386 | DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A data writing method, a memory storage device, and a memory controlling circuit unit are provided. The writing method includes: grouping logical erasing units into a first region and an second region; determining if a first logical erasing unit which a host system intends to write belongs to the first region or the second region; if the first logical erasing unit belongs to the first region, writing data to a spare physical programming unit, wherein the physical erasing unit to which the spare physical programming belongs further stores data belonging to another logical erasing unit; if the first logical erasing unit belongs to the second region, writing data to a physical erasing unit in which all the valid data belong to the first logical erasing unit. Accordingly, a speed of sequential writing is guaranteed to be greater than a target value. | 2015-05-14 |
20150131387 | LOGIC EMBEDDED NONVOLATILE MEMORY DEVICE - A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal. | 2015-05-14 |
20150131388 | HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT - The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations. | 2015-05-14 |
20150131389 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. | 2015-05-14 |
20150131390 | APPARATUSES AND METHODS FOR PERFORMING COMPARE OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells. | 2015-05-14 |
20150131391 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal. | 2015-05-14 |
20150131392 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING THE SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a memory having bit cells; and a frequency detector outputting a switching signal to switch a test mode from first to second test modes. Further, the memory includes an internal clock generator generating an internal clock in synchronization with the external clock; a writing part writing data into the bit cells based on the internal clock; a delayed clock generator generating a delayed clock by adding a designated delay to the internal clock; a first selector inputting the internal clock and the delayed clock, and, when the frequency of the high-speed clock is less than a designated frequency, selecting the delayed clock based on the switching signal; and a reading part reading the data of the bit cells based on the delayed clock. | 2015-05-14 |
20150131393 | METHOD OF REPAIRING A MEMORY DEVICE AND METHOD OF BOOTING A SYSTEM INCLUDING THE MEMORY DEVICE - A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units. | 2015-05-14 |
20150131394 | METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT - A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold. | 2015-05-14 |
20150131395 | Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device - A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the count value reaches a predetermined value. | 2015-05-14 |
20150131396 | SEMICONDUCTOR MEMORY DEVICE WITH SWITCHES FOR SUSPENDING POWER SUPPLY - A method of making a semiconductor integrated circuit includes forming switches configured to suspend, on a way-specific basis, power supply to ways allocated to one or more RAM macros. | 2015-05-14 |
20150131397 | MEMORY SYSTEM AND ASSEMBLING METHOD OF MEMORY SYSTEM - According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information. | 2015-05-14 |
20150131398 | TIMING-DRIFT CALIBRATION - The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device. | 2015-05-14 |
20150131399 | SYSTEMS AND METHODS OF REGULATING TEMPERATURE OF A SOLID-STATE SHEAR PULVERIZATION OR SOLID-STATE MELT EXTRUSION DEVICE - Systems and methods for controlling the temperature of a solid-state screw extruder may include providing an extrusion screw that incorporates one or more screw shaft channels. The shaft channels may be configured to conduct a flow of a heat conducting medium along a length of the shaft. The shaft channels may be incorporated into an exterior surface or within the body of the screw shaft. The extruder may include extrusion screw elements in mechanical communication with the shaft. Each of the elements may further include one or more element channels also configured to conduct a flow of the medium. The shaft channels and the element channels may be disposed to permit a flow of the medium therebetween. The temperature of the extrusion screws and/or screw elements may be controlled by circulating the medium from a source, through the shaft and element channels, and back to the source. | 2015-05-14 |
20150131400 | KNEADING MACHINE - A two-shaft continuous kneading machine is disclosed wherein airtightness in a housing is assured by a simple means without using a mechanical seal. A magnetic coupling mechanism is formed between the mechanism in the housing ( | 2015-05-14 |
20150131401 | DEVICE FOR TRANSPORTING VISCOUS COMPOUNDS AND PASTES - A device for the controlled transport of viscous compounds and pastes in at least one process space ( | 2015-05-14 |
20150131402 | APPARATUS AND METHOD FOR MIXING AND COOLING A BEVERAGE - A beverage shaker for mixing ingredients, cooling the beverage, and, shaving ice and simultaneously producing shavings of flavoring ingredients and/or ice to enhance the flavor, appearance, and refreshment of the desired beverage. The beverage shaker has a tumbler, a top or cap, and a shaving tool incorporated within one of the tumbler or top of the beverage shaker. The shaving tool typically has circumferential ridges, spiral threads, or other protrusions and a pointed end to bruise any fruit added to the beverage being mixed and to create shavings from included flavor ingredients and ice. The shaving tool may be removably disposed in either the tumbler or the top. The shaving tool may have a liquid-filled hollow portion. More than one shaving tool may be commonly connected to the tumbler or top. | 2015-05-14 |
20150131403 | SUBSTRATE LIQUID PROCESSING APPARATUS AND SUBSTRATE LIQUID PROCESSING METHOD - A substrate liquid processing apparatus includes a tank; a circulation line; a processing unit connected to the circulation line through a branch line and configured to perform a liquid processing on a substrate using a processing liquid flowing through the circulation line; a processing liquid producing mechanism configured to produce the processing liquid by mixing at least two kinds of raw material liquids supplied from respective raw material liquid sources at a controlled mixing ratio; a concentration measuring device configured to measure a concentration of the processing liquid flowing through the circulation line and a concentration of the processing liquid flowing through the processing liquid supply line; and a control device configured to control the processing liquid producing mechanism based on the measured concentrations of the processing liquid. | 2015-05-14 |
20150131404 | Laboratory Mixer - A laboratory mixer for mixing a sample and a diluent in a bag. An enclosure defines a mixing chamber, and at least one movable mixing element is retained for mixing the sample and the diluent within the bag. At least one liquid detector is retained relative to the enclosure for detecting liquid leaked from the bag. The sensor can be a capacitive, inductive, or optical sensor. The sensor can be a conductivity sensor with two electrodes shaped like combs and a gap less than or equal to a diameter of a drip of diluent solution. A ledge with a low point can be retained by an access door. The sensor or sensors can be disposed adjacent to the access door, on a mixing element, in direct contact with the bag, or on a tank. An alarm and cessation of operation can be triggered upon a detection of leaked liquid. | 2015-05-14 |
20150131405 | MAGNETIC MIXING FOR CONTINUOUS LATEX PREPARATION - A mixing process and system for mixing fluid such as a latex can include a first fluid and a second fluid that are combined to form, for example, a latex precursor. A plurality of magnetic particles are dispensed within the precursor. The precursor is dispensed within a mixing zone that may include a mixing tube. Two or more opposing electromagnets are activated out of phase (i.e., out of sync) to affect a travel path of the magnetic particles to form a turbulence within the precursor to provide an effective mixing of the precursor to form a material such as latex. The magnetic particles may be removed from the material, for example by filtering, or may remain within the material during use. | 2015-05-14 |
20150131406 | APPARATUS AND METHOD FOR ENTRAINING A POWDER IN A FLUID - An apparatus for entraining a powder in a process fluid is provided. The apparatus ( | 2015-05-14 |
20150131407 | AGITATOR AND AGITATING HOOK PROVIDED THEREIN - Provided are an agitator and an agitating hook provided therein. The agitator includes a rotary shaft rotatably installed in a reactor, rotor blades installed at an outer circumference of the rotary shaft and rotated with the rotary shaft to agitate a material therein, and an agitating hook constituted by a pair of members spaced apart from each other at an inner wall of the reactor and through which the rotor blades pass. Here, a gap between the agitating hook is larger at an outlet port through which the rotor blade leaves than at an inlet port through which the rotor blade enters. Since a pressure is uniformly applied from the inlet port through which the rotor blade enters to the outlet port through which the rotor blade leaves, a torsional moment applied to the agitating hook is minimized. Therefore, it is possible to improve durability of the agitating hook and increase reliability of products. | 2015-05-14 |
20150131408 | LASER-INDUCED ULTRASOUND GENERATOR AND METHOD OF MANUFACTURING THE SAME - Provided are a laser-induced ultrasound generator and a method of manufacturing the laser-induced ultrasound generator. The laser-induced ultrasound generator includes: a substrate including a plurality of nanostructures provided on a first surface of the substrate; and a thermoelastic layer provided on the first surface of the substrate, the thermoelastic layer being configured to generate an ultrasound by absorbing a laser beam incident onto a second surface of the substrate, the second surface facing the first surface. The nanostructures may be cylinder-shaped nano-pillars. | 2015-05-14 |
20150131409 | SEISMIC SOURCE CODING, ACTIVATION, AND ACQUISITION - The Monte-Carlo method of generating Popcorn shooting patterns starts with the number and sizes of the guns available and the length in time of the desired Popcorn pattern. The firing times and order of the guns will be randomly perturbed and a large number of Popcorn patterns built. Candidate Popcorn patterns will then be tested against a set of criteria to identify acceptable or the best patterns. These criteria may include limits on maximum peak strength, distinctiveness compared to the other patterns, and the size of the notches and peaks in the spectra. | 2015-05-14 |
20150131410 | Wellbore Telemetry and Noise Cancelation Systems and Methods for the Same - A method of signal processing includes providing at least a first pressure sensor and a second pressure sensor spaced in a drilling system and using an algorithm to separate the downwardly propagating waves from the upwardly propagating waves. In one or more examples, an algorithm may include determining a velocity of pressure signals in a wellbore, time-shifting and stacking pressure signals from at least the first pressure sensor and the second pressure sensor to determine a downwardly propagating noise signal, and subtracting the downwardly propagating noise signal from at least the signal from the first pressure sensor. | 2015-05-14 |
20150131411 | USE OF HYBRID TRANSDUCER ARRAY FOR SECURITY EVENT DETECTION SYSTEM - Security events, such as gunshots may be determined using hybrid sensors. The hybrid sensors have at least two different elements that are sensitive to the security event, such as conventional microphone and a fiber optic microphone, which, in the case of a gunshot, permits a better scanning of the report of the gunshot to better determine its direction, signature features, and time of arrival. Additionally, sensor can be employed having multiple elements that are sensitive to a security event where at least one of the elements is not coplanar with the rest. This displacement along an orthogonal axis may be used to improve the ability of a network of such sensors to determine the direction and origin of a security event in a three dimensional system. | 2015-05-14 |
20150131412 | TIMEPIECE WITH DISPLAY DEVICES - A watch including a case in which there is arranged a control system, which includes a time base and is arranged to be able to perform several functions, the watch further including at least two analogue display elements and a digital display controlled independently by the control system, the watch further including a control acting on the control system. The watch is arranged in a first, normal operating mode to provide the user with a time indication by the analogue display elements driven by the control system fitted with the time base, and the watch is arranged in a second, special operating mode to allow the user to select a function via the control, to display on the digital display a value associated with the selected function, and to move an analogue display element opposite the value associated with the selected function. | 2015-05-14 |
20150131413 | TIMEPIECE COMPRISING A DECOUPLING BETWEEN THE ENERGY TRANSMISSION MEANS AND THE COUNTING MEANS - The invention concerns a timepiece comprising a timepiece movement cooperating with a display device, the timepiece movement comprising a mechanical energy source and a system of energy transmission from the energy source to at least one resonator including a first distribution device controlled by the at least one resonator. According to the invention, the timepiece also comprises a counting system mounted between the at least one resonator and the display device, and including a second distribution device controlled by the at least one resonator and cooperating with the display device to uncouple the energy transmission means from the counting means. | 2015-05-14 |
20150131414 | Escapement Device for Timepiece - Escapement device of a timepiece movement includes an escapement wheel, a first mobile having means of locking with the escapement wheel and of mechanical transmission with the escapement wheel, a second mobile and the balance roller. The second mobile has means of locking with the escapement wheel and means of mechanical transmission with the escapement wheel and the first mobile. The mobiles are driven by the escapement wheel tangentially. | 2015-05-14 |
20150131415 | MODE CONVERTER COUPLING ENERGY AT A HIGH-ORDER TRANSVERSE ELECTRIC MODE TO A PLASMONIC TRANSDUCER - A waveguide is configured to couple light from a light source at a fundamental transverse electric (TE) mode. A mode converter outputs the light to an output region of the waveguide at a higher-order TE mode. A plasmonic transducer receives the light at the higher order TE mode and generates surface plasmons that heat a recording medium. The plasmonic transducer includes: an input end proximate the output region of the waveguide and comprising a first convex curved edge; an output end proximate a surface that faces the recording medium, the output end comprising a second convex curved edge and a peg; and linear edges between the first and second convex curved edges. | 2015-05-14 |
20150131416 | MAGNETIC DEVICES WITH OVERCOATS - A magnetic device including a magnetic writer; and an overcoat positioned over at least the magnetic writer, the overcoat including oxides of yttrium, oxides of scandium, oxides of lanthanoids, oxides of actionoids, oxides of zinc, or combinations thereof | 2015-05-14 |
20150131417 | NEAR FIELD TRANSDUCER HAVING SACRIFICIAL STRUCTURE - Near field transducers (NFTs) and devices that include a peg having an air bearing region and an opposing back region, the back region including a sacrificial structure, a disc having a first surface in contact with the peg, and a barrier structure, the barrier structure positioned between the opposing back region of the peg and the first surface of the disc. | 2015-05-14 |
20150131418 | DEVICES INCLUDING AT LEAST ONE ADHESION LAYER AND METHODS OF FORMING ADHESION LAYERS - Devices that include a near field transducer (NFT), the NFT having at least one external surface; and at least one adhesion layer positioned on at least a portion of the at least one external surface, the adhesion layer including oxides of yttrium, oxides of scandium, oxides of lanthanoids, oxides of actionoids, oxides of zinc, or combinations thereof. | 2015-05-14 |
20150131419 | DEVICES INCLUDING AT LEAST ONE ADHESION LAYER - Devices that include a near field transducer (NFT), the NFT having at least one external surface; and at least one adhesion layer positioned on at least a portion of the at least one external surface, the adhesion layer including arsenic (As), antimony (Sb), selenium (Se), tellurium (Te), polonium (Po), bismuth (Bi), sulfur (S), or combinations thereof. | 2015-05-14 |
20150131420 | OPTICAL RECORDING DEVICE, OPTICAL RECORDING METHOD AND MULTI-LAYER DISK - An optical recording device that records to a multi-layer disk having multiple recording layers includes a controller which sets a data area in which user data is recorded, and a calibration area including a main calibration area and at least one sub-calibration area which are used to calibrate the intensity of laser light for recording, with the same layout among the plurality of recording layers, conducts first calibration for performing initial recording in the data area by using the main calibration area, records dummy data in the remainder of the main calibration area, and conducts second calibration for performing additional recording in the data area by using the sub-calibration area. | 2015-05-14 |
20150131421 | OPTICAL DISK APPARATUS, CONTROL METHOD, CONTROL PROGRAM AND INFORMATION STORAGE MEDIUM - Disclosed herein is an optical disc apparatus including: an optical pickup radiating light having a first wavelength provided for an optical disc medium of a first type and light having a second wavelength which is smaller than the first wavelength and provided for another optical disc medium of a second type; a signal outputting section outputting a signal according to light reflected by the optical disc medium to reflect light radiated by the optical pickup; and a type determination section requesting the optical pickup to radiate light having the first wavelength to an object optical disc medium to acquire the signal output by the signal outputting section and determining the type of the object optical disc medium in accordance with the number of peaks appearing in the acquired output signal output by the signal outputting section while moving the optical pickup in a direction to the object optical disc medium. | 2015-05-14 |
20150131422 | OPTICAL DISK APPARATUS, CONTROL METHOD, CONTROL PROGRAM AND INFORMATION STORAGE MEDIUM - Disclosed herein is an optical disc apparatus capable of reading out information stored in an optical disc medium, the optical disc apparatus including: a light emitting device radiating light; an object lens converging light radiated by the light emitting device on the optical disc medium; and a control section carrying out control to shift the center position of the object lens with respect to the optical-axis position of light radiated by the light emitting device in an operation to read out information from the optical disc medium. | 2015-05-14 |
20150131423 | OPTICAL DISC DEVICE, CONTROL METHOD THEREOF, PROGRAM, AND INFORMATION STORAGE MEDIUM - An optical disc device that reads information recorded in an optical disc medium includes an objective lens that focuses light on the optical disc medium, a spherical aberration correction mechanism that changes an amount of spherical aberration of the objective lens according to a setting value of a predetermined parameter, and an evaluation value measurement section that measures an evaluation value indicating the accuracy of reading of information from the optical disc medium. The optical disc device further includes a control section that executes adjustment processing in which the control section carries out plural times of measurement of the evaluation value by the evaluation value measurement section concurrently with changing the amount of spherical aberration of the objective lens by the spherical aberration correction mechanism and calculates an optimum setting value of the parameter based on plural evaluation values obtained by the plural times of measurement. | 2015-05-14 |
20150131424 | OPTICAL INFORMATION RECORDING/REPRODUCTION DEVICE, RECORDING CONDITION ADJUSTMENT METHOD, AND OPTICAL INFORMATION RECORDING MEDIUM - An optical information recording/reproduction device appropriately adjusting a recording condition and a method and a medium therefor are provided in order to cope with a problem that the signal-to-noise ratio (SNR) during reproduction decreases, unless the condition during recording is adjusted, because of variation in the environment during recording, variation of components such as laser output, variation of production of the device, and the like in the optical information recording/reproduction device using holography. In an optical information recording/reproduction device configured to record or reproduce information to an optical information recording medium by using holography, a recording condition is adjusted, before user data are recorded, in an adjustment area provided for recording condition adjustment in an optical information recording medium. | 2015-05-14 |
20150131425 | OPTICAL OSCILLATION DEVICE AND RECORDING APPARATUS - Provided is a recording apparatus including a self-excited oscillation semiconductor laser that has a double quantum well separate confinement heterostructure and includes a saturable absorber section to which a negative bias voltage is applied and a gain section into which a gain current is injected, an optical separation unit, an objective lens, a light reception element, a pulse detection unit, a reference signal generation unit, a phase comparison unit, a recording signal generation unit, and a control unit. | 2015-05-14 |