20th week of 2015 patent applcation highlights part 46 |
Patent application number | Title | Published |
20150132827 | Emulsifier Centrifuge Tube Fermenter - A centrifuge tube fermenter for culturing cells in a nutrient medium wherein the centrifuge tube fermenter is comprised of a top end, a bottom end, a vertical cylindrical outer wall positioned between the top end and the bottom end, and an inner wall positioned inside the outer wall, the bottom end further comprised of a plurality of baffles which protrude from inner wall toward a theoretical center of the vertical cylindrical outer wall terminating in a conical tip. | 2015-05-14 |
20150132828 | BACTERIAL HOST STRAIN COMPRISING A MUTANT SPR GENE AND HAVING REDUCED TSP ACTIVITY - The present invention provides a recombinant gram-negative bacterial cell comprising a mutant spr gene encoding a spr protein having a mutation at one or more amino acids selected from D133, H145, H157, N31, R62, I70, Q73, C94, S95, V98, Q99, R100, L108, Y115, V135, L136, G140, R144 and G147 and wherein the cell has reduced Tsp protein activity compared to a wild-type cell. | 2015-05-14 |
20150132829 | INDUCTION OF FLOCCULATION IN PHOTOSYNTHETIC ORGANISMS - The present invention provides compositions and methods for producing flocculation moieties in photosynthetic organisms. The photosynthetic organisms are genetically modified to effect production, secretion, or both, of the flocculation moieties. Also provided are methods of flocculating organisms. | 2015-05-14 |
20150132830 | Trap Type Carbon Replenishing Device for Culturing Microalgae of Opened Pool and Carbon Replenishing Method Thereof - The invention relates to the field of microalgae culture and specifically relates to a trap-type carbon supplement device and carbon supplement method for cultivating microalgae in an open pond. The trap-type carbon supplement device for cultivating microalgae in an open pond, comprises a trap-type container, a partition plate and a gas distributor, wherein the gas distributor is positioned at the culture solution inlet of the trap-type carbon supplement device; the thickness of the trap-type carbon supplement device on the side of the culture solution inlet is 0.5-2 times of the depth of the culture solution in the open pond; the gap between the lower end of the partition plate and the bottom of the trap-type container is 0.5-2 times of the thickness of the trap- type carbon supplement device on the side of the culture solution inlet; the upper end of the partition plate is higher than the wall of the trap-type container; and the width of the partition plate is matched with the trap-type container. The carbon supplement device of the invention can make the gas-liquid contact time longer and reduce the depth of the trap-type container, therefore it can reduce the flow resistance of the liquid in the carbon supplement device and save energy consumption. | 2015-05-14 |
20150132831 | Compositions Comprising Lipase and Methods of Use Thereof - The invention relates to a cleaning composition comprising a lipase with at least 75% identity to SEQ ID NO: 2, and a surfactant, wherein said composition is more effective in removing lipid stains present at a surface in comparison with an equivalent composition lacking the lipase. | 2015-05-14 |
20150132832 | MULTIUSE, ENZYMATIC DETERGENT AND METHODS OF STABILIZING A USE SOLUTION - Stabilized use solutions of low phosphorus, alkali metal carbonate detergents employing enzymes for cleaning compositions are disclosed. In particular, the present invention is a composition for, and method of, removing soils, preventing redeposition of protein soils and reducing foam, using stabilized enzyme cleaning compositions, namely use solutions of the same. | 2015-05-14 |
20150132833 | MULTIUSE, ENZYMATIC DETERGENT AND METHODS OF STABILIZING A USE SOLUTION - Stabilized use solutions of low phosphorus, alkali metal carbonate detergents employing enzymes for cleaning compositions are disclosed. In particular, the present invention is a composition for, and method of, removing soils, preventing redeposition of protein soils and reducing foam, using stabilized enzyme cleaning compositions, namely use solutions of the same. | 2015-05-14 |
20150132834 | METHOD FOR REMOVAL OF TRIGLYCERIDES IN LIPOPROTEINS OTHER THAN LOW-DENSITY LIPOPROTEINS - Disclosed is a method for selectively eliminating triglycerides in lipoproteins other than low density lipoprotein, which method allows one to provide a method for directly and differentially quantifying LDL-TG in a sample with excellent simplicity, specificity and accuracy using an automated analyzer or the like without performing a laborious operation of pretreatment such as centrifugation or electrophoresis. The method for eliminating triglycerides in lipoproteins other than low density lipoproteins includes allowing lipoprotein lipase, cholesterol esterase, glycerol kinase and glycerol-3-phosphate oxidase to act on a sample in the presence of a surfactant that acts on lipoproteins other than low density lipoprotein and/or a surfactant having LDL-protecting action, and eliminating hydrogen peroxide produced thereby. | 2015-05-14 |
20150132835 | DEVICES, SYSTEMS, AND METHODS FOR DIAGNOSTIC TESTING - The present disclosure relates to devices, systems, and methods for performing diagnostic tests. The disclosed diagnostic devices are capable of performing analytic tests and communicating with a portable multifunctional device (PMD) or other computing device. Through input and manipulation of materials within the diagnostic device, a large range of tests may be performed. For example, alteration or customization of chemical components of the diagnostic device may enable many analytic applications to be provided. These analytic tests may include, but are not limited to, sensing or quantification of chemicals from sample input, whether gaseous, liquid, or otherwise, sensing or quantification of analytes, antibodies, or antigens, sensing or quantification of genetic material, or other substances. | 2015-05-14 |
20150132836 | Method And System For Detecting Lymphosarcoma in Cats Using Biomarkers - The invention provides a method and system for developing and using diagnoses of lymphosarcoma in feline subjects using Thymidine kinase (TK) and haptoglobin (HP) as biomarkers. The invention provides a method for obtaining the level of each biomarker and computing an index for a feline subject. The invention provides predefined index ranges to which the index value may be matched in order to determine whether the subject has a high probability of being affected by lymphosarcoma, even when the subject shows apparent symptoms that may be common with inflammatory bowel disease. | 2015-05-14 |
20150132837 | MICROFLUIDIC DEVICES FOR RELIABLE ON-CHIP INCUBATION OF DROPLETS IN DELAY LINES - The present invention relates generally to droplet creation, fusion and sorting, and incubation for droplet-based microfluidic assays. More particularly, the present invention relates to delay-lines, which allow incubation of reactions for precise time periods. More particularly, the present invention relates to delay lines for incubations up to three hours, while reducing back-pressure and dispersion in the incubation time due to the unequal speeds with which droplets pass through the delay line. | 2015-05-14 |
20150132838 | Ventilation Unit for Flow Reversal - A ventilation unit is arranged to effect flow reversal, according to two opposite directions, of a gas flow generated by a fan without reversing the rotation direction of the fan. The ventilation unit includes a fan, at least a first piping arrangement through which a gas flow is intended to pass in one of the two possible directions depending on whether it is blown or sucked by the fan, and a switching assembly arranged between the fan and the first piping arrangement, at least a switching device being provided in the switching assembly and being movable between two positions for selectively and alternately connecting the first piping arrangement to a delivery duct and to a suction duct of the fan, so as to allow the passage of a gas flow in a direction or in the opposite direction within the first piping arrangement. | 2015-05-14 |
20150132839 | SYSTEMS AND METHODS FOR BIO-MASS ENERGY GENERATION - A closed loop system for generating energy is described herein. The closed loop system can include a solar collector, a tank, and the combustor. The solar collector can collect electromagnetic energy from a light source including, the sun. This electromagnetic energy can be transported from the solar collector to the tank via a light guide. The tank is illuminated with electromagnetic energy and biomass grows in the tank. The biomass is transported to the combustor and burned to generate heat energy. This heat energy can be used to generate electricity. | 2015-05-14 |
20150132840 | SINGLE-USE BIOREACTOR AND HEAD PLATE, AND A PROCESS FOR MANUFACTURING SAME - A single-use bioreactor, suitable in particular for use in a parallel bioreactor system for applications in cell culture and/or microbiology, a head plate for such a single-use bioreactor and a process for manufacturing the single-use bioreactor and the head plate. The single-use bioreactor comprises a head plate, a dimensionally stable container and a mixer, the head plate and the container enclosing a reaction chamber, and the mixer having a mixer shaft and a stirring member, said mixer shaft being mounted rotatably about a rotational axis in a bearing and the stirring member being fastened torsionally rigidly to the mixer shaft. The mixer and the bearing are arranged entirely within the reaction chamber and the mixer shaft has a magnetic portion which is arranged and adapted in such a way that it can be coupled magnetically in an axial direction to a rotary drive. | 2015-05-14 |
20150132841 | VESSEL HOLDER AND CAP ASSEMBLY - A vessel holder assembly is provided. A vessel holder, for receiving one or more vessels, includes a first set of attachment features. A cap assembly, for covering the vessel(s) includes a second set of attachment features. Respective attachment features of the vessel holder and the cap assembly may be complementary, such that engagement between complementary attachment members results in an attachment between the cap assembly and the vessel holder. Such an attachment may be manually removable, or may be locked so as to require a tool, or other suitable method, for detaching the cap assembly from the vessel holder. | 2015-05-14 |
20150132842 | PACKAGE FOR CELL-CONTAINING MATERIAL AND PACKAGE CONTAINING CELL-CONTAINING MATERIAL - A package for cell-containing material includes an inner and outer bag. The periphery of the inner bag except an opening is sealed. The periphery of the outer bag except an opening is sealed. The outer bag contains the inner bag so the opening faces outward. A portion of the opening outside the inner bag is sealed and forms an outer bag sealed portion. A portion of the opening that overlaps the inner bag is sealed and forms an inter-bag sealed portion. A sterilized closed space may be surrounded by the outer surface of the inner bag and the inner surface of the outer bag. An adhesive strength of heat sealing of the inner surfaces of the opening of the inner bag may be greater than an adhesive strength of the inter-bag sealed portion and an adhesive strength of the outer bag sealed portion. | 2015-05-14 |
20150132843 | Processes for the Preparation of Highly Pure Plasmid Compositions - The present disclosure generally relates to processes for preparing highly pure plasmid compositions. The processes generally involve treating a composition comprising plasmid DNA with a polypeptide to digest colanic acid. The treated plasmid DNA is then separated from the treated composition. | 2015-05-14 |
20150132844 | Dendritic Cell Compositions and Methods - Methods are provided for the production of dendritic cells from monocytes that have been incubated at a temperature of 1° C.-34° C. for a period of approximately 6 to 96 hours from the time they are isolated from a subject. After the incubation period, the monocytes can then be induced to differentiate into dendritic cells. Mature dendritic cells made by the methods of the invention have increased levels of one or more of CD80, CD83, CD86, MHC class I molecules, or MHC class II molecules as compared to mature dendritic cells prepared from monocytes that have not been held at 1° C.-34° C. for at least 6 hours from the time they were isolated from a subject. Dendritic cells made by the methods of the invention are useful for the preparation of vaccines and for the stimulation of T cells. | 2015-05-14 |
20150132845 | DEVICE AND METHOD FOR CONTINUOUS CELL CULTURE AND OTHER REACTIONS - Devices, systems, and methods for continuous cell culture and other reactions are generally described. In some embodiments, chambers (e.g., cell growth chambers) including at least a portion of a wall formed of a flexible member are provided. A retaining structure can be incorporated outside and proximate to the chamber such that when liquid is added to the chamber, the flexible member is consistently and predictably deformed, and a consistent volume of liquid is added. The flexible member can be formed of, in some embodiments, a gas-permeable medium. In some embodiments, reaction chambers can be arranged in a fluidic loop, and a bypass channel can be used to introduce and/or extract fluid from the loop without affecting loop operation. | 2015-05-14 |
20150132846 | SCALABLE PRIMATE PLURIPOTENT STEM CELL AGGREGATE SUSPENSION CULTURE AND DIFFERENTIATION THEREOF - The present invention relates to methods for production of undifferentiated or differentiated embryonic stem cell aggregate suspension cultures from undifferentiated or differentiated embryonic stem cell single cell suspensions and methods of differentiation thereof. | 2015-05-14 |
20150132847 | ENCAPSULATION AND CARDIAC DIFFERENTIATION OF hiPSCs IN 3D PEG-FIBRINOGEN HYDROGELS - The present invention relates to the production of cell cultures and tissues from undifferentiated pluripotent stem cells using three-dimensional biomimetic materials. The resultant cell cultures or tissues can be used in any of a number of protocols including testing chemicals, compounds, and drugs. Further, the methods and compositions of the present invention further provide viable cell sources and novel cell delivery platforms that allow for replacement of diseased tissue and engraftment of new cardiomyocytes from a readily available in vitro source. The present invention includes novel methods required for the successful production of cell cultures and tissues, systems and components used for the same, and methods of using the resultant cell and tissue compositions. | 2015-05-14 |
20150132848 | HIGH COMPLEXITY siRNA POOLS - The present invention relates to a method for producing pools of siRNA molecules suitable for RNA interference. | 2015-05-14 |
20150132849 | EX VIVO MATURATION OF ISLET CELLS - The invention relates to methods for promoting maturation of islet cells from pre-weaned mammals for the purpose of optimizing the islets for their use as donor tissue for xenotransplantation. The method of the invention removes the pancreas from donor animals and reduces the pancreas tissue to fragments that are greater than the size of an intact islet while retaining islets in their whole, insulin-producing condition. The method of the invention also serially cultures the digested tissue in novel maturation media that enhance the glucose responsiveness of the cultured islets, and selects islets that are sufficiently glucose-responsive for use in transplantation procedures. | 2015-05-14 |
20150132850 | STEM CELLS FROM THE MAMMALIAN NEURAL PLATE - The present invention relates to methods for deriving novel stem cells from the mammalian early neural plate. | 2015-05-14 |
20150132851 | SYSTEMS AND METHODS FOR PROCESSING CELLS - The present invention efficiently and cost-effectively extracts and collects cells from a tissue. The inventors have discovered that the tissue can be effectively fragmented and the resulting cells can be purified using a system or kit with multiple components. An advantage of the present invention is that tissue processing takes place in a closed system such that sterility can be maintained throughout the process, even if certain components are removed during processing, for example through the use of valves, clamps, and heat seals. Furthermore, any or all of the steps can be automated or manually accomplished, according to the specific needs of the application or the user. | 2015-05-14 |
20150132852 | TISSUE CULTURING METHOD, CULTURING METHOD OF FERNS AND EXPLANT OBTAINED THEREFROM - A tissue culturing method includes following steps: providing a chopped gametophyte, generating calluses by culturing the chopped gametophyte, and performing apogamic regeneration of sporophytes, by culturing the calluses in a culture fluid to develop the sporophytes from the calluses. The present invention also provides a tissue culturing method of ferns and an explant. | 2015-05-14 |
20150132853 | CYTOPLASMIC TRANSFER TO DE-DIFFERENTIATE RECIPIENT CELLS - Methods for de-differentiating or altering the life-span of desired “recipient” cells, e.g., human somatic cells, by the introduction of cytoplasm from a more primitive, less differentiated cell type, e.g., oocyte or blastomere are provided. These methods can be used to produce embryonic stem cells and to increase the efficiency of gene therapy by allowing for desired cells to be subjected to multiple genetic modifications without becoming senescent. Such cytoplasm may be fractionated and/or subjected to subtractive hybridization and the active materials (sufficient for de-differentiation) identified and produced by recombinant methods. | 2015-05-14 |
20150132854 | Tuned Synthetic Dendrimer Calibrants for Mass Spectrometry - Provided are synthetic dendrimer calibrants for mass spectrometry. The calibrants are distinguished by their relative ease and rapidity of synthesis, comparatively low cost, long shelf life, high purity, and amenability to batch synthesis as mixtures. The latter characteristic enables parallel preparation of higher molecular weight compounds displaying useful distributions of discrete molecular weights, thereby providing multi-point mass spectrometry calibration standards. Methods of making, tuning and using said calibrants are provided. | 2015-05-14 |
20150132855 | INTERFACE FOR DISPOSABLE SENSORS - Techniques described herein enable a mobile multifunction device to detect a disposable sensor card at an interface coupled to the mobile multifunction device, wherein the disposable sensor card is mounted inside an opening in the mobile multifunction device, detect analog information associated with the disposable sensor card, and convert analog information to digital information. Detecting analog information comprises detecting a non-transient change in at least a portion of the disposable sensor card, wherein at least a portion of the first disposable sensor card changes form in response to exposure to one or more stimuli from an environment of the first disposable sensor card. A non-transient change may include one or more of changing color, changing shape, changing chemical composition or changing electrical characteristics. Furthermore, the interface may be configured to receive disposable sensor cards with varying sensing capabilities. Each disposable sensor card may have one or more disposable sensors. | 2015-05-14 |
20150132856 | DETECTION OF QUANTITY OF WATER FLOW USING QUANTUM CLUSTERS - The preparation of silver quantum clusters embedded in organic-templated-boehmite-nanoarchitecture (OTBN) and its use as a sensor for quantity of water flow measured by change of color in visible light upon flow of contaminated water have been provided. Silver quantum clusters-embedded OTBN are highly luminescent. Since the quantum clusters are embedded in the matrix, they are highly stable over a long period of time. The composition described here is utilized in the form of a device for ‘visible/ultraviolet light color change-based detection’ upon passage of water through a water purification device. Upon interaction with ions present in water, luminescent silver clusters undergo chemical transformation to Ag | 2015-05-14 |
20150132857 | Systems, Sensing Devices And Methods For Detection Of Airborne Contaminants - A device for detecting airborne contaminants includes a protonated, electrically conductive sensing material with affinity for binding with, and capable of being deprotonated by, the airborne contaminant. Electronics measure a property of the sensing material that is sensitive to deprotonation and generates signals indicative of the airborne contaminant. A method for detecting airborne contaminants includes: determining a property change of the protonated, electrically conductive material; and determining presence of the airborne contaminant based on the change. A system for detecting airborne contaminants includes: a data center in remote communication with multiple sensing devices each having: protonated, electrically conductive sensing material with affinity for binding with, and capable of being depronated by, an airborne contaminant, and electronics for relaying signals indicative of a sensing material deprotonation property to the data center; and wherein a user associated with a sensing device is notified of an abnormal level of the airborne contaminant. | 2015-05-14 |
20150132858 | METHOD AND APPARATUS FOR ANALYZING ACETONE IN BREATH - Methods and devices are provided for analyzing acetone in breath. One such method comprises disposing a reactant in a reaction zone within the breath analysis device, wherein the reactant comprises a primary amine disposed on a surface, and wherein the reaction zone has an optical characteristic that is at a reference level. It also comprises pre-storing a liquid nitroprusside solution within the breath analysis device separately from the reactant. The method further comprises using the breath analysis device to cause the breath to contact the reactant in the reaction zone so that the acetone in the breath reacts with the reactant to form a reaction product and, after the reaction product has been formed, using the breath analysis device to cause the nitroprusside solution to contact and react with the reaction product and to facilitate a change in the optical characteristic of the reaction zone relative to the reference level. | 2015-05-14 |
20150132859 | VIBRIO CHOLERAE LIPOPROTEIN 15 (Lp15) VARIANTS AS ANTI-INTERFERENCE ADDITIVE IN TpN17-BASED IMMUNOASSAYS FOR DETECTION OF ANTI-TREPONEMA ANTIBODIES - The invention relates to a method for detecting antibodies against the TpN17 antigen of | 2015-05-14 |
20150132860 | CLINICAL DIAGNOSTIC SYSTEM INCLUDING INSTRUMENT AND CARTRIDGE - In embodiments disclosed herein, a diagnostic system is provided having a cartridge comprising at least one needle; at least one reservoir; at least one fluidic seal; and at least one fluidic channel of a fluidic pathway, wherein the cartridge is configured to store at least one reagent and at least one waste material on the cartridge. The diagnostic system is provided also having a diagnostic instrument comprising the fluidic pathway; an electrochemiluminescence (ECL) detection system; and a pump, wherein the fluidic pathway begins and ends in the cartridge and has a substantially single direction of flow in a pathway fluidically connecting the diagnostic instrument and the cartridge. | 2015-05-14 |
20150132861 | CLINICAL DIAGNOSTIC SYSTEMS - A diagnostic system is provided herein that includes an instrument comprising an electrochemiluminescence (ECL) detector, and a cartridge configured to fit within a portion of the instrument, wherein the cartridge includes at least one reagent including an ECL label and a blood collection holder. Also provided herein is a system that includes a diagnostic instrument, which includes a pump, an ECL detector, an incubator, a magnet, and an output device, and a cartridge configured to fit within a portion of the diagnostic instrument, a sample holder configured to fit within the cartridge, and a closed fluidic loop between the diagnostic instrument and the cartridge when the cartridge is fit within a portion of the diagnostic instrument, wherein the cartridge is configured to accept a sample from the sample holder and place the sample in fluidic communication with the diagnostic instrument via the closed fluidic loop. | 2015-05-14 |
20150132862 | IN-SITU RELAXATION FOR IMPROVED CMOS PRODUCT LIFETIME - Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation. | 2015-05-14 |
20150132863 | PLASMA PROCESSING APPARATUS AND HEATER TEMPERATURE CONTROL METHOD - A plasma processing apparatus is provided that converts a gas into plasma using a high frequency power and performs a plasma process on a workpiece using an action of the plasma. The plasma processing apparatus includes a processing chamber that can be depressurized, a mounting table that is arranged within the processing chamber and holds the workpiece, an electrostatic chuck that is arranged on the mounting table and electrostatically attracts the workpiece by applying a voltage to a chuck electrode, a heater arranged within or near the electrostatic chuck, and a temperature control unit. The heater is divided into a circular center zone, at least two middle zones arranged concentrically at an outer periphery side of the center zone, and an edge zone arranged concentrically at an outermost periphery. The temperature control unit adjusts a control temperature of the heater with respect to each of the zones. | 2015-05-14 |
20150132864 | MANUFACTURING METHOD FOR ELECTROLUMINESCENT ELEMENT - A method for manufacturing an electroluminescent element including: a first manufacturing step of layering on a substrate, in the following order, a first electroconductive layer, a dielectric layer in which plural contact holes are formed which pass therethrough in a direction orthogonal to the substrate, a second electroconductive layer which is electrically connected to the first electroconductive layer inside the contact holes and which fills the contact holes, a light-emitting layer, and a third electroconductive layer; a temperature distribution measurement step of applying a voltage to the first electroconductive layer and the third electroconductive layer, causing the light-emitting layer to emit light, and measuring the temperature distribution of the electroluminescent element to obtain temperature unevenness information for the electroluminescent element; and a second manufacturing step of adjusting, on the basis of the temperature unevenness information, the density of the plural contact holes that pass through the dielectric layer. | 2015-05-14 |
20150132865 | METHOD FOR FORMING BUMPS, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME, SUBSTRATE PROCESSING APPARATUS, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP. | 2015-05-14 |
20150132866 | Silicon Wafer Coated With A Passivation Layer - Production of a silicon wafer coated with a passivation layer. The coated silicon wafer may be suitable for use in photovoltaic cells which convert energy from light impinging on the front face of the cell into electrical energy. | 2015-05-14 |
20150132867 | SEMICONDUCTOR PROCESS - The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units. | 2015-05-14 |
20150132868 | Method of Electrically Isolating Leads of a Lead Frame Strip - A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles and covering the unit lead frames with a molding compound after the semiconductor dies are attached to the die paddles. Spaced apart cuts are formed in the periphery of each unit lead frame that sever the leads from the periphery of each unit lead frame and extend at least partially into the molding compound in regions of the periphery where the leads are located so that the molding compound remains intact between the cuts. The lead frame strip is processed after the cuts are formed, and the unit lead frames are later separated into individual packages. | 2015-05-14 |
20150132869 | METHODS OF FABRICATING SEMICONDUCTOR DIE ASSEMBLIES - Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies. | 2015-05-14 |
20150132870 | METHODS FOR PRODUCING NEW SILICON LIGHT SOURCE AND DEVICES - The present invention relates to production method and device applications of a new silicon (Si) semiconductor light source that emits at a single wavelength at 1320 nm with a full width at half maximum (FWHM) of less than 200 nm and a photoluminescence quantum efficiency of greater than 50% at room temperature. The semiconductor that is the base for the new light source includes a surface which is treated by an acid vapor involving heavy water or Deuterium Oxide (D2O) and a surface layer producing the light source at 1320 nm. | 2015-05-14 |
20150132871 | OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING OXIDE SEMICONDUCTOR DEVICES, DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING DISPLAY DEVICES HAVING OXIDE SEMICONDUCTOR DEVICES - An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure. | 2015-05-14 |
20150132872 | DEVICE AND METHOD FOR THE SURFACE TREATMENT OF A SUBSTRATE AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - Various embodiments may relate to a device for the surface treatment of a substrate, including a processing head, which is mounted rotatably about an axis of rotation, and which comprises multiple gas outlets, which are at least partially implemented on a radial outer edge of the processing head. | 2015-05-14 |
20150132873 | Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays - Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems. | 2015-05-14 |
20150132874 | SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING FLIP-CHIP MOUNTED SOLID-STATE RADIATION TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS - Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device includes a radiation transducer (e.g., a light-emitting diode) and a transmissive support assembly including a transmissive support member, such as a transmissive support member including a converter material. A lead can be positioned at a back side of the transmissive support member. The radiation transducer can be flip-chip mounted to the transmissive support assembly. For example, a solder connection can be present between a contact of the radiation transducer and the lead of the transmissive support assembly. | 2015-05-14 |
20150132875 | MASK FOR FORMING LAYER, FORMING METHOD OF LAYER, AND MANUFACTURING METHOD OF ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY USING THE SAME - A mask for forming a layer, a method of forming a layer, and a manufacturing method of an organic light-emitting diode (OLED) display are disclosed. In one aspect, the mask includes at least one light absorption portion and at least one reflection portion that are formed in a unit region, the unit region corresponding to a region where a continuous layer is formed, wherein the light absorption portion and the reflection portion in the unit region are formed at different areas from each other. | 2015-05-14 |
20150132876 | METHOD FOR FABRICATING ORGANIC ELECTROLUMINESCENT DEVICES - A method of fabricating an organic electroluminescent device includes forming an organic electroluminescent layer emitting a light and a plurality of nano-sized embossing layers stacked to improve light extraction efficiency of the emitted light. | 2015-05-14 |
20150132877 | METHOD FOR PRODUCING OPTICAL SEMICONDUCTOR DEVICE - A method for producing optical semiconductor devices includes: forming a stacked semiconductor layer on a device substrate to provide an epitaxial substrate having a size corresponding to a section arrangement; forming, on the epitaxial substrate, a mask having a pattern for a semiconductor mesa and for a trench of at least one optical semiconductor device, a width of the trench in the pattern being determined according to a trench width map in which trench width is based upon an in-plane distribution of the thickness of a resin layer of the at least one device, and upon a correlation between the thickness of the resin layer and the trench width; forming a trench structure including the semiconductor mesa and the trench by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer. | 2015-05-14 |
20150132878 | METHOD FOR MANUFACTURING ORGANIC EL ELEMENT, ORGANIC EL ELEMENT, ORGANIC EL DISPLAY PANEL, ORGANIC EL DISPLAY APPARATUS, AND ORGANIC EL LIGHT-EMITTING APPARATUS - Method for manufacturing organic EL element, including: reducing internal pressure of vacuum chamber by vacuum pump connected thereto in state where substrate with applied film formed thereon is placed in vacuum chamber, applied film having been formed by applying material of organic light-emitting layer to substrate; and purifying applied film having passed through reducing the internal pressure of the vacuum chamber. Diphenylamine is used in portion of vacuum pump that is connected to inside of vacuum chamber. Reducing internal pressure of vacuum chamber is performed such that molecules of diphenylamine fly from vacuum pump into vacuum chamber and some of molecules are taken into applied film, and purifying is performed so that content of diphenylamine in applied film is in range from more than 0 nmol/cm | 2015-05-14 |
20150132879 | INKJET DEVICE, AND METHOD FOR MANUFACTURING ORGANIC EL DEVICE - An ink jet device includes a plurality of ink jet heads each including an ink housing unit that houses therein ink, a pressure application unit that ejects a droplet of the ink by applying pressure to the ink, and a nozzle through which the droplet of the ink is ejected, wherein with respect to at least one of the plurality of ink jet heads, a preliminary drive operation and a main drive operation are performed, the preliminary drive operation is an operation of pushing the ink toward an outer edge of the nozzle to the extent that the droplet of the ink is not ejected through the nozzle, and the main drive operation is an operation of ejecting the droplet of the ink through the nozzle after performance of the preliminary drive operation. | 2015-05-14 |
20150132880 | MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating MEMS device includes providing a silicon substrate. A structural dielectric layer is formed over a first side of the silicon substrate. Structure elements are embedded in the structural dielectric layer. The structure elements include a conductive backplate disposed over the silicon substrate, having venting holes and protrusion structures on top of the conductive backplate; and diaphragm located above the conductive backplate by a distance. A chamber is formed between the diaphragm and the conductive backplate. A cavity is formed in the silicon substrate at a second side. The cavity corresponds to the structure elements. An isotropic etching is performed on a dielectric material of the structural dielectric layer to release the structure elements. A first side of the diaphragm is exposed by the chamber and faces to the protrusion structures of the conductive backplate. A second side of the diaphragm is exposed to an environment space. | 2015-05-14 |
20150132881 | ADVANCED HYDROGENATION OF SILICON SOLAR CELLS - A method of hydrogenation of a silicon photovoltaic junction device is provided, the silicon photovoltaic junction device comprising p-type silicon semiconductor material and n-type silicon semiconductor material forming at least one p-n junction. | 2015-05-14 |
20150132882 | IMAGE SENSORS AND METHODS OF MANUFACTURING THE SAME - In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern. | 2015-05-14 |
20150132883 | PHOTO DETECTOR CONSISTING OF TUNNELING FIELD-EFFECT TRANSISTORS AND THE MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors. | 2015-05-14 |
20150132884 | METHOD OF MAKING IMAGE SENSOR DEVICES - A method of forming an image sensor device where the method includes forming a first dielectric layer on a substrate. The method further includes patterning the first dielectric layer to define an area for a reflective shield, where the area defined for the reflective shield is above a photodiode. Additionally, the method includes forming the reflective shield on the substrate by filling the defined area with a high reflectivity material, and the high reflective material comprises a polymer. | 2015-05-14 |
20150132885 | CIGS LIGHT-ABSORBING INK AND METHOD FOR PREPARING CIGS LIGHT-ABSORBING LAYER - The present invention relates to a method for preparing a CIS- or CIGS-based light-absorbing layer which is included in a thin film solar cell. More particularly, the present invention relates to a method for preparing a CIS- or CIGS-based light-absorbing layer which ultimately improves the efficiency of a solar cell since the remaining carbon impurities in the formed light-absorbing layer are minimized and additional sulfurization treatment or selenium treatment is made optional, not requisite. | 2015-05-14 |
20150132886 | DIKETOPYRROLOPYRROLE POLYMERS AND SMALL MOLECULES - The present invention relates to polymers, comprising a repeating unit of the formula (I), and compounds of formula (II), wherein Y, Y | 2015-05-14 |
20150132887 | DITHIENOBENZOFURAN POLYMERS AND SMALL MOLECULES FOR ELECTRONIC APPLICATION - The present invention relates to polymers comprising a repeating unit of the formula (I), and compounds of formula (VIII), or (IX), wherein Y, Y | 2015-05-14 |
20150132888 | METHODS OF FORMING WIRE INTERCONNECT STRUCTURES - A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location. | 2015-05-14 |
20150132889 | Package-On-Package (PoP) Structure Including Stud Bulbs and Method - Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. | 2015-05-14 |
20150132890 | Signal Transmission Arrangement - A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement. | 2015-05-14 |
20150132891 | BONDED STACKED WAFERS AND METHODS OF ELECTROPLATING BONDED STACKED WAFERS - A method including: providing a first wafer stack; applying a first bonding layer on the first wafer stack; providing a second wafer stack, where the second wafer stack includes vias; and applying a second bonding layer to the second wafer stack. The vias extend through the second wafer stack and to the second bonding layer. The second bonding layer is bonded to the first bonding layer. A seed layer is applied on a side of the second wafer stack opposite the second bonding layer such that a material of the seed layer (i) contacts the vias, and (ii) extends over and past ends of the second wafer stack and onto the first bonding layer. | 2015-05-14 |
20150132892 | Packaging Methods for Semiconductor Devices - Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated. | 2015-05-14 |
20150132893 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly. | 2015-05-14 |
20150132894 | Heat spreading substrate with embedded interconnects - Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another. | 2015-05-14 |
20150132895 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The semiconductor device includes a cathode region of the diode, a first buffer region adjacent to the cathode region at a rear surface side of a semiconductor substrate, a collector region of the IGBT, and a second buffer region adjacent to the collector region at the rear surface side. The method includes forming the step portion on the front surface so that the thin portion and the thick portion are formed in the semiconductor substrate, and injecting n-type impurities to a range on the front surface extending across the thin and thick portions so that the first buffer region and the second buffer region are formed. | 2015-05-14 |
20150132896 | NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES - Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing. | 2015-05-14 |
20150132897 | SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. | 2015-05-14 |
20150132898 | Semiconductor Device With Raised Source/Drain And Replacement Metal Gate - In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised source/drain regions are epitaxially formed adjacent to the dummy gate, and a protective cap is formed thereon. An etch process employing at least one acid is used to remove the dummy gate from the ETSOI. A gate dielectric layer is deposited on the protective cap and the ETSOI after removing the dummy gate. A replacement metal gate is then formed on the gate dielectric layer to replace the removed dummy gate, the gate dielectric layer is removed from the protective metal cap, and the protective cap is removed from the raised source/drain regions. | 2015-05-14 |
20150132899 | METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL - A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region. | 2015-05-14 |
20150132900 | VERTICAL GaN JFET WITH LOW GATE-DRAIN CAPACITANCE AND HIGH GATE-SOURCE CAPACITANCE - An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type. | 2015-05-14 |
20150132901 | Semiconductor Device and Fabricating the Same - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a gate region, source and drain (S/D) regions separated by the gate region and a first fin structure in a gate region in the N-FET region. The first fin structure is formed by a first semiconductor material layer as a lower portion, a semiconductor oxide layer as a middle portion and a second semiconductor material layer as an upper portion. The semiconductor device also includes a second fin structure in S/D regions in the N-FET region. The second fin structure is formed by the first semiconductor material layer as a lower portion and the semiconductor oxide layer as a first middle portion, the first semiconductor material layer as a second middle portion beside the first middle and the second semiconductor material layer as an upper portion. | 2015-05-14 |
20150132902 | POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 2015-05-14 |
20150132903 | Structure and Method For SRAM Cell Circuit - The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first and a second pull-up devices; a first and a second pull-down devices configured with the first and second pull-up devices to form two cross-coupled inverters for data storage; and a first and second pass-gate devices configured with the two cross-coupled inverters to form a port for data access, wherein the first and second pull-down devices each includes a first channel doping feature of a first doping concentration, and the first and second pass-gate devices each includes a second channel doping feature of a second doping concentration greater than the first doping concentration. | 2015-05-14 |
20150132904 | Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET. | 2015-05-14 |
20150132905 | STRUCTURE AND METHOD FOR SINGLE GATE NON-VOLATILE MEMORY DEVICE HAVING A CAPACITOR WELL DOPING DESIGN WITH IMPROVED COUPLING EFFICIENCY - The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode. | 2015-05-14 |
20150132906 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 2015-05-14 |
20150132907 | TECHNIQUES FOR ION IMPLANTATION OF NON-PLANAR FIELD EFFECT TRANSISTORS - A method of forming a fin field effect transistor (finFET) device includes forming a fin structure on a substrate, the substrate comprising a semiconductor material and forming a replacement gate cavity comprising an exposed portion of the fin structure and a sidewall portion adjacent the exposed portion, wherein the exposed portion of the fin structure defines a channel region. The method further includes performing at least one implant into the exposed portion of the fin structure. | 2015-05-14 |
20150132908 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device and method of fabricating the device, includes forming a fin-type active pattern that projects above a field insulating layer and forming a dummy gate structure that includes an epitaxial growth prevention layer to suppress nodule formation. | 2015-05-14 |
20150132909 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING PLASMA DOPING PROCESS AND SEMICONDUCTOR DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level. | 2015-05-14 |
20150132910 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion. | 2015-05-14 |
20150132911 | SELECTIVE FIN-SHAPING PROCESS - A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins. | 2015-05-14 |
20150132912 | METHOD FOR FABRICATING FIN FIELD EFFECT TRANSISTORS - A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric. | 2015-05-14 |
20150132913 | MECHANISMS FOR FORMING SEMICONDUCTOR DEVICE HAVING STABLE DISLOCATION PROFILE - Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions. | 2015-05-14 |
20150132914 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION - Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers. | 2015-05-14 |
20150132915 | Non-Volatile Memory Devices and Manufacturing Methods Thereof - There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer | 2015-05-14 |
20150132916 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer. | 2015-05-14 |
20150132917 | LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS - Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements. | 2015-05-14 |
20150132918 | Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer. | 2015-05-14 |
20150132919 | PHOTOMASK AND METHOD FOR FORMING DUAL STI STRUCTURE BY USING THE SAME - In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench. | 2015-05-14 |
20150132920 | Fin Structure for a FinFET Device - A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the substrate, a shallow trench isolation (STI) region disposed over the substrate and formed on opposing sides of the first semiconductor material, and a second semiconductor material forming a first fin and a second fin disposed on the STI region, the first fin spaced apart from the second fin by a width of the first semiconductor material. The fin structure may be used to generate the FinFET device by forming a gate layer formed over the first fin, a top surface of the first semiconductor material disposed between the first and second fins, and the second fin. | 2015-05-14 |
20150132921 | GAP-FILL METHODS - Provided are gap-fill methods. The methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief image comprising a plurality of gaps to be filled; (b) applying a gap-fill composition over the relief image, wherein the gap-fill composition comprises a self-crosslinkable polymer and a solvent, wherein the self-crosslinkable polymer comprises a first unit comprising a polymerized backbone and a crosslinkable group pendant to the backbone; and (c) heating the gap-fill composition at a temperature to cause the polymer to self-crosslink. The methods find particular applicability in the manufacture of semiconductor devices for the filling of high aspect ratio gaps. | 2015-05-14 |
20150132922 | ION REDUCED, ION CUT-FORMED THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (IC) (3DICS), AND RELATED METHODS AND SYSTEMS - Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a monolithic 3DIC, extra ions are implanted in the donor wafer to effectuate the ion-cut. Excess, residual implanted ions remain implanted in a top layer of the transfer layer of the 3DIC. However, these residual implanted ions can interfere with operation of electronic components in the 3DIC. In this regard, the 3DIC and methods disclosed herein involve reduction or removal of the residual extra ions before further electronic components are created and layered in a 3DIC. In this manner, the extra charge elements introduced by such extra ions are reduced or removed providing for better functionality in the completed device. | 2015-05-14 |
20150132923 | PROCESS FOR FABRICATING A HETEROSTRUCTURE LIMITING THE FORMATION OF DEFECTS - The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate. | 2015-05-14 |
20150132924 | HANDLER WAFER REMOVAL - A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer. | 2015-05-14 |
20150132925 | WAFER PROCESSING METHOD - A wafer processing method including a mask forming step of forming a mask for covering a region corresponding to each device on a functional layer formed on the front side of a substrate constituting a wafer, a groove forming step of spraying a fluid containing abrasive grains against the front side of the wafer to thereby form a groove for dividing the functional layer along each street, and an etching step of performing dry etching from the front side of the wafer to thereby form an etched groove along each street. Accordingly, it is possible to prevent that the functional layer may be separated to cause damage to each device. Furthermore, a wide area of the wafer can be processed at a time, so that the productivity can be improved. | 2015-05-14 |
20150132926 | PROCESS FOR LARGE-SCALE AMMONOTHERMAL MANUFACTURING OF GALLIUM NITRIDE BOULES - Large-scale manufacturing of gallium nitride boules using m-plane or wedge-shaped seed crystals can be accomplished using ammonothermal growth methods. Large-area single crystal seed plates are suspended in a rack, placed in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and crystals are grown ammonothermally. The orientation of the m-plane or wedge-shaped seed crystals are chosen to provide efficient utilization of the seed plates and of the volume inside the autoclave or high pressure apparatus. | 2015-05-14 |