20th week of 2020 patent applcation highlights part 63 |
Patent application number | Title | Published |
20200152425 | SUBSTRATE PROCESSING CHAMBER COMPONENT ASSEMBLY WITH PLASMA RESISTANT SEAL - Embodiments disclosed herein relate to a substrate processing chamber component assembly with plasma resistant seal. In one embodiment, the semiconductor processing chamber component assembly includes a first semiconductor processing chamber component, a second semiconductor processing component, and a sealing member. The sealing member has a body formed substantially from polytetrafluoroethylene (PTFE). The sealing member provides a seal between the first and second semiconductor processing chamber components. The body includes a first surface, a second surface, a first sealing surface, and a second sealing surface. The first surface is configured for exposure to a plasma processing region. The second surface is opposite the first surface. The first sealing surface and the second sealing surface extend between the first surface and the second surface. The first sealing surface contacts the first semiconductor processing chamber component. The second sealing surface contacts the second semiconductor processing chamber component. | 2020-05-14 |
20200152426 | SEMICONDUCTOR REACTOR AND METHOD FOR FORMING COATING LAYER ON METAL BASE MATERIAL FOR SEMICONDUCTOR REACTOR - A method for forming a coating layer on a metal base material for a semiconductor reactor according to an aspect of the present invention comprises the steps of: immersing a metal base material for a semiconductor reactor in an aqueous alkaline electrolyte solution containing NaOH and NaAlO | 2020-05-14 |
20200152427 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a substrate chuck having a first surface for supporting a substrate, a second surface opposite to the first surface, and a sidewall, a focus ring for surrounding a perimeter of the substrate, and an edge block for supporting the focus ring. The edge block includes a side electrode on the sidewall of the substrate chuck and a bottom electrode on the second surface of the substrate chuck. | 2020-05-14 |
20200152428 | SUBSTRATE SUPPORT, PLASMA PROCESSING APPARATUS, AND FOCUS RING - A substrate support for a plasma processing apparatus includes a first support area configured to support a substrate placed thereon; a second support area configured to support a focus ring placed thereon, and extending in a circumferential direction outward in a radial direction with respect to the first support area; a conductive structure configured to be connected to the focus ring; and a holder configured to hold the connection member to press the connection member downward, and also to cause the connection member to press the surface of the focus ring. The conductive structure includes a first conductive path which provides a terminal area outward in the radial direction with respect to the second support area, and a connection member configured to electrically connect the focus ring and the terminal area, and disposed on the terminal area to face a surface of the focus ring. | 2020-05-14 |
20200152429 | SUBSTRATE SUPPORT AND PLASMA PROCESSING APPARATUS - A substrate support for a plasma processing apparatus includes a first support area configured to support a substrate placed thereon; and a second support area configured to support a focus ring placed thereon. The second support area includes a lower electrode, a chuck area, and a bonding area. The chuck area includes a first electrode and a second electrode, and is configured to hold the focus ring by a potential difference set between the first electrode and the second electrode. The first electrode and the second electrode extend in the circumferential direction, and the first electrode is provided inward in the radial direction with respect to the second electrode. The substrate support further includes a first conducting wire and a second conducting wire each extending around a center or on the center between an inner boundary and an outer boundary of the second support area. | 2020-05-14 |
20200152430 | DEVICE AND METHOD FOR PLASMA TREATMENT OF ELECTRONIC MATERIALS - Plasma applications are disclosed that operate with argon and other molecular gases at atmospheric pressure, and at low temperatures, and with high concentrations of reactive species. The plasma apparatus and the enclosure that contains the plasma apparatus and the substrate are substantially free of particles, so that the substrate does not become contaminated with particles during processing. The plasma is developed through capacitive discharge without streamers or micro-arcs. The techniques can be employed to remove organic materials from a substrate, thereby cleaning the substrate; to activate the surfaces of materials, thereby enhancing bonding between the material and a second material; to etch thin films of materials from a substrate; and to deposit thin films and coatings onto a substrate; all of which processes are carried out without contaminating the surface of the substrate with substantial numbers of particles. | 2020-05-14 |
20200152431 | PROCESSING CHAMBER WITH SUBSTRATE EDGE ENHANCEMENT PROCESSING - Embodiments of the present disclosure generally provide an apparatus and methods for processing a substrate. More particularly, embodiments of the present disclosure provide a processing chamber having an enhanced processing efficiency at an edge of a substrate disposed in the processing chamber. In one embodiment, a processing chamber comprises a chamber body defining an interior processing region in a processing chamber, a showerhead assembly disposed in the processing chamber, wherein the showerhead assembly has multiple zones with an aperture density higher at an edge zone than at a center zone of the showerhead assembly, a substrate support assembly disposed in the interior processing region of the processing chamber, and a focus ring disposed on an edge of the substrate support assembly and circumscribing the substrate support assembly, wherein the focus ring has a step having a sidewall height substantially similar to a bottom width. | 2020-05-14 |
20200152432 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes a processing container configured to accommodate a substrate and perform a substrate processing that generates a byproduct that becomes a source of a harmful gas; and a liquid holder provided in an area of the processing container where the byproduct generated by the substrate processing adheres and configured to hold a liquid that adsorbs the byproduct. | 2020-05-14 |
20200152433 | METHODS AND APPARATUS FOR MICROWAVE PLASMA ASSISTED CHEMICAL VAPOR DEPOSITION REACTORS - The disclosure relates to microwave cavity plasma reactor (MCPR) apparatus and associated optical measurement system that enable microwave plasma assisted chemical vapor deposition (MPACVD) of a component such as diamond while measuring the local surface properties of the component while being grown. Related methods include deposition of the component, measurement of the local surface properties, and/or alteration of operating conditions during deposition in response to the local surface properties. As described in more detail below, the MPCR apparatus includes one or more electrically conductive, optically transparent regions forming part of the external boundary of its microwave chamber, thus permitting external optical interrogation of internal reactor conditions during deposition while providing a desired electrical microwave chamber to maintain selected microwave excitation modes therein. | 2020-05-14 |
20200152434 | MASS SPECTROMETER, MASS SPECTROMETRY METHOD, AND MASS SPECTROMETRY PROGRAM - A device that performs MSn analysis including: a mass window group setting information input receiver that receives input of information concerning the number of mass window groups, the number of mass windows, and a mass-to-charge ratio width of each of the mass windows; a mass window group setter that sets a first mass window group and a second mass window group, in which a mass-to-charge ratio at a boundary of adjacent mass windows differs from a mass-to-charge ratio at a boundary of mass windows in the first mass window group; a product-ion scan measurement section that performs, for each of the first and second mass window groups, an operation of performing scan measurement of product ions by use of the plurality of mass windows in sequence to acquire pieces of product-ion scan data; and a product-ion spectrum generator that generate a product-ion spectrum by integrating pieces of product-ion scan data. | 2020-05-14 |
20200152435 | Method and Apparatus for the Analysis of Molecules Using Mass Spectrometry and Optical Spectroscopy - A method of analyzing molecules, comprising: generating ions from a sample of molecules; cooling the generated ions below ambient temperature; fragmenting at least some of the cooled ions by irradiating the ions with light at a plurality of different wavelengths (λ) within one or more predetermined spectral intervals; recording a fragment mass spectrum of the fragmented ions comprising a detected signal (I) versus m/z over a predetermined range of m/z values for each of the plurality of different wavelengths (λ), thereby recording a two-dimensional dependency of the detected signal (I) on m/z and irradiation wavelength (λ); and determining from the recorded two-dimensional dependency an identity of at least one of the generated ions and/or relative abundances of different generated ions and thereby determining an identity of at least of one of the molecules and/or relative abundances of different molecules in the sample. | 2020-05-14 |
20200152436 | AMBIENT IONISATION SOURCE UNIT - An ambient ionisation source unit ( | 2020-05-14 |
20200152437 | TAPERED MAGNETIC ION TRANSPORT TUNNEL FOR PARTICLE COLLECTION - An apparatus for particle collection is provided. The apparatus includes a magnetic element configured to generate a tapered magnetic ion transport tunnel that collects particles from a local environment, a detector configured to perform one or more measurements of the collected particles, and ion optics configured to transport the collected particles to the detector. | 2020-05-14 |
20200152438 | MASS SPECTROMETER, LASER LIGHT INTENSITY ADJUSTING METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM - A mass spectrometer includes a MALDI ion source, an ion separator that separates ions generated from the MALDI ion source, a detector that detects ions ejected from the ion separator, a data processor that acquires a mass spectrum of the ion detected in the detector, and a controller that controls intensity of laser light with which the MALDI ion source is irradiated. The controller includes a determiner that determines whether a peak of a matrix is detected in the mass spectrum acquired in the data processor while increasing intensity of laser light emitted to a sample matrix mixture from a first intensity, and a setter that acquires intensity of laser light at a time point at which the peak of the matrix is detected as a second intensity, and sets the second intensity as intensity of laser light used for analysis of the sample. | 2020-05-14 |
20200152439 | WIDE-RANGE HIGH MASS RESOLUTION IN REFLECTOR TIME-OF-FLIGHT MASS SPECTROMETERS - The invention relates to the operation of an energy-focusing and solid-angle-focusing reflector for time-of-flight mass spectrometers with pulsed ion acceleration into a flight tube, e.g. from an ion source with ionization by matrix-assisted laser desorption (MALDI). The objective of the invention is to generate high mass resolution in wide mass ranges up to high masses above eight kilodaltons by varying at least one operating voltage on one of the diaphragms of the reflector which can be varied according to a suitable time function during the spectrum acquisition. It may also be advantageous to adapt the operation of the accelerating voltages in the starting region of the ions accordingly. These measures make it possible to achieve a mass resolution much higher than R=100,000 in a wide mass range extending up to and above eight kilodaltons. | 2020-05-14 |
20200152440 | TIME OF FLIGHT MASS ANALYSER WITH SPATIAL FOCUSSING - A Time of Flight mass analyser is disclosed comprising: at least one ion mirror (( | 2020-05-14 |
20200152441 | ORTHOGONAL ACCELERATION TIME-OF-FLIGHT MASS SPECTROMETRY - A multipole ion guide ( | 2020-05-14 |
20200152442 | LIGHT-EMITTING TUBE ARRAY-TYPE LIGHT SOURCE DEVICE, LIGHT SOURCE MODULE USING THE SAME, AND FLUID TREATMENT DEVICE USING THE SAME LIGHT SOURCE DEVICE - A light-emitting tube array-type light source device includes: a plurality of light-emitting gas discharge tubes | 2020-05-14 |
20200152443 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes a processing liquid supply mechanism | 2020-05-14 |
20200152444 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - There is provided a technique that includes forming a film containing silicon, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing silicon, carbon, and nitrogen by performing a set a predetermined number of times, the set including: supplying a first precursor, which contains at least two Si—N bonds and at least one Si—C bond in one molecule, to the substrate; and supplying a second precursor, which contains nitrogen and hydrogen, to the substrate; and forming a second layer by supplying an oxidant to the substrate, to thereby oxidize the first layer. | 2020-05-14 |
20200152445 | METHOD FOR MANUFACTURING BACKSIDE METALIZED COMPOUND SEMICONDUCTOR WAFER - A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including aurum on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer. | 2020-05-14 |
20200152446 | ULTRATHIN ATOMIC LAYER DEPOSITION FILM ACCURACY THICKNESS CONTROL - Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature. | 2020-05-14 |
20200152447 | SUBSTRATE DRYING METHOD AND SUBSTRATE PROCESSING APPARATUS - An upper surface of a substrate is supplied with a pre-drying processing liquid which is a solution of a sublimable substance and a solvent. Thereafter, the solvent is evaporated from the pre-drying processing liquid on the substrate and a solid of the sublimable substance is precipitated in the pre-drying processing liquid on the substrate. Thereafter, at least a portion of the solid of the sublimable substance is dissolved in the pre-drying processing liquid on the substrate. Thereafter, the solvent is evaporated from the pre-drying processing liquid in which the solid of the sublimable substance has been dissolved and the solid of the sublimable substance is precipitated onto the substrate. Thereafter, the solid of the sublimable substance is sublimated and removed from the upper surface of the substrate. | 2020-05-14 |
20200152448 | METHOD FOR LAYER BY LAYER GROWTH OF CONFORMAL FILMS - Techniques herein include methods of forming conformal films on substrates including semiconductor wafers. Conventional film forming techniques can be slow and expensive. Methods herein include depositing a self-assembled monolayer (SAM) film over the substrate. The SAM film can include an acid generator configured to generate acid in response to a predetermined stimulus. A polymer film is deposited over the SAM film. The polymer film is soluble to a predetermined developer and configured to change solubility in response to exposure to the acid. The acid generator is stimulated and generates acid. The acid is diffused into the polymer film. The polymer film is developed with the predetermined developer to remove portions of the polymer film that are not protected from the predetermined developer. These process steps can be repeated a desired number of times to grow an aggregate film layer by layer. | 2020-05-14 |
20200152449 | Treatment System and Method - A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer. | 2020-05-14 |
20200152450 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH GATE SPACER - A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process in a process chamber. The atomic layer deposition process includes alternately and sequentially introducing a first precursor gas and a second precursor gas over the sidewall of the gate stack to form the sealing layer. The second precursor gas has a different atomic concentration of carbon than that of the first precursor gas. The atomic layer deposition process also includes removing a reaction byproduct from the process chamber after the first precursor gas is introduced and before the second precursor gas is introduced. The method also includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack. | 2020-05-14 |
20200152451 | METHOD FOR OXIDIZING A SILICON CARBIDE BASED ON MICROWAVE PLASMA AT AN AC VOLTAGE - A method for oxidizing a silicon carbide based on microwave plasma at an AC voltage, including: step one, providing a silicon carbide substrate, and placing the silicon carbide substrate in a microwave plasma generating device; step two, introducing oxygen-containing gas to generate oxygen plasma at an AC voltage; step three, controlling movements of oxygen ions and electrons in the oxygen plasma by the AC voltage to generate an oxide layer having a predetermined thickness on the silicon carbide substrate, wherein when a voltage of the silicon carbide substrate is negative, the oxygen ions move close to an interface and perform an oxidation reaction with the silicon carbide, and when the voltage of the silicon carbide substrate is positive, the electrons move close to the interface and perform a reduction reaction with the silicon carbide, removing carbon residue; step four, stopping the introduction of oxygen-containing gas and the reaction completely. | 2020-05-14 |
20200152452 | METHODS OF ENCAPSULATION - Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C. | 2020-05-14 |
20200152453 | SYSTEMS AND METHODS FOR INHIBITING DEFECTIVITY, METAL PARTICLE CONTAMINATION, AND FILM GROWTH ON WAFERS - Methods for processing a substrate are provided. The method includes receiving a substrate. The substrate has a front side surface, a backside surface, and a side edge surface. The method also includes coating the front side surface, the backside surface and the side edge surface with a self-assembled monolayer and exposing an area of interest with actinic radiation. The actinic radiation causes a de-protection reaction within the self-assembled monolayer within the central region. The method also includes removing the self-assembled monolayer from the area of interest while the self-assembled monolayer remains on remaining surfaces of the substrate. | 2020-05-14 |
20200152454 | MULTI-STATE DEVICE BASED ON ION TRAPPING - A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region. | 2020-05-14 |
20200152455 | A Compound Semiconductor Substrate, A Pellicle Film, And A Method For Manufacturing A Compound Semiconductor Substrate - A compound semiconductor substrate, a pellicle film, and a method for manufacturing a compound semiconductor substrate that can achieve thinning of SiC film are provided. | 2020-05-14 |
20200152456 | SYSTEMS AND METHOD FOR INTEGRATED DEVICES ON AN ENGINEERED SUBSTRATE - A method of forming a plurality of devices on an engineered substrate structure includes forming an engineered substrate by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core with a first adhesion shell, encapsulating the first adhesion shell with a barrier layer, forming a bonding layer on the barrier layer, and forming a substantially single crystal layer coupled to the bonding layer. The method further comprises forming a buffer layer coupled to the substantially single crystal layer, forming one or more epitaxial III-V layers on the buffer layer according to requirements associated with the plurality of devices, and forming the plurality of devices on the substrate by removing a portion of the one or more epitaxial III-V layers disposed between the plurality of devices and removing a portion of the buffer layer disposed between the plurality of devices. | 2020-05-14 |
20200152457 | SEMICONDUCTOR STACK - A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed potion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm | 2020-05-14 |
20200152458 | Metal Oxide Film and Manufacturing Method Thereof, Thin Film Transistor and Array Substrate - A metal oxide film and a manufacturing method thereof, a thin film transistor and an array substrate are provided. The manufacturing method of the metal oxide film includes: forming a metal oxide film on a base substrate; and suppling a negative ion to the metal oxide film for a preset time period by performing a anodization method, to convert a portion of metal ions in the metal oxide film into a metal oxide. | 2020-05-14 |
20200152459 | PROCESS FOR PREPARING A SUPPORT FOR A SEMICONDUCTOR STRUCTURE - A process for preparing support comprises the placing of a substrate on a susceptor in a chamber of a deposition system, the susceptor having an exposed surface not covered by the substrate; the flowing of a precursor containing carbon in the chamber at a deposition temperature so as to form at least one layer on an exposed face of the substrate, while at the same time depositing species of carbon and of silicon on the exposed surface of the susceptor. The process also comprises, directly after the removal of the substrate from the chamber, a first etch step consisting of the flowing of an etch gas in the chamber at a first etching temperature not higher than the deposition temperature so as to eliminate at least some of the species of carbon and silicon deposited on the susceptor. | 2020-05-14 |
20200152460 | GRADED HARDMASK INTERLAYER FOR ENHANCED EXTREME ULTRAVIOLET PERFORMANCE - A patterning stack and methods are provided for semiconductor processing. The method includes forming a graded hardmask, the graded hardmask including a first material and a second material with extreme ultraviolet (EUV) absorption cross sections for absorption of EUV wavelengths, the second material configured to provide adhesion to photoresist materials. The method also includes depositing a photoresist layer over the graded hardmask. The method additionally includes patterning the photoresist layer. The method further includes etching the graded hardmask. The method also includes removing the photoresist layer | 2020-05-14 |
20200152461 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming first sacrificial cores on a first region of a lower structure and second sacrificial cores on a second region of the lower structure, forming spacers on side walls of the first sacrificial cores and side walls of the second sacrificial cores, forming a protective pattern covering the second sacrificial cores on the second region of the lower structure, removing the first sacrificial cores from the first region, and etching the lower structure using the spacers on the first region, and the second sacrificial cores and the spacers on the second region. | 2020-05-14 |
20200152462 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a “U” shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns. | 2020-05-14 |
20200152463 | DEPOSITION MASK, DEPOSITION MASK APPARATUS, MANUFACTURING METHOD OF DEPOSITION MASK, AND MANUFACTURING METHOD OF DEPOSITION MASK APPARATUS - A deposition mask includes: a first mask having an opening formed therein; and a second mask superposed on the first mask and having a plurality of through-holes formed therein, the through-hole having a planar dimension smaller than a planar dimension of the opening; wherein: the deposition mask has a plurality of joints that join the second mask and the first mask to each other; the plurality of joints are arranged along an outer edge of the second mask; and a notch is formed at a position in the outer edge of the second mask, the position corresponding to a space between the adjacent two joints. | 2020-05-14 |
20200152464 | Fin Patterning Methods for Increased Process Margins - The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel. | 2020-05-14 |
20200152465 | Methods to Design and Uniformly Co-fabricate Small Vias and Large Cavities through a Substrate - A method of forming concurrently openings in a substrate or wafer or a portion of substrate or wafer openings therein at least one of the openings has a relatively high aspect ratio and another one of the openings has a relatively low aspect ratio, the method comprising: bonding the substrate or wafer or a portion of substrate or wafer to a carrier substrate; forming a ring trench in the substrate or wafer or in a portion of the substrate or wafer, the ring trench having an outer perimeter that corresponds an outer perimeter of the another one of the openings having said relatively low aspect ratio and having an inner perimeter spaced from the outer perimeter by a predetermined distance; forming an opening in said substrate or wafer or in a portion of substrate or wafer having said high aspect ratio concurrently with the forming of the ring trench; and separating the substrate or wafer or in a portion of the substrate or wafer from the carrier substrate. | 2020-05-14 |
20200152466 | METHOD AND APPARATUS FOR NON LINE-OF-SIGHT DOPING - A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature. | 2020-05-14 |
20200152467 | PLATING SYSTEMS HAVING REDUCED AIR ENTRAINMENT - Electroplating processing systems according to the present technology may include a recirculating tank containing a first volume of processing fluid. The recirculating tank may be fluidly coupled with a delivery pump. The systems may include a vessel configured to receive the processing fluid from the pump. The vessel may include an inner chamber and an outer chamber, and the inner chamber may be sized to hold a second volume of processing fluid less than the first volume of processing fluid. A liquid level sensor may be associated with the vessel to provide a liquid level indication in the outer chamber. The systems may include a return line coupled with an outlet of the vessel and coupled with an inlet of the recirculating tank. The systems may also include a return pump fluidly coupled with the return line. The return pump may be electrically coupled with the liquid level sensor. | 2020-05-14 |
20200152468 | Methods of Reducing Pattern Roughness in Semiconductor Fabrication - A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant. | 2020-05-14 |
20200152469 | METHOD OF MANUFACTURE INCLUDING POLISHING PAD MONITORING METHOD AND POLISHING APPARATUS INCLUDING POLISHING PAD MONITORING DEVICE - In a method of manufacture, a displacement sensor is provided over a conditioner disk. The conditioner disk is rotated to perform a conditioning process on a polishing surface of a polishing pad. A displacement of the rotating conditioner disk is detected using the displacement sensor during the conditioning process. A height of the conditioner disk is calculated from the detected displacement. An end point of the conditioning process is determined on the polishing surface based on the calculated height. | 2020-05-14 |
20200152470 | METHOD OF ETCHING COPPER INDIUM GALLIUM SELENIDE (CIGS) MATERIAL - Methods for dry plasma etching thin layers of material including Cu(In, Ga)Se, e.g., CIGS material on semiconductor substrates are provided. A method of etching a CIGS material layer such as copper indium gallium selenide film, includes: flowing an etching gas including a mixture of gases into a process chamber having a substrate disposed therein, the substrate including a copper indium gallium selenide layer having a patterned film stack disposed thereon, the patterned film stack covering a first portion of the copper indium gallium selenide layer and exposing a second portion of the copper indium gallium selenide layer; and contacting the copper indium gallium selenide layer with the etching gas to remove the second portion and form one or more copper indium gallium selenide edges of the first portion. | 2020-05-14 |
20200152471 | POLISHING METHOD - A polishing method for polishing by sliding a semiconductor silicon wafer, held by a polishing head, against a polishing pad attached to a turn table while supplying a polishing agent, wherein the semiconductor silicon wafer is subjected to primary polishing, secondary polishing, and final polishing in turn, the secondary polishing comprises polishing by an alkaline based polishing agent which includes free abrasive grains and does not include a water-soluble polymer agent, and subsequent rinse polishing by a polishing agent which includes a water-soluble polymer agent and the rinse polishing includes two stages of polishing, wherein, after performing a first stage of the rinse polishing while supplying a polishing agent which includes a water-soluble polymer agent, a second stage of the rinse polishing is performed while supplying a switched polishing agent whose water-soluble polymer agent has an average molecular weight larger than the polishing agent of the first stage. | 2020-05-14 |
20200152472 | METHOD FOR PLANARIZATION OF ORGANIC FILMS - Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation. | 2020-05-14 |
20200152473 | METHOD FOR FORMING AND USING STRESS-TUNED SILICON OXIDE FILMS IN SEMICONDUCTOR DEVICE PATTERNING - A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern. | 2020-05-14 |
20200152474 | PROCESSING METHOD FOR PRODUCING PHOTOMASK WITH DOUBLE PATTERNS AND STORAGE MEDIUM THEREOF - A process method for producing a photomask with double patterns. The processing method includes obtaining a contact distribution pattern, having multiple contacts. The contacts are sorted into multiple contact blocks in array type, pair type and isolation type. The contacts are decomposed into a first patterning group and a second patterning group, which are configured to interpose to each other. The numbers of contacts of the first patterning group and the second patterning group are equal within an error range. The first patterning group and the second patterning group are check whether or not having adjacent two contacts with a distance less than a minimum distance. If it is less than a minimum distance, one of the adjacent two contacts is changed from a current one of the first patterning group and the second patterning group to another. The first/second patterning groups are output to from first/second photomasks. | 2020-05-14 |
20200152475 | Method of Fabricating Semiconductor Device, Vacuum Processing Apparatus and Substrate Processing Apparatus - There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer. | 2020-05-14 |
20200152476 | Via Connection to a Partially Filled Trench - An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via. | 2020-05-14 |
20200152477 | DOPED METAL-CHALCOGENIDE THIN FILM AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a doped metal chalcogenide thin film includes depositing a dopant atom on a base material; and forming a doped metal chalcogenide thin film on the dopant atom-deposited base material by supplying heat and a reaction gas comprising a metal precursor and a chalcogen precursor to the dopant atom-deposited base material. | 2020-05-14 |
20200152478 | DEVICE MANUFACTURING METHOD - There is provided a method of manufacturing a device, which comprises: a preparation step of preparing a workpiece having a recess formed therein; a burying step of burying a sacrificial material composed of a thermally decomposable organic material in the recess; a lamination step of laminating a preliminary sealing film on the sacrificial material buried in the recess; a first removal step of removing the sacrificial material in the recess through the preliminary sealing film, by annealing the workpiece at a first temperature and thermally decomposing the sacrificial material; a processing step of performing a predetermined process on a portion other than the recess in the workpiece, in a state in which the recess is covered with the preliminary sealing film; and a second removal step of removing the preliminary sealing film. | 2020-05-14 |
20200152479 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface. | 2020-05-14 |
20200152480 | METHOD OF FASTENING A SEMICONDUCTOR CHIP ON A LEAD FRAME, AND ELECTRONIC COMPONENT - A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame. | 2020-05-14 |
20200152481 | Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices - Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias. | 2020-05-14 |
20200152482 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, an electronic component electrically connected to the semiconductor element, a connection member electrically connecting the electronic component to the semiconductor element, and a sealing resin portion having a first surface and a second surface opposite to the first surface and integrally holding the semiconductor element, the electronic component, and the connection member in a state where a semiconductor top surface as a surface of the semiconductor element and a component surface as a surface of the electronic component are exposed from the sealing resin portion on a side adjacent to the first surface. | 2020-05-14 |
20200152483 | CONTROL OF UNDER-FILL USING AN ENCAPSULANT AND A TRENCH OR DAM FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE - Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls in combination with a dam or a trench to control the distribution of an under-fill material between one or more components and a packaging substrate. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant reduces the tendency of the under-fill material to wick around the solder balls by capillary action which can prevent or limit the capillary under-fill material from flowing onto or contacting other components. The dam or trench aids in retaining the under-fill material within a keep out zone to prevent or limit the under-fill material from contacting other components. | 2020-05-14 |
20200152484 | CARRIER SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE CARRIER SUBSTRATE - A carrier substrate includes a core layer and at least one unit pattern portion, and the unit pattern portion includes a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, a second metal layer disposed on the release layer, and a third metal layer disposed on the second metal layer and covering side surfaces of the release layer, and a method of manufacturing a semiconductor package using the carrier substrate. | 2020-05-14 |
20200152485 | IMPROVEMENTS IN OR RELATING TO PUMPING LINE ARRANGEMENTS - A pumping line arrangement includes a chamber connecting line which is fluidly connectable to a process chamber that forms part of a semiconductor fabrication tool. The pumping line arrangement also includes a valve module which is fluidly connected to the chamber connecting line. The valve module splits the chamber connecting line into respective first and second pumping lines. The first pumping line is intended to carry a first process flow and the second pumping line is intended to carry a second process flow which is incompatible with the first process flow. At least one of the first pumping line or the second pumping line includes fluidly connected therewithin a pre-abatement module that is configured to remove one or more incompatible constituents from the process flow intended to be carried by the other pumping line. | 2020-05-14 |
20200152486 | SUBSTRATE DRYING METHOD, PHOTORESIST DEVELOPING METHOD, PHOTOLITHOGRAPHY METHOD INCLUDING THE SAME, AND SUBSTRATE DRYING SYSTEM - Disclosed are substrate drying methods, photoresist developing methods, and/or photolithography methods. The substrate drying method including providing a drying liquid on a substrate, increasing a pressure of the drying liquid to produce a supercritical fluid, and removing the supercritical fluid to dry the substrate may be provided. | 2020-05-14 |
20200152487 | METHOD OF CLEANING A SEMICONDUCTOR CHIP AND APPARATUS FOR PERFORMING THE SAME - A method of and apparatus for cleaning a semiconductor chip, the method including applying a first polar composition to a protection layer on a surface of at least one semiconductor chip to remove a particle from the surface of the at least one semiconductor chip and suspend the particle in the first polar composition; and applying a second polar composition, having a surface tension that is lower than that of the first polar composition, to a central portion of the applied first polar composition to push the first polar composition and the particle toward an outskirt of the at least one semiconductor chip. | 2020-05-14 |
20200152488 | CLEANING WATER SUPPLY DEVICE - A cleaning water supply device includes an ultrapure water line through which ultrapure water flows by a fixed amount, a production unit that produces cleaning water by adding a solute to the ultrapure water line by a fixed amount, a storage tank for the cleaning water, cleaning machines to which the cleaning water is supplied from the storage tank, and a controller that controls the cleaning water production unit so that a water level in the storage tank is in a predetermined range. | 2020-05-14 |
20200152489 | SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM - A substrate processing method includes etching a substrate on which a silicon oxide film and a silicon nitride film are formed with a phosphoric acid processing liquid. In the etching, a silicon concentration in the phosphoric acid processing liquid is a first silicon concentration at which the silicon oxide film is etched, from a start time until a first time interval has elapsed. | 2020-05-14 |
20200152490 | HEATING ELEMENT, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A heating element which is made of a material heated by absorbing an electromagnetic wave supplied from a heating device and which has an electromagnetic wave transmission region which transmits the electromagnetic wave and an electromagnetic wave non-transmission region which does not transmit the electromagnetic wave. | 2020-05-14 |
20200152491 | COMPONENT RECEIVING DEVICE WITH OPTICAL SENSOR - A receiving device for components. The receiving device is designed to be adjusted in a controlled manner relative to a deposit point at least partly along a first, second, and/or third axis by at least one linear drive and/or move a support guided by the receiving device along one of the first and/or second axes by a drive. The receiving device has a position sensor which is paired with a component deposit point in order to detect a component which has only been partly deposited in a pocket of the support at the component deposit point, where the position sensor is connected to the receiving device laterally of the support such that the position sensor is moved directly together with the receiving device. | 2020-05-14 |
20200152492 | FORMATION OF ELASTOMERIC LAYER ON SELECTIVE REGIONS OF LIGHT EMITTING DEVICE - A light emitting diode (LED) includes an elastomeric material that facilitates adhesive attachment with a pick-up head for pick and place operations. The LED includes an epitaxial layer defining a mesa structure and a light emitting surface. The mesa structure includes an active layer to emit light, and the emitted light is reflected at the mesa structure toward a light emitting region of the light emitting surface and transmitted at the light emitting region. An elastomeric material is on a portion of the light emitting surface, such as the light emitting region or a passive region. At the light emitting region, the elastomeric material may be shaped as a lens that collimates light transmitted from the light emitting region, and also facilitates adhesion to the pick-up head. At the passive region, the elastomeric material facilitates adhesion to the pick-up head without interfering with light emitted from the light emitting region. | 2020-05-14 |
20200152493 | INTEGRATED SEMICONDUCTOR PROCESSING - Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system. | 2020-05-14 |
20200152494 | WAFER-LIKE SENSOR - A wafer-like semiconductor sensor includes a wafer-like base formed of a plurality of layers of chemically-hardened glass and an electronics module mounted to a recessed pocket in the base and containing a sensor. | 2020-05-14 |
20200152495 | 3D IC BUMP HEIGHT METROLOGY APC - The present disclosure, in some embodiments, relates to a substrate metrology system. The substrate metrology system includes a warpage measurement module configured to determine one or more substrate warpage parameters of a substrate. The substrate includes a plurality of conductive interconnect layers within a dielectric structure over a semiconductor substrate. A metrology module is located physically downstream of the warpage measurement module and has an optical element configured to measure one or more dimensions of the substrate. The metrology module is configured to place the optical element at a plurality of different initial positions, which are directly over a plurality of different locations on the substrate, based upon the one or more substrate warpage parameters. A substrate transport system is configured to transfer the substrate from a first position within the warpage measurement module to a non-overlapping second position within the metrology module. | 2020-05-14 |
20200152496 | MICROENVIRONMENT FOR FLEXIBLE SUBSTRATES - A substrate container ( | 2020-05-14 |
20200152497 | SYSTEMS, APPARATUS, AND METHODS FOR AN IMPROVED LOAD PORT BACKPLANE - A method is for sealing a backplane component of a load port system to an equipment front end module (EFEM). The method includes mounting a leveling block to the EFEM. A conical hole adjustment assembly is coupled between a first distal end of the leveling block and the backplane component. The method further includes rotating a first leveling adjustment bolt in the conical hole adjustment assembly to align the backplane component with the EFEM. | 2020-05-14 |
20200152498 | APPARATUS AND METHOD FOR ALIGNING INTEGRATED CIRCUIT LAYERS USING MULTIPLE GRATING MATERIALS - Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer. | 2020-05-14 |
20200152499 | WAFER STAGE AND METHOD OF MANUFACTURING THE SAME - A wafer stage includes an electrostatic chuck (ESC) plate, an upper supporting plate, a lower supporting plate and a temperature controller. The ESC plate includes a first surface that supports a wafer. The upper supporting plate is bonded to a second surface of the ESC plate opposite to the first surface. The lower supporting plate overlaps the upper supporting plate. The temperature controller is disposed between the upper supporting plate and the lower supporting plate. The ESC plate includes ceramics. The upper supporting plate includes a composite material of aluminum or aluminum alloy and ceramics or carbon. The ESC plate and the upper supporting plate are directly bonded to each other by a room temperature solid bonding process. Thus, the wafer stage has sufficient strength to withstand pressure differences between a vacuum and atmospheric pressure, improved temperature response by minimizing heat capacity, and prevents warpage of the ESC plate. | 2020-05-14 |
20200152500 | TUNABLE TEMPERATURE CONTROLLED SUBSTRATE SUPPORT ASSEMBLY - Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heating assembly. The substrate support assembly comprises a body having a substrate support surface and a lower surface, one or more main resistive heaters disposed in the body, a plurality of spatially tunable heaters disposed in the body, and a spatially tunable heater controller coupled to the plurality of spatially tunable heaters, the spatially tunable heater controller configured to independently control an output one of the plurality of spatially tunable heaters relative to another of the plurality of spatially tunable heaters. | 2020-05-14 |
20200152501 | APPARATUS FOR MANUFACTURING A DISPLAY DEVICE AND A MANUFACTURING METHOD THEREOF - An apparatus for manufacturing a display device includes a first jig including a first side, the first side having a concave groove for receiving a cover window, wherein the cover window includes a first planar portion, a first curved portion and a second curved portion, wherein the first and second curved portions are disposed at opposite ends of the first planar portion in a first direction, a second jig including a planar side for receiving a display panel, wherein when the second jig is moved in a second direction crossing the first direction with the display panel on the planar side, the display panel is disposed between the first and second curved portions of the cover window, and a pair of third jigs for supporting the first and second curved portions of the cover window. | 2020-05-14 |
20200152502 | METHODS AND APPARATUS FOR A THREE-DIMENSIONAL (3D) ARRAY HAVING ALIGNED DEEP-TRENCH CONTACTS - Methods and apparatus for a three-dimensional (3D) array having aligned deep-trench contacts are disclosed. In an embodiment, a method includes forming an array stack having conductor layers and insulator layers, and forming a hard mask on top of the array stack. The hard mask includes a plurality of holes. The method also includes forming a pull-back mask on top of the hard mask, and etching the pull-back mask so that at least one hole of the hard mask is exposed. The method also includes etching through one or more exposed holes of the hard mask to remove one or more layers of the array stack. | 2020-05-14 |
20200152503 | INTEGRATED ELECTRONIC CIRCUIT WITH AIRGAPS - A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures. | 2020-05-14 |
20200152504 | AIRGAP SPACERS FORMED IN CONJUNCTION WITH A LATE GATE CUT - Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer. | 2020-05-14 |
20200152505 | METHOD FOR MANUFACTURING BONDED SOI WAFER - The present invention is a method for manufacturing a bonded SOI wafer, including: preparing, as a base wafer, a silicon single crystal wafer whose initial interstitial oxygen concentration is 15 ppma or more ('79ASTM); forming a silicon oxide film on a surface of the base wafer by heating the base wafer in an oxidizing atmosphere such that a feeding temperature at which the base wafer is fed into a heat treatment furnace for the heat treatment is 800° C. or more, and the base wafer is heated at the feeding temperature or higher; bonding the base wafer to the bond wafer with the silicon oxide film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a method for manufacturing a bonded SOI wafer by a base oxidation method which suppresses the formation of oxide precipitates in a base wafer while suppressing slip dislocation. | 2020-05-14 |
20200152506 | SEMICONDUCTOR DIE HAVING EDGE WITH MULTIPLE GRADIENTS AND METHOD FOR FORMING THE SAME - A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening. | 2020-05-14 |
20200152507 | INTEGRATED CIRCUIT WITH CONDUCTIVE LINE HAVING LINE-ENDS - A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion. | 2020-05-14 |
20200152508 | METHOD FOR CONTACTING A BURIED INTERCONNECT RAIL OF AN INTEGRATED CIRCUIT CHIP FROM THE BACK SIDE OF THE IC - A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs. | 2020-05-14 |
20200152509 | FORMATION OF TRENCH SILICIDE SOURCE OR DRAIN CONTACTS WITHOUT GATE DAMAGE - A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner. | 2020-05-14 |
20200152510 | METALLIC INTERCONNECT STRUCTURES WITH WRAP AROUND CAPPING LAYERS - Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect. | 2020-05-14 |
20200152511 | METALLIC INTERCONNECT STRUCTURES WITH WRAP AROUND CAPPING LAYERS - Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect. | 2020-05-14 |
20200152512 | INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES - A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line. | 2020-05-14 |
20200152513 | FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH FIN STRUCTURES - A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a semiconductor substrate. The method includes forming an oxygen-absorbing layer on a surface of the first conductive feature. The oxygen-absorbing layer absorbs oxygen from the first conductive feature and becomes an oxygen-containing layer. The method includes removing the oxygen-containing layer to expose the surface originally covered by the oxygen-containing layer. The method includes forming a metal-containing layer on the surface. The method includes forming a second conductive feature on the metal-containing layer. | 2020-05-14 |
20200152514 | SELF-ALIGNED CONTACT ON A SEMICONDUCTOR DEVICE - A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device. | 2020-05-14 |
20200152515 | METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF - Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a first substrate; forming a semiconductor structure having a first conductive contact over a front side of the first substrate; and forming a second conductive contact at a backside of the first substrate, wherein the second conductive contact extends through a backside of the dielectric layer and connects to a second end of the first conductive contact. The 3D integrated wiring structure can include a first substrate; a dielectric layer in the first substrate; a semiconductor structure over the front side of the first substrate, having a first conductive contact; and a second conductive contact at the backside of the first substrate, and the second conductive contact extends through a backside of the dielectric layer and connects to the second end of the first conductive contact. | 2020-05-14 |
20200152516 | Semiconductor Device and Method of Manufacture - A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices. | 2020-05-14 |
20200152517 | JUNCTION FORMATION IN THICK-OXIDE AND THIN-OXIDE VERTICAL FETS ON THE SAME CHIP - A method for manufacturing a semiconductor device includes forming a first plurality of fins in a first device region on a substrate, forming a second plurality of fins in a second device region on the substrate, forming bottom source/drain regions on the substrate and around lower portions of each of the first and second plurality of fins in the first and second device regions, forming a dummy spacer layer on the bottom source/drain region in the first device region, wherein the dummy spacer layer includes one or more dopants, and forming a plurality of doped regions in the first and second plurality of fins in the first and second device regions, wherein the plurality of doped regions in the first device region extend to a greater height on the first plurality of fins than the plurality of doped regions in the second device region on the second plurality of fins. | 2020-05-14 |
20200152518 | INTEGRATED GATE CONTACT AND CROSS-COUPLING CONTACT FORMATION - Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer. | 2020-05-14 |
20200152519 | FIN DAMAGE REDUCTION DURING PUNCH THROUGH IMPLANTATION OF FINFET DEVICE - Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section. | 2020-05-14 |
20200152520 | SEMICONDUCTOR FINS WITH DIELECTRIC ISOLATION AT FIN BOTTOM - A method is presented for forming dielectric isolated fins. The method includes forming a plurality of fin structures over a semiconductor substrate, forming spacers adjacent each of the plurality of fins, recessing the semiconductor substrate to form bottom fin profiles, and forming shallow trench isolation (STI) regions between the plurality of fins and the bottom fin profiles. The method further includes etching the STI regions, a select number of the plurality of fins, and a portion of a select number of the bottom fin profiles to create cavities between a mechanical anchor defined between a pair of fins of the plurality of fins, the etching resulting in undercutting of remaining fins. | 2020-05-14 |
20200152521 | Methods of Forming Metal Gates - A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen. | 2020-05-14 |
20200152522 | Forming Transistor by Selectively Growing Gate Spacer - A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin. | 2020-05-14 |
20200152523 | PRODUCTION OF SEMICONDUCTOR REGIONS IN AN ELECTRONIC CHIP - A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus. | 2020-05-14 |
20200152524 | Techniques for Forming Vertical Transport FET - Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided. | 2020-05-14 |