20th week of 2020 patent applcation highlights part 65 |
Patent application number | Title | Published |
20200152625 | DISTRIBUTED RC TERMINATION - An integrated resistor-capacitor (RC) structure ( | 2020-05-14 |
20200152626 | TIPLESS TRANSISTORS, SHORT-TIP TRANSISTORS, AND METHODS AND CIRCUITS THEREFOR - An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor. | 2020-05-14 |
20200152627 | SYSTEM ON CHIP - A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact. | 2020-05-14 |
20200152628 | GATE CUT WITH INTEGRATED ETCH STOP LAYER - A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting. | 2020-05-14 |
20200152629 | VERTICAL FIELD-EFFECT TRANSISTORS FOR MONOLITHIC THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES - Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device | 2020-05-14 |
20200152630 | LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION - A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level. | 2020-05-14 |
20200152631 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of | 2020-05-14 |
20200152632 | Hybrid Scheme for Improved Performance for P-type and N-type FinFETs - A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed. | 2020-05-14 |
20200152633 | Array of Cross Point Memory Cells and Methods of Forming an Array of Cross Point Memory Cells - A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed. | 2020-05-14 |
20200152634 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate. | 2020-05-14 |
20200152635 | THIN FILM TRANSISTORS WITH SPACER CONTROLLED GATE LENGTH - Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed. | 2020-05-14 |
20200152636 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction. | 2020-05-14 |
20200152637 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer. | 2020-05-14 |
20200152638 | MICRO-PATTERN FORMING METHOD, CAPACITOR AND METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE - A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided. | 2020-05-14 |
20200152639 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a base and a plurality of protrusions extending from the base and spaced apart from each other; a first oxide layer substantially disposed between two adjacent protrusions and exposing an upper portion of the protrusion between portions of the first oxide layer; a bit line contact covering the upper portion of the protrusion; a bit line disposed over the bit line contact; a first nitride layer disposed on lateral surfaces of the bit line contact and the bit line and on an upper surface and a sidewall of the first oxide layer exposed to the bit line contact; and a second nitride layer at least formed over the first nitride layer disposed on the lateral surfaces with an interval and connected to the first nitride layer disposed on the sidewall, thereby forming an air gap between the first and second nitride layers. | 2020-05-14 |
20200152640 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via. | 2020-05-14 |
20200152641 | USING THREE OR MORE MASKS TO DEFINE CONTACT-LINE-BLOCKING COMPONENTS IN FINFET SRAM FABRICATION - A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device. | 2020-05-14 |
20200152642 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other. | 2020-05-14 |
20200152643 | SEMICONDUCTOR DEVICE, SYSTEMS AND METHODS OF MANUFACTURE - A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed. | 2020-05-14 |
20200152644 | Integrated Assemblies Having Ferroelectric Transistors with Heterostructure Active Regions - Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material. | 2020-05-14 |
20200152645 | Memory Cell And An Array Of Memory Cells - A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed. | 2020-05-14 |
20200152646 | NON-VOLATILE MEMORY - A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate. | 2020-05-14 |
20200152647 | SEMICONDUCTOR STRUCTURE AND THE FORMING METHOD THEREOF - The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer. | 2020-05-14 |
20200152648 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction. | 2020-05-14 |
20200152649 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD FOR THE SAME - The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion. | 2020-05-14 |
20200152650 | MEMORY DEVICE WITH A SPLIT STAIRCASE - Embodiments of the present disclosure are directed towards a memory device with a split staircase, in accordance with some embodiments. In one embodiment, the memory device includes one or more pillars disposed in a die, and a plurality of wordlines formed in a stack of multiple tiers and coupled with the one or more pillars. At least some of the wordlines are split across the tiers into at least first and second portions. Respective ends of at least some wordlines of at least one of the first or second portions, at a location of the split, are exposed to provide electrical coupling with other components of the device. Other embodiments may be described and/or claimed. | 2020-05-14 |
20200152651 | Methods of Filling Openings with Conductive Material, and Assemblies Having Vertically-Stacked Conductive Structures - Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions. | 2020-05-14 |
20200152652 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes a step of reducing a thickness of a silicon oxide film embedded in an element isolation trench including fins in order to form protruded fins. In the step, the silicon oxide film is etched while covering part of an upper surface of the silicon oxide film with a resist pattern. At this time, the resist pattern is formed such that a distance between the fin and the resist pattern is equal to or less than a predetermined interval which is an arrangement interval of the plurality of fins. | 2020-05-14 |
20200152653 | THROUGH ARRAY CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE - Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit. | 2020-05-14 |
20200152654 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. A three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepwise portion on the connection region, an etch stop structure on the stepwise portion of the electrode structure, and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and connected to corresponding pad portions of the electrodes, respectively, may be provided. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, which has have a uniform thickness and covers a top surface and a bottom surface of an etch stop pattern. | 2020-05-14 |
20200152655 | THREE-DIMENSIONAL MULTILEVEL DEVICE CONTAINING SEAMLESS UNIDIRECTIONAL METAL LAYER FILL AND METHOD OF MAKING SAME - A vertical repetition of a unit layer stack including an insulating layer, a sacrificial material layer, and a nucleation promoter layer is formed over a substrate. Memory stack structures are formed through the vertical repetition. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the nucleation promoter layers within the vertical repetition. Electrically conductive layers are formed in the backside recesses by selectively growing a metallic material from physically exposed surfaces of the nucleation promoter layers while suppressing growth of the metallic material from physically exposed surfaces of the insulating layers. | 2020-05-14 |
20200152656 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY - A method of manufacturing a semiconductor memory includes: forming a first lamination on a substrate; forming a first hole through the first lamination; embedding a first sacrificial material including a thermally decomposable organic material in the first hole; forming a recess at an upper portion of the first hole; forming an oxide film in the recess; removing the first sacrificial material under the oxide film; embedding a second sacrificial material on the oxide film in the recess; forming a second lamination on the first lamination and the second sacrificial material; forming a second hole through the second lamination at a position corresponding to the first hole by etching the second lamination in an extension direction of the first hole; and removing the oxide film and the second sacrificial material. | 2020-05-14 |
20200152657 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width. | 2020-05-14 |
20200152658 | Methods of Fabricating Integrated Structures - Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures. | 2020-05-14 |
20200152659 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure. | 2020-05-14 |
20200152660 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method of manufacturing a semiconductor device, the method includes: forming a stack structure; forming a channel layer penetrating the stack structure; forming a first dielectric layer in the channel layer; forming a second dielectric layer in the first dielectric layer; forming an opening by selectively etching the first dielectric layer; selectively etching the second dielectric layer exposed through the opening; and forming a pad in the opening. | 2020-05-14 |
20200152661 | STANDARD CELL HAVING MIXED FLIP-WELL AND CONVENTIONAL WELL TRANSISTORS - An LVT-RVT cell includes an LVT PMOS transistor adjacent to an RVT NMOS transistor, whereby the LVT and RVT transistors are placed inside a common p-well and are biased using the same voltage potential. The cell thus employs a flipped well for the PMOS transistor and a conventional (unflipped) well for the NMOS transistor. By arranging the LVT-RVT cell in this way, the cell can function at lower voltages, thereby conserving power, while also improving the performance of the composite function. Furthermore, the LVT-RVT cell can be placed adjacent to RVT cells to further reduce power consumption and improve performance of the RVT cells within the block. | 2020-05-14 |
20200152662 | PIXEL ARRAY SUBSTRATE - A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer. | 2020-05-14 |
20200152663 | ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF, AND DISPLAY DEVICE - A fabricating method of an array substrate includes: forming a first semiconductor pattern and a first insulating layer on a substrate; forming a first gate pattern and a second gate pattern isolated from each other; forming a second insulating layer; forming a second semiconductor pattern; forming a first metal pattern and a second metal pattern and a third metal pattern respectively lap-jointed with the second semiconductor pattern; forming a third insulating layer; and forming a first via hole, a second via hole, first source and drain electrodes, and second source and drain electrodes, where the first source and drain electrode are respectively connected to the first semiconductor pattern through the first via hole, and the second source and drain electrodes are respectively connected to the second semiconductor pattern through the second via hole. | 2020-05-14 |
20200152664 | DISPLAY DEVICE INCLUDING A PATTERNED CONDUCTIVE LAYER - A display device includes: a gate line including a gate line portion; a data line; a transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; and a connecting member disposed between the data line and the source electrode, connected to the data line and the source electrode to cross a gate electrode edge of the gate electrode. A connecting portion where a data line edge and a connecting member edge are connected to each other does not overlap the gate line and the gate electrode in a plan view. The data line includes a first data line portion crossing the gate line and a second data line portion connected to the first data line portion and does not overlap the gate line in the plan view. | 2020-05-14 |
20200152665 | DISPLAY APPARATUS - A display apparatus includes a substrate, a circuit, and a pixel electrode. The substrate includes a display area and a peripheral area outside the display area. The circuit is disposed in the display area. The circuit includes a plurality of conductive layers, and each conductive layer contacts a corresponding inorganic layer arranged directly below the each conductive layer. The pixel electrode is arranged over the circuit and is electrically connected to at least one of the conductive layers. | 2020-05-14 |
20200152666 | Integrated Circuit Structure and Method with Hybrid Orientation for FinFET - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction. | 2020-05-14 |
20200152667 | SUBSTRATE FOR ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - An element substrate serving as a substrate for an electro-optical device includes a base material, a TFT disposed on the base material, the TFT including a semiconductor layer, and a first insulating film including a silicon oxide film disposed between the base material and the semiconductor layer, wherein a content of hydrogen in the silicon oxide film is 1.0×10 | 2020-05-14 |
20200152668 | DISPLAY DEVICE - The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor | 2020-05-14 |
20200152669 | CONDUCTIVE WIRE STRUCTURE AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present disclosure provides a conductive wire structure, a manufacturing method thereof, an array substrate and a display device. The conductive wire structure includes a first conductive wire and a second conductive wire on a first plane, wherein a connection end of the first conductive wire is spaced apart from a connection end of the second conductive wire by a gap so as to discharge charges accumulated on the first conductive wire and the second conductive wire through the gap; an electrical connector connected to the connection end of the first conductive wire and the connection end of the second conductive wire, respectively, wherein a part of the electrical connector is located on a second plane different from the first plane. | 2020-05-14 |
20200152670 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - This application discloses an array substrate, a display panel and a display device; a first storage capacitor is formed in a small spacing between a 2nd metal layer and an electrode layer of the array substrate. | 2020-05-14 |
20200152671 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage V | 2020-05-14 |
20200152672 | METHOD FOR MANUFACTURING BACK CHANNEL ETCHING TYPE OXIDE SEMICONDUCTOR TFT SUBSTRATE - The present application provides a method for fabricating a back channel etching oxide semiconductor TFT substrate, by depositing the first passivation layer on the source, the drain and the active layer, and treating the oxygen element containing plasma to a surface of the first passivation layer, infiltrating traces of oxygen element into the superficial layer of the channel region of the active layer through the first passivation layer, then using an oxygen element containing plasma to treat the surface of the first passivation layer, so that the traces of oxygen element infiltrates into the superficial layer of the channel region of the active layer via the first passivation layer, to supply the oxygen element to the superficial layer of the channel region, and ensure the oxygen element balance in the superficial layer, the first passivation layer acts as a barrier layer to ensure the stability of the TFT. | 2020-05-14 |
20200152673 | PEELING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( | 2020-05-14 |
20200152674 | IMAGE SENSOR AND METHOD FOR MANUFACTURING IMAGE SENSOR - An image sensor comprising a semiconductor substrate and a trench isolation structure that is formed in the semiconductor substrate, wherein the trench isolation structure sequentially includes, from an outer portion to an inner portion of the trench isolation structure, a first oxide layer, a nitride layer, a second oxide layer and a semiconductor material layer that respectively extend in a thickness direction of the semiconductor substrate, such that a semiconductor-oxide-nitride-oxide-semiconductor structure is formed from the semiconductor substrate to the inner portion of the trench isolation structure via the outer portion of the trench isolation structure. | 2020-05-14 |
20200152675 | BOND PAD STRUCTURE FOR BONDING IMPROVEMENT - Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening. | 2020-05-14 |
20200152676 | METHOD OF MAKING A SEMICONDUCTOR DEVICE - A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material. | 2020-05-14 |
20200152677 | IMAGE SENSING DEVICE - An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove. | 2020-05-14 |
20200152678 | PIXELS - A photodiode has an absorption layer and a cap layer operatively connected to the absorption layer. A pixel is formed in the cap layer and extends into the absorption layer to receive charge generated from photons therefrom. The pixel defines an annular diffused area to reduce dark current and capacitance. A photodetector includes the photodiode. The photodiode includes includes an array of pixels formed in the cap layer. At least one of the pixels extends into the absorption layer to receive charge generated from photons therefrom. At least one of the pixels defines an annular diffused area to reduce dark current and capacitance. | 2020-05-14 |
20200152679 | PHOTO DETECTION ELEMENT, OPTICAL SENSOR, AND METHOD OF MANUFACTURING PHOTO DETECTION ELEMENT - A photo detection element includes: a substrate; a light-receiving layer formed over the substrate, the light-receiving layer including graphene layers that are stacked such that lattices of the graphene layers are randomly displaced from each other in plan view; a first electrode that is in contact with the light-receiving layer; and a second electrode that is in contact with the light-receiving layer, a material of the second electrode differing from a material of the first electrode. | 2020-05-14 |
20200152680 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including photosensor capable of imaging with high resolution is disclosed. The semiconductor device includes the photosensor having a photodiode, a first transistor, and a second transistor. The photodiode generates an electric signal in accordance with the intensity of light. The first transistor stores charge in a gate thereof and converts the stored charge into an output signal. The second transistor transfers the electric signal generated by the photodiode to the gate of the first transistor and holds the charge stored in the gate of the first transistor. The first transistor has a back gate and the threshold voltage thereof is changed by changing the potential of the back gate. | 2020-05-14 |
20200152681 | Image Sensor Flip Chip Package - Implementations of semiconductor packages may include: a semiconductor device included within a cavity within a glass block. The package may also include a substrate coupled with a first side of the semiconductor device and two or more edges of the glass block. A fill material may be included between the substrate and the second conductor device and an opaque material may be between a side surface of the semiconductor device and an inner surface of the cavity. The opaque material may be configured to block light from contacting the side surface of the semiconductor device. | 2020-05-14 |
20200152682 | AN IMAGE SENSOR COMPRISING AT LEAST ONE SENSING UNIT WITH LIGHT GUIDING MEANS - The present disclosure concerns an image sensor comprising at least one sensing unit, said at least one sensing unit comprising means for converting light into a readable electric signal. The image sensor is remarkable in that said at least one sensing unit comprises light guiding means for guiding light in direction to said means for converting light into a readable electric signal, said light guiding means comprising:
| 2020-05-14 |
20200152683 | IMAGING ELEMENT AND SOLID-STATE IMAGING DEVICE - An imaging element of the present disclosure includes: a photoelectric conversion section | 2020-05-14 |
20200152684 | Support Structure for Integrated Circuitry - Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry. | 2020-05-14 |
20200152685 | Semiconductor Device and Method of Manufacturing the Same, and Electronic Apparatus - A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips. | 2020-05-14 |
20200152686 | STACKED TSV STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked TSV structure comprises: a logic region in which a first metal wiring layer is formed, a pixel region located on the logic region, in which a second metal wiring layer is formed, and a through-silicon via including a first via penetrating from the first metal wiring layer upward through the logic region to the second metal wiring layer, wherein a contact is filled and formed in the through-silicon via, the contact contacting the first metal wiring layer and the second metal wiring layer, thereby electrically connecting the first metal wiring layer to the second metal wiring layer. | 2020-05-14 |
20200152687 | IMAGE SENSOR WITH PAD STRUCTURE - The present disclosure relates to an image sensor with a pad structure formed during a front-end-of-line process. The pad structure can be formed prior to formation of back side deep trench isolation structures and metal grid structures. An opening is formed on a back side of the image sensor device to expose the embedded pad structure and to form electrical connections. | 2020-05-14 |
20200152688 | X-RAY DETECTOR - Disclosed herein is an apparatus suitable for detecting X-ray. The apparatus may comprise an X-ray absorption layer, an electronics layer and a distribution layer. The X-ray absorption layer may comprise a first plurality of electric contacts and configured to generate electrical signals on the first plurality of electric contacts from X-ray incident on the X-ray absorption layer. The electronics layer may comprise a second plurality of electric contacts and an electronic system, wherein the electric system electrically connects to the second plurality of electric contacts and is configured to process or interpret the electrical signals. The first plurality of electric contacts and the second plurality of electric contacts have different spatial distributions. The distribution layer is configured to electrically connect the first plurality of electric contacts to the second plurality of electric contacts. | 2020-05-14 |
20200152689 | SEMICONDUCTOR ON INSULATOR TYPE STRUCTURE, NOTABLY FOR A FRONT SIDE TYPE IMAGER, AND METHOD OF MANUFACTURING SUCH A STRUCTURE - A semiconductor on insulator type structure, which may be sued for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate. | 2020-05-14 |
20200152690 | SOLID-STATE IMAGING DEVICE - An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material. | 2020-05-14 |
20200152691 | LIGHT EMITTING DEVICE - A light emitting device including a light emitting structure including a plurality of light emitting parts, a dielectric structure disposed outside the light emitting structure, and a plurality of pads disposed on a first surface of the light emitting structure and electrically coupled with the light emitting parts, in which outer sidewalls of the pads are disposed inside an outer sidewall of the light emitting structure and an outer sidewall of the dielectric structure, at least one of the pads extends to a first surface of the dielectric structure, and the first surface of the dielectric structure is coplanar with the first surface of the light emitting structure. | 2020-05-14 |
20200152692 | LED DISPLAY - An LED display includes a wafer-level substrate, a first adhesive layer, a plurality of first light-emitting assemblies, and a first conductive structure. The wafer-level substrate includes a plurality of control circuits, each of which has a conductive contact. The first adhesive layer is disposed on the wafer-level substrate. Each first light-emitting assembly includes a plurality of first LED structures disposed on the first adhesive layer. The first conductive structure is electrically connected between the corresponding first LED structure and the control circuit. Thereby, each first light-emitting assembly including a plurality of first LED structures and a wafer-level substrate having a plurality of control circuits can be connected to each other through a first adhesive layer. | 2020-05-14 |
20200152693 | MICRO-LED DEVICE, DISPLAY APPARATUS AND METHOD FOR MANUFACTURING A MICRO-LED DEVICE - A micro-LED device, a display apparatus and a method for manufacturing a micro-LED device are provided. The micro-LED device comprises: a growth substrate; a plurality of vertical micro-LEDs formed on the growth substrate; a first type electrode formed on top of each of the vertical micro-LEDs; and a second type electrode formed on side surface of each of the vertical micro-LEDs. | 2020-05-14 |
20200152694 | LIGHT EMITTING MODULE AND AUTOMOTIVE ILLUMINATION DEVICE INCLUDING THE SAME - Disclosed are light emitting modules and automobile illumination devices including the same. The light emitting module comprises a module substrate, a light emitting device on the module substrate, and a light guide structure apart from the module substrate and in plan view surrounding the light emitting device. The light emitting device comprises a first pixel and a second pixel each including a light emitting diode (LED) chip that emits light whose wavelength falls within a range of blue color or ultraviolet ray, and a wavelength conversion material on a top surface of at least one of the first and second pixels. | 2020-05-14 |
20200152695 | SEMICONDUCTOR SENSOR DEVICE AND SEMICONDUCTOR SENSOR DEVICE MANUFACTURING METHOD - Connection with a wiring structure can be reliably achieved, whereby a semiconductor sensor device and a semiconductor sensor device manufacturing method with increased reliability are provided. A semiconductor sensor device in which a multiple of signal lines and a sensor detection portion are disposed includes a conductive film, disposed on a substrate, that configures the signal lines and whose upper face is exposed by an aperture portion of a width smaller than a width of the signal lines, a conductive member formed on the conductive film and electrically connected to the conductive film via the aperture portion, and a wiring structure, formed on an upper face of the conductive member, of an air bridge structure that connects the signal lines or the signal lines and the sensor detection portion, wherein an upper surface of the conductive member is in contact with the wiring structure, and a side face is exposed. | 2020-05-14 |
20200152696 | VERTICAL SILICON-ON-METAL SUPERCONDUCTING QUANTUM INTERFERENCE DEVICE - Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer. | 2020-05-14 |
20200152697 | PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCERS AND METHODS FOR FABRICATING THEREOF - According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein. | 2020-05-14 |
20200152698 | Cooling for PMA (Perpendicular Magnetic Anisotropy) Enhancement of STT-MRAM (Spin Torque Transfer-Magnetic Random Access Memory) Devices - A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly. | 2020-05-14 |
20200152699 | MULTILAYERED MAGNETIC FREE LAYER STRUCTURE FOR SPIN-TRANSFER TORQUE (STT) MRAM - A multilayered magnetic free layer structure is provided that includes a first magnetic free layer and a second magnetic free layer separated by a non-magnetic layer in which the second magnetic free layer has a lower perpendicular magnetic anisotropy field, H | 2020-05-14 |
20200152700 | MAGNETIC MEMORY DEVICES - A magnetic memory device includes a first magnetic tunnel junction pattern on a substrate, a second magnetic tunnel junction pattern on the first magnetic tunnel junction pattern, and a conductive line between the first magnetic tunnel junction pattern and the second magnetic tunnel junction pattern. The conductive line is configured such that a current flowing through the conductive line flows in parallel to an interface between the conductive line and each of the first and second magnetic tunnel junction patterns. | 2020-05-14 |
20200152701 | MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other. | 2020-05-14 |
20200152702 | REDUCTION OF METAL RESISTANCE IN VERTICAL RERAM CELLS - Embodiments of the invention include resulting structures and a method for fabricating a vertical ReRAM array structure. The embodiments of the invention include forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, masking one or more portions of a topmost layer of the alternating layers, and etching one or more portions of the alternating layers down to the metal layer. Embodiments of the invention also include depositing a lateral electrode layer over the etched one or more portions of the alternating layers, performing an etch back on the lateral electrode layer, and forming a vertical electrode layer over the structures. | 2020-05-14 |
20200152703 | PHOTOELECTRIC CONVERSION DEVICES AND ORGANIC SENSORS AND ELECTRONIC DEVICES - A photoelectric conversion device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and the second electrode and configured to absorb light in at least one part of a wavelength spectrum of light and to convert it into an electric signal, and an inorganic nanolayer between the first electrode and the photoelectric conversion layer and including a lanthanide element, calcium (Ca), potassium (K), aluminum (Al), or an alloy thereof. An organic CMOS image sensor may include the photoelectric conversion device. An electronic device may include the organic CMOS image sensor. | 2020-05-14 |
20200152704 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device including a base layer including a thin film transistor, a pixel definition layer including an opening, first to third organic light emitting elements each including a first electrode, a second electrode, and a light emitting layer therebetween, an encapsulation member including a first inorganic layer covering the organic light emitting elements, a second inorganic layer disposed thereon, a first color conversion pattern disposed between the inorganic layers and overlapping the first organic light emitting element, and a second color conversion pattern disposed between the inorganic layers and overlapping the second organic light emitting element, and first and second color filter patterns having different colors from each other and overlapping the first and second color conversion patterns, respectively, in which colors of light emitted from the first and second color conversion patterns are substantially the same as colors of the first and second color filter patterns, respectively. | 2020-05-14 |
20200152705 | DISPLAY DEVICE - A display device includes a first substrate; light-emitting elements disposed on the first substrate; an encapsulation film covering the light-emitting elements; a second substrate facing the first substrate; a first outermost film disposed on the second substrate to face the encapsulation film and including AO | 2020-05-14 |
20200152706 | DISPLAY DEVICE - A display device is disclosed. The display device may include a first pixel and a second pixel. The first pixel may include a first light emitter and a first color converter overlapping the first light emitter. The second pixel may immediate neighbor the first pixel, may include a second light emitter and a second color converter overlapping the second light emitter. When a distance between the first light emitter and the second light emitter is x and a distance between the first light emitter and the first color converter is y, the following equation is satisfied: | 2020-05-14 |
20200152707 | Display Device - A display device prevents cracks from spreading to an active area. The display device includes a substrate including an active area and a non-active area having a bending area, a thin-film transistor disposed in the active area, a light-emitting element disposed in the active area and connected to the thin-film transistor, an encapsulation layer disposed on the light-emitting element, a touch sensor disposed on the encapsulation layer, a touch pad disposed in the non-active area, a first routing line connecting the touch sensor to the touch pad via a second routing line in the bending area, and a crack prevention layer disposed on the second routing line in the bending area. Thus, the crack prevention layer is capable of preventing the occurrence of cracks in the bending area BA, thus preventing cracks from spreading to the active area AA. | 2020-05-14 |
20200152708 | DISPLAY DEVICE - Disclosed is a display device capable of being manufactured through a simplified process and having improved touch sensitivity. The display device includes an encapsulation unit disposed on a light-emitting element, a touch sensor disposed on the encapsulation unit, and an intermediate layer disposed between the encapsulation unit and the touch sensor. The intermediate layer includes a first intermediate layer, having a dielectric constant that is lower than a dielectric constant of an organic film disposed above or under the intermediate layer, and a second intermediate layer, having greater hardness than the first intermediate layer, whereby touch sensitivity is improved while processing is simplified. | 2020-05-14 |
20200152709 | FOLDABLE, FLEXIBLE DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A foldable, flexible display apparatus includes a flexible display panel which displays an image and includes a display side on which the image is displayed and of which portions thereof face each other in a folded state of the flexible display apparatus; a cover window on the display side of the flexible display panel and including: a window film comprising a transparent plastic film having a modulus of elasticity of about 6.3 gigapascals or more; and a coating layer on the window film, and configured to be transparent and to protect the window film from physical damage thereto; and an adhesive layer between the window film and the display side of the flexible display panel, and configured to have elasticity and bond the window film and the flexible display panel to each other. | 2020-05-14 |
20200152710 | DISPLAY DEVICE - A display device includes a display panel, and a touch sensing unit on the display panel, the touch sensing unit including a first conductive pattern on the display panel, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, partially crossing the first conductive pattern, and having a thickness that is greater than a thickness of the first conductive pattern. | 2020-05-14 |
20200152711 | Display Substrate And Method Of Manufacturing The Same, And Display Panel - In one embodiment, there is provided a display substrate including: a base substrate; a plurality of pixels on the base substrate; and a pixel definition layer on the base substrate, defining the pixels and separating the pixels from one another. Each of the pixels includes: a first electrode assembly, a light-emitting function layer and a second electrode arranged sequentially in a direction away from the base substrate, and the second electrodes of the pixels form a common electrode layer extending over the pixel definition layer. In each of the pixels, a distance between a surface of the pixel definition layer away from the base substrate and a surface of the light-emitting function layer away from the base substrate in the direction away from the base substrate is less than or equal to a preset threshold that is in a range of about 0 Å to about 300 Å. | 2020-05-14 |
20200152712 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Discussed are embodiments of an organic light emitting display device, which includes a plurality of pixels, each including at least one red sub pixel, a plurality of green sub pixels, and at least one blue sub pixel, wherein red sub pixels and blue sub pixels of adjacent pixels are aligned in a first direction and a second direction, wherein green sub pixels of the adjacent pixels are aligned in the first direction and are also aligned in the second direction, wherein the plurality of green sub pixels is disposed between the at least one red sub pixel and the at least one blue sub pixel of each pixel, and wherein the plurality of green sub pixels is offset from the at least one red sub pixel and the at least one blue sub pixel in the first direction and the second direction in the each pixel. | 2020-05-14 |
20200152713 | DISPLAY PANEL AND ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME - A display panel includes first pixels each including a first organic light emitting element which outputs red color light, second pixels each including a second organic light emitting element which outputs green color light, and third pixels each including a third organic light emitting element which outputs blue color light. The first organic light emitting elements are arranged in point symmetry with respect to the second organic light emitting element, the third organic light emitting elements are arranged in point symmetry with respect to the second organic light emitting element, an anode of the first organic light emitting element is spaced apart from an anode of the second organic light emitting element by a first distance, and the anode of the second organic light emitting element is spaced apart from an anode of the third organic light emitting element by a second distance which is shorter than the first distance. | 2020-05-14 |
20200152714 | Electronic Devices Having Displays with Openings - An electronic device may have a display. The display may have an active region in which display pixels are used to display images. The display may have one or more openings and may be mounted in a housing associated with the electronic device. An electronic component may be mounted in alignment with the openings in the display. The electronic component may include a camera, a light sensor, a light-based proximity sensor, status indicator lights, a light-based touch sensor array, a secondary display that has display pixels that may be viewed through the openings, antenna structures, a speaker, a microphone, or other acoustic, electromagnetic, or light-based component. One or more openings in the display may form a window through which a user of the device may view an external object. Display pixels in the window region may be used in forming a heads-up display. | 2020-05-14 |
20200152715 | POLYMERIC FILMS AND DISPLAY DEVICES CONTAINING SUCH FILMS - Polymeric films, which may be adhesive films, and display devices including such polymeric films, wherein a polymeric film includes: a first polymeric layer having two major surfaces, wherein the first polymeric layer includes a first polymeric matrix and particles. The first polymeric layer includes: a first a polyolefin-based low WVTR adhesive polymeric matrix having a refractive index n | 2020-05-14 |
20200152716 | DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - Disclosed are a display panel, a manufacturing method thereof, and a display device. The display panel includes a base substrate, the base substrate including a display region and a border region surrounding the display region, wherein the border region includes a specially-shaped border region; a first barrier structure configured to be disposed in at least the specially-shaped border region; and at least one second barrier structure configured to be disposed only in the specially-shaped border region. | 2020-05-14 |
20200152717 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a display device may include forming a preliminary first pixel definition layer by coating a first material on a base substrate including a first electrode, forming a first pixel definition layer by forming a first opening in the preliminary first pixel definition layer, the first opening exposing the first electrode, performing a plasma treatment on the first pixel definition layer, forming a preliminary organic layer by providing a first organic material, forming a preliminary second pixel definition layer by coating a second material on the first pixel definition layer, forming a second pixel definition layer by forming a second opening in the preliminary second pixel definition layer, the second opening overlapping with the first opening, and forming an organic layer by providing a second organic material. A thickness of the organic layer may be greater than a thickness of the preliminary organic layer. | 2020-05-14 |
20200152718 | PATTERN PART, METHOD FOR FORMING PATTERN PART AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING SAME - A method of forming a pattern part includes forming a first film on a target object, the first film having a first cure shrinkage ratio, forming a second film on the first film, the second film having a second cure shrinkage ratio greater than the first cure shrinkage ratio, and patterning the first film and the second film to form a pattern. | 2020-05-14 |
20200152719 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus including a substrate; a pixel electrode on the substrate; a pixel-defining layer including an opening exposing at least a portion of the pixel electrode; an intermediate layer including a center area on the pixel electrode and a side area extending from the center area and arranged on the pixel-defining layer, the intermediate layer including one or more common layers and an emission layer; a protective layer covering top surfaces of the center area and the side area of the intermediate layer and exposing at least a portion of the pixel-defining layer; and an opposite electrode spaced apart from the intermediate layer by the protective layer and arranged on the protective layer and portions of the pixel-defining layer, the portions being exposed by the protective layer. | 2020-05-14 |
20200152720 | DISPLAY SUBSTRATES, METHODS FOR MANUFACTURING THE DISPLAY SUBSTRATES, AND DISPLAY PANELS - The present application provides a display substrate, including an array substrate and a pixel defining layer. The pixel defining layer is formed on the array substrate and defines a plurality of sub-pixel areas. The pixel defining layer further defines a first groove, and the first groove is arranged to surround a sub-pixel area of the plurality of sub-pixel areas. When the display panel receives a falling impact, the impact is transferred to the pixel defining layer, so that the pixel defining layer expands in its extending direction. The groove is similar to a structure of a wall performing a function of releasing stresses and reducing expansion of the pixel defining layer. The present application further discloses a method for manufacturing a display substrate, and a display panel. | 2020-05-14 |
20200152721 | DISPLAY MODULE, DISPLAY APPARATUS INCLUDING THE SAME AND METHOD OF MANUFACTURING DISPLAY MODULE - A display module, a display apparatus including a display module, and a method of manufacturing a display module are provided. The method of manufacturing a display module includes forming a non-conductive layer that includes a fluxing function on a substrate, providing a plurality of light-emitting diodes (LEDs) on the substrate, wherein each LED of the plurality of LEDs has a first electrode pad and a second electrode pad spaced apart by a predetermined interval, and the substrate has a plurality of connection pads that are configured to electrically connect to the first electrode pads and the second electrode pads; thermally compressing the plurality of LEDs; and electrically connecting the plurality of LEDs and the substrate via a plurality of soldering members that are provided on at least one of the plurality of LEDs or the substrate. | 2020-05-14 |
20200152722 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device includes a circuit tier including a planarization layer; and a light emitting pixel over the planarization layer, and including a light emitting material, wherein the light emitting mated al includes a sublayer including a thickness. The planarization layer includes an area substantially vertically aligned with an effective light emitting area of the light emitting pixel, and the area includes a local flatness (LF) and the ratio between the local flatness and the thickness is not greater than a predetermined value. | 2020-05-14 |
20200152723 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device may include a substrate, a first layer on the substrate, the first layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a second layer on the first layer, an active pattern on the second layer, the active pattern overlapping only the first portion of the first layer, a gate electrode on the active pattern, a source electrode and a drain electrode on the gate electrode and connected to the active pattern, a first electrode connected to one of the source electrode and the drain electrode, a pixel defining layer on the first electrode, the pixel defining layer having an opening portion exposing at least a portion of the first electrode, an emission layer in the opening portion on the first electrode, and a second electrode on the emission layer. | 2020-05-14 |
20200152724 | ELECTRONIC DEVICE AND ILLUMINANCE SENSING METHOD BASED ON DISPLAY INFORMATION ON ELECTRONIC DEVICE - An electronic device is provided. The electronic device includes a housing including a front surface and a rear surface facing, a display exposed through a portion of the front surface, an illuminance sensor disposed between the display and the rear surface to overlap an area of the display when viewed from above the front surface, a processor positioned inside the housing and operatively connected with the display, and a memory positioned inside the housing and operatively connected with the processor, wherein the memory stores instructions configured to, when executed, enable the processor to receive first illuminance data measured using the illuminance sensor, identify display parameter information associated with the first illuminance data, obtain second illuminance data based on at least a part of the display parameter information and the first illuminance data, and adjust a brightness of the display based on at least a part of the second illuminance data. | 2020-05-14 |