20th week of 2014 patent applcation highlights part 21 |
Patent application number | Title | Published |
20140132227 | REGULATION METHOD - The invention relates to a method for automatic regulation of a system in which a plurality of parameters characteristic of the system are measured and in which at least one control parameter (u) is applied as a function of the measured parameters (y). The method includes choosing a nominal operating point of the system, and defining a nominal model (Mn) of the system at this nominal operating point. The method further includes determining a set of representative models ([Mk]) of the possible variations relative to the nominal model (Mn) and parameterizing the error of the nominal model (Mn) of the system by decomposition ([δ | 2014-05-15 |
20140132228 | PWM CONTROLLER DETECTING TEMPERATURE AND AC LINE VIA A SINGLE PIN AND POWER CONVERTER USING SAME - A PWM controller detecting temperature and AC line via a single pin and a power converter using the PWM controller, the PWM controller comprising: an output pin for providing a PWM signal; and a dual-function pin for receiving a temperature signal when the PWM signal is at a high level, and for receiving an AC line signal when the PWM signal is at a low level. | 2014-05-15 |
20140132229 | STATIC SYNCHRONOUS COMPENSATOR SYSTEMS AND RELATED METHODS - Static synchronous compensator (STATCOM) systems and methods are disclosed. An example STATCOM system includes a reactive component configured for electrical connection to a power network. For example, the reactive component may be a capacitor bank. The system also includes an inductor electrically connected in series with the reactive component. Further, the system includes a converter electrically connected in series with the reactive component and the inductor. A method may include using the static synchronous compensator system to provide one of reactive power and active power to the power network. | 2014-05-15 |
20140132230 | POWER FACTOR CORRECTION CIRCUIT AND POWER SUPPLY CIRCUIT - Embodiments of the present application provide a power factor correction circuit and a power supply circuit. The power factor correction circuit includes a main correction circuit and a switch module. The main correction circuit includes: a first correction circuit and a second correction circuit that are configured to perform power factor correction on an forward alternating current voltage, and a third correction circuit and a fourth correction circuit that are configured to perform power factor correction on an inverse alternating current voltage. The switch module includes first switch units that are connected in parallel between an input terminal of the first correction circuit and an input terminal of the third correction circuit, and second switch units that are connected in parallel between an input terminal of the second correction circuit and an input terminal of the fourth correction circuit. | 2014-05-15 |
20140132231 | DC Conversion Circuit - A DC conversion circuit in the disclosure includes a buck-boost converter and a resonant stage circuit. The buck-boost converter has two input ends, a negative output end and a positive output end. The buck-boost converter receives a first DC signal via its two input ends, and outputs a second DC signal via its two output ends. The resonant stage circuit has two input ends and two output ends. The resonant stage circuit receives the second DC signal via its two input ends, converts the second DC signal into energy for power charging, and outputs the energy to a load via its two output ends. Then, the resonant stage circuit converts the energy, which is used for power charging, to form a negative voltage by a resonance effect, and outputs the energy to the load via its two output ends. | 2014-05-15 |
20140132232 | BUCK DC-DC CONVERTER WITH ACCURACY ENHANCEMENT - A buck switching regulator includes a feedback control circuit including a first gain circuit generating a first feedback signal indicative of the regulated output voltage; a ripple generation circuit generating a ripple signal that is injected to the first feedback signal; and a comparator receiving a first reference signal and the first feedback signal to generate a comparator output signal. The switching regulator further includes an offset compensation circuit including a second gain circuit generating a second feedback signal indicative of the regulated output voltage; and an operational transconductance amplifier (OTA) configured to receive the second feedback signal and the first reference signal and to generate an output signal. The output signal of the OTA is coupled to the comparator to adjust an offset to the comparator so as to cancel the offset at the regulated output voltage due to the injected ripple signal. | 2014-05-15 |
20140132233 | ELECTRONIC APPARATUS, POWER SUPPLY APPARATUS, AND POWER SUPPLY METHOD - An electronic apparatus, a power supply apparatus, and a power supply method. The electronic apparatus may include a controller to provide a control signal to generate a multiphase signal through conversion of an input power and to receive a feedback of an output voltage that is generated using the multiphase signal; and a power supply including a plurality of unit converters having upper and lower switching elements of a half or full-bridge type, being operated by the control signal, and configured to provide the output voltage by the multiphase signal generated according to driving of the plurality of unit converters, wherein the power supply detects whether the upper and lower switching elements are simultaneously turned on in the plurality of unit inverters and turns off the operation of the unit converters according to the detection result. | 2014-05-15 |
20140132234 | DYNAMIC IMPEDANCE MATCHING FOR IMPROVED TRANSIENT PERFORMANCE IN A DIRECT CURRENT-TO-DIRECT CURRENT ('DC/DC') CONVERTER FOR DELIVERING A LOAD TO AN ELECTRICAL COMPONENT - A direct current-to-direct current (‘DC/DC’) converter for delivering a load to an electrical component, the DC/DC converter including: a coupled inductor, wherein the coupled inductor receives a source input voltage level and a outputs an output voltage level; a transient winding; and a variable impedance switch coupled to the transient winding, the variable impedance switch configured to operate by adjusting a delivered resistance level in dependence upon a change in the load to be delivered to the electrical component by the DC/DC converter. | 2014-05-15 |
20140132235 | CIRCUIT BOARD AND POWER SOURCE MANAGEMENT SYSTEM OF CIRCUIT BOARD - A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor. | 2014-05-15 |
20140132236 | Slope Compensation Module - A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module. | 2014-05-15 |
20140132237 | DYNAMIC IMPEDANCE MATCHING FOR IMPROVED TRANSIENT PERFORMANCE IN A DIRECT CURRENT-TO-DIRECT CURRENT ('DC/DC') CONVERTER FOR DELIVERING A LOAD TO AN ELECTRICAL COMPONENT - A direct current-to-direct current (‘DC/DC’) converter for delivering a load to an electrical component, the DC/DC converter including: a coupled inductor, wherein the coupled inductor receives a source input voltage level and a outputs an output voltage level; a transient winding; and a variable impedance switch coupled to the transient winding, the variable impedance switch configured to operate by adjusting a delivered resistance level in dependence upon a change in the load to be delivered to the electrical component by the DC/DC converter. | 2014-05-15 |
20140132238 | SYSTEM AND METHOD FOR SENSING AND MITIGATING HYDROGEN EVOLUTION WITHIN A FLOW BATTERY SYSTEM - A method is provided for mitigating hydrogen evolution within a flow battery system that includes a plurality of flow battery cells, a power converter and an electrochemical cell. The method includes providing hydrogen generated by the hydrogen evolution within the flow battery system to the electrochemical cell. A first electrical current generated by an electrochemical reaction between the hydrogen and a reactant is sensed, and the sensed current is used to control an exchange of electrical power between the flow battery cells and the power converter. | 2014-05-15 |
20140132239 | Fully Integrated Adjustable DC Current Reference Based on an Integrated Inductor Reference - A novel fully integrated adjustable DC current reference is developed. The reference current is set by the ratio of a DC voltage generated using a band-gap reference and a tuned resistor based on an inductor reference. An AC signal is necessary to develop a relationship between the resistor tuned and the inductor reference. A computation unit which could be designed as an analog circuit is necessary to compute the value of the resistor in relationship to the reference inductor. Classic circuits are used to develop and analyze the relationship between the reference inductor and the tunable resistor that sets the DC current reference. Results show that the value of the inductance is insensitive to process, voltage and temperature variations. Therefore, assuming the DC bandgap reference voltage is insensitive to changes in process, voltage and temperature variations, so is the the DC current reference. | 2014-05-15 |
20140132240 | TEMPERATURE DEPENDENT TIMER CIRCUIT - A timer to provide pulses at a comparator output wherein a frequency of the pulses is dependent on temperature, wherein providing each pulse includes biasing a first input of the comparator at a voltage and operating a transistor in a subthreshold region of operation to change the voltage of the first input of a comparator at a rate dependent upon temperature. The output of the comparator changes state when the voltage of the first input crosses a voltage of a second input of the comparator. | 2014-05-15 |
20140132241 | SMALL-CIRCUIT-SCALE REFERENCE VOLTAGE GENERATING CIRCUIT - A BGR circuit controls a switch circuit in synchronization with a clock signal from a control signal generating circuit and an inverted signal thereof, and thereby, alternately switches between a differential input terminal receiving a voltage VIM and a differential input terminal receiving a voltage VIP. An LPF circuit includes capacitive elements, a switch connected between an input node and each capacitive element, and a switch connected between an output node and each capacitive element. The LPF circuit controls ON/OFF of the switches in synchronization with a clock signal CLK, and thereby, calculates a moving average value of an output voltage of the BGR circuit in the most recent one clock cycle. | 2014-05-15 |
20140132242 | CURRENT MIRROR CIRCUITS - A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical. | 2014-05-15 |
20140132243 | TWO-WIRE TRANSMITTER STARTER CIRCUIT AND TWO-WIRE TRANSMITTER INCLUDING THE SAME - A two-wire transmitter starter circuit is configured to stably supply power at the time of start-up. The two-wire transmitter starter circuit includes a starter current generation circuit. The starter current generation circuit is connected in parallel with a current conversion unit configured to convert a detection signal of a sensor to a predetermined DC current. The starter current generation circuit includes a first series circuit where a first resistor and a shunt regulator are connected in series, and a second series circuit where a switching element and a second resistor are connected in series. The shunt regulator includes a first control terminal connected to a connection point of the switching element and the second resistor. The switching element includes a second control terminal connected to a connection point of the first resistor and the shunt regulator. | 2014-05-15 |
20140132244 | FINGER VOLTAGE SENSOR - The present invention is a finger voltage sensor that includes a base finger ring worn by a user that works near an electrical source, an electricity sensor disposed on the base finger ring, the electricity sensor detects one or more electrical fields associated with the electrical source and a warning light disposed on the base finger ring, the warning light emits a constant light when the electricity sensor is activated and is in communication with the electricity sensor. The finger voltage sensor can also include a beeper instead of a warning light and a base finger ring that includes a hook and loop fastener that is releasably attached to a user's finger. | 2014-05-15 |
20140132245 | HIGH-RESOLUTION PHASE DETECTOR - A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples. | 2014-05-15 |
20140132246 | CIRCUIT AND METHOD FOR DETECTING ZERO-CROSSINGS AND BROWNOUT CONDITIONS ON A SINGLE-PHASE OR MULTI-PHASE SYSTEM - A circuit configuration detects zero-crossings and/or a brownout condition. The circuit configuration contains a zero-crossing detection circuit, a brownout detection circuit, an isolation and digitization circuit connected to the zero-crossing detection circuit and the brownout detection circuit, and a filtering circuit connected to the isolation and digitization circuit. The single circuit configuration can be used for detecting zero-crossings of single-phase and multi-phase systems as well as ascertaining a brownout condition of either the single-phase or the multi-phase systems. | 2014-05-15 |
20140132247 | CURRENT SENSOR - A current sensor ( | 2014-05-15 |
20140132248 | CURRENT SENSOR - A current sensor includes a casing including a pair of arms and coupling part, multiple magneto-electric transducers arranged on the circumference of a virtual ellipse whose major axis or minor axis extends between the arms, a support disposed obliquely relative to the major axis or the minor axis of the virtual ellipse within an angle formed by the major axis and the minor axis so as to be close to one of the arms when viewed from the center of a wire disposed and fastened between the arms, and a band wound around a circumferential surface of the wire fastened between the arms, part of the band being caught by the support, the wire being fastened by the band such that the central axis or center of the wire is held close to the support. | 2014-05-15 |
20140132249 | MIXED CURRENT SENSOR AND METHOD FOR FITTING SAID SENSOR - The invention relates to a mixed current sensor comprising in a case:
| 2014-05-15 |
20140132250 | Integrated Magnatoresistive Sensing device - An integrated magnetoresistive sensing device includes a substrate, a magnetoresistive sensing element and a built-in self test (BIST) unit. The substrate comprises a first surface and a second surface opposite to the first surface. The magnetoresistive sensing element is disposed above the first surface and comprises at least a magnetoresistive layer not parallel to the first surface. The BIST unit is disposed above the first surface and comprises at least a conductive part corresponding to the magnetoresistive layer. The conductive part is configured to generate a magnetic field along a direction perpendicular to the first surface. A projection of the conductive part on the first surface does not overlap with a projection of the magnetoresistive layer on the first surface. | 2014-05-15 |
20140132251 | POSITION DETECTION DEVICE, DRIVE DEVICE, AND LENS BARREL - A position detection device includes a detection portion and a magnetism generation portion. The detection portion includes a first magnetism detection element and a second magnetism detection element. The first magnetism detection element and the second magnetism detection element are disposed on a plane. The magnetism generation portion is disposed at a position opposite the detection portion. The magnetism generation portion includes mutually opposing magnetic fluxes with respect to the detection portion by performing bipolar magnetization on a face opposite the plane where the first magnetism detection element and the second magnetism detection element are disposed. | 2014-05-15 |
20140132252 | WIRING STRUCTURE OF DISPLACEMENT SENSOR - Coil patterns and connecting wirings of a slider part or the like are prepared using a printed board (slider board). Connecting wiring patterns prepared using the printed board are arranged at multiple layers. The coil patterns and the connecting wiring patterns are connected via through-holes. | 2014-05-15 |
20140132253 | INDUCTIVE SENSOR - In one embodiment, an electronic device includes an excitation control; a first excitation element coupled to the excitation control; a second excitation element coupled to the excitation control; a target positioned near the first and second excitation elements and within the electromagnetic fields generated by the first and second excitation elements; a receiving element positioned near the target and within the electromagnetic fields generated by the first and second excitation elements; and a signal processor coupled to the receiving element and coupled to the excitation control. | 2014-05-15 |
20140132254 | HALL EFFECT MEASUREMENT INSTRUMENT WITH TEMPERATURE COMPENSATION - Disclosed is a Hall Effect instrument with the capability of compensating for temperature drift consistently, accurately and in real time of operation. The instrument embodies a four-point ohm meter circuit measuring Hall Effect sensor resistance and tracking the effect of temperature on the Hall Effect sensor. The instrument takes into account a relationship between the temperature and a temperature compensation index on a per probe basis, which has exhibited a deterministic difference observed by the present inventor. | 2014-05-15 |
20140132255 | SURFACE CURRENT PROBE - A surface current probe includes two current detection coils disposed so as to detect a magnetic field in a direction vertical to an current detection target plane; two disturbance-control coils, each thereof being disposed at a position farther away from each of the two current detection coils, against the current detection target plane, so as to be disposed for detection of a magnetic field in a direction parallel to the current detection target plane; and a terminal resistor coupled to each of the two disturbance-control coils. The two disturbance-control coils are disposed such that induced voltages generated against the current detection target plane at the time of detection of a magnetic field on the outer side of the two current detection coils are opposed in polarity to each other. | 2014-05-15 |
20140132256 | CURRENT SENSORS USING MAGNETOSTRICTIVE MATERIAL - A current sensor device. The current sensor device includes a strain distribution converter; an optical fiber coupled with the strain distribution converter; and a magnetostrictive material associated with the strain distribution converter such that a change in shape of the magnetostrictive material causes a change in length of the optical fiber. | 2014-05-15 |
20140132257 | MAGNETIC DETECTION DEVICE - To increase an output from a magnetoresistive element without using a special magnetic material, provided is a magnetic detection device including a magnetoresistive element including a ferromagnetic reference layer having a fixed magnetization direction, to which a spin wave induction layer is connected, so that the spin wave induction layer injects, into the ferromagnetic reference layer, electrons having spins in a specific direction by a spin electromotive force internally generated. | 2014-05-15 |
20140132258 | ASPHALTENE EVALUATION BASED ON NMR MEASUREMENTS AND TEMPERATURE / PRESSURE CYCLING - Asphaltene content and its spatial distribution in a reservoir containing crude oil is an important factor in determining the potential for formation damage and pipeline impairment, as well as planning for processing and refining of the oil. Exemplary uses include: reservoir modeling, development and depletion planning, pressure maintenance, and surface facilities management. A convenient method has been developed which uses two-dimensional NMR techniques during a temperature and/or pressure cycle to quantify the asphaltene content of the crude oil without the need for extracting the oil from the reservoir rock. The technique can be applied to core, down-hole logs, or, a combination of both. | 2014-05-15 |
20140132259 | NMR METHOD TO DETERMINE GRAIN SIZE DISTRIBUTION IN MIXED SATURATION - A method for determining particle size distribution of a subsurface rock formation having pore spaced filled with at least two different fluids using measurements of at least one nuclear magnetic resonance property thereof made from within a wellbore penetrating the rock formation includes determining a distribution of nuclear magnetic relaxation times from the measurements of the at least one nuclear magnetic resonance property. A fractional volume of the pore spaces occupied by each of the at least two fluids is determined. A surface relaxivity of the rock formation for portions of the rock pore spaces occupied by each of the at least two fluids is determined from a measurement of a formation parameter. The relaxation time distribution and the surface relaxivities are used to determine the particle size distribution. | 2014-05-15 |
20140132260 | NUCLEAR MAGNETIC FLOW METER AND METHOD FOR OPERATION OF NUCLEAR MAGNETIC FLOW METERS - A nuclear magnetic flow meter ( | 2014-05-15 |
20140132261 | MAGNETIC RESONANCE IMAGING SYSTEM AND MAGNETIC RESONANCE IMAGING METHOD - A magnetic resonance imaging (MRI) method includes defining a plurality of sub-volumes so that each of the sub-volumes includes a plurality of sequential slices of a plurality of slices that make up a volume of a subject, wherein the sub-volumes are divided into a plurality of groups so that any neighboring sub-volumes belong to different groups; applying radio-frequency (RF) pulses including a plurality of frequency components and a selection gradient to the subject to simultaneously excite a plurality of sub-volumes in each of the groups; performing three-dimensional (3D) encoding on each of the excited sub-volumes so that only some slices of the plurality of slices in each of the excited sub-volumes are encoded in a slice direction; acquiring magnetic resonance signals from the encoded sub-volumes; and reconstructing the acquired magnetic resonance signals into image data corresponding to each of the plurality of slices in each of the encoded sub-volumes. | 2014-05-15 |
20140132262 | Method and Apparatus for SAR Reduction Using B0 Specific RF Excitation - A method for generation of a radio-frequency (RF) pulse for excitation of nuclear spins in a predetermined layer of a specimen for magnetic resonance imaging and a magnetic resonance imaging device for performing the method are provided. The method includes determining a variation of a magnetic field in a measuring volume, and defining a spectral frequency distribution of the RF pulse. The RF pulse with the spectral frequency distribution is configured to excite nuclear spins in the specimen. The nuclear spins are polarized by the magnetic field at a predetermined flip angle in the measuring volume under a boundary condition of a substantially minimum energy content. The method also includes generating the RF pulse with the defined spectral frequency distribution. | 2014-05-15 |
20140132263 | MEASURING SYSTEM FOR NUCLEAR MAGNETIC MEASURING DEVICES - A measuring system for nuclear magnetic measuring devices having a controller, a signal generator and a signal processor with signal path having an input stage and a signal conditioner, interfering signals caused by the excitation signals and not occurring simultaneously with the measuring signals being received at an input of the input stage, the measuring signal having signal swing less than that of the interfering signal and the controller determining excitation signal output instants. A switch is located in the signal path between the input stage output and the signal conditioner input, and being switchable between first and second switching states by the controller. The controller switches the switch in the first switching state only in the periods in which there are no interfering signals at the input stage input, and a dynamic range of the signal conditioner input is adapted to the voltage swing of the measuring signals. | 2014-05-15 |
20140132264 | MAGNETIC RESONANCE IMAGING SYSTEM AND MAGNETIC RESONANCE IMAGING METHOD - A magnetic resonance imaging (MRI) method includes: applying radio-frequency (RF) pulses comprising a plurality of frequency components and a selection gradient to a subject to simultaneously excite a plurality of sub-volumes in each of a plurality of groups, wherein a plurality of sub-volumes making up a volume of the subject are divided into the plurality of groups so that any neighboring sub-volumes belong to different groups; performing three-dimensional (3D) encoding on each of the excited sub-volumes using a plurality of encoding methods; acquiring magnetic resonance signals from the encoded sub-volumes; and reconstructing the acquired magnetic resonance signals into image data corresponding to each of the encoded sub-volumes. | 2014-05-15 |
20140132265 | MULTIPLE RESONANCE NMR SPECTROSCOPY USING A SINGLE TRANSMITTER - An NMR imaging system comprising a transceiver module configured to couple with a magnetic resonance transmitter coil, where the transceiver module includes a first transmitter channel and a pulse programmer configured to control the transceiver module, the transceiver module generating a precession and nutation for observing rotation at multiple intervals about the carrier (“PANORAMIC”) waveform, the PANORAMIC waveform configured to produce nuclear polarization. The PANORAMIC waveform may a single-banded PANORAMIC waveform or a multiple-banded PANORAMIC waveform. A method of NMR spectroscopy or imaging, the method comprising: determining for a nuclear spin rotation at least one frequency interval and at least one corresponding phase; creating a PANORAMIC waveform for the at least one frequency interval and the at least one corresponding phase; and applying the PANORAMIC waveform from an amplifier output to a probe input. The PANORAMIC waveform may be a single-banded PANORAMIC waveform or a multiple-banded PANORAMIC waveform. | 2014-05-15 |
20140132266 | MAGNETIC RESONANCE IMAGING APPARATUS AND TRANSMISSION CONTROL METHOD - According to one embodiment, a magnetic resonance imaging apparatus provided with a plurality of transmission channels includes a signal processing unit and a control unit. The signal processing unit acquires a radio frequency magnetic field emitted from each of the plurality of transmission channels through a receiver coil mounted on an object and measure a phase of the radio frequency magnetic field. The control unit determines a phase difference between the plurality of transmission channels based on the phase of the radio frequency magnetic field of each of the plurality of transmission channels measured by the signal processing unit. The control unit controls a phase of a radio frequency pulse inputted to each of the plurality of transmission channels, based on the phase difference. | 2014-05-15 |
20140132267 | MR ACTIVE TRACKING SYSTEM - An active tracking system that overcomes the heating problems of conventional transmission line and signal line conductors is provided. The active tracking system includes at least one active tracking coil; at least one integrated circuit proximate the active tracking coil; a tracking receiver; a first MR safe means configured for transmitting a received signal to the tracking receiver; and a second MR safe means configured for communicating one or more signals from the tracking receiver to the integrated circuit at coil. The integrated circuit may also include frequency estimations, analog to digital conversion at the tracking coil location to reduce the amount of processing required in the tracking receiver thereby decreasing the potential for signals passing from the tracking coil location to the tracking receiver to interfere with MR imaging signals. | 2014-05-15 |
20140132268 | MAGNETIC RESONANCE IMAGING APPARATUS AND IMAGING POSITION SETTING ASSISSTING METHOD - In order to provide a magnetic resonance imaging apparatus capable of maximizing the effect of an automatic positioning function without increasing the load on an operator even in imaging of an examination part having a plurality of examination sections, when setting an imaging position of an examination part having a plurality of examination sections, automatic positioning processing for automatically detecting all examination sections of the examination part on a scanogram image acquired in advance is performed first. A stack is displayed at a position, which is detected by this automatic positioning processing, on the scanogram image. | 2014-05-15 |
20140132269 | MULTI-FREQUENCY LOCATING SYSTEMS AND METHODS - Multi-frequency buried object location system transmitters and locators are disclosed. A transmitter may generate and provide output signals to a buried object at a plurality of frequencies, which may be selected based on a connection type. Corresponding locators may simultaneously receive a plurality of magnetic field signals emitted from the buried object and generate visual and/or audible output information based at least in part on the plurality of received magnetic field signals. The visual and/or audible output may be further based on signals received from a quad-gradient antenna array. | 2014-05-15 |
20140132270 | QUAD-GRADIENT COILS FOR USE IN LOCATING SYSTEMS - Buried object locators including an omnidirectional antenna array and a quad gradient array are disclosed. A locator display may include information associated with a buried object based on both omnidirectional antenna array signals and quad gradient antenna array signals. | 2014-05-15 |
20140132271 | APPARATUS AND METHOD FOR DEEP RESISTIVITY MEASUREMENT USING COMMUNICATION SIGNALS NEAR DRILL BIT - An apparatus for utilizing a pre-existing telemetry transmitter near a drill bit for transmitting or receiving signals to make measurements of surrounding formation resistivity includes a drill collar, at least two toroidal receiving antennas deployed on the drill collar and spaced at an axial distance from each other for receiving or transmitting signals from or to the telemetry transmitter, at least two receiver modules coupled to the toroidal receiving antennas for processing signals received or to be transmitted from or to the telemetry transmitter and adjusting frequency the receiver modules work at, and a converting module coupled to the receiver modules. The converting module includes a microprocessor for calculating the surrounding formation resistivity and controlling the frequency tuners in the receiver modules. A corresponding method for utilizing a multiple dimensional conversion chart to convert data of measured flow-out current through the formation into data of formation resistivity is also provided. | 2014-05-15 |
20140132272 | Analyzing Subterranean Formation With Current Source Vectors - A method analyzes a subterranean formation. At least one property of a well casing in the subterranean formation is determined and a plurality of current source vectors at respective positions along a trajectory of the well casing are determined. The effect of the well casing is determined based upon the plurality of current source vectors and the at least one property of the well casing. | 2014-05-15 |
20140132273 | LIGHT-EMITTING ELEMENT FAILURE DETECTOR AND METHOD FOR DETECTING LIGHT-EMITTING ELEMENT FAILURE - A light emitting element failure detector ( | 2014-05-15 |
20140132274 | METHOD AND APPARATUS FOR PROVIDING INFORMATION IN AN ELECTROLYTE MEASURMENT SYSTEM - An electrolyte measurement assembly includes an electrolyte measurement system having removable components including a removable reagent pack and at least one removable electrode and a computer chip embedded in at least one of the removable components, the computer chip having a memory and providing and receiving data about usage and condition of the at least one removable component. | 2014-05-15 |
20140132275 | DETERMINATION OF ISOELECTRIC POINTS OF BIOMOLECULES USING CAPACITIVE SENSORS - A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values. | 2014-05-15 |
20140132276 | DETERMINATION OF ISOELECTRIC POINTS OF BIOMOLECULES USING CAPACITIVE SENSORS - A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values. | 2014-05-15 |
20140132277 | Photo ionization detector for gas chromatography having two separately ionizing sources and methods of use - A detector for gas chromatography using two ionization sources within a single body to separately provide ionization energy to a column gas eluent to provide electrical discharge to two or more collecting electrodes provides improved selectivity and may be so used. Use is made of combined bias/collecting electrodes. The use of two ionization sources permits generation of two detector outputs from within a common body and of a common constituent flow. The ionization sources and any applicable discharge gas and dopant may be selected based on desired selectivity. | 2014-05-15 |
20140132278 | Hybrid/Electrical Vehicle HV AC System Leakage and Ground Fault Detection - Apparatus and methods for detection of a ground fault on a DC side as well as on an AC side of an inverter are presented. A detection means can receive forward and reverse current and provide an induced current based on the difference between them. A parameter associated with the induced current, or a parameter associated with a voltage generated by conduction of the induced current through a device, can be used to detect a ground fault. In addition, a detection means can be configured to receive transient current, and a resulting voltage at the detection means can be used for fault detection. A detection means can be disposed at the DC side of an inverter or at the AC side of the inverter. Apparatus and methods can be configured to detect AC leakage current caused by a ground fault. | 2014-05-15 |
20140132279 | APPARATUS AND METHOD FOR INSPECTING INFRARED SOLID-STATE IMAGE SENSOR - An apparatus includes: a current control unit to control an amount of constant current and supply a first and second constant currents to an infrared detection pixel; a constant current supply time control unit to control periods of time in which the first and second constant currents are supplied to the infrared detection pixel; an A-D converter to convert a first and second electrical signals from the infrared detection pixel into a first and second digital signals, the first and second electrical signals being generated when the first and second constant currents is supplied to the infrared detection pixel, respectively; a subtracting unit to calculate a difference between the first and second digital signals; and a determining unit to determine whether the infrared detection pixel is a defective pixel based on the absolute value of the difference calculated by the subtracting unit. | 2014-05-15 |
20140132280 | Method And Device For Monitoring A Test Interval For A Residual Current Protective Device - A method and device for monitoring a test interval for a residual current protective device includes measuring an operating time of the residual current protective device, triggering an alarm report if the measured operating time exceeds an operating time limit, and restarting the operating time measurement upon detection of a trigger process of the residual current protective device. In an embodiment of the invention, a time period is measured independent of the operating time of the residual current protective device. | 2014-05-15 |
20140132281 | State Monitoring or Diagnostics System - The present disclosure concerns a state monitoring or diagnostics system, and also a method for monitoring the state of devices or for diagnosing devices, in particular for overvoltage protection devices, as well as a method for transmitting measured values. Each of the devices comprises a functional component to be monitored and a monitoring and transmitting apparatus, wherein the monitoring and transmitting apparatus consists solely of a resonator circuit made of passive electrical components with no microchip, in particular with no RFID transponder. The information to be interrogated resides in the resonant frequency of the resonator circuit. | 2014-05-15 |
20140132282 | DEVICE AND METHOD FOR EMI SOURCE LOCATION - An electronics device, comprising one or more circuit boards and a plurality of power converters on one or more of said circuit boards, each power converter comprising one or more transducers for measuring a voltage or a current in the power converter, the electronics device additionally comprising a sub-system for locating sources of electromagnetic interference. The transducers of two or more of the power converters are also connected to the sub-system for locating sources of electromagnetic interference to supply it with measurement data. The sub-system for locating sources of electromagnetic interference is arranged to use the measurement data from the transducers in order to locate sources of electromagnetic interference. | 2014-05-15 |
20140132283 | OVERLAY MARK AND MEASUREMENT METHOD THEREOF - An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark. | 2014-05-15 |
20140132284 | INTEGRATED LOW-NOISE SENSING CIRCUIT WITH EFFICIENT BIAS STABILIZATION - An integrated low-noise sensing circuit with efficient bias stabilization in accordance with the present invention comprises a first capacitance sensing element, a second capacitance sensing element, a sub-threshold transistor and an amplifier circuit wherein the first stage is an input transistor. The second capacitance sensing element is connected to the first capacitance sensing element. The sub-threshold transistor comprises a body, a gate, a source, a drain, a source-body junction diode and a bulk. The gate forms on top of the body. The source forms on the body and is connected to the first capacitance sensing element and the second capacitance sensing element. The drain forms on the body and is connected to the gate and the amplifier output terminal The source-body junction diode comprises an anode and a cathode. The anode is connected to the ground. | 2014-05-15 |
20140132285 | METHOD FOR VERIFYING CORRECT ADHESION OF A SUBSTRATE ON AN ELECTRICALLY AND THERMALLY CONDUCTIVE BODY - A method of verifying a correct adhesion of a substrate on a body which is configured to be electrically conductive and thermally conductive includes providing the body, providing the substrate comprising a top face and a rear face, connecting to the top face of the substrate an electric circuit comprising conductive paths and electronic components, attaching to the rear face the body via an adhesive layer comprising an adhesive, connecting the conductive paths and the body to an respective opposite terminal of a voltage source via contact tabs, measuring a capacity, and determining a quality of the adhesive layer from the measured capacity. | 2014-05-15 |
20140132286 | NONCONTACT DETERMINATION OF INTERFACE TRAP DENSITY FOR SEMICONDUCTOR-DIELECTRIC INTERFACE STRUCTURES - Embodiments of the subject method and apparatus relate to a sequence of noncontact Corona-Kelvin Metrology, C-KM, that allows the determination and monitoring of interface properties in dielectric/wide band gap semiconductor structures. The technique involves the incremental application of precise and measured quantities of corona charge, Q | 2014-05-15 |
20140132287 | CAPACITIVE SENSOR DEVICE - A processing system for a capacitive sensor device comprises circuitry and logic; and the capacitive sensor device comprises a first plurality of sensor electrodes and a second plurality of sensor electrodes. The processing system is configured to acquire a first plurality of capacitive measurements by emitting and receiving first electrical signals with the first plurality of sensor electrodes of the capacitive sensor device. The processing system is also configured to select a first set of the first plurality of sensor electrodes based on the first plurality of capacitive measurements. The processing system is further configured to acquire a second plurality of capacitive measurements by emitting second electrical signals with the first set of the first plurality of sensor electrodes and receiving the second electrical signals with the second plurality of sensor electrodes. | 2014-05-15 |
20140132288 | METHOD FOR MEASURING ELECTRICAL CONDUCTIVITY AND ELECTRICAL CONDUCTIVITY MEASURING SYSTEM USING THE SAME - The present disclosure relates to a method for measuring electrical conductivity and a system for measuring electrical conductivity using the same. The method includes obtaining a cell constant of a conductance cell using a conductivity standard solution, pouring a solution desired to be measured in the conductance cell, and applying predetermined direct current (DC) voltages to electrodes, disposed in the conductance cell, in a manner of changing the predetermined DC voltages in stages at each preset time (t), obtaining resistance of the solution, as a slope, from a linear relationship between the voltage and a peak current, measured for each voltage, and calculating electrical conductivity of the solution using the cell constant and the resistance of the solution. | 2014-05-15 |
20140132289 | LINING/FAIRING PANEL AND METHOD FOR MEASURING THE ELECTRICAL BONDING RESISTANCE OF A LINING/FAIRING PANEL - A lining/fairing panel, in particular a lining/fairing panel for an airborne vehicle such as an aircraft or a spacecraft is provided. The lining/fairing panel includes a panel body having a first surface and a second surface opposite to the first surface, an electrically conductive coating applied to the first surface or the second surface, and a via arranged in the panel body reaching from the first surface to the second surface of the panel body. The via is formed in an inner region of the panel body. The borders of the inner region are spaced apart by a predetermined distance from the borders of the first and second surface of the panel body. | 2014-05-15 |
20140132290 | FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN - Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO. | 2014-05-15 |
20140132291 | SCALABLE BUILT-IN SELF TEST (BIST) ARCHITECTURE - A circuit with built-in self test (BIST) capability includes a master BIST controller, a plurality of slave BIST controllers, and a collector. The master BIS controller issues test instructions in response to a master resume input signal. The plurality of slave BIST controllers is coupled to the master BIST controller. Each slave BIST controller is adapted to perform a test on a functional circuit in response to a test instruction and to provide a resume signal at a conclusion of the test. The collector receives a corresponding resume signal from each of the multiple slave BIST controllers after the master BIST controller issues the test instruction, and subsequently provides the master resume signal in response to an activation of all of the corresponding resume signals. | 2014-05-15 |
20140132292 | TEST BOARD - A test board is disclosed. The test board serves as an interface for testing a conference phone. The test board includes a plurality of test channel selectors. Each of the test channel selectors receives a plurality of test voltages provided by the conference phone and a first and a second control signals. The test voltages are divided into a plurality test voltage pairs, and each of the test channel selectors selects one of the test voltages in each of the test voltage pairs for generating a plurality of selected voltages according to the first control signal. Each of the test channel selectors selects two of the selected voltages for generating a first and a second output voltages according to the second control signal, where the first and the second output voltages are transmitted to a test machine for testing the conference phone. | 2014-05-15 |
20140132293 | INTEGRATED CIRCUIT WITH DEGRADATION MONITORING - An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a programmable delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node that is delayed by a programmable amount. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line. | 2014-05-15 |
20140132294 | APPARATUS AND METHOD FOR TESTING A CAPACITIVE TRANSDUCER AND/OR ASSOCIATED ELECTRONIC CIRCUITRY - A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit. | 2014-05-15 |
20140132295 | DRIVE FAILURE PROTECTION - The present techniques include methods and systems for detecting a failure in a capacitor bank of an electrical drive system. Embodiments include using discharge resistors to discharge capacitors in the capacitor bank, forming a neutral node of the capacitor bank. In different capacitor configurations, the neutral node is measured, and the voltage is analyzed to determine whether a capacitor bank unbalance has occurred. In some embodiments, the node is a neutral-to-neutral node between the discharged side of the discharge resistors and a neutral side of the capacitor bank, or between the discharged side of the discharge resistors and a discharged side of a second set of discharge resistors. In some embodiments, the node is a neutral-to-ground node between the discharged side of the discharge resistors and a ground potential. | 2014-05-15 |
20140132296 | HEAT SINK BLADE PACK FOR DEVICE UNDER TEST TESTING - Embodiments of the present disclosure provide an apparatus configured to engage a device for testing the device via automatic test equipment. The apparatus includes a heat sink, wherein the heat sink comprises a plurality of fins extending from the heat sink, and wherein the heat sink is configured to engage the device. The apparatus further includes a heat conduction layer coupled to the heat sink, a first leg coupled to the heat conduction layer, and a second leg coupled to the heat conduction layer. The second leg is spaced apart from the first leg. A vacuum path is defined through (i) the heat conduction layer and (ii) the heat sink. The vacuum path permits the apparatus to engage the device to be tested by the automatic test equipment. | 2014-05-15 |
20140132297 | RECONFIGURABLE ELECTRIC FIELD PROBE - Systems and methods for EMC, EMI and ESD testing are described. A probe comprises a center conductor extending along an axis of the probe, a probe tip, and a shield coaxially aligned with the center conductor and configured to provide electromagnetic screening for the probe tip. One or more actuators may change the relative positions of the probe tip and shield with respect to a device under test, thereby enabling control of sensitivity and resolution of the probe. | 2014-05-15 |
20140132298 | FINE PITCH PROBES FOR SEMICONDUCTOR TESTING, AND A METHOD TO FABRICATE AND ASSEMBLE SAME - An apparatus for testing electronic devices is disclosed. The apparatus includes a plurality of probes attached to a substrate; each probe capable of elastic deformation when the probe tip comes in contact with the electronic; each probe comprising a plurality of isolated electrical vertical interconnected accesses (vias) connecting each probe tip to the substrate, such that each probe tip of the plurality is capable of conducting an electrical current from the device under test to the substrate. The plurality of probes may form a probe comb. Also disclosed is a probe comb holder that has at least one slot where the probe comb may be disposed. A method for assembling and disassembling the probe comb and probe comb holder is also disclosed which allows for geometric alignment of individual probes. | 2014-05-15 |
20140132299 | Electrical Inspection of Electronic Devices Using Electron-Beam Induced Plasma Probes - A non-mechanical contact signal measurement apparatus includes a first conductor on a structure under test and a gas in contact with the first conductor. At least one electron beam is directed into the gas so as to induce a plasma in the gas where the electron beam passes through the gas. A second conductor is in electrical contact with the plasma. A signal source is coupled to an electrical measurement device through the first conductor, the plasma, and the second conductor when the plasma is directed on the first conductor. The electrical measurement device is responsive to the signal source. | 2014-05-15 |
20140132300 | FINE PITCH PROBES FOR SEMICONDUCTOR TESTING, AND A METHOD TO FABRICATE AND ASSEMBLE SAME - An apparatus for testing electronic devices is disclosed. The apparatus includes a plurality of probes attached to a substrate; each probe capable of elastic deformation when the probe tip comes in contact with the electronic; each probe comprising a plurality of isolated electrical vertical interconnected accesses (vias) connecting each probe tip to the substrate, such that each probe tip of the plurality is capable of conducting an electrical current from the device under test to the substrate. The plurality of probes may form a probe comb. Also disclosed is a probe comb holder that has at least one slot where the probe comb may be disposed. A method for assembling and disassembling the probe comb and probe comb holder is also disclosed which allows for geometric alignment of individual probes. | 2014-05-15 |
20140132301 | WIRELESS CURRENT-VOLTAGE TRACER WITH UNINTERRUPTED BYPASS SYSTEM AND METHOD - A measurement instrument capable of electrically isolating the connected photovoltaic (“PV”) module in an array of PV modules to perform a health diagnosis including of current versus voltage measurements on the attached device by using a resistive load to acquire the current-voltage (“IV”) curve in the positive power quadrant of the module. The instrument is capable of switching a charge storage element into the array during the period when the solar module is under test to provide uninterrupted electrical power to the PV array. The measurement instrument contains a battery and charger allowing the device to run from the connected PV module's energy. The instrument contains a microprocessor to allow a high degree of configuration through software, including altering the speed of an IV sweep, the interval between sweeps, and integrating temperature and tilt measurements. The instrument is equipped with low power radio devices to communicate wirelessly, further negating the need for a common ground. | 2014-05-15 |
20140132302 | METHOD FOR MEASURING POTENTIAL INDUCED DEGRADATION OF AT LEAST ONE SOLAR CELL OR OF A PHOTOVOLTAIC PANEL AS WELL AS THE USE OF SAME METHOD IN THE PRODUCTION OF SOLAR CELLS AND PHOTOVOLTAIC PANELS - The invention relates to a method for measuring the high-voltage induced degradation (PID) of at least one solar cell. According to the invention, a conductive plastic material is pressed on the upper side or bottom side of the respective solar cell, in particular on the front side thereof, and a DC voltage greater than 50 V is applied between the plastic material and the respective solar cell. Alternatively, corona discharges may be applied to solar cells or photovoltaic modules. In one embodiment, a characteristic electric parameter of the respective solar cell or of the photovoltaic module is repeatedly measured at time intervals. The method according to the invention can be carried out on individual solar cells, which can be further processed directly after passing the test and without further complex processing, e.g. to a photovoltaic module. In principle, the method is also suitable for measurements on complete photovoltaic modules. | 2014-05-15 |
20140132303 | APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH - An integrated circuit implements a transistor mismatch sensor comprising first and second inverter chains coupled to a register. The register comprises a plurality of flip-flops having clock inputs driven by an output of the first inverter chain and data inputs driven by an output of the second inverter chain. Data outputs of the flip-flops of the register are indicative of an amount of mismatch between transistors of different conductivity types in the first and second inverter chains. For example, the register may comprise a thermometer encoded register providing a digital output signal having a first value indicative of an approximate match in speed, drive strength or other characteristics between the transistors of the first and second conductivity types, with values above and below the first value being indicative of respective first and second different types of relative mismatch in speed, drive strength or other characteristics. | 2014-05-15 |
20140132304 | DEVICE AND METHOD FOR DIRECT MIXING OF PULSE DENSITY MODULATION (PDM) SIGNALS - A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal; | 2014-05-15 |
20140132305 | CLOCK NETWORK ARCHITECTURE - An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional. | 2014-05-15 |
20140132306 | CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS - This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor. | 2014-05-15 |
20140132307 | Comparator and calibration thereof - A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal. | 2014-05-15 |
20140132308 | FAST LOCK ACQUISITION AND DETECTION CIRCUIT FOR PHASE-LOCKED LOOPS - A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock. | 2014-05-15 |
20140132309 | SELF-CALIBRATION OF OUTPUT BUFFER DRIVING STRENGTH - An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay. | 2014-05-15 |
20140132310 | DRIVING INTEGRATED CIRCUIT - A driving integrated circuit (IC) is disclosed. The driving IC comprises a signal processing circuit, a receiver and a terminal resistance providing circuit. The receiver is coupled to a first transmission line and a second transmission line and is output to the signal processing circuit after receiving a transmission signal through the first transmission line and the second transmission line. The terminal resistance providing circuit is coupled to the receiver. | 2014-05-15 |
20140132311 | HIGH-VOLTAGE BULK DRIVER - This application discusses, among other things, apparatus and methods for driving the bulk of a high-voltage transistor using transistors having gates with low-voltage ratings. In an example, a bulk driver can include an output configured to couple to bulk of a high-voltage transistor, a pick circuit configured to couple the output to an input voltage at an input terminal of the high-voltage transistor or an output voltage at the output terminal of the high-voltage transistor when the high-voltage transistor is in a high impedance state, and a bypass circuit configured to couple the output of the bulk driver to the output voltage when the high-voltage transistor is in a low impedance state. | 2014-05-15 |
20140132312 | EFFICIENCY OPTIMIZED DRIVER CIRCUIT - Driver circuitry and methods are provided for driving a semiconductor device. The driver circuitry includes a buck converter configured to generate a baseline current, and a capacitor coupled between an output of the buck converter and ground, the capacitor configured to store charge during an off-state of the buck converter and to discharge the stored charge as a peak current during an on-state of the buck converter, wherein the baseline current reaches a current limit prior to the capacitor being fully discharged, and an output current at an output of the buck converter is based, at least in part, on the baseline current and the peak current. | 2014-05-15 |
20140132313 | FREQUENCY MULTIPLIER AND ASSOCIATED METHOD - A frequency multiplier and associated method are provided, wherein the frequency multiplier includes a waveform generator and a slicer. The waveform generator generates a waveform in response to an input signal, and the slicer induces transitions in an output signal whenever the waveform crosses each of a plurality of reference levels, such that a frequency of the output signal is a multiple of a frequency of the input signal. | 2014-05-15 |
20140132314 | TRIANGULAR WAVEFORM GENERATING APPARATUS - There is provided a triangular waveform generating apparatus. The triangular waveform generating apparatus includes: a capacitor connected between an output terminal and a ground; a charging/discharging unit including a plurality of current sources to charge the capacitor with currents generated from the plurality of current sources or discharge currents therefrom; and a control unit comparing a charge voltage of the capacitor with a plurality of preset reference voltages and controlling the charging/discharging unit to allow a quantity of current charged in or discharged from the capacitor to be different in each of a plurality of periods formed by the plurality of reference voltages. | 2014-05-15 |
20140132315 | INTEGRATED CIRCUIT WITH DEGRADATION MONITORING - An integrated circuit including a degradation monitoring circuit. The degradation monitoring circuit includes a comparison circuit having a delay element including an input coupled to a data node of a timing path and having an output to provide a delayed signal of a data signal of the data node. The comparison circuit includes a logic comparator that provides a logic comparison between a data signal of the data node and the output of the delay element. The monitoring circuit includes a sampling circuit that provides a sampled signal of the output of the logic comparator that is a sampled with respect to a clock signal of the clock signal line. The monitoring circuit includes a hold circuit that provides a signal indicative of a data signal of the data node transitioning within a predetermined time of an edge transition of a clock signal of the clock signal line. | 2014-05-15 |
20140132316 | SEMICONDUCTOR APPARATUS - In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes. | 2014-05-15 |
20140132317 | SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1. | 2014-05-15 |
20140132318 | PLL LOCKING CONTROL IN DAISY CHAINED MEMORY SYSTEM - A method, system and apparatus to provide a solution of PLL locking issue in the daisy chained memory system. A first embodiment uses consecutive PLL on based on locking status of backward device on the daisy chained memory system with no requirement of PLL locking status checking pin. A second embodiment uses Flow through PLL control with a locking status pin either using an existing pin or a separated pin. A third embodiment uses a relocking control mechanism to detect PLL relocking from the device. A fourth variation uses flag signal generation to send to the controller. | 2014-05-15 |
20140132319 | DLL CIRCUIT AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device is provided with first to third circuits. The first circuit generates first information that indicates a corresponding relationship between a period of a reference clock and a delay amount per delay element. The second circuit generates second information that indicates the number of stages of delay elements corresponding to a set phase difference based on the first information. The third circuit generates a delayed clock by delaying the reference clock just a delay amount of stages of the delay elements indicating the second information. | 2014-05-15 |
20140132320 | LOSS OF LOCK DETECTOR FOR CLOCK AND DATA RECOVERY SYSTEM - An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values. | 2014-05-15 |
20140132321 | IMPLEMENTING COMPACT CURRENT MODE LOGIC (CML) INDUCTOR CAPACITOR (LC) VOLTAGE CONTROLLED OSCILLATOR (VCO) FOR HIGH-SPEED DATA COMMUNICATIONS - A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit. | 2014-05-15 |
20140132322 | INPUT CIRCUIT - An input circuit includes a first P-channel MOS transistor including a first terminal supplied with a high-potential power supply voltage and a second terminal coupled to a first node, a second P-channel MOS transistor including a first terminal coupled to the first node and a second terminal coupled to a second node, a first N-channel MOS transistor including a first terminal coupled to the second node and a second terminal coupled to a third node, and a second N-channel MOS transistor including a first terminal coupled to the third node and a second terminal supplied with a low-potential power supply voltage. An input signal is supplied to gate terminals of the P-channel MOS transistors and the N-channel MOS transistors. A control circuit controls the potential at the first node and the potential at the third node based on the input signal and the potential at the second node. | 2014-05-15 |
20140132323 | LATCH APPARATUS AND APPLICATIONS THEREOF - A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage. | 2014-05-15 |
20140132324 | INTEGRATED CIRCUIT WITH MULTI-FUNCTIONAL PARAMETER SETTING AND MULTI-FUNCTIONAL PARAMETER SETTING METHOD THEREOF - An integrated circuit with multi-functional parameter setting and a multi-functional parameter setting method of the integrated circuit are provided. The multi-functional parameter setting method includes following steps: providing the integrated circuit which includes a switch unit and a multi-functional pin that is coupled to an external setting unit, sensing a programmable reference voltage of the external setting unit through one operation of the switch unit and executing a first function setting according to the programmable reference voltage, and sensing a programmable reference current of the external setting unit through another operation of the switch unit and executing a second function setting according to the programmable reference current. | 2014-05-15 |
20140132325 | CONTROL CIRCUIT FOR USE WITH A FOUR TERMINAL SENSOR, AND MEASUREMENT SYSTEM INCLUDING SUCH A CONTROL CIRCUIT - A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1. | 2014-05-15 |
20140132326 | PULSE NOISE SUPPRESSION CIRCUIT AND PULSE NOISE SUPPRESSION METHOD THEREOF - Provided is a pulse noise suppression circuit. The pulse noise suppression circuit includes a filter circuit converting an input signal of a pulse type into an increasing or decreasing filter signal, a level reset circuit resetting the filter signal in response to the input signal and an output signal and an output circuit converting the filter signal into the output signal of a pulse type, wherein the level reset circuit resets the filter signal to have a high level when the input signal and the output signal all have a high level, and resets the filter signal to have a low level when the input signal and the output signal all have a low level. | 2014-05-15 |