20th week of 2014 patent applcation highlights part 67 |
Patent application number | Title | Published |
20140136835 | SECURE COMPUTER NETWORK - A computer network ( | 2014-05-15 |
20140136836 | METHOD AND SYSTEM FOR PROVIDING TOKENLESS SECURE LOGIN BY VISUAL CRYPTOGRAPHY - A method and system for providing tokenless secure login by visual cryptography. The method includes generating a password sequence and converting the password sequence to a password image. The method also includes encrypting the password image into a first image cipher and a second image cipher. The method further includes transmitting the first image cipher to a first electronic device of a user. Further, the method includes displaying the second image cipher on a second electronic device of the user. Moreover, the method includes enabling decryption of the password image by matching the first image cipher and the second image cipher using an image capture device on the first electronic device. The system includes a plurality of electronic devices, communication interface, memory, and processor. | 2014-05-15 |
20140136837 | METHOD FOR IDENTIFYING AND AUTHENTICATING A USER VIA A PORTABLE DEVICE - The method comprises:
| 2014-05-15 |
20140136838 | ENTITY NETWORK TRANSLATION (ENT) - The present invention provides an Entity Network Translation (ENT) scheme for identifying and authenticating abstract identities using public-private key technology and PKI concepts such as a certificate authority and certificate chaining. ENT may grant any number of authentic, indefinite, abstract identifiers to any number of requestors. These abstract identifiers are each referred to as a verinym, which loosely means “verified name”. They allow any person or entity, for any purpose, to establish and control the authentic identities of things electronically, and establish relationships between these identities. According to some embodiments, ENT sidesteps traditional PKI relationship establishment issues by issuing abstract identifiers to users that request them. It is the use of these abstract identifiers, and the relationships formed between entities that define their real-world significance. | 2014-05-15 |
20140136839 | METHODS AND SYSTEMS FOR DYNAMIC UPDATES OF DIGITAL CERTIFICATES - Methods and systems of the present invention allow for dynamic updates of digital certificates. In one system, a server computer is configured to communicate with a certificate authority via a communications network. The server computer is configured to receive a first security certificate from the certificate authority. The first security certificate has a term. The first security certificate is installed onto the server computer, and at least one of a current time and the term of the first security certificate are analyzed to determine whether the first security certificate is to be updated. When the first security certificate is to be updated, a request for update is transmitted to the certificate authority, a second security certificate is received from the certificate authority, and the first security certificate is replaced with the second security certificate on the server computer. | 2014-05-15 |
20140136840 | COMPUTER SYSTEM FOR STORING AND RETRIEVAL OF ENCRYPTED DATA ITEMS USING A TABLET COMPUTER AND COMPUTER-IMPLEMENTED METHOD - A computer system comprising multiple sets of client computers coupled to a database system via a network. Each client computer having installed thereon an application program that comprises client computer specific log-in information. The database system having a log-in component for logging-in the client computers, and being partitioned into multiple relational databases. Each one of the relational databases being assigned to one set of the sets of client computers. Each one of the relational databases storing encrypted data items. Each data item being encrypted with one of the user or user-group specific cryptographic keys. A key identifier of the cryptographic key with which one of the data items is encrypted being stored in the relational database as an attribute of the one of the encrypted data items. The log-in component comprising assignment information indicative of the assignment of the databases to the set of client computers. | 2014-05-15 |
20140136841 | DEVICE - According to one embodiment, a device includes a first data generator configured to generate a second key (HKey) by encrypting a host constant (HC) with the first key (NKey); a second data generator configured to generate a session key (SKey) by encrypting a random number (RN) with the second key (HKey); a one-way function processor configured to generate an authentication information (Oneway-ID) by processing the secret identification information (SecretID) with the session key (SKey) in one-way function operation; and a data output interface configured to output the encrypted secret identification information (E-SecretID) and the authentication information (Oneway-ID) to outside of the device. | 2014-05-15 |
20140136842 | METHOD AND SYSTEM FOR GENERATING A SECURE MESSAGE AS A URL MESSAGE - A method for generating and delivering a message via a web service is provided. A message for a recipient is converted to a URL and sent. A request is received from a sender to send a message to a recipient. A URL message is created in response to receiving the request to send the message to the recipient and the URL message is sent to the recipient. A URL message response is received from the recipient and a landing message is sent to the recipient in response to receiving the URL message response. The landing message includes a hint requesting an answer from the recipient. An answer is received from the recipient and the message is sent to the recipient in response to receiving the answer. | 2014-05-15 |
20140136843 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - Provided is an information processing apparatus including a message generating unit that generates a message based on a multi-order multivariate polynomial set F=(f | 2014-05-15 |
20140136844 | Method and Apparatus for Link Setup - A method for link setup includes sending a first authentication message including a user identifier to an access point (AP). A second authentication message sent by the AP according to the user identifier is received and includes an EAP method request message and a ANonce of the AP. A first PTK is generated according to the ANonce, an SNonce, and a first MSK. A third authentication message is sent to the AP. The third authentication message includes an EAP method response message, the SNonce, and a first MIC that is generated according to the first PTK. A fourth authentication message is sent by the AP when it authenticates, according to a second PTK, that the first MIC is correct. The fourth authentication message includes an EAP-Success message, configuration information configured by the AP for the terminal, and a second MIC. The second MIC is authenticated according to the first PTK. | 2014-05-15 |
20140136845 | APPARATUS AND METHOD FOR USING MEMORY DEVICE - A method and an apparatus for using a memory device are provided. A host device includes a transmitter that transmits data; a receiver that receives data; and a controller configured to receive configuration information of the memory device including the information related to the data stored in the one or more slots determined according to each vendor of the memory device, identify information related to predetermined data in the configuration data of the memory device, and receive the predetermined data from the memory device. | 2014-05-15 |
20140136846 | METHOD AND SYSTEM FOR GENERATING A SECURE MESSAGE AS A URL MESSAGE - A method for generating and delivering a message via a web service is provided. A message for a recipient is converted to a URL and sent. A request is received from a sender to send a message to a recipient. A URL message is created in response to receiving the request to send the message to the recipient and the URL message is sent to the recipient. A URL message response is received from the recipient and a landing message is sent to the recipient in response to receiving the URL message response. The landing message includes a hint requesting an answer from the recipient. An answer is received from the recipient and the message is displayed to the recipient in response to receiving the answer. | 2014-05-15 |
20140136847 | SECURITY AND AUTHENTICATION SYSTEMS AND METHODS FOR PERSONALIZED PORTABLE DEVICES AND ASSOCIATED SYSTEMS - Systems and methods for client authentication and verification in a distributed client-server system are described. An authentication and verification system may include a plurality of client devices containing private keys, a first server configured to interface with the plurality of client devices, and a second, secure server configured to interface with the first server and store public keys associated with the private keys on the client devices. A method is further described for verifying client devices in conjunction with the first and second servers. The first server may contain secure tokens that can be decrypted in conjunction with the authentication and verification method. | 2014-05-15 |
20140136848 | DISTRIBUTING KEYPAIRS BETWEEN NETWORK APPLIANCES, SERVERS, AND OTHER NETWORK ASSETS - A method and apparatus for providing an automated key distribution to enable communication between two networked devices. A monitoring device receives a request from a network device to send a certificate using a second secure connection prior to an expiration of a timeout period, wherein the second secure connection was created using a known port in response to determining that a request to create a first secure connection was rejected. The monitoring device sends the certificate to the network device using the second secure connection, and establishes the first secure connection with the network device in response to the network device receiving the public key of the monitoring device from a server system by using the certificate. | 2014-05-15 |
20140136849 | METHOD FOR OPERATING A MOBILE DEVICE BY MEANS OF A MOTOR VEHICLE - A method for operating a mobile device, not assigned to a motor vehicle, via an electronic device with a display and operator control device of the motor vehicle is made available. The program has program parts for a user interface and for operator control sequences which are assigned a digital certificate. The user interface comprises fixed areas for displaying variable contents. The program parts are transmitted together with the digital certificate to the electronic device of the motor vehicle and are carried out when the certificate is successfully checked. The transmission of data without protection by a digital certificate is restricted to the variable contents for display in the fixed areas of the user interface. | 2014-05-15 |
20140136850 | PASSWORD INPUT SYSTEM AND METHOD FOR INPUTTING PASSWORD - A password input system and a method inputting a password are provided. The password input system includes a signal receiving unit, a processing unit and a storage device. The signal receiving unit receives input signals comprising key-pressing signals and key-releasing signals respectively corresponding to the key-pressing signals and each key-pressing signal corresponds to an alphanumeric symbol. The processing unit, according to a predetermined key-releasing rule, sequentially groups the alphanumeric symbols corresponding to the key-pressing signals into groups. Each group is regarded as a password element and the password elements together form a multi-key input password set. The storage device stores the multi-key input password set. | 2014-05-15 |
20140136851 | BIOMETRIC-BASED WIRELESS DEVICE ASSOCIATION - According to one aspect of the present disclosure, a method and technique for automatically associating a wireless device to a data processing system using biometric data is disclosed. The method includes: receiving biometric data corresponding to a user of a data processing system; creating a certificate by the data processing system based on the biometric data; discovering a wireless device able to communicate with the data processing system; responsive to discovering the wireless device, automatically requesting a certificate from the wireless device; and, responsive to the certificate from the wireless device matching the certificate created by the data processing system, automatically associating the wireless device with the data processing system. | 2014-05-15 |
20140136852 | SECURE CIRCUIT INTEGRATED WITH MEMORY LAYER - A secure integrated circuit comprises a lower logic layer, and one or more memory layers disposed above the lower logic layer. A security key is provided in one or more of the memory layers for unlocking the logic layer. | 2014-05-15 |
20140136853 | APPARATUS AND METHOD FOR PERFORMING DIFFERENT CRYPTOGRAPHIC ALGORITHMS IN A COMMUNICATION SYSTEM - A communication apparatus performs encryption on data transmitted from another communication apparatus by using first or second cryptographic algorithm, or performs decryption on the data that has been encrypted using the first or second cryptographic algorithm, by using one of the first and second cryptographic algorithms used for the encryption, where the second cryptographic algorithm provides a higher security level than the first cryptographic algorithm. The communication apparatus includes an encryption unit configured to perform, upon receiving the data including a cryptographic class identifying a parameter to be used for performing the encryption or the decryption, the encryption or the decryption by using one of the first and second cryptographic algorithms, based on the cryptographic class. | 2014-05-15 |
20140136854 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND COMPUTER PROGRAM - Provided is an information processing apparatus including a program execution unit configured to read, interpret and execute a code of a computer program that is created in a procedural language, and a backup unit configured to create a backup in a format in which a variable definition and a function definition in the code being executed by the program execution unit are interpretable as a code in the procedural language. | 2014-05-15 |
20140136855 | SECURE KEY ACCESS WITH ONE-TIME PROGRAMMABLE MEMORY AND APPLICATIONS THEREOF - A device includes a key store memory that stores one or more cryptographic keys. A rule set memory stores a set of rules for accessing the cryptographic keys. A key store arbitration module grants access to the cryptographic keys in accordance with the set of rules. The device can be used in conjunction with a key ladder. The device can include a one-time programmable memory and a load module that transfers the cryptographic keys from the one one-time programmable memory to the key store memory and the set of rules to the rule set memory. A validation module can validate the cryptographic keys and the set of rules stored in the key store and rule set memories, based on a signature defined by a signature rule. | 2014-05-15 |
20140136856 | SYSTEM AND METHOD FOR UPDATING FIRMWARE - A mechanism that allows firmware for a computing device to be updated in a secure manner by utilizing an update validation procedure included in a ROM image is discussed. | 2014-05-15 |
20140136857 | POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM - A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement. | 2014-05-15 |
20140136858 | POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM - An active memory system includes a computer and an active memory device including layers of memory forming a three-dimensional memory device and individual columns of chips forming vaults in communication with a processing element and logic. The processing element is configured to communicate to the chips and other processing elements. The active memory system also includes a compiler configured to implement a method. The method includes dividing a power budget for the active memory device into a discrete number of power tokens, each of the power tokens having an equal value of units of power. The method also includes determining a power requirement for executing a code segment on the processing element of the active memory device based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, one or more power tokens to satisfy the power requirement. | 2014-05-15 |
20140136859 | HUMIDITY MEASURING CIRCUIT - A humidity measuring circuit includes a comparing circuit and a switch circuit. The comparing circuit measures humidity and compares the measured humidity with a preset value, to output a first control signal or a second control signal. The switch circuit receives the first or second control signal and controls a computer to be powered on or not. When humidity measured by the comparing circuit is greater than the preset value, the comparing circuit outputs the first control signal to the switch circuit. The switch circuit is turned on and controls the computer not to be powered on. When humidity measured by the comparing circuit is equal to or less than the preset value, the comparing circuit outputs the second control signal to the switch circuit. The switch circuit is turned off and controls the computer to be powered on. | 2014-05-15 |
20140136860 | APPARATUS AND SYSTEM FOR GENERATING A SIGNAL WITH PHASE ANGLE CONFIGURATION - Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators. | 2014-05-15 |
20140136861 | DATA REQUEST PATTERN GENERATING DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - A data request pattern generating device may include a sequence detector configured to generate data request sequence information based on a plurality of data request signals. The data request signals may be output from a plurality of function blocks. The device may include a time detector configured to generate data request time information based on the data request signals. The device may include a pattern generator configured to generate a data request pattern based on the data request sequence information and the data request time information. | 2014-05-15 |
20140136862 | PROCESSOR AND CIRCUIT BOARD INCLUDING THE PROCESSOR - The present invention provides a processor and a circuit board including the processor. The processor includes a data processing unit, and an external power supply component that is coupled to the data processing unit; wherein the data processing unit includes a power management unit that is integrated into the data processing unit, and the power management unit is used for performing power management for the data processing unit; and the power management unit further includes a pulse signal output terminal which is used for outputting a pulse-width modulation signal, and the pulse-width modulation signal controls the external power supply component to supply a stable operating voltage to the data processing unit. The present invention provides a processor with the improved performance, the improved stability and the simplified structure. | 2014-05-15 |
20140136863 | HIGH VOLTAGE CHARGING FOR A PORTABLE DEVICE - Techniques for performing high-voltage charging of electronic devices are provided. A portable device can communicate with a power supply over a data communication line to determine if the power supply is capable of performing the high-voltage charging operation. If yes, the portable device instructs the power supply to provide a specific voltage. | 2014-05-15 |
20140136864 | MANAGEMENT TO REDUCE POWER CONSUMPTION IN VIRTUAL MEMORY PROVIDED BY PLURALITY OF DIFFERENT TYPES OF MEMORY DEVICES - Reduction of memory power consumption in virtual memory systems that have a combination of different types of physical memory devices working together in a system's primary memory to achieve performance with optimum reductions in power consumption by storing in the virtual memory in the kernel, topology data for each of the different memory devices used. | 2014-05-15 |
20140136865 | Cooperatively Managing Enforcement of Energy Related Policies Between Virtual Machine and Application Runtime - A mechanism is provided in a data processing system for runtime based enforcement of energy policies collaboratively. The application runtime environment executing within a virtual machine on the data processing system receives notification of a change in energy policy for the virtual machine or the physical host it is running on. Responsive to determining the virtual machine is to be run under a power cap based on the notification of a change in energy policy, the application runtime environment dynamically modifies execution of an application in the application runtime environment or requests the execution environment for delaying enforcement of energy policies. The application comprises a set of application modules. | 2014-05-15 |
20140136866 | RACK AND POWER CONTROL METHOD THEREOF - A power control method of a rack having a plurality of nodes includes the following steps. Power information of each node is received. a total power consumption value of the plurality of nodes according to the power information is calculated. A number of power supply units to be turned on according to the total power consumption value and a maximum supplied power value of a single power supply unit is calculated. At least one primary power supply unit and at least one secondary power supply unit in pairs according to the number of power supply units to be turned on is started. The at least one primary power supply unit provides a duty voltage to the plurality of nodes, and the at least one secondary power supply unit does not provide the duty voltage to the plurality of nodes. | 2014-05-15 |
20140136867 | ELECTRONIC DEVICE, CONTROL METHOD OF ELECTRONIC DEVICE, AND PROGRAM - Aspects of the present invention include a device comprising a memory storing instructions and a processing circuit executing the instructions to detect a first user action. The instructions may further include instructions to establish a first user action state based on the detected first user action, designate a first mode based on the first user action state, determine if a second user action, consistent with a first detection condition associated with the first mode, has taken place, when the second user action has taken place, establish a second user action state based on the second user action, and designate a second mode based on the second user action state, the second mode consuming more power than the first mode. | 2014-05-15 |
20140136868 | POWER SAVING METHOD AND HANDHELD ELECTRONIC DEVICE USING THE SAME - A power saving method and a handheld electronic device using the same are provided. The method includes the following steps. A trigger signal is received. An user interface is displayed in a touch display panel unit of the handheld electronic device, wherein the user interface includes at least one control item and the at least one control item respectively corresponds to at least one working mode of the handheld electronic device. An operating signal corresponding to one of the at least one control item is received from the touch display panel unit. The working mode of the handheld electronic device is switched according to the operating signal and a working frequency of the handheld electronic device is adjusted according to the working mode. | 2014-05-15 |
20140136869 | ADAPTIVE CONNECTED STANDBY FOR A COMPUTING DEVICE - Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery. | 2014-05-15 |
20140136870 | TRACKING MEMORY BANK UTILITY AND COST FOR INTELLIGENT SHUTDOWN DECISIONS - A device receives an indication that a memory bank is to be powered down, and determines, based on receiving the indication, shutdown scores corresponding to powered up memory banks. Each shutdown score is based on a shutdown metric associated with powering down a powered up memory bank. The device may power down a selected memory bank based on the shutdown scores. | 2014-05-15 |
20140136871 | MOBILE ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - There is provided a mobile electronic device for reducing power consumption, the device including a user input unit receiving a power saving condition; a sensing unit acquiring state information; and a controller changing an operating mode based on the power saving condition and the state information. | 2014-05-15 |
20140136872 | Monitoring transaction requests using a policy engine within a storage drive driver to change power capability and latency settings for a storage drive - With embodiments of the invention, a more robust solution is provided using a storage driver that may already be used for the platforms operating system. This is efficient because the storage driver typically already monitors storage drive access requests, and thus knows when traffic is outstanding (performance may be critical) or when it's not outstanding (and power may be saved). | 2014-05-15 |
20140136873 | TRACKING MEMORY BANK UTILITY AND COST FOR INTELLIGENT POWER UP DECISIONS - A device receives an indication that a memory bank is to be powered up, and determines, based on receiving the indication, power scores corresponding to powered down memory banks. Each power score corresponds to a power metric associated with powering up a powered down memory bank. The device powers up a selected memory bank based on the plurality of power scores. | 2014-05-15 |
20140136874 | LOW LATENCY DISCOVERY FOR POWER OVER ETHERNET - Embodiments of the present disclosure provide systems and methods for reducing discovery time in a power over Ethernet (PoE) system where the nature of a load is known or can be safely assumed. By using prior knowledge of the nature of the load, the discovery procedure can be simplified. A power source device (PSE) controller measures a port voltage to determine if an open circuit exists or if a short circuit exists. If neither an open circuit or a short circuit exists, the system can be safely powered up. | 2014-05-15 |
20140136875 | APPARATUS AND METHOD OF CONTROLLING CLOCK SIGNALS - An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval. | 2014-05-15 |
20140136876 | Complementary Output Generator Module - A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications. | 2014-05-15 |
20140136877 | GENERATION AND DISTRIBUTION OF A SYNCHRONIZED TIME SOURCE - An apparatus comprising a first oscillator, a time source controller coupled with the first oscillator and corrected time interval counters coupled with the time source controller. The first oscillator is configured to transmit a raw time interval pulse at regular or near regular intervals. The time source controller is configured to receive an indication of time that indicates at least one of the current day and the current time and to determine that the raw interval pulse should be adjusted based on the indication of time. The time source controller is also configured to generate a steered time interval pulse based, at least partly, on the raw time interval pulse and the indication of time, and distribute the steered time interval pulse to a plurality of hardware components. The time interval counters are configured to host a time value based on the output from the time source controller. | 2014-05-15 |
20140136878 | Scaling Up and Scaling Out of a Server Architecture for Large Scale Real-Time Applications - Scaling up and scaling out of a server architecture for large scale real-time applications is provided. A group of users may be provisioned by assigning them to a server pool and allotting them to a group. Grouped users help to reduce inter-server communication when they are serviced by the same server in the pool. High availability may be provided by choosing a primary server and one or more secondary servers from the pool to ensure that grouped users are serviced by the same server. Operations taken on the primary server are synchronously replicated to secondary servers so that when a primary server fails, a secondary server may be chosen as the primary for the group. Servers for multiple user groups may be load balanced to account for changes in either the number of users or the number of servers in a pool. Multiple pools may be paired for disaster recovery. | 2014-05-15 |
20140136879 | TRANSMISSION APPARATUS AND TRANSMISSION APPARATUS CONTROL METHOD - A first interface board includes a first signal processing unit that performs a predetermined process on a signal. A second interface board includes a second signal processing unit that performs the predetermined process on a signal. When no failure occurs in both interface boards, a switching control unit selects the first interface board. When a failure occurs in the first interface board, the switching control unit selects the second interface board. When there is no failure in both the interface boards and the first interface board does not satisfy a predetermined degradation condition, the electrical power supply control unit supplies electrical power to the first interface board and prohibits the supply of electrical power to the second interface board. When there is no failure in both the interface boards but the predetermined degradation condition is satisfied, the electrical power supply control unit supplies electrical power to both the interface boards. | 2014-05-15 |
20140136880 | NON-DISRUPTIVE FAILOVER OF RDMA CONNECTION - A novel RDMA connection failover technique that minimizes disruption to upper subsystem modules (executed on a computer node), which create requests for data transfer. A new failover virtual layer performs failover of an RDMA connection in error so that the upper subsystem that created a request does not have knowledge of an error (which is recoverable in software and hardware), or of a failure on the RDMA connection due to the error. Since the upper subsystem does not have knowledge of a failure on the RDMA connection or of a performed failover of the RDMA connection, the upper subsystem continues providing requests to the failover virtual layer without interruption, thereby minimizing downtime of the data transfer activity. | 2014-05-15 |
20140136881 | MANAGING FATE-SHARING IN SHARED-MEDIA COMMUNICATION NETWORKS - In one embodiment, a management device receives one or more fate-sharing reports locally generated by one or more corresponding reporting nodes in a shared-media communication network, the fate-sharing reports indicating a degree of localized fate-sharing between one or more pairs of nodes local to the corresponding reporting nodes. The management device may then determine, globally from aggregating the fate-sharing reports, one or more fate-sharing groups indicating sets of nodes having a global degree of fate-sharing within the communication network. As such, the management device may then advertise the fate-sharing groups within the communication network, wherein nodes of the communication network are configured to select a plurality of next-hops that minimizes fate-sharing between the plurality of next-hops. | 2014-05-15 |
20140136882 | INFORMATION DEVICE, STORAGE MEDIUM AND INITIAL STATE RESTORATION METHOD - An information device has a storage medium storing information items which includes a first program provided on a first partition, a second program and data Provided on a second partition to restore the first program on the first partition to a predetermined state, a boot block which causes system activation from one of the first partition and the second partition, and an active-partition switching program which indicates, to the boot block, one of the first and second partitions An input/output system activates the active-partition switching program when a specific operation is performed. The active-partition stitching program indicates to the boot block that system activation is to be executed from the second partition. | 2014-05-15 |
20140136883 | READ DISTURB EFFECT DETERMINATION - An apparatus comprising a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) accumulate a read disturb count for a first region of the non-volatile memory, (ii) accumulate error statistics for a second region of the non-volatile memory, (iii) determine, based upon both the read disturb count and the error statistics, whether the first region has reached a read disturb limit, and (iv) in response to determining that the first region has reached the read disturb limit, relocate at least some data of the first region. | 2014-05-15 |
20140136884 | READ DISTURB HANDLING FOR NON-VOLATILE SOLID STATE MEDIA - Described embodiments track a read disturb limit of a solid-state media coupled to a media controller. The media controller receives a read operation from a host device. In response to the received read operation, the media controller determines one or more associated regions of the solid-state media accessed by the read operation and reads the associated regions to provide read data to the host device. Based on a probability value corresponding to each of the associated regions, the media controller selectively increments a read count of each of the associated regions. Based upon each read count, the media controller determines whether each region has reached a read disturb limit. If a given region has reached the read disturb limit, the media controller relocates data of the given region to a free region of the solid-state media. Otherwise, the media controller maintains the data in the given region. | 2014-05-15 |
20140136885 | ISOLATING AND CORRECTING VPD DATA MISMATCH AND/OR CORRUPTION - Disclosed is a method of detecting a product data error in a storage system. First and second vital product data (VPD) EEPROMs are read. Indicators of whether wither or both reads failed are received. Based on these indicators, the contents of the VPD EEPROMs may be compared. Based on a result of the comparing indicating a match, an arbitrary one of the VPD EEPROMS is used. Based on an indicator indicating an error with the first VPD EEPROM, the second VPD EEPROM is used. | 2014-05-15 |
20140136886 | METHOD FOR THE OPTIMIZATION OF PERFORMANCE, CAPACITY AND REDUNDANCY IN DIGITAL DATA STORAGE SYSTEMS - A method and system of optimizing the performance, capacity and data redundancy in a storage system by defining the LBA range on each storage element managing that corresponding range (slice) on each device using a data protection method optimized for the performance and level of data protection required. The creation of such a storage array along with the replacement of failed elements and the expansion of the capacity through the addition of additional elements is managed is an automatic and transparent manner. | 2014-05-15 |
20140136887 | DISK ARRAY HAVING MIRROR CONFIGURATION AND REBUILDING METHOD THEREFOR - One aspect includes a disk array having a mirror configuration to rebuild. The disk array includes a buffer to temporarily store data (data X) in a read or write request from a host (read/write request), a redundant first disk and second disk having a mirror configuration, and an auxiliary disk. A redundancy management table logs disk locations of data stored in the first disk and copied to the auxiliary disk. A controller controls reading and writing of data X between the buffer and two redundant disks in response to a request. The controller is configured to: (a) copy to the auxiliary disk, data X stored in the buffer for rebuilding, in parallel with reading and writing data X, when the second disk fails; (b) log, in the redundancy management table, copied disk locations of data X copied in (a); and (c) return a response to the host after copying completion. | 2014-05-15 |
20140136888 | CORE FILE LIMITER FOR ABNORMALLY TERMINATING PROCESSES - Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold. | 2014-05-15 |
20140136889 | DIRECTORY-LEVEL RAID - A method and system for reducing replication factor in a file system are provided. In some embodiments, two or more requested files may be grouped together under a leaf directory for RAID process. All data under the directory are grouped into one or more data stripes, each of which comprises a plurality of data blocks. One or more parity data blocks may be generated for each data stripe according to a computing algorithm, such as an exclusive OR (XOR) code or a Reed-Solomon (RS) code. Parity blocks corresponding to the one or more data stripes are concatenated into one parity file. Data blocks of the two or more requested files and their corresponding parity blocks are stored in separate partitions and/or separate storage drives of the file system. | 2014-05-15 |
20140136890 | CORE FILE LIMITER FOR ABNORMALLY TERMINATING PROCESSES - Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold. | 2014-05-15 |
20140136891 | MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD - Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response. | 2014-05-15 |
20140136892 | VIRTUAL TAPE LIBRARY DEVICE AND DATA RECOVERY METHOD - The present invention provides a VTL device and a data recovery method. The method includes: receiving a data recovery instruction from a user equipment, and sending the data recovery instruction to a file drive unit; responding, by a file drive unit to the data recovery instruction, acquiring virtual tape configuration information corresponding to to-be-recovered backup data from a VTL configuration unit, wherein the virtual tape configuration information is generated by the VTL configuration unit during completion of data backup and comprises an offset position of a data block used for storing the backup data and a size of the data block in a virtual tape; reading, by an input/output management unit, recovery data from a storage medium according to the virtual tape configuration information, and sending the recovery data to the NAS interface unit; and returning, by the NAS interface unit, the recovery data to the user equipment. | 2014-05-15 |
20140136893 | SYSTEM FILE REPAIR METHOD AND APPARATUS - A method and an apparatus for repairing a system file are provided. The computer-implemented method for repairing a system file, comprises: detecting, by a processor, a corrupted system file in an operating system; sending identification information of the operating system and an identifier of the corrupted system file to a server; receiving an integrity identifier of an intact system file to be used in repairing the corrupted system file, wherein the intact system file is determined by the server according to the identification information of the operating system and the identifier of the corrupted system file; verifying, by the processor, the received integrity identifier with a locally stored integrity identifier of the corrupted system file; and if the received integrity identifier passes the verification, obtaining, from the server, the intact system file corresponding to the verified integrity identifier and repairing the corrupted system file with the obtained intact system file. | 2014-05-15 |
20140136894 | EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK - An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error. | 2014-05-15 |
20140136895 | EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK - An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error. | 2014-05-15 |
20140136896 | DIAGNOSING DISTRIBUTED APPLICATIONS USING APPLICATION LOGS AND REQUEST PROCESSING PATHS - A method for monitoring a distributed application for errors includes constructing a transaction path for each request received by the distributed application, detecting a writing action to a log of the distributed application, and annotating the transaction path in accordance with the writing action to produce an annotated transaction path. In another embodiment, a method for building a knowledge base for use in diagnosing an error occurring in a distributed application includes executing the distributed application on a replica of a production server that supports the distributed application, constructing a transaction path for a request received by the distributed application, wherein the transaction path traverses the replica, injecting a fault into the transaction path, detecting a writing action to a log of the distributed application, wherein the writing action is a response to the fault, and storing an association between the fault and the writing action. | 2014-05-15 |
20140136897 | DATA VERIFICATION - A data verification application receives a test configuration data, the test configuration data comprising a seed value and a parameter. The data verification application generates a pseudo-random test data stream comprising a plurality of words, wherein a value of each of the plurality of words is based on the seed value, the parameter and an offset of each word within the pseudo-random test data stream. | 2014-05-15 |
20140136898 | Run-Time Default Detection in a Component Associated with an Application Programming Interface Platform - Methods and apparatuses for fault detection in a component associated with an application programming interface platform are provided. In an embodiment, the component is determined to have been invoked to process a transaction. A forward progress counter is monitored to determine whether the component is processing the transaction, wherein the forward progress counter increments at determined intervals when the component is processing the transaction. A test transaction is executed for the component when a determination is made that the forward progress counter has not incremented for a threshold fault period. A fault alarm indicator is generated based on the determination that the forward progress counter has not incremented for the threshold fault period. | 2014-05-15 |
20140136899 | METHODS AND SYSTEMS FOR AIDING THE ANALYSIS OF A SIGNAL - Method and related systems are described for navigating through information related to the status of one or more layers of a signal, such as a serial or parallel bus. Information may be displayed by selecting fields within a visual depicted on an oscilloscope or similar measuring instrument. By selecting particular fields, and indicators, different aspects of a layer may be analyzed without the need to have extensive knowledge of the operation of the measuring instrument. | 2014-05-15 |
20140136900 | Method for Ranking Fault-Test Pairs Based on Waveform Statistics in a Mutation-Based Test Program Evaluation System - Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a test run of the design code injected with a fault. Relative differences between the first and second multitudes of waveform statistics for each bit of each faulty output with respect to the corresponding reference output are determined. A waveform difference based on the relative differences for each signal of each faulty output is determined. A ranking result of fault-test pairs is determined according to the waveform differences of the faulty outputs. | 2014-05-15 |
20140136901 | PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS - An incompatible software level of an information technology infrastructure component is determined by comparing collected inventory information to a minimum recommended software level. If a knowledge base search finds that the incompatible software level is associated with a prior infrastructure outage event, an outage count score is determined for the incompatible software level by applying an outage rule to a historic count of outages caused by a similar incompatible software level, and combined with an average outage severity score assigned to the incompatible software level based on a level of severity of an actual historic failure of the component within a context of the infrastructure to generate a normalized historical affinity risk score. The normalized historical affinity risk score is provided for prioritizing the correction of the incompatible software level in the context of other normalized historical risk level scores of other determined incompatible software levels. | 2014-05-15 |
20140136902 | APPARATUS AND METHOD OF PROCESSING ERROR IN ROBOT COMPONENTS - An apparatus for processing an error of a robot component includes an event reception unit configured to receive event information; and an error detection unit configured to analyze the event information to determine whether there is a component where an error occurs from among the multiple components. | 2014-05-15 |
20140136903 | REDUNDANCY FOR LOSS-TOLERANT DATA IN NON-VOLATILE MEMORY - A memory device includes a memory array including a plurality of memory sections characterized by a plurality of memory types and control logic integrated with and distributed over the memory array. The control logic is operable to selectively allocate redundant sections in the plurality of memory sections. | 2014-05-15 |
20140136904 | COMPUTER SYSTEM - A computer system includes multiple hard disk devices, a hard disk device backplane, an information management unit, a middle backplane and multiple motherboards. The hard disk device backplane is coupled to and configured to manage the hard disk devices. The information management unit, coupled to the hard disk device backplane, is configured to acquire statuses of the hard disk devices. The middle backplane is coupled to the hard disk device backplane. The motherboards, coupled to the information management unit and the middle backplane, respectively have a baseboard management controller. When the operating system is loaded for operation on the motherboards, the baseboard management controllers are coupled to the hard disk device backplane via the middle backplane to acquire the statuses of the hard disk devices. When the motherboards are not operated normally, the baseboard management controllers acquire the statuses of the hard disk devices via the information management unit. | 2014-05-15 |
20140136905 | Methods for Testing Network Circuitry - A method of operating a test equipment system that is coupled to network circuitry is described. The method displays only selected information. Furthermore, the method may display the selected information in a manner as to allow a user of the test equipment to easily identify errors in the network circuitry. The method may select the information to be displayed by processing received signals according to a stacked protocol hierarchical structure. | 2014-05-15 |
20140136906 | Method And System To Distribute Fault Information In A Large Scale Communication Network System - The present invention relates to a method and an arrangement for distributing fault information from a lower level network management node to a higher level network management node in a network management architecture comprising modules logically representing network nodes and network links under management. The higher level network management node subscribes to at least some detailed fault information. And, a notification comprising a summary of fault information sent by the lower level network management node is received by the higher level network management node. Then, the higher level network management node retrieves the subscribed detailed fault information from said received notification. | 2014-05-15 |
20140136907 | ERROR RATE THRESHOLD FOR STORAGE OF DATA - Embodiments of the invention relate to calculation of error rate for data storage which includes determining a completion status of a read operation of data stored in a storage device, the completion status being one of at least partially complete or not complete. The fault monitoring count is incremented based on the completion status being not complete. The fault monitoring count is decreased based on the completion status being at least partially complete. The fault monitoring count being decreased according to a value based on the number of bytes successfully read. The error rate indicator value is being calculated based on an exponential decay rate related to the number of bytes read. The fault monitoring count threshold is monitored every time the fault monitoring count is incremented and the storage device is identified as faulty once the threshold limit is exceeded. | 2014-05-15 |
20140136908 | Fault Protection Method and Fault Protection Apparatus in a Multi-Domain Network - The present invention relates to a fault protection method and a fault protection device for an inter-domain link of a multi-domain network. The invention may be particularly applied to multi-domain networks providing end to end services such as an Ethernet service. Embodiments of the invention use a link protection group for an inter-domain link. Link protection group information relating to the link protection group is used to identify a replacement inter-domain link for a faulty inter-domain link that is configured for an inter-domain service. Once the replacement link is identified, the routing of the inter-domain service may be re-configured from the network element ports of the faulty inter-domain link to the network element ports of the identified second inter-domain link. | 2014-05-15 |
20140136909 | TESTING OF SRAMS - Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM. | 2014-05-15 |
20140136910 | DATA COMMUNICATION APPARATUS AND CONTROL METHOD - A data communication apparatus includes a data generation unit, a control register, a memory, a memory address generation unit, a failure setting unit, and a transmission unit. The data generation unit generates data. The control register outputs an enable signal and a test control signal. In the memory, pseudo failure data is written during the test. The pseudo failure data is used to modify generated data to data having a pseudo failure. The memory address generation unit generates a readout address of the memory during the test on the basis of the enable signal and the test control signal. The failure setting unit reads out pseudo failure data from the memory using a readout address generated by the memory address generation unit, and modifies the generated data to data having the pseudo failure. The transmission unit transmits the data having the pseudo failure modified by the failure setting unit. | 2014-05-15 |
20140136911 | REMOTE MONITORING SYSTEMS AND RELATED METHODS AND RECORDING MEDIUMS USING THE SAME - Remote monitoring systems for remotely monitoring execution status of a PLC (Programmable Logic controller) program of a machine include a storage module, a parameter retrieval module and a monitoring module. The storage module stores ladder diagram information corresponding to a PLC source program, wherein the ladder diagram information includes PLC signal address relation information, a plurality of logic switches and a responsive collect command of each logic switch of a ladder diagram. The PLC signal address relation information indicates the relations of the logic switches on the ladder diagram. The parameter retrieval module respectively retrieves parameter data corresponding to the logic switches using the responsive collect commands. The monitoring module generates a status of ladder diagram according to the logic switches, the parameter data and the PLC signal address relation information to display the parameter data corresponding to each logic switch when the machine is executing the PLC source program. | 2014-05-15 |
20140136912 | COMBO DYNAMIC FLOP WITH SCAN - A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit. | 2014-05-15 |
20140136913 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 2014-05-15 |
20140136914 | HIGHLY SECURE AND EXTENSIVE SCAN TESTING OF INTEGRATED CIRCUITS - In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register. | 2014-05-15 |
20140136915 | ERROR CORRECTION WITH NON-VOLATILE MEMORY ON AN INTEGRATED CIRCUIT - A memory device includes but is not limited to a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to maintain a plurality of copies of data in the non-volatile memory array and detect errors by comparison of selected ones of the plurality of copies. | 2014-05-15 |
20140136916 | DIFFERENTIAL FORMATTING BETWEEN NORMAL AND RETRY DATA TRANSMISSION - A system and method are disclosed for error corrected data transmission using an error detection and retry scheme. Data frames are sent from a transmitting chip to a receiving chip either formatted as PHITs or combined, compressed, and formatted as ePHITs. The ePHIT formatting includes hashing one or more CRC with a sequence number that is generated in the receiver. Upon error detection, a retry operation may retransmit the data in a different format than the original transmission. | 2014-05-15 |
20140136917 | BUFFER MANAGEMENT USING SIDE INFORMATION - Devices and/or methods for managing a buffer containing failed data may utilize side information related to the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors and/or a local host requested status for buffered or unbuffered failed data. | 2014-05-15 |
20140136918 | RECONSTRUCTIVE ERROR RECOVERY PROCEDURE (ERP) USING RESERVED BUFFER - According to one embodiment, a method for reading data from a medium includes reading a data set from a medium repeatedly using different settings until either: a reconstructed data set is sent to a host and/or stored, or a maximum number of rereads has been reached, after each reading of the data set, storing each row to the reserved data buffer that has no errors or errors in the row are correctable using C1-Error Correction Code (ECC) unless a matching row already exists in the reserved data buffer that has fewer corrected errors therein, assembling the data set from the rows stored in the reserved data buffer to form an assembled data set, correcting any remaining errors in the assembled data set using C2-ECC to form the reconstructed data set, and sending the reconstructed data set to the host and/or storing the reconstructed data set. | 2014-05-15 |
20140136919 | RECONSTRUCTIVE ERROR RECOVERY PROCEDURE (ERP) FOR MULTIPLE DATA SETS USING RESERVED BUFFER - In one embodiment, a system includes logic adapted to read a plurality of data sets from a medium one or more times; logic adapted to store portions of some of the data sets to a reserved data buffer when the portions are correctable using C1-error correction code (ECC); logic adapted to aggregate all stored portions for each of the complete data sets to form assembled data sets; logic adapted to determine whether C2-ECC is capable of correcting all errors in the assembled data sets, to correct any remaining errors in the assembled data sets, and to send the corrected data sets to a host when C2-ECC is capable of correcting all errors in the assembled data sets; and logic adapted to reread at least a first uncorrected data set from the medium using a different setting when an error in the first uncorrected data set is not correctable. | 2014-05-15 |
20140136920 | MEMORY CONTROLLER CHANGING PARTIAL DATA IN MEMORY DEVICE AND METHOD FOR CHANGING PARTIAL DATA THEREOF - A partial data changing method of a memory controller includes receiving a request to change partial data from a host; detecting an error of old data, the old data being partial data read from a memory device using an error detection code; if the old data is not erroneous, calculating a data difference between new data provided from the host and the old data, and calculating a new parity using the data difference and an old parity read from the memory device; and storing the new data and the new parity at the memory device. | 2014-05-15 |
20140136921 | ENCODING METHOD, DECODING METHOD - An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. | 2014-05-15 |
20140136922 | RADIO TRANSMITTING/RECEIVING DEVICE, COMMUNICATION SYSTEM, AND CHANNEL CODING PROCESSING METHOD USED THEREBY - A radio transmitting/receiving device uses a channel interleaver with turbo codes serving as error-correcting codes to convert burst errors into random errors. The radio transmitting/receiving device, in Code Block Concatenation ( | 2014-05-15 |
20140136923 | METHOD FOR ENCODING DATA IN BURSTS - A process of encoding information data in a sequence of bursts ( . . . , B | 2014-05-15 |
20140136924 | METHOD AND SYSTEM FOR DETERMINING STORING STATE OF FLASH MEMORY - A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage. | 2014-05-15 |
20140136925 | METHOD OF OPERATING A DATA STORAGE DEVICE - A method of operating a data storage device including a nonvolatile memory device includes reading last programmed data from the nonvolatile memory device, detecting an error included in the data read in the reading, correcting the error of if the error is correctable, and reprogramming the corrected data to the nonvolatile memory device. | 2014-05-15 |
20140136926 | NON-SYSTEMATIC CODED ERROR CORRECTION - Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption. | 2014-05-15 |
20140136927 | ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE - Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time. | 2014-05-15 |
20140136928 | PROGRAMMING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) - A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells. | 2014-05-15 |
20140136929 | STORAGE MEDIUM, SYSTEM AND METHOD UTILIZING THE SAME - A storage medium receiving write data provided by a host device, providing read data to the host and including a first module and a second module is disclosed. The first module includes a first memory cell and a first controller. The first memory cell stores the write data. The first controller reads the first memory cell to generate a first accessing result. The second module includes a second memory cell and a second controller. The second memory cell stores the write data. The second controller reads the second memory cell. When the first accessing result has an error and the error cannot be corrected by the first controller, the first controller requests the second controller to read the second memory cell to generate a second accessing result, and the second controller serves the second accessing result as the read data and provides the read data to the host. | 2014-05-15 |
20140136930 | DATA DECODING USING SIDE INFORMATION - Devices and/or methods may decode failed data, e.g., utilizing side information related to the failed data to determine how to decode the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors within a failed data portion, a remaining amount of unread portions of a data block including failed data, an amount of requested portions of a data block including failed data, if the failed data is buffered, and a decoding status of any previously-failed data. | 2014-05-15 |
20140136931 | ERROR-CORRECTING DECODER - Provided is an error-correcting decoder including: a syndrome generation unit for calculating, as a syndrome, coefficients of a residual polynomial that are obtained by dividing received data by a generator polynomial; information bit error pattern generation unit for generating all error patterns of information bits; a check bit error pattern generation unit for calculating, for each of the error patterns of the information bits, an error pattern of check bits based on the syndrome value; and an error correction unit for correcting the error pattern generated for a combination of codes having a weight of the error patterns of the information bits and the check bits smaller than a threshold value. | 2014-05-15 |
20140136932 | COMPENSATING FOR GAPS IN WORKLOAD MONITORING DATA - Gaps in performance data are corrected for through data transformations and conversion. A raw sequence is transformed by correction logic into an interval sequence by partitioning a performance monitoring period into equal intervals and assigning values based on the raw sequence. Locality sequence entries can indicate whether the interval sequence relies on estimation. The interval sequence is converted into an absence length sequence whose entries indicate null value periods in performance data. Conversion includes generating a presence sequence from the interval sequence, and deriving the absence length sequence from the presence sequence, by using a set-based algorithm or other mechanism. Excessive absence length values support treating intervals as downtime for the machine. Correction logic may include a stored procedure residing in a database, for example, which produces the absence length sequence without using a procedural language. | 2014-05-15 |
20140136933 | USER PROFILE IMPROVEMENT SYSTEM - A method and a system for superimposing a prompt over a second user profile page being displayed on a client device, the prompt inviting a first user to update a first user profile page associated with the first user, based on the second user profile page being displayed. | 2014-05-15 |
20140136934 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An image processing apparatus includes a reception unit configured to receive specification of a plurality of material electronic documents and an instruction on generation of an integrated electronic document based on the plurality of material electronic documents, a display unit configured to, when the reception unit receives the instruction, display on a display unit a setting screen for receiving setting on the generation of the integrated electronic document from the plurality of material electronic documents before the integrated electronic document is generated, and a generation unit configured to, based on the setting received via the setting screen, generate the integrated electronic document from the plurality of material electronic documents. | 2014-05-15 |