20th week of 2017 patent applcation highlights part 60 |
Patent application number | Title | Published |
20170141186 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface. | 2017-05-18 |
20170141187 | NITRIDE COMPOUND SEMICONDUCTOR - A nitride compound semiconductor has a substrate and a nitride compound semiconductor stack on the substrate. The nitride compound semiconductor stack includes a multilayer buffer layer, a channel layer on this multilayer buffer layer, and an electron supply layer on this channel layer. A recess extends from the surface of the electron supply layer through the channel layer and the multilayer buffer layer. A heat dissipation layer in this recess is contiguous to the multilayer buffer layer and the channel layer and has a higher thermal conductivity than the multilayer buffer layer. | 2017-05-18 |
20170141188 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over a semiconductor substrate. The first semiconductor layer and the second semiconductor layer include different materials. The semiconductor device structure also includes a gate stack covering a first portion of the first semiconductor layer. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element covers the second semiconductor layer and a second portion of the first semiconductor layer. The thickness of the second semiconductor layer is different from the thickness of the second portion. | 2017-05-18 |
20170141189 | FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulation portion distributed therein. The semiconductor fin is sandwiched by the insulators. The gate stack is disposed over portions of the semiconductor fin and over portions of the insulators. The strained material covers portions of the semiconductor fin that are revealed by the gate stack. In addition, a method for fabricating the FinFET is provided. | 2017-05-18 |
20170141190 | GAN-ON-SI SWITCH DEVICES - A low leakage current switch device ( | 2017-05-18 |
20170141191 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE - Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases. | 2017-05-18 |
20170141192 | Group III-V Device Structure Having a Selectively Reduced Impurity Concentration - There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface. | 2017-05-18 |
20170141193 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE, THEIR MANUFACTURING METHODS, AND DISPLAY DEVICE - The present disclosure provides a TFT, an array substrate, their manufacturing method, and a display device. The method for manufacturing the TFT includes a step of forming a pattern of a semiconductor active layer on a transparent substrate through a patterning process, and the pattern of the semiconductor active layer includes a lanthanum boride pattern. | 2017-05-18 |
20170141194 | SEMICONDUCTOR ELECTRONIC DEVICE FORMED OF 2-D VAN DER WAALS MATERIAL WHOSE FREE CHARGE CARRIER CONCENTRATION IS DETERMINED BY ADJACENT SEMICONDUCTOR'S POLARIZATION - Embodiments of the present invention are directed to semiconductor electronic devices formed of 2-D van der Waals material whose free charge carrier concentration is determined by adjacent semiconductor's polarization. According to one particular embodiment, a semiconductor electronic device is composed of one or more layers of two dimensional (2-D) van der Waals (VDW) material; and one or more layers of polarized semiconductor material adjacent to the one or more layer of 2-D VDW material. The polarization of the adjacent semiconductor material establishes the free carrier charge concentration of the 2-D VDW material. | 2017-05-18 |
20170141195 | SEMICONDUCTOR SUBSTRATE - Provided is a semiconductor substrate including a seed layer disposed on a substrate, a buffer layer disposed on the seed layer, a plurality of nitride semiconductor layers disposed on the buffer layer, and at least one stress control layer between the plurality of nitride semiconductor layers. The buffer layer includes a plurality of step regions and at least one heterogeneous region. The plurality of step regions includes the same nitride semiconductor material. The heterogeneous region includes a different nitride semiconductor material from the step regions. | 2017-05-18 |
20170141196 | Semiconductor Device Having an Oxygen Diffusion Barrier - A semiconductor device includes a semiconductor body having opposite first and second surfaces, a drift or base zone in the semiconductor body and an oxygen diffusion barrier in the semiconductor body. The drift or base zone is located between the first surface and the oxygen diffusion barrier and directly adjoins the oxygen diffusion barrier. The semiconductor device further includes first and second load terminal contacts. At least one of the first and the second load terminal contacts is electrically connected to the semiconductor body through the first surface. | 2017-05-18 |
20170141197 | SELF ALIGNED REPLACEMENT METAL SOURCE/DRAIN FINFET - A fin-shaped field effect transistor (finFET) device comprising includes a substrate, an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate. | 2017-05-18 |
20170141198 | MOSFET WITH ASYMMETRIC SELF-ALIGNED CONTACT - A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates. | 2017-05-18 |
20170141199 | Method for Forming a Field Effect Transistor Device Having an Electrical Contact - A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region. | 2017-05-18 |
20170141200 | FLASH CELL AND FORMING PROCESS THEREOF - A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip. | 2017-05-18 |
20170141201 | Memory First Process Flow and Device - A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed. | 2017-05-18 |
20170141202 | POLYMER ON GRAPHENE - A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer. | 2017-05-18 |
20170141203 | METAL GATE PROCESS FOR FINFET DEVICE IMPROVEMENT - In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole. | 2017-05-18 |
20170141204 | An Array Substrate And A Method Thereof And A Display Panel Including The Same - The present invention teaches an array substrate, its manufacturing method, and a display panel using the array substrate. The array substrate contains a substrate and a number of thin film transistors (TFTs) on a top side of the substrate. Each TFT contains a gate electrode, a gate insulating layer, a channel layer, a source electrode, and a drain electrode. The gate insulating layer is between the gate electrode and the channel layer so as to prevent the conduction between the gate electrode and the channel layer. The source and drain electrodes are both on top of the channel layer. The gate insulating layer is an AlN thin film. The present invention prevents TFT threshold voltages from shifting, and guarantees the reliability of TFTs. | 2017-05-18 |
20170141205 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure. | 2017-05-18 |
20170141206 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A recombination center is formed within the bandgap of at least a silicon carbide material used to form an n | 2017-05-18 |
20170141207 | NANOSHEET MOSFET WITH FULL-HEIGHT AIR-GAP SPACER - A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer. | 2017-05-18 |
20170141208 | HEMT TRANSISTOR OF THE NORMALLY OFF TYPE INCLUDING A TRENCH CONTAINING A GATE REGION AND FORMING AT LEAST ONE STEP, AND CORRESPONDING MANUFACTURING METHOD - A HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer. | 2017-05-18 |
20170141209 | Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages - A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element | 2017-05-18 |
20170141210 | Method of Cutting Metal Gate - A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate, forming a first metal-gate line over a first and a second gate regions, applying a first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming a second metal-gate line over the first sub-metal gate line and the second sub-metal gate line, applying a second line-cut to separate the second metal-gate line into a third sub-metal gate line and a fourth sub-metal gate line such that a gap is formed between the third sub-metal gate line and the fourth sub-metal gate line and forming an isolation region within the gap. | 2017-05-18 |
20170141211 | SINGLE AND DOUBLE DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES - One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench. | 2017-05-18 |
20170141212 | METHOD FOR FABRICATING A NANOWIRE SEMICONDUCTOR TRANSISTOR HAVING AN AUTO-ALIGNED GATE AND SPACERS - Method of making a transistor with semiconducting nanowires, including:
| 2017-05-18 |
20170141213 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode. | 2017-05-18 |
20170141214 | METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES - At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the second region. | 2017-05-18 |
20170141215 | Devices Including Gate Spacer with Gap or Void and Methods of Forming the Same - Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion. | 2017-05-18 |
20170141216 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region. | 2017-05-18 |
20170141217 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are. | 2017-05-18 |
20170141218 | METHOD FOR MANUFACTURING A HEMT TRANSISTOR AND HEMT TRANSISTOR WITH IMPROVED ELECTRON MOBILITY - A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer. | 2017-05-18 |
20170141219 | EPITAXIAL BUFFER LAYERS FOR GROUP III-N TRANSISTORS ON SILICON SUBSTRATES - Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an Al | 2017-05-18 |
20170141220 | Integrated Circuit Structure with Substrate Isolation and Un-Doped Channel - The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having a first region and a second region; a first fin feature formed on the substrate within the first region; and a second fin feature formed on the substrate within the second region. The first fin feature includes a first semiconductor feature of a first semiconductor material formed on a dielectric feature that is an oxide of a second semiconductor material. The second fin feature includes a second semiconductor feature of the first semiconductor material formed on a third semiconductor feature of the second semiconductor material. | 2017-05-18 |
20170141221 | FINFET AND METHOD OF FABRICATING THE SAME - A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess. | 2017-05-18 |
20170141222 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A recess where an edge termination region is lower than an active region is disposed on a silicon carbide base body and an n | 2017-05-18 |
20170141223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Trenches and n | 2017-05-18 |
20170141224 | SEMICONDUCTOR DEVICE - A semiconductor device comprising:
| 2017-05-18 |
20170141225 | Top Drain LDMOS - In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate. | 2017-05-18 |
20170141226 | METHODS OF FORMING PMOS AND NMOS FINFET DEVICES ON CMOS BASED INTEGRATED CIRCUIT PRODUCTS - One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device. | 2017-05-18 |
20170141227 | METHODS OF FORMING PMOS FINFET DEVICES AND MULTIPLE NMOS FINFET DEVICES WITH DIFFERENT PERFORMANCE CHARACTERISTICS - One method disclosed includes forming first, second and third fins for a first NMOS device, a PMOS device and a second NMOS device, respectively. According to this method, the first fin consists entirely of the substrate material, the second and third fins comprise a lower substrate fin portion made of the substrate material and an upper fin portion made of a second semiconductor material and a third semiconductor material, respectively, wherein the second semiconductor material and the third semiconductor material are each different from the substrate material. The method also includes forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device. | 2017-05-18 |
20170141228 | FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed on the substrate and between the recesses and the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. The strained source and drain regions are disposed in the recesses and on two opposite sides of the at least one gate structure, and top edges of the strained source and drain regions are covered by the spacers and located beneath the spacers. | 2017-05-18 |
20170141229 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines. | 2017-05-18 |
20170141230 | OXIDE SEMICONDUCTOR AND SEMICONDUCTOR DEVICE - According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent. | 2017-05-18 |
20170141231 | THIN FILM TRANSISTOR AND ORGANIC EL DISPLAY DEVICE - A thin film transistor includes: a substrate; an undercoat layer disposed on the substrate; an oxide semiconductor layer formed above the undercoat layer and including at least indium; a gate insulating layer located opposite the undercoat layer with the oxide semiconductor layer being between the gate insulating layer and the undercoat layer; a gate electrode located opposite the oxide semiconductor layer with the gate insulating layer being between the gate electrode and the oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein fluorine is included in a region which is an internal region in the oxide semiconductor layer and is close to the undercoat layer. | 2017-05-18 |
20170141232 | SEMICONDUCTOR STRUCTURE WITH OXIDE SEMICONDUCTOR LAYER - The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. | 2017-05-18 |
20170141233 | SEMICONDUCTOR FILM, TRANSISTOR, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE - Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed. | 2017-05-18 |
20170141234 | SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE, DISPLAY MODULE INCLUDING THE DISPLAY DEVICE, AND ELECTRONIC APPLIANCE INCLUDING THE SEMICONDUCTOR DEVICE, THE DISPLAY DEVICE, AND THE DISPLAY MODULE - A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 1×10 | 2017-05-18 |
20170141235 | Negative Capacitance Field Effect Transistor With Charged Dielectric Material - The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack. | 2017-05-18 |
20170141236 | TFT SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a TFT substrate structure and a manufacturing method thereof. In the manufacturing method of a TFT substrate structure according to present invention, a graphene layer is formed on a semiconductor layer and after the formation of a second metal layer, the second metal layer is used as a shielding mask to conduct injection of fluoride ions into the graphene layer to form a modified area in a portion of the graphene layer that is located on and corresponds to a channel zone of the semiconductor layer, wherein the modified area of the graphene layer shows a property of electrical insulation and a property of blocking moisture/oxygen so as to provide protection to the channel zone; portions of the graphene layer that are located under source and drain electrodes are not doped with ions and preserves the excellent electrical conduction property of graphene and thus electrical connection between the source and drain electrodes and the semiconductor layer can be achieved without formation of a via in the graphene layer, making a TFT device so manufactured showing excellent I-V (current-voltage) output characteristics and stability, saving one mask operation process, shortening the manufacturing time, and lowering down the manufacturing cost. | 2017-05-18 |
20170141237 | FIELD-EFFECT TRANSISTOR, DISPLAY ELEMENT, DISPLAY, SYSTEM, AND METHOD OF MANUFACTURING FIELD-EFFECTIVE TRANSISTOR - A field-effect transistor includes a gate electrode, a source electrode and a drain electrode to take out electric current according to an application of a voltage to the gate electrode, a semiconductor layer disposed adjacent to the source electrode and the drain electrode, the semiconductor layer forming a channel between the source electrode and the drain electrode, a first insulating layer as gate insulating film disposed between the semiconductor layer and the gate electrode, and a second insulating layer covering at least a part of a surface of the semiconductor layer, the second insulating layer including an oxide including silicon and alkaline earth metal. | 2017-05-18 |
20170141238 | ESL TFT SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides an ESL TFT substrate structure and a manufacturing method thereof. In the ESL TFT substrate structure, an etch stop layer ( | 2017-05-18 |
20170141239 | NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS - Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires. | 2017-05-18 |
20170141240 | OXIDE SEMICONDUCTOR SUBSTRATE AND SCHOTTKY BARRIER DIODE - A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component. | 2017-05-18 |
20170141241 | Optical Device - Disclosed are optical devices and methods of manufacturing optical devices. An optical device can include a substrate; an optical emitter chip affixed to the front surface of the substrate; and an optical sensor chip affixed to the front surface of the substrate. The optical sensor chip can include a main sensor and a reference sensor. The optical device can include an opaque dam separating the main optical sensor and the reference sensor. The optical device can include a first transparent encapsulation block encapsulating the optical emitter chip and the reference optical sensor and a second transparent encapsulation block encapsulating the main optical sensor. The optical device can include an opaque encapsulation material encapsulating the first transparent encapsulation block and the second transparent encapsulation block with a first opening above the main optical sensor and a second opening above the optical emitter chip. | 2017-05-18 |
20170141242 | ANTI-REFLECTIVE AND ANTI-SOILING COATINGS WITH SELF-CLEANING PROPERTIES - Disclosed herein is a method of forming a glass coating including making a sol by hydrolyzing an organosilane in the presence of a least one solvent and at least one catalyst, further adding at least one alkoxysilane, and aging the sol for at least 24 hours. | 2017-05-18 |
20170141243 | PHOTODETECTOR - A photodetector including a substrate, a light absorption layer arranged over the substrate, the light absorption layer including a stack including a semiconductor layer that absorbs light of a wavelength having an electric field vector parallel to a normal direction of a substrate surface, a lower contact layer arranged on a first side of the light absorption layer, a lower electrode contacting with the lower contact layer, an upper contact layer arranged on a second side of the light absorption layer, and an upper electrode contacting with the upper contact layer. An uneven structure including polarization-selective shapes of projections or depressions on the second side of the upper contact layer is provided, the shapes of projections or depressions each having a size of a wavelength or less of incident light in the semiconductor layer and half the wavelength or greater and being periodically arranged in at least one direction. | 2017-05-18 |
20170141244 | METHODS FOR TREATING A POLYCARBONATE GLASS SURFACE AND FORMING DIRECTED HIERARCHICAL NANOPATTERNING AND INCREASING HYDROPHOBICITY - A method of treating a polycarbonate glass surface, such as a bisphenol A polycarbonate, whereby the glass surface is immersed in a liquid phase polar aprotic solvent, such as dichloromethane, and exposed to a vapor phase polar aprotic solvent, such as acetone thus obtaining a textured glass surface with a hierarchical patterned nanoporous structure wherein the textured glass surface has a higher surface hydrophobicity and a marginally reduced optical light transmittance relative to the polycarbonate glass surface prior to the immersion, the exposure, or both. | 2017-05-18 |
20170141245 | CONDUCTIVE PASTE COMPOSITION AND SEMICONDUCTOR DEVICES MADE THEREWITH - A conductive paste composition contains a source of an electrically conductive metal, a first oxide component comprising an alkali metal vanadium oxide composition, an optional second non-oxide, non-metal component, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the paste composition on a semiconductor device substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and establish electrical contact between it and the substrate. | 2017-05-18 |
20170141246 | TITANIUM OXIDE HAVING HEXAGONAL COLUMN SHAPE, METHOD OF FABRICATING THE SAME, SOLAR CELL INCLUDING THE SAME, AND METHOD OF FABRICATING SOLAR CELL INCLUDING THE SAME - A method of fabricating titanium oxide having a hexagonal column shape is provided. The fabricating method includes preparing a first mixture solution containing oxalic acid and sodium dodecylbenzenesulfonate (SDBS), and adding a second mixture solution including titanium to the first mixture solution to fabricate titanium oxide having a hexagonal column shape. | 2017-05-18 |
20170141247 | COMPOSITION FOR FORMING SOLAR CELL ELECTRODES AND ELECTRODES FABRICATED USING THE SAME - The present invention relates to a composition for forming solar cell electrodes which includes a conductive powder, a glass frit and an organic vehicle, and has a tackiness of about 60% to about 90% represented by Expression 1. | 2017-05-18 |
20170141248 | ORGANIC VEHICLE FOR ELECTROCONDUCTIVE PASTE - An organic vehicle comprising at least about 0.5 wt % and no more than about 45 wt % of at least one of a natural essential oil, based upon 100% total weight of the organic vehicle, at least about 0.5 wt % and no more than about 10 wt % of at least one resin, an organic solvent, and a thixotropic agent is provided. The invention also provides a solar cell and a method of forming a solar cell with the electroconductive paste of the invention. | 2017-05-18 |
20170141249 | A SILVER PASTE CONTAINING ORGANOBISMUTH COMPOUNDS AND ITS USE IN SOLAR CELLS - The present invention is directed to a silver paste for a silicon solar cell comprising an organobismuth additive and a solar cell having a silicon wafer with the silver paste on its front-side surface. The resultant cell exhibits improved efficiency. | 2017-05-18 |
20170141250 | METHOD OF FORMING CHALCOGEN COMPOUND LIGHT-ABSORPTION LAYER THIN FILM FOR SOLAR CELL - Disclosed is a method of forming a chalcogen compound thin film suitable for use in a light-absorption layer of a solar cell. The method includes manufacturing a precursor liquid including an Sn precursor material and an S precursor material, applying the precursor liquid to form a precursor film, and heat-treating the precursor film. The Sn precursor material and the S precursor material are liquid materials. The present invention provides a method of forming a chalcogen compound thin film using a liquid precursor material without a sulfurization process, thereby forming a high-quality SnS thin film at low cost using a process which is suitable for mass production. Further, the light-absorption layer is formed using a process which is suitable for mass production, thus enabling the manufacture of a solar cell including the chalcogen compound thin film at low cost. | 2017-05-18 |
20170141251 | MONO-BACKSHEET FOR SOLAR CELL MODULES - The current invention relates to a solar-cell module backing monolayer obtained by melt-extruding a polymer composition comprising (a) a polyamide, (b) an elastomer and (c) an elastomer that contains groups that bond chemically and/or interact physically with the polyamide, and wherein the elastomer constitutes the continuous phase of the polymer composition and the polyamide constitutes the dispersed phase of the polymer composition, characterized in that the polymer composition comprises from 10 to 50 wt. % of the polyamide (a) and from 50 to 90 wt. % of the elastomer (b) and (c) (of the total weight of polyamide (a) and elastomer (b) and (c) present in the polymer composition). | 2017-05-18 |
20170141252 | SOLAR CELL PANEL, AND APPARATUS AND METHOD FOR ATTACHING INTERCONNECTOR OF SOLAR CELL PANEL - Disclosed is a method for attaching an interconnector of a solar cell panel, including moving the interconnector, unwound from a winding roll, in a processing direction, and attaching the interconnector to a solar cell. In the moving, the interconnector, which is wound around the winding roll, is unwound so as to pass through one end of the winding roll in a longitudinal direction. | 2017-05-18 |
20170141253 | SOLAR CELL MODULE AND SOLAR CELL MODULE PRODUCTION METHOD - This solar module has: a base member that is curved in the vertical direction and the horizontal direction; strings each constituted from a plurality of solar cells and first wiring members connecting adjacent solar cells in the vertical direction, wherein a plurality of the strings are arranged side by side on the base member; and a string group constituted from a plurality of the strings and second wiring members, which are disposed at both sides in the vertical direction of the strings and connected to the first wiring members, thereby connecting adjacent strings to one another in the horizontal direction. The string group is divided into at least two blocks that are side by side in the vertical direction. Second wiring members are disposed adjacent in the horizontal direction, or second wiring members are disposed adjacent in the vertical direction between the blocks, and are secured to one another. | 2017-05-18 |
20170141254 | PASSIVATED CONTACT FORMATION USING ION IMPLANTATION - Methods for forming passivated contacts include implanting compound-forming ions into a substrate to about a first depth below a surface of the substrate, and implanting dopant ions into the substrate to about a second depth below the surface. The second depth may be shallower than the first depth. The methods also include annealing the substrate. | 2017-05-18 |
20170141255 | BLISTER-FREE POLYCRYSTALLINE SILICON FOR SOLAR CELLS - Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer. | 2017-05-18 |
20170141256 | MULTI-JUNCTION OPTOELECTRONIC DEVICE WITH GROUP IV SEMICONDUCTOR AS A BOTTOM JUNCTION - A multi-junction optoelectronic device and method of manufacture are disclosed. The method comprises providing a first p-n structure on a substrate, wherein the first p-n structure comprises a first base layer of a first semiconductor with a first bandgap such that a lattice constant of the first semiconductor matches a lattice constant of the substrate, and wherein the first semiconductor comprises a Group III-V semiconductor. The method includes providing a second p-n structure, wherein the second p-n structure comprises a second base layer of a second semiconductor with a second bandgap, wherein a lattice constant of the second semiconductor matches a lattice constant of the first semiconductor, and wherein the second semiconductor comprises a Group IV semiconductor. The method also includes lifting off the substrate the multi-junction optoelectronic device having the first p-n structure and the second p-n structure, wherein the multi-junction optoelectronic device is a flexible device. | 2017-05-18 |
20170141257 | SEMICONDUCTOR PACKAGE STRUCTURES AND METHOD OF MANUFACTURING THE SAME - An optical device includes a substrate, a light emitter, a light detector, a conductive structure, and an opaque material. The light emitter, the light detector and the conductive structure are disposed on a surface of the substrate and are electrically connected to traces on the surface of the substrate. The light emitter includes an emitting area facing the substrate. The light detector includes a receiving area facing the substrate. The light emitter emits light within a range of wavelengths, and the substrate passes the light emitted by the light emitter. The opaque material is disposed on the substrate, and absorbs or attenuates the light within the range of wavelengths. | 2017-05-18 |
20170141258 | METHODS FOR MANUFACTURING PHOTOELECTROSYNTHETICALLY ACTIVE HETEROSTRUCTURES - A photoelectrosynthetically active heterostructure (PAH) is manufactured by forming or providing cavities in an electrically insulating material; forming or providing an electrically conductive layer on a side of the electrically insulating material; depositing an electrocatalyst cathode layer in the cavities; depositing one or more layers of light-absorbing semiconductor material in the cavities; depositing an electrocatalyst anode layer in the cavities; removing the layer of electrically conductive metal; and forming a hydrogen permeable layer over the electrocatalyst cathode layer. The one or more layers of light-absorbing semiconductor material can form a p-n junction or Schottky junction. The PAH can be used in photoelectrosynthetic processes to produce desired products, such as reduction product (e.g., methane gas, methanol, or carbon monoxide) from carbon dioxide and liquid waste streams. | 2017-05-18 |
20170141259 | NITRIDE SEMICONDUCTOR WAFER AND MANUFACTURING METHOD THEREOF - Provided is a nitride semiconductor wafer in which, above a nitride semiconductor template having a nitride semiconductor layer as a top layer thereof, a light emitting layer having a multiple quantum well structure that is formed by a regrown nitride semiconductor and a p-type nitride semiconductor layer are stacked. Here, when the light emitting layer having a multiple quantum well structure includes a plurality of well layers and one of the well layers that is the closest to the p-type nitride semiconductor layer is referred to as a top well layer, a distance t from a regrowth interface of the nitride semiconductor layer of the nitride semiconductor template to the top well layer is 1 μm or less, and the top well layer has an oxygen concentration of 5.0×10 | 2017-05-18 |
20170141260 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias. | 2017-05-18 |
20170141261 | Light Emitting Diodes and Fabrication Method - A light emitting diode (LED) includes quantum dots serving as the quantum well layer in the multiple-quantum well (MQW) structure, which can greatly improve the combination efficiency of electrons and holes due to quantum confinement effect; a nanoscale metal reflective layer is formed between the quantum barrier layer with nanoscale pits to instantly reflect the light emitted downwards from the MQW to the front of epitaxial structure; in addition, the nanoscale metal reflective layer can form surface plasmon to further improve light emitting efficiency. | 2017-05-18 |
20170141262 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device including an N-type semiconductor layer, a P-type semiconductor layer, a light emitting layer and a strain relief layer is provided. The light emitting layer is disposed between the N-type semiconductor layer and the P-type semiconductor layer, and the light emitting layer is a multiple quantum well structure. The strain relief layer is disposed between the light emitting layer and the N-type semiconductor layer, and is made of In | 2017-05-18 |
20170141263 | ULTRAVIOLET LIGHT-EMITTING DIODE - The present invention relates to an ultraviolet light-emitting diode (LED), which includes a gradual superlattice layer. The gradual superlattice layer comprises a first superlattice layer and a second superlattice layer. The first superlattice layer includes a multi-layer structure having repetitive stacks of a unit formed by a first layer and a second layer. The second superlattice layer includes a multi-layer structure having repetitive stacks of a unit formed by a third layer and a fourth layer. The concentrations of aluminum in the first, second, third, and fourth layers decrease sequentially. By disposing the gradual superlattice layer, the quality of the epitaxial structure may be improved apparently. | 2017-05-18 |
20170141264 | METHOD FOR RANDOMLY TEXTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for texturing a semiconductor substrate ( | 2017-05-18 |
20170141265 | Semiconductor Chip and Method for Producing a Semiconductor Chip - A semiconductor chip and a method for producing a semiconductor chip are disclosed. In an embodiment, the semiconductor chip includes a semiconductor layer sequence and a structured substrate including a surface, wherein the surface is in contact with the semiconductor layer sequence, wherein the surface has a structure of depressions, each depression is delimited at an underside by a smooth end region, or wherein the surface has a structure of elevations, each elevation is delimited at a top side by a smooth end region, and wherein the end regions are laterally spaced apart with respect to one another. | 2017-05-18 |
20170141266 | Patterned Sapphire Substrate and Light Emitting Diode - A patterned sapphire substrate has a first surface and a second surface opposite to each other; the connection zone between first protrusion portions has no C surface (i.e. (0001) surface); and the patterned sapphire substrate may have no C surface on the growth surface to reduce the threading dislocation density of the GaN epitaxial material on the sapphire substrate. | 2017-05-18 |
20170141267 | SEMICONDUCTOR OPTICAL DEVICE - A semiconductor optical device has a multilayer structure | 2017-05-18 |
20170141268 | HIGH-PERFORMANCE LED FABRICATION - High-performance light-emitting diode together with apparatus and method embodiments thereto are disclosed. The light emitting diode devices emit at a wavelength of 390 nm to 470 nm or at a wavelength of 405 nm to 430 nm. Light emitting diode devices are characterized by having a geometric relationship (e.g., aspect ratio) between a lateral dimension of the device and a vertical dimension of the device such that the geometric aspect ratio forms a volumetric light emitting diode that delivers a substantially flat current density across the device (e.g., as measured across a lateral dimension of the active region). The light emitting diode devices are characterized by having a current density in the active region of greater than about 175 Amps/cm | 2017-05-18 |
20170141269 | NITRIDE SEMICONDUCTOR TEMPLATE AND LIGHT EMITTING ELEMENT - A nitride semiconductor template includes a substrate, an AlN layer that is formed on the substrate and that includes Cl, and a nitride semiconductor layer formed on the AlN layer. In the AlN layer, a concentration of the Cl in a region on a side of the substrate is higher than that in a region on a side of the nitride semiconductor layer. Also, a light-emitting element includes the nitride semiconductor template, and a light-emitting layer formed on the nitride semiconductor template. | 2017-05-18 |
20170141270 | SEMICONDUCTOR MULTILAYER STRUCTURE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer. | 2017-05-18 |
20170141271 | LED Structure and Fabrication Method - A light-emitting diode (LED) structure includes a substrate; a first semiconductor layer on the substrate; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; and an electrode on the semiconductor layer composed of a body and an extension body, wherein, the electrode extension portion is in a certain angle with the contacting semiconductor layer and separates the electrode body from the light emitted to its top surface and sides with a semi-wrapping structure. | 2017-05-18 |
20170141272 | FRAME FOR SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a frame for a semiconductor light emitting device to receive a semiconductor light emitting chip, the frame including: a side wall; and a bottom part, which is connected to the side wall and has at least one hole for receiving a semiconductor light emitting chip. | 2017-05-18 |
20170141273 | LIGHT EMITTING DEVICE, RESIN PACKAGE, RESIN-MOLDED BODY, AND METHODS FOR MANUFACTURING LIGHT EMITTING DEVICE, RESIN PACKAGE AND RESIN-MOLDED BODY - A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means or an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part. | 2017-05-18 |
20170141274 | Chip Substrate - A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity. | 2017-05-18 |
20170141275 | SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - A semiconductor light emitting device package is provided and includes a light emitting diode (LED) chip including a first electrode and a second electrode, the LED chip having a first surface on which the first electrode and the second electrode are disposed, and a second surface opposing the first surface; a dam structure disposed on the first surface, an outside edge of the dam structure being co-planar with an outside edge of the LED chip; and a wavelength conversion layer disposed on side surfaces of the LED chip, the second surface of the LED chip, and a surface of the dam structure, the wavelength conversion layer containing a wavelength conversion material. | 2017-05-18 |
20170141276 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a light emitting element and a sealing resin member. The substrate includes a flexible base, a plurality of wiring portions and a groove portion. The groove portion is formed between the plurality of wiring portions spaced apart from each other, and includes a first groove portion, a second groove portion, and a third groove portion extending in a direction intersecting the first and second groove portions. The first and third groove portions are connected to each other with a curve. The second and third groove portions are connected to each other with a curve. The sealing resin member seals the light emitting element and the substrate. The sealing resin member is arranged on the third groove portion and spaced apart from the first groove portion and the second groove portion. | 2017-05-18 |
20170141277 | ASSEMBLING STRUCTURES OF LIGHT EMITTING COMPONENTS - The present invention discloses an assembling structure of light emitting components including a substrate, a light emitting component, and at least one connecting part. The light emitting component is arranged on the substrate, the light emitting component includes a first pin and a second pin embedded within the substrate, and at least one connecting part is embedded within the substrate. The connecting part electrically connects to the substrate. The connecting part connects the first pin and the second pin. Compared to the conventional solution, wherein the pins of the light emitting component and the lead are configured outside of the substrate, the light beams are prevented from being blocked by the components. Not only the light beams may be more uniform, but also the light beams are prevented from being absorbed by the lead. | 2017-05-18 |
20170141278 | LED ASSEMBLY FOR LED PACKAGE WITH SIDEWALL ELECTRODES - The present disclosure provides a novel light-emitting diode assembly comprising a housing and an LED package having sidewall electrodes. The housing comprises sidewalls with contacts that are in electrical connection with electrodes of the LED package. The electrodes of the LED package are substantially exposed along the sidewalls of a resin carrier layer of the LED package. | 2017-05-18 |
20170141279 | Method Of Manufacturing Nano-Scale LED Electrode Assembly Comprising Selective Metal Ohmic Layer - A method of manufacturing a nano-scale LED electrode assembly including a selective metal ohmic layer is disclosed. Specifically, the method can be useful in increasing conductivity between a nano-scale LED device and electrodes and also reducing contact resistance therebetween by depositing a conductive material in a region in which the nano-scale LED device comes in contact with the electrodes so as to improve the contact between the nano-scale LED device and the electrodes, thereby further improving light extraction efficiency of the nano-scale LED device. | 2017-05-18 |
20170141280 | Flip-chip High-voltage Light Emitting Device and Fabrication Method - A flip-chip high-voltage light-emitting device includes: a light emitting module composed of a plurality of flip-chip light emitting units in series with a first surface and a second surface opposite to each other, wherein, gap is formed between flip-chip light emitting units, and each comprises an n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer; a light conversion layer on the first surface of the light emitting module that covers side surfaces of light emitting units; an insulation layer that covers the second surface of the entire light emitting module and is only exposed to the n-type semiconductor layer in the first light emitting unit and the p-type semiconductor layer in the last light emitting unit of the light emitting module; a first support electrode and a second support electrode on the insulation layer. | 2017-05-18 |
20170141281 | Thermoelectric Generator - A thermoelectric generator includes: a heat-receiving plate configured to receive heat; a cooling plate configured to be kept at a lower temperature than a temperature of the heat-receiving plate; and a thermoelectric generation module interposed between the heat-receiving plate and the cooling plate, in which the thermoelectric generation module includes: an opposed surface that is opposed to the cooling plate; a plurality of thermoelectric elements; a terminal configured to electrically conduct to the thermoelectric elements; and a lead member bonded to the terminal, in which the lead member penetrates the opposed surface and extends to the cooling plate. | 2017-05-18 |
20170141282 | Half-Heusler Compounds for Use in Thermoelectric Generators - A thermoelectric generator includes a hot side heat exchanger, a cold side heat exchanger, a plurality of n-type semiconductor legs arranged between the hot side heat exchanger and the cold side heat exchanger, and a plurality of p-type semiconductor legs arranged between the hot side heat exchanger and the cold side heat exchanger and alternating electrically in series with the plurality of n-type semiconductor legs. At least one of the plurality of n-type semiconductor legs and the plurality of p-type semiconductor legs is formed of an alloy having a half-Heusler structure and comprising Si and Sn with molar fractions of x Sn and 1-x Si, and x is less than 1. | 2017-05-18 |
20170141283 | THERMOELECTRIC POLYMER COMPOSITE, METHOD OF MAKING AND USE OF SAME - A thermoelectric composite includes a plurality of particles comprising a crosslinked polymer having a heat deflection temperature greater than or equal to 200° F. and a segregated network comprising a first filler material which is disposed between the particles to produce a thermoelectric response in response to application of a voltage difference or temperature difference across the thermoelectric composite. The first filler material includes a carbon material, a metal, a metal disposed on a carbon material, or a combination thereof. A process for preparing a thermoelectric article includes combining a first filler material and a plurality of particles comprising a polymer to form a composition and molding the composition to form a thermoelectric article, wherein the thermoelectric article is configured to produce a thermoelectric response in response to application of a voltage difference or temperature difference across the article. | 2017-05-18 |
20170141284 | THERMOELECTRIC GENERATOR COMPRISING LIQUID METAL HEAT EXCHANGE UNIT - The present invention relates to a thermoelectric generator comprising a liquid metal heat exchanger, the thermoelectric generator comprising: a thermoelectric element; a power generation unit electrically connected to the thermoelectric element; a liquid metal heat exchange unit, which is connected to the high-temperature side of the thermoelectric element and has a liquid metal flowing therein; and a heat source unit connected to the liquid metal heat exchange unit so as to exchange heat therewith. | 2017-05-18 |
20170141285 | Nanoscale Device Comprising an Elongated Crystalline Nanostructure - The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures. | 2017-05-18 |