20th week of 2016 patent applcation highlights part 57 |
Patent application number | Title | Published |
20160140974 | NOISE FILLING IN MULTICHANNEL AUDIO CODING - In multichannel audio coding, an improved coding efficiency is achieved by the following measure: the noise filling of zero-quantized scale factor bands is performed using noise filling sources other than artificially generated noise or spectral replica. In particular, the coding efficiency in multichannel audio coding may be rendered more efficient by performing the noise filling based on noise generated using spectral lines from a previous frame of, or a different channel of the current frame of, the multichannel audio signal. | 2016-05-19 |
20160140975 | LINEAR PREDICTION ANALYSIS DEVICE, METHOD, PROGRAM, AND STORAGE MEDIUM - An autocorrelation calculation unit | 2016-05-19 |
20160140976 | SPEECH CODING APPARATUS AND METHOD THEREFOR - In a CELP-type speech coding apparatus, switching between an orthogonal search of a fixed codebook and a non-orthogonal search is performed in a practical and effective manner. The CELP-type speech coding apparatus includes a parameter quantizer that selects an adaptive codebook vector and a fixed codebook vector so as to minimize an error between a synthesized speech signal and an input speech signal. The parameter quantizer includes a fixed codebook searcher that switches between the orthogonal fixed codebook search and the non-orthogonal fixed codebook search based on a correlation value between a target vector for the fixed codebook search and the adaptive codebook vector obtained as a result of a synthesis filtering process. | 2016-05-19 |
20160140977 | NOISE CANCELLATION METHOD - An embodiment of the invention provides a noise cancellation method for an electronic device. The method comprises: receiving an audio signal; applying a Fast Fourier Transform operation on the audio signal to generate a sound spectrum; acquiring a first spectrum corresponding to a noise and a second spectrum corresponding to a human voice signal from the sound spectrum; estimating a center frequency according to the first spectrum and the second spectrum; and applying a high pass filtering operation to the sound spectrum according to the center frequency. | 2016-05-19 |
20160140978 | Customizable Local Media Mixing And Stream Selection In Group Communications - Systems, methods, and devices for managing audio streams in a group communication session. A processor of a receiving communication device may send to a transmitting communication device an instruction to adjust a gain of an audio stream of the transmitting communication device via a feedback communication link. A processor of the transmitting communication device may receive the instruction and may adjust the gain of the audio stream responsive to the instruction. The processor of the transmitting communication device may transmit the audio stream using the adjusted gain. | 2016-05-19 |
20160140979 | APPARATUS AND METHOD FOR DECODING AN ENCODED AUDIO SIGNAL USING A CROSS-OVER FILTER AROUND A TRANSITION FREQUENCY - Apparatus for decoding an encoded audio signal including an encoded core signal, including: a core decoder for decoding the encoded core signal to obtain a decoded core signal; a tile generator for generating one or more spectral tiles having frequencies not included in the decoded core signal using a spectral portion of the decoded core signal; and a cross-over filter for spectrally cross-over filtering the decoded core signal and a first frequency tile having frequencies extending from a gap filling frequency to an upper border frequency or for spectrally cross-over filtering a first frequency tile and a second frequency tile. | 2016-05-19 |
20160140980 | APPARATUS FOR DECODING AN ENCODED AUDIO SIGNAL WITH FREQUENCY TILE ADAPTION - Apparatus for decoding an encoded audio signal including an encoded core signal and parametric data, including: a core decoder for decoding the encoded core signal to obtain a decoded core signal; an analyzer for analyzing the decoded core signal before or after performing a frequency regeneration operation to provide an analysis result; and a frequency regenerator for regenerating spectral portions not included in the decoded core signal using a spectral portion of the decoded core signal, the parametric data, and the analysis result. | 2016-05-19 |
20160140981 | APPARATUS AND METHOD FOR DECODING OR ENCODING AN AUDIO SIGNAL USING ENERGY INFORMATION VALUES FOR A RECONSTRUCTION BAND - An apparatus for decoding an encoded audio signal having an encoded representation of a first set of first spectral portions and an encoded representation of parametric data indicating spectral energies for a second set of second spectral portions, has: an audio decoder for decoding the encoded representation of the first set of the first spectral portions to obtain a first set of first spectral portions and for decoding the encoded representation of the parametric data to obtain a decoded parametric data for the second set of second spectral portions indicating, for individual reconstruction bands, individual energies; a frequency regenerator for reconstructing spectral values in a reconstruction band having a second spectral portion using a first spectral portion of the first set of the first spectral portions and an individual energy for the reconstruction band, the reconstruction band having a first spectral portion and the second spectral portion. | 2016-05-19 |
20160140982 | SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD, ENCODER AND ENCODING METHOD, DECODER AND DECODING METHOD, AND PROGRAM - Methods and apparatus for performing signal processing. The signal processing comprises demultiplexing input encoded data into data including information for a segment including frames and coefficient information for a coefficient selected in the frames of the segment, and low band encoded data, decoding the low band encoded data to produce a low band signal, selecting a coefficient of a frame to be processed from a plurality of the coefficients based on the data, calculating a high band sub-band power of a high band sub-band signal of each sub-band constituting a high band signal of the frame to be processed based on a low band sub-band signal of each sub-band constituting the low band signal of the frame to be processed and the selected coefficient, and producing the high band signal of the frame to be processed based on the high band sub-band power and the low band sub-band signal. | 2016-05-19 |
20160140983 | RATE CONVERTOR - Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power. | 2016-05-19 |
20160140984 | PREDICTING INDIVIDUAL OR CROWD BEHAVIOR BASED ON GRAPHICAL TEXT ANALYSIS OF POINT RECORDINGS OF AUDIBLE EXPRESSIONS - Embodiments relate to determining a crowd behavior. A method of determining a crowd behavior is provided. The method collects, at one or more recording points in a crowd of individuals, audible expressions that the individuals of the crowd make. The method generates a graph of the audible expressions as the audible expressions are collected from the individuals. The method determines a crowd behavior by performing a graphical text analysis on the graph. The method outputs an indication of the crowd behavior to trigger a crowd control measure. | 2016-05-19 |
20160140985 | SIMULATION - A simulation method and system. A computing system receives a first audio and/or video data stream. The first audio and/or video data stream includes data associated with a first person. The computing system monitors the first audio and/or video data stream. The computing system identifies emotional attributes comprised by the first audio and/or video data stream. The computing system generates a second audio and/or video data stream associated with the first audio and/or video data stream. The second audio and/or video data stream includes the data without the emotional attributes. The computing system stores the second audio and/or video data stream. | 2016-05-19 |
20160140986 | MONITORING TREATMENT COMPLIANCE USING COMBINED PERFORMANCE INDICATORS - Methods and systems for monitoring compliance of a patient with a prescribed treatment regimen are described. Two or more patient activities (including e.g., speech activity) are analyzed to determine compliance with a treatment for a brain-related disorder. Activity is detected unobtrusively during performance of routine activities with activity sensor(s) at the patient location, patient speech is detected during use of a communication system such as a mobile telephone, and activity data is sent to a monitoring system at a monitoring location. Activity and/or speech data is processed at the patient location or monitoring location to identify activity parameters or patterns that indicate whether the patient has complied with the treatment regimen. Patient identity may be determined through biometric identification or other authentication techniques. The system may provide a report to an interested party, for example a medical care provider or insurance company, regarding patient compliance. | 2016-05-19 |
20160140987 | FLEXIBLE CIRCUIT WITH PARTIAL GROUND PATH - A head assembly for a magnetic tape storage device includes a head and a flexible circuit connected to the head. The flexible circuit includes a gripping portion, an end including electrical contacts for the head, conductors extending from the electrical contacts, and ink patterned onto the electrical contacts and gripping portion to form electrical paths therebetween. The ink conducts electrostatic charge from the electrical contacts and conductors to a grounded user in response to skin of the user contacting the ink. | 2016-05-19 |
20160140988 | METHOD OF MANUFACTURING HEAD SUSPENSION HAVING LOAD BEAM AND FLEXURE ALIGNED WITH LOAD BEAM - A reference block which is machined from a single body of material and is a single block with reference pins integral therewith is configured for use in a method of manufacturing a head suspension by laser-welding the flexure to the load beam at a first welding spot so that a tongue is pressed against a convex portion under predetermined load. The method includes steps of forming, before joining the flexure and load beam together, at least one positioning reference hole in each of the flexure and load beam within a circular range that is defined around the first welding spot with a radius equal to a distance between the first welding spot and the projection, laying the flexure and load beam one on another, inserting the reference pins of the reference pin block into the reference holes, and laser-welding the flexure and load beam to each other at the first welding spot. | 2016-05-19 |
20160140989 | READ ASSEMBLY, DATA STORAGE SYSTEM, AND METHODS OF USING THE SAME - In various embodiments, a read assembly for reading a dual-layered medium may be provided. The dual-layered medium may include a servo layer and a data layer over the servo layer. The read assembly may include a data read head configured to read the data layer. The read assembly may also include a servo read head configured to read the servo layer. | 2016-05-19 |
20160140990 | MAGNETIC DISK DEVICE AND METHOD OF CONTROLLING MAGNETIC DISK DEVICE - According to one embodiment, a method of controlling a magnetic disk device, includes acquiring a retry rate indicating a ratio of the number of retries to the number of seeks for a seek distance selected in a seek operation related to a read operation and a write operation, and adjusting a predicted seek time for the selected seek distance based on the acquired retry rate. | 2016-05-19 |
20160140991 | SELF-ASSEMBLED NANOPARTICLES WITH POLYMERIC AND/OR OLIGOMERIC LIGANDS - In one embodiment, a structure includes: a substrate; and a monolayer of nanoparticles positioned above the substrate, where the nanoparticles are each grafted to one or more oligomers and/or polymers, and where each of the polymers and/or oligomers includes at least a first functional group configured to bind to the nanoparticles. In another embodiment, a structure includes: a substrate; a structured layer positioned above the substrate, the structured layer comprising a plurality of nucleation regions and a plurality of non-nucleation regions; and a crystalline layer positioned above the structured layer, where the plurality of nucleation regions have a pitch in a range between about 5 nm to about 20 nm. | 2016-05-19 |
20160140992 | Magnetic Graphene - A method of making magnetic graphene comprising transferring or growing a graphene film on a substrate, functionalizing the graphene film, hydrogenating the graphene film and forming fully hydrogenated graphene, manipulating the extent of the hydrogen content, and forming areas of magnetic graphene and non-magnetic graphene. A ferromagnetic graphene film comprising film that has a thickness of less than two atom layers thick. | 2016-05-19 |
20160140993 | THERMAL RETENTION STRUCTURE FOR A DATA DEVICE - A data device may have at least a magnetic lamination with a thermal retention structure deposited on a substrate and configured to maintain a predetermined temperature for a predetermined amount of time. Such predetermined temperature and amount of time may allow for the growth of a magnetic layer with a predetermined magnetic anisotropy. | 2016-05-19 |
20160140994 | DIRECTED SELF-ASSEMBLY OF NANOPARTICLES WITH POLYMERIC AND/OR OLIGOMERIC LIGANDS - In one embodiment, a method includes: depositing a plurality of nanoparticles on a substrate; and forming a monolayer of the nanoparticles on the substrate via self-assembly, where each of the nanoparticles comprises a nanoparticle core grafted to one or more oligomers and/or polymers, where each of the polymers and/or oligomers includes at least a first functional group configured to bind to the nanoparticles. In another embodiment, a method includes: depositing a plurality of nanoparticles on a substrate; and forming a monolayer of the nanoparticles on the substrate via self-assembly, where the nanoparticles each comprise a nanoparticle core grafted to one or more oligomers and/or polymers, each of the polymers and/or oligomers including a first terminal functional group configured to bind to the nanoparticles, and an optional second terminal functional group configured to bind to the substrate, where the substrate comprises guiding features configured to direct the self-assembly of the nanoparticles. | 2016-05-19 |
20160140995 | Servo Processor Receiving Photodetector Signals - An optical disk drive and a digital servo method for the optical disk drive includes controlling functions of the optical disk drive with a microprocessor. Low-pass filtered and gain-adjusted versions of photodetector output signals resulting from an illumination of an optical disk are received. Versions of the photodetector signals are digitized to produce digital signals. A focus control signal is determined through at least one servo algorithm executed by a digital signal processor based on a focus error determined from the digital signals. Alternatively, a tracking control signal is determined through at least one servo algorithm executed by the digital signal processor based on a tracking error determined from the digital signals. The digital signal processor has a specialized structure and arrangement for processing digital signals at a higher speed than the microprocessor | 2016-05-19 |
20160140996 | DISK SEPARATOR PLATES AND METHOD OF MAKING DISK SEPARATOR PLATES FOR HARD DISK DRIVES - A hard disk drive with a multiple disk stack normally utilizes disk separator plates near the disk surfaces to reduce wind induced vibrations in the disks and the read/write heads. The manufacturing methods currently used to make these separator plates, metal casting and machining, or injection molded plastic, or extruding and machining, or cold forging tends to be expensive and creates unwanted weight and bulk without the desired precision. Stamping disk separator plates from metal provides exceptional dimensional control at reduced cost, but cannot readily provide the thicknesses required. Stamping and extruding the offsets, or stamping and folding the offsets, is a manufacturing process that provides the required dimensions for the offsets, and dimensional control and reduced cost. | 2016-05-19 |
20160140997 | METHOD AND SYSTEM FOR GENERATING MULTIMEDIA CLIP - A method and a device for generating a multimedia clip from multimedia content without interrupting playback of the multimedia content and with no user inputs or at least minimal user inputs are provided. A multimedia content being currently played is stored in a buffer. A current time or a current frame is designated as an end point of the multimedia clip. A start point of the multimedia clip is either computed or received. The multimedia clip is generated by retrieving from the buffer a portion of the multimedia content between the start point and the end point. | 2016-05-19 |
20160140998 | SMOOTH PLAYING OF VIDEO - A computer-implemented method, including detecting an event associated with an image displayed on a display device within a software application, loading a media player into the software application behind the image, where the media player is configured to play a media file associated with the image, and causing a representation of a frame of the media file to be displayed within the media player instead of the image. | 2016-05-19 |
20160140999 | METHODS, SYSTEMS AND APPARATUSES FOR MULTI-DIRECTIONAL STILL PICTURES AND/OR MULTI-DIRECTIONAL MOTION PICTURES - The disclosure is generally directed to methods, systems and apparatuses for multi-directional still pictures and/or multi-directional motion pictures and their applications on mobile, embedded, and other computing devices and applications. | 2016-05-19 |
20160141000 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND RECORDING MEDIUM - The present invention comprises an input part for inputting image data, a receiving part for receiving production, information relating to production transmitted from another apparatus, a recording part for recording the production information received by the receiving part and image data input by the input part, a detection part for detecting a recording position on a recording medium at an editing point of image data recorded by the recording part, and a transmission part for transmitting information of the recording position detected by the detection part, whereby identification information for identifying image data and voice data is recorded in a recording medium or a recording device, this relieving a burden on a photographer and an editor and facilitating extraction of image data and voice data. | 2016-05-19 |
20160141001 | MEDIA CLIP CREATION AND DISTRIBUTION SYSTEMS, APPARATUS, AND METHODS - Various embodiments for creating media clips are disclosed. In one embodiment, media clips are created by a server in response to receiving a primary media recording of at least a portion of an event from a first content capture device, and activity identification information from a content tagging device, the activity identification information comprising a selection time when an activity indicator was selected by a user in response to an activity that occurred during the event. A processor executes machine-executable instructions stored in memory that causes the server to determine whether the first primary media recording is associated with the event, and create a first media clip from the first primary media recording when the first primary media recording is determined to be associated with the event. | 2016-05-19 |
20160141002 | SYSTEMS AND METHODS FOR MECHANICAL ISOLATION OF INFORMATION HANDLING RESOURCES - In accordance with embodiments of the present disclosure, a system may include a structural member and an isolator/guide. The structural member may define at least a portion of each of two laterally adjacent bays, each bay for receiving a respective modular information handling resource. The isolator/guide may be mechanically coupled to the structural member and include at least one guide pin and a vibrational isolator. The at least one guide pin may be configured to engage with modular information handling resources disposed in each of the two laterally adjacent bays in order to mechanically guide the modular information handling resources during insertion into and removal from the bays. The vibrational isolator may be mechanically coupled between the structural member and the at least one guide pin such that the vibrational isolator provides vibrational isolation between the at least one guide pin and the structural member. | 2016-05-19 |
20160141003 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array disposed on the semiconductor substrate, a capacitor and a control circuit. The memory cell array includes a plurality of memory cells. The control circuit supplies a voltage to the memory cell array. The memory cell array includes a first conductive body disposed in a first region on the semiconductor substrate. The first conductive body extends in a first direction intersecting with a surface of the substrate. The capacitor includes first and second electrodes disposed in a second region different from the first region on the semiconductor substrate. The electrodes each include a second conductive body extending in the first direction. The first conductive body and the second conductive body include an identical material. | 2016-05-19 |
20160141004 | POWER MANAGEMENT IN AN ELECTRONIC SYSTEM THROUGH REDUCING ENERGY USAGE OF A BATTERY AND/OR CONTROLLING AN OUTPUT POWER OF AN AMPLIFIER THEREOF - A method includes automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage of the battery exceeds a recovery trip voltage or exceeds a shutdown trip voltage but is less than the recovery trip voltage and opened whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein. The method also includes rendering a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of a discharge switch following the charging of the capacitor. | 2016-05-19 |
20160141005 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DRIVING THE SAME - Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, Each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal. | 2016-05-19 |
20160141006 | POWER MANAGEMENT IN AN ELECTRONIC SYSTEM THROUGH REDUCING ENERGY USAGE OF A BATTERY AND/OR CONTROLLING AN OUTPUT POWER OF AN AMPLIFIER THEREOF - A method includes configuring a battery and a voltage regulator configured to regulate an output voltage of the battery to supply power to a memory of an electronic circuit also comprising non-memory circuitry. The method also includes switching the supply of power between the battery and the voltage regulator such that: the memory is powered from the battery when the non-memory circuitry is inactive, the memory is powered from a combination of voltage from the battery and the voltage regulator when the memory is about to communicate with the non-memory circuitry during a transition of the non-memory circuitry into an active state thereof, and the memory and the non-memory circuitry are powered from the voltage regulator during the active state of the non-memory circuitry. Thus, minimal current is drawn from the battery while a state of the memory of the electronic circuit is preserved. | 2016-05-19 |
20160141007 | METHOD FOR CONTROLLING AN INTERNAL SUPPLY VOLTAGE BASED ON A CLOCK FREQUENCY OF AN EXTERNAL CLOCK SIGNAL AND A LOOK-UP TABLE - A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal. | 2016-05-19 |
20160141008 | LOW POWER MEMORY DEVICE - A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured. | 2016-05-19 |
20160141009 | SEMICONDUCTOR APPARATUS AND OPERATING METHOD THEREOF - A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data. | 2016-05-19 |
20160141010 | SEMICONDUCTOR MEMORY APPARATUS AND SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes a DBI calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The DBI calculation block performs a DBI calculation and outputs a DBI result signal based on a result of the DBI calculation. The inversion latch block inverts data and outputs the inverted data when a DBI enable signal is enabled. The inverted data selective output block outputs the inverted data as a data inversion signal in response to the DBI result signal and a pipe input signal. The pipe latch block receives the data, which is not inverted, and the inverted data, and outputs one of the data and the inverted data according to the result of the DBI calculation. | 2016-05-19 |
20160141011 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes. | 2016-05-19 |
20160141012 | MANAGING SKEW IN DATA SIGNALS - An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory. | 2016-05-19 |
20160141013 | MANAGING SKEW IN DATA SIGNALS WITH ADJUSTABLE STROBE - An apparatus for controlling memory includes a memory controller, and a data interface that interfaces with and is in data communication with data lines, each having inherent skew. Each data line carries a data signal. The data lines connect the memory controller to the memory. The apparatus also includes data de-skewers, each associated with a corresponding data line, a strobe interface that interfaces with a strobe line that connects the memory controller to the memory and that applies a timing signal to the strobe line, and a strobe de-skewer connected to the strobe line. Each data de-skewer operates in read or write mode. A particular data line's data de-skewer applies a compensation skew to a data signal carried by that line. | 2016-05-19 |
20160141014 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip. | 2016-05-19 |
20160141015 | MEMORY DEVICE INCLUDING POWER-UP CONTROL CIRCUIT, AND MEMORY SYSTEM HAVING THE SAME - A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level. | 2016-05-19 |
20160141016 | CONTROLLED MULTI-STEP DE-ALIGNMENT OF CLOCKS - An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals. | 2016-05-19 |
20160141017 | CONTROLLED DYNAMIC DE-ALIGNMENT OF CLOCKS - A controller includes first and second functional units, first and second clock-signal sources that provide corresponding first and second clock signals that drive the first and second functional units respectively. The second clock-signal generates its second clock-signal based on the first clock-signal. The clock-retardation unit dynamically causes the second clock-signal to have a target time-domain offset relative to the first clock-signal. | 2016-05-19 |
20160141018 | MANAGING SKEW IN DATA SIGNALS WITH MULTIPLE MODES - A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing the first data signal by a first compensation skew, causing the data de-skewer to operate in a reading mode, at the data de-skewer, receiving a second signal, and skewing the second signal by a second compensation skew, wherein the first signal is representative of a bit from a byte that is to be written to the memory, and wherein the second signal is representative of a bit from a byte that has been read from the memory. | 2016-05-19 |
20160141019 | MULTI-PORT MEMORY CELL - A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value. | 2016-05-19 |
20160141020 | STATIC RANDOM ACCESS MEMORY FREE FROM WRITE DISTURB AND TESTING METHOD THEREOF - A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively. The row decoder is arranged to assert one of the memory cell rows according to a row address. The plurality of word-line drivers are each coupled to the row decoder and one of the memory cell rows. The arbiter is arranged to prevent multiple memory cells at a same word-line from being accessed at a same time. | 2016-05-19 |
20160141021 | SHARED GLOBAL READ AND WRITE WORD LINES - An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer. | 2016-05-19 |
20160141022 | APPARATUS FOR REDUCING WRITE MINIMUM SUPPLY VOLTAGE FOR MEMORY - Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation. | 2016-05-19 |
20160141023 | MEMORY DEVICE - Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell. | 2016-05-19 |
20160141024 | NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ - This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal | 2016-05-19 |
20160141025 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data. | 2016-05-19 |
20160141026 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a memory device including memory blocks, each of the memory blocks including pages, each of the pages including memory cells that are electrically coupled to word lines, wherein the memory cells store data that is requested from a host; and a controller suitable for reading first data corresponding to a read command received from the host, from a page of a first memory block among the memory blocks, storing the first data in a buffer, providing the first data stored in the buffer, to the host, and writing and storing the first data stored in the buffer, in a page of a second memory block among the memory blocks. | 2016-05-19 |
20160141027 | RESISTANCE VARIABLE MEMORY APPARATUS, READ CIRCUIT UNIT AND OPERATION METHOD THEREFOR - A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code by repeating a cyclic analog-to-digital conversion (ADC) process a designated number of times, generate read data from the digital code, and output the generated read data during a normal read mode for the memory cell array, and to generate test data corresponding to the cell current and output the generated test data during a test read mode for the memory cell to array. | 2016-05-19 |
20160141028 | REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS - Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing. | 2016-05-19 |
20160141029 | HEALTH DATA ASSOCIATED WITH A RESISTANCE-BASED MEMORY - A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path. | 2016-05-19 |
20160141030 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has at least one memory cell using a resistance variable element, and a control circuit which controls writing to and reading from the memory cell. Operations by the control circuit include a first writing operation, a second writing operation, and a rewriting operation. The first writing operation is a writing operation for applying a first voltage of a first polarity to the memory cell. The second writing operation is a writing operation for applying a second voltage of a second polarity opposite to the first polarity to the memory cell. The rewriting operation is a writing operation for, when the first writing operation fails, further executing a second A writing operation for applying the second voltage of the second polarity to the memory cell and a first A writing operation for applying the first voltage of the first polarity to the memory cell. | 2016-05-19 |
20160141031 | NON-VOLATILE REGISTER FILE INCLUDING MEMORY CELLS HAVING CONDUCTIVE OXIDE MEMORY ELEMENT - Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction. | 2016-05-19 |
20160141032 | EEPROM ARCHITECTURE WHEREIN EACH BIT IS FORMED BY TWO SERIALLY CONNECTED CELLS - An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors. | 2016-05-19 |
20160141033 | MEMORY SYSTEM AND ASSEMBLING METHOD OF MEMORY SYSTEM - According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information. | 2016-05-19 |
20160141034 | Transistor Design For Use In Advanced Nanometer Flash Memory Devices - Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed. | 2016-05-19 |
20160141035 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The device may include a memory cell array including a plurality of memory blocks and a peripheral circuit configured for selecting one of the plurality of memory blocks and performing a program operation on selected memory cells of the selected memory block when the program operation is performed. The peripheral circuit may be configured to float a plurality of source select lines and a plurality of drain select lines of an unselected memory block of the plurality of memory blocks when the program operation is performed. | 2016-05-19 |
20160141036 | NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD - A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells. | 2016-05-19 |
20160141037 | SEMICONDUCTOR MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory system includes: programming LSB data into a memory cell of a selected word line included in a memory block; storing MSB data to be programmed into the memory cell of the selected word line, from a controller into a page buffer; reading the programmed LSB data from the memory cell of the selected word line; performing an ECC operation on the read LSB data when a difference between a reference amount and an amount of bit line current, which flows through bit lines included in the memory block, does not fall in a predetermined range from a first current amount to a second current amount; and programming the MSB data stored in the page buffer into the memory cell of the selected word line based on the ECC-corrected LSB data. | 2016-05-19 |
20160141038 | SEMICONDUCTOR DEVICE - A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages, and an operation circuit suitable for outputting operating voltages to local lines of the memory blocks to perform a program loop, an erase loop and a read operation on the plurality of memory cells, wherein the operation circuit is suitable for applying a dummy pulse having a positive potential to the local lines after the program loop or the erase loop is completed. | 2016-05-19 |
20160141039 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, which restrains a breakdown of a low-voltage transistor constructing a bit line selecting circuit, is provided. An NAND string unit and transistors (BLSe, BLso, BIASe, BIASo) that construct bit line selecting circuit are formed in a P-well. The transistors are set in a floating state during erasing operation. The voltages of the transistors are increased when an erasing voltage is applied to the P-well. When the erasing voltage is discharged from the P-well, the gates of the transistors are connected to a reference potential via a discharging circuit ( | 2016-05-19 |
20160141040 | METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE - A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal | 2016-05-19 |
20160141041 | Partial Erase of Nonvolatile Memory Blocks - Erasing blocks of a nonvolatile memory may include two erase steps. A first erase step brings the memory cells of a block to an intermediate state between their programmed states and an erased state. The block is then maintained with the memory cells in the intermediate state for a period of time. Subsequently, a second erase step on the block brings the memory cells from the intermediate state to the erased state | 2016-05-19 |
20160141042 | CONFIGURATION PARAMETER MANAGEMENT FOR NON-VOLATILE DATA STORAGE - Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage differences in one or more storage characteristics for blocks of a non-volatile memory medium within one or more established limits. A block classification module is configured to group blocks of a non-volatile memory medium based on one or more other storage characteristics. A configuration parameter module is configured to use a configuration parameter for at least one group of blocks based on a grouping. A configuration parameter update module is configured to update a configuration parameter for at least one group in response to a change in one or more managed storage characteristics. | 2016-05-19 |
20160141043 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device may include a memory block including memory strings connected to respective bit lines coupled to a substrate and commonly connected to a common source line coupled to the substrate. The semiconductor device may include an operation circuit configured to perform an operation on memory cells included in the memory strings. The bit lines may be classified into a plurality of groups. The operation circuit may be configured to apply a voltage to bit lines of a selected group and set the common source line to a voltage level for the operation. | 2016-05-19 |
20160141044 | CONFIGURATION PARAMETER MANAGEMENT USING A CONFIGURATION TOOL - Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. An initialization module is configured to initialize a value for a configuration parameter for a set of cells of a non-volatile memory medium. The initialization module may initialize the configuration parameter value based on a predetermined model for the set of cells. An update module is configured to adjust the configuration parameter using an existing function of the non-volatile memory medium. The existing function may use the initialized value to adjust the configuration parameter. The update module may adjust the configuration parameter in response to a trigger. An access module is configured to access the set of storage cells using the adjusted configuration parameter. | 2016-05-19 |
20160141045 | NONVOLATILE MEMORY DEVICE, ERASE METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - An erase method of a nonvolatile memory device including a plurality of cell strings on a substrate is provided. Each string includes a plurality of memory cells stacked in a direction perpendicular to the substrate, a ground select transistor between the memory cells and the substrate, and string select transistors between the memory cells and a bit line. The erase method includes applying a precharge voltage during a first time to a first string select line, floating the first string select line during a second time after the first time, and applying an erase voltage to the substrate after the first time. The first string select line is connected to the string select transistors at a first height in the cell strings of a same row | 2016-05-19 |
20160141046 | Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory - Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read. | 2016-05-19 |
20160141047 | Boundary Word Line Operation in Nonvolatile Memory - One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block. | 2016-05-19 |
20160141048 | BACKGROUND THRESHOLD VOLTAGE SHIFTING USING BASE AND DELTA THRESHOLD VOLTAGE SHIFT VALUES IN NON-VOLATILE MEMORY - In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS | 2016-05-19 |
20160141049 | ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME - An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor. | 2016-05-19 |
20160141050 | Processor Having a Programmable Function Unit - A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic. | 2016-05-19 |
20160141051 | SHIFT REGISTER - A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal. | 2016-05-19 |
20160141052 | ELECTRONIC MEMORY DEVICE AND TEST METHOD OF SUCH A DEVICE - The electronic memory device comprises a non-volatile memory matrix organized in rows and columns, an address decoder with address input lines for selecting a row according to a particular address given on the address input lines. Additional address mask input lines are provided, each address mask input line being assigned to an address input line, wherein an address mask input line in activated state has the effect of ignoring the assigned address input line. The method for testing said electronic memory device is performed with a significant lower number of read/write operations, since by ignoring a particular address line a plurality of write operations can be performed simultaneously. | 2016-05-19 |
20160141053 | SUPERSONIC MOLECULAR BEAM INJECTING DEVICE - This device includes a molecular beam valve, a cold/hot precipitator and a magnetic shielding cylinder, wherein molecular beam valve is nested in cold/hot precipitator and precipitator is nested in magnetic shielding cylinder and molecular beam valve is fixed on flange connected to vacuum chamber of a fusion device, outlet of molecular beam valve has a lengthened Laval nozzle. The device solves technical problem that plasma feeding efficiency of existing supersonic gas injector is below 20% during operation of a high-performance Tokamak high confinement mode and constraint is poor; and an effect of applying device to existing large-scale superconducting Tokamak has shown: feeding efficiency reaches 40%; and a function of triggering a low constraint mode converted to a high constraint mode; and a function of mitigating instability of an edge localized mode, so heating load on wall surfaces of fusion device is reduced by 50%, thereby maintaining normal H-mode operation. | 2016-05-19 |
20160141054 | IN-VESSEL AND EX-VESSEL MELT COOLING SYSTEM AND METHOD HAVING THE CORE CATCHER - The present invention relates to the in-vessel and ex-vessel melt cooling system having the core catcher. This system includes a reactor vessel having the core inside of the vessel, a core catcher that can cool the core melt ejecting from the damaged reactor vessel, a reactor cavity including the reactor vessel and the core catcher, IRWST (In-Containment Refueling Water Storage Tank) that can supply cooling water to the reactor cavity, and a control unit that can cut out the cooling water supply when the reactor cavity is filled with cooling water to the required level. | 2016-05-19 |
20160141055 | PIT GATE, PIT EQUIPMENT, NUCLEAR POWER FACILITY, AND INSTALLATION METHOD OF PIT GATE - A pit gate | 2016-05-19 |
20160141056 | Passive Nuclear Reactor Emergency Cooling System Using Compressed Gas Energy and Coolant Storage Outside Nuclear Plant - A passive safety system for a nuclear power plant ( | 2016-05-19 |
20160141057 | Excavation and Weld Repair Methodology for Pressurized Water Reactor Piping and Vessel Nozzles - The invention is an innovative design/repair methodology for PWR piping nozzles and vessel nozzles that are attached to the piping/vessel base material with a full penetration weld joint geometry. The development of a robust repair methodology for nozzles of this configuration is necessary due to plant aging, potential material degradation in the original materials of construction, potential increased nondestructive examination requirements, and PWSCC phenomena in the susceptible original materials of construction. The purpose/objective of the repair methodology is to provide a means of partially replacing the existing pressure boundary susceptible materials with PWSCC-resistant materials to facilitate the long-term repair life of the plant. The invention may be applied to a plurality of nozzle, piping, and vessel sizes with a full penetration weld joint. | 2016-05-19 |
20160141058 | APPARATUS AND METHOD FOR REMOVAL OF NUCLIDES FROM HIGH LEVEL LIQUID WASTES - A method for treating a liquid waste is provided. The method includes supplying the liquid waste to a plurality of cross flow filters from at least one high level waste tank; filtering the liquid waste via the plurality of cross flow filters to form a clarified salt solution; removing at least one radionuclide from the clarified salt solution via a plurality of elutable ion exchange columns filled with an ion exchange media to form an eluate and a decontaminated salt solution; and removing at least one radionuclide from the eluate via a first non-elutable adsorption component to form a dewatered radionuclide sorbent and a decontaminated eluate solution. | 2016-05-19 |
20160141059 | METHOD AND PLANT FOR THE WET-ROUTE OXIDATION TREATMENT OF HAZARDOUS ORGANIC WASTE, NOTABLY RADIOACTIVE WASTE, CONTAINING MINERAL FILLERS - A method and plant for wet-route oxidation treatment of hazardous organic waste products, notably radioactive wastes, which may contain mineral fillers, the waste products being treated in a secure environment. The plant comprises a closed space, with a mechanism for bringing a volume of hazardous organic waste products containing mineral fillers, adding a given quantity of water mixed with a base to the predetermined volume in order to adjust the pH to a determined value so as to make a solution and/or a liquid suspension, with a pressure reactor and with mechanism for transferring the solution and/or liquid suspension into the pressure reactor, and a device for introducing an oxygen atmosphere into the pressure reactor and for pressurizing the atmosphere. A heating mechanism is provided for subjecting the contents of the pressure reactor to heat treatment at a temperature between 150 and 350° C. to complete the wet-route oxidation. | 2016-05-19 |
20160141060 | SYSTEM AND METHOD FOR VITRIFICATION OF WASTE - A method for vitrifying waste to prevent the formation of molybdate secondary phases includes forming a feed mixture that includes the waste, a source of vanadium, and at least one of glass frit or glass forming chemicals and vitrifying the feed mixture in a melter to produce a glass product that includes the waste. | 2016-05-19 |
20160141061 | SYSTEM AND METHOD FOR PRODUCING TECHNETIUM-99M USING EXISTING PET CYCLOTRONS - The present invention relates generally to a system and method for producing Technetium-99m. More specifically, the present invention relates to a novel method and device for modifying commercially-available, widely-used low energy positron emission tomography (PET) cyclotrons in order to produce Technetium-99m in a more efficient, less expensive manner that previously known. | 2016-05-19 |
20160141062 | TARGET BODY FOR AN ISOTOPE PRODUCTION SYSTEM AND METHOD OF USING THE SAME - In accordance with one exemplary embodiment, a target body of a target system for an isotope production system is disclosed. The target body includes a target chamber having a first chamber with a first surface area and a second chamber with a second surface area greater than the first surface area. The first chamber is configured to hold a liquid target medium for bombardment by a charged particle beam. A component is coupled to the target body and configured to generate a radioactivity. | 2016-05-19 |
20160141063 | LASER COOLING VIA STIMULATED PHOTON EMISSIONS - An example laser cooling system may include a first laser to induce a transition of a plurality of electrons in a medium to an excited energy state via absorption of photons. The laser cooling system may also include a second laser to stimulate emission from the medium of emitted photons having a higher energy than an energy of the absorbed photons. | 2016-05-19 |
20160141064 | RADIATION SOURCE CONTAINER - A source container for a radiation source includes a vessel having an external wall defining a space within which is located a shield formed from a radiation absorbing material and defining a cavity for receiving a radiation source, the shield including a window extending from the cavity through the radiation absorbing material, and at least two shutters, each shutter being movable between a closed position in which the shutter covers the window and an open position in which the shutter does not cover the window. The provision of two or more shutters provides a way to emit radiation of different intensities from the same source and container. | 2016-05-19 |
20160141065 | POROUS SUBSTRATE ELECTRODE BODY AND METHOD FOR PRODUCING SAME - The object of the present invention is to provide an electrode member with the hydrogel substrate, capable of producing a high-voltage pulse. Further, the other object of the present invention is to provide an electrode member which is not broken due to a deformation of the hydrogel. The object can be solved by a porous substrate electrode member characterized in that an electrode is bound to a porous body by an adhesion layer of an electrically conducting polymer, and the electrode is at least one selected from a group consisting of a metallic electrode, a stretch electrode, a carbon electrode, and a composite electrode thereof. | 2016-05-19 |
20160141066 | GLASS FRIT, AND CONDUCTIVE PASTE COMPOSITION AND SOLAR CELL COMPRISING THE SAME - The present invention relates to a glass frit, a conductive paste composition comprising the glass frit, and a solar cell fabricated using the conductive paste composition. The glass frit of the present invention comprises SiO | 2016-05-19 |
20160141067 | ELECTRICALLY CONDUCTIVE THIN FILMS - An electrically conductive thin film including: a material including a compound represented by Chemical Formula 1 and having a layered crystal structure, | 2016-05-19 |
20160141068 | PASTE FOR FORMING SOLAR CELL ELECTRODE AND ELECTRODE PREPARED USING THE SAME - A paste for solar cell electrodes includes a conductive powder, a glass frit, and an organic vehicle. The glass frit includes bismuth (Bi), tellurium (Te), and antimony (Sb), and has a mole ratio of bismuth (Bi) to tellurium (Te) of about 1:1 to about 1:30. | 2016-05-19 |
20160141069 | ELECTROCONDUCTIVE POLYPROPYLENE RESIN FOAMED PARTICLES AND ELECTROCONDUCTIVE POLYPROPYLENE RESIN IN-MOLD FOAM MOLDED ARTICLE HAVING EXCELLENT FLAME RETARDANCY AND ELECTRIC CONDUCTIVITY - From electroconductive polypropylene resin foamed particles produced by foaming electroconductive polypropylene resin particles including an electroconductive polypropylene resin composition that contains 11 parts by weight or more and 25 parts by weight or less of an electroconductive carbon black relative to 100 parts by weight of a polypropylene resin and has a melt index of 1.0 g/10 min or more and 4.0 g/10 min or less where the melt index is determined at a load of 5,000 g at 230±0.2° C., a polypropylene resin in-mold foam molded article having excellent electric conductivity and also having higher flame retardancy without any flame retardant can be obtained. | 2016-05-19 |
20160141070 | HYBRID CABLE, METHOD FOR ITS MANUFACTURE AND USE OF SUCH A HYBRID CABLE - An electric lead contains at least three conductors. Each of conductors has a line which is surrounded by a conductor sheath. Two of the conductors are embodied as signal conductors, and form, with a common partial lead sheath surrounding them, a first partial lead, in particular a signal lead. Another of the conductors is embodied as a power conductor and forms a second partial lead, in particular a power lead. The conductors are surrounded by a separating sleeve, which is in turn surrounded by a common sheath of the electric lead. The lead is characterized in that the partial lead sheath has an inner sheath section and an outer sheath section, and the outer sheath section is harder than the inner sheath section. | 2016-05-19 |
20160141071 | COAXIAL CABLE AND MEDICAL CABLE USING SAME - A coaxial cable includes a central conductor, and an electrical insulator formed around a circumference of the central conductor. The electrical insulator is made of an electrical insulating tape wrapped and overlapped around the circumference of the central conductor. The electrical insulating tape includes a plurality of voids formed on one outer circumferential surface. | 2016-05-19 |
20160141072 | ELECTRIC WIRE AND CABLE - An electric wire includes a conductor having a cross-sectional area of not less than 225 mm | 2016-05-19 |
20160141073 | ELECTRIC WIRE AND CABLE - An electric wire includes a conductor having a cross-sectional area of not less than 290 mm | 2016-05-19 |