20th week of 2016 patent applcation highlights part 60 |
Patent application number | Title | Published |
20160141274 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors. | 2016-05-19 |
20160141275 | SEMICONDUCTOR POWER MODULE USING DISCRETE SEMICONDUCTOR COMPONENTS - An electronic power module is disclosed. The module includes a baseplate and a plurality of internally isolated discrete electronic devices mounted to the baseplate such that their electrical leads are oriented away from the baseplate. Electrical leads may be coupled to a printed circuit board (PCB). Other features disclosed include a thermal interface material and an application-specific heat sink. The assembly may be overmolded via injection molding or potted using an encapsulant. Example electronic devices include thyristors, diodes, and transistors. | 2016-05-19 |
20160141276 | LIGHT-EMITTING STRUCTURE FOR PROVIDING PREDETERMINED WHITENESS - A light-emitting structure for providing a predetermined whiteness includes a substrate and a light-emitting unit. The light-emitting unit includes a plurality of first and second light-emitting groups disposed on the substrate. Each first light-emitting group includes a plurality of first LED chips having a first predetermined wavelength. Each second light-emitting group includes a plurality of second LED chips having a second predetermined wavelength. When surface areas of the first and the second LED chips are substantially the same or currents passing through the first and the second LED chips are substantially the same in advance, the light-emitting structure can provide a predetermined whiteness according to different requirements by adjusting the current ratio or the surface area ratio of the first and the second LED chips, respectively. | 2016-05-19 |
20160141277 | ARRANGEMENT AND METHOD FOR GENERATING MIXED LIGHT - The invention relates to an arrangement for generating mixed light, which comprises three semiconductor chips, emitting in the blue spectral range, of three devices. Arranged in the light paths of the individual semiconductor chips are different conversion elements which are configured to convert primary radiation into secondary radiation. The total radiation (S1, S2, S3) exiting the respective devices ( | 2016-05-19 |
20160141278 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of pads. The micro light emitting chips are disposed on the substrate in dispersion. Each of the micro light emitting chips includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer. The conductive bumps are disposed corresponding to the micro light emitting chips and located between the micro light emitting chips and the substrate. The micro light emitting chips are electrically connected to the pads of the substrate by the conductive bumps. An orthogonal projection area of each of the conductive bumps on the substrate is greater than an orthogonal projection area of each of the micro light emitting chips on the substrate. | 2016-05-19 |
20160141279 | METHODS FOR PERFORMING EXTENDED WAFER-LEVEL PACKAGING (eWLP) AND eWLP DEVICES MADE BY THE METHODS - Embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies and methods of making them are provided. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations. | 2016-05-19 |
20160141280 | Device-Embedded Image Sensor, And Wafer-Level Method For Fabricating Same - A device-embedded image sensor includes an image sensor formed in a first semiconductor substrate; a top conductive pad formed on a top surface of the first semiconductor substrate; and a semiconductor device formed in a second semiconductor substrate bonded to a bottom surface of the first semiconductor substrate, the semiconductor device electrically connected to the top conductive pad. A method for fabricating a device-embedded image sensor from a CMOS image sensor wafer assembly that includes an image sensor and a conductive pad. The method includes exposing the conductive pad; forming an isolation layer; exposing a surface of each conductive pad; forming a patterned redistribution layer (RDL) having a plurality of RDL elements on the isolation layer; electrically isolating adjacent RDL elements; and laminating the CMOS image sensor wafer assembly and a semiconductor device wafer to form undiced device-embedded image sensors. | 2016-05-19 |
20160141281 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING EMBEDDED SEMICONDUCTOR ELEMENTS - A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement. | 2016-05-19 |
20160141282 | METHOD OF FABRICATING MULTI-SUBSTRATE SEMICONDUCTOR DEVICES - A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern. | 2016-05-19 |
20160141283 | INTEGRATED THINFILM RESISTOR AND MIM CAPACITOR WITH A LOW SERIAL RESISTANCE - An electronic device comprising a semiconductor structure having a back end capacitor and a back end thin film resistor and a method of manufacturing the same. The semiconductor structure includes a first dielectric layer, a bottom plate of the capacitor and a thin film resistor body. The bottom plate and the resistor body are laterally spaced apart portions of the same thin film layer. The bottom plate further includes a conductive layer overlying the thin film layer. A second dielectric layer is disposed on the conductive layer of the bottom plate of the capacitor. A top plate of the capacitor is disposed on the second dielectric layer. | 2016-05-19 |
20160141284 | SEMICONDUCTOR DEVICE - A transistor ( | 2016-05-19 |
20160141285 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. In addition, the ESD protection device further includes a first doping region formed in a portion of the at least one portion of the semiconductor substrate separating the pair of first well regions, having a second conductivity type opposite to the first conductivity type. Moreover, the ESD protection device further includes a pair of second doping regions respectively formed in one of the first well regions, having the first conductivity type, and a pair of insulating layers respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the second doping regions. | 2016-05-19 |
20160141286 | Carrier For An Optoelectronic Semiconductor Chip And Optoelectronic Component - A carrier ( | 2016-05-19 |
20160141287 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT, STRUCTURE AND METHOD OF MAKING THE SAME - An ESD structure, including a first conductive type substrate, a second conductive type well region in the substrate, first/second doped regions (the first type), fourth to sixth doped regions (second conductive type), and first/second gates, is provided. The first/second doped regions are respectively disposed in the well region and the substrate. The first/second gates are on the substrate surface with no well region below. A third doped region is between the first and second gates in the substrate. The fourth doped region is in the substrate and on one side of the first/second gates. The fifth doped region is in the substrate, extends into the well region, and on another side of the first/second gates. The first doped region is located between the fifth and sixth doped region. The first/sixth doped regions and the first gate are connected. The fourth/second doped region and the second gate are connected. | 2016-05-19 |
20160141288 | FIN SHAPE STRUCTURE - A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer. | 2016-05-19 |
20160141289 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET. | 2016-05-19 |
20160141290 | METHOD OF FORMING A MEMORY CAPACITOR STRUCTURE USING A SELF-ASSEMBLY PATTERN - A capacitor structure and method of forming thereof on a substrate is described. The capacitor structure includes a substrate having a plurality of capacitor electrodes formed within an insulative retaining material, and a collar layer structure in contact with the plurality of capacitor electrodes, wherein the collar layer structure interconnects the plurality of capacitor electrodes and exposes the underlying insulative retaining material through openings having an unguided, random self-assembly pattern. Furthermore, the insulative retaining material may be removed from the capacitor structure. The method includes using a self-assembly process to form the interconnecting collar layer structure. | 2016-05-19 |
20160141291 | METAL SEGMENTS AS LANDING PADS AND LOCAL INTERCONNECTS IN AN IC DEVICE - Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer. | 2016-05-19 |
20160141292 | CMOS Gate Stack Structures and Processes - A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface. | 2016-05-19 |
20160141293 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a memory cell; and a peripheral transistor. The memory cell includes a first channel, a first insulating film provided on the first channel, a charge storage film provided on the first insulating film, a second insulating film provided on the charge storage film, a first semiconductor film provided on the second insulating film, and a first electrode film provided on the first semiconductor film and containing a metal. The peripheral transistor includes a second channel, a third insulating film provided on the second channel, a second semiconductor film provided on the third insulating film, a fourth insulating film provided on the second semiconductor film, a third semiconductor film provided on the second semiconductor film and a side surface of the fourth insulating film, and a second electrode film. | 2016-05-19 |
20160141294 | THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF - A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material. | 2016-05-19 |
20160141295 | ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMMING AND READING A MEMORY ARRAY COMPRISING THE SAME - A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure. | 2016-05-19 |
20160141296 | RELIABLE NON-VOLATILE MEMORY DEVICE - Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memoir), cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D) region for adjacent first and second memory cells. An erase gate is formed over the common S/D region. | 2016-05-19 |
20160141297 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device includes one or more interconnects insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects. | 2016-05-19 |
20160141298 | STI RECESS METHOD TO EMBED NVM MEMORY IN HKMG REPLACEMENT GATE TECHNOLOGY - The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon. | 2016-05-19 |
20160141299 | VERTICAL AND 3D MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A memory device is described, which includes a block of memory cells comprising a plurality of stacks of horizontal active lines such as NAND string channel lines, with a plurality of vertical slices penetrated by, and surrounding, the horizontal active lines to provide a gate-all-around structure. A memory film is disposed between the horizontal active lines in the plurality of stacks and the vertical slices in the plurality of vertical slices. A 3D, horizontal channel, gate-all-around NAND flash memory is provided. A method for manufacturing a memory involves a buttress process. The buttress process enables horizontal channel, gate-all-around structures. | 2016-05-19 |
20160141300 | THREE-DIMENSIONAL MEMORY AND METHOD FOR MANUFACTURING THE SAME - A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping. | 2016-05-19 |
20160141301 | THREE DIMENSIONAL NON-VOLATILE MEMORY WITH SEPARATE SOURCE LINES - A three dimensional stacked non-volatile memory device comprises alternating dielectric layers and conductive layers in a stack, a plurality of bit lines below the stack, and a plurality of source lines above the stack. There is a separate source line for each bit line. Each source lines is connected to a different subset of NAND strings. Each bit line is connected to a different subset of NAND strings. Multiple data states are verified concurrently. Reading is performed sequentially for the data states. The data states are programmed concurrently with memory cells being programmed to lower data states having their programming slowed by applying appropriate source line voltages and bit line voltages. | 2016-05-19 |
20160141302 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups. | 2016-05-19 |
20160141303 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit. | 2016-05-19 |
20160141304 | METHOD TO MATCH SOI TRANSISTORS USING A LOCAL HEATER ELEMENT - An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. | 2016-05-19 |
20160141305 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - An array substrate comprises a TFT, a data line, a gate line and a passivation layer covering the TFT, the data line and the gate line. The array substrate further includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is disposed on the passivation layer and above the TFT, and the second conductive structure is disposed on the passivation layer and above the data line and/or gate line. A method for manufacturing the array substrate and a display device having such an array substrate are also provided. | 2016-05-19 |
20160141306 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE THEREOR AND DISPLAY DEVICE - The present disclosure provides a method for manufacturing an array substrate, an array substrate and a display device. The method includes: forming a gate line, a gate electrode and an insulating layer which covers the gate line and the gate electrode on a first surface of a substrate; forming a semiconductive film on the insulating layer; patterning the semiconductive film using the gate electrode and the gate line as a mask, so as to form an source semiconductive layer at a region where the gate line and the gate electrode are located; and manufacturing a target semiconductive layer using the source semiconductive layer. | 2016-05-19 |
20160141307 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A method of manufacturing an array substrate includes applying a first color filter and a second color filter over a first and second pixel regions respectively and the color filters have an overlapped portion in wiring region; and forming a contact hole, which partially exposes the drain electrode therethrough, by etching at least one of the overlapping first and the second color filters, and the forming the contact hole includes selectively etching an upper part of the overlapped portion during etching a photoresist layer covering the overlapped portion, the overlapped portion of first and second color filters is etched without requiring an additional masking process, preventing a decrease of liquid crystal margin due to large height difference of the overlapped color filters, preventing misalignment of color filters and mixing of colors. | 2016-05-19 |
20160141308 | DISPLAY DEVICE - By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included. | 2016-05-19 |
20160141309 | DISPLAY DEVICE AND ELECTRONIC DEVICE - An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed. | 2016-05-19 |
20160141310 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes a base substrate, an active pattern disposed on the base substrate, a gate insulation pattern disposed on the active pattern, a gate electrode disposed on the gate insulation pattern and overlapping the channel, and a light-blocking pattern disposed between the base substrate and the active pattern and having a size greater than the active pattern. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. | 2016-05-19 |
20160141311 | THIN FILM TRANSISTOR AND A MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND A MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of the array substrate includes depositing an amorphous silicon thin film layer on a base substrate; performing a patterning process on the amorphous silicon thin film layer, so as to form a pattern with multiple small pores at a surface of the amorphous silicon thin film layer. With this method, when a laser annealing treatment of amorphous silicon is performed, the molten silicon after melting fills the space of small pores at a surface of the amorphous silicon thin film layer firstly, thereby avoiding forming a protruded grain boundary that is produced because the excess volume of polysilicon is squeezed. | 2016-05-19 |
20160141312 | DISPLAY DEVICE - A display device includes: a pixel electrode; a switching element that is connected to the pixel electrode and charges the pixel electrode; a reference potential terminal set at a reference potential; and a resistive element that is connected to the pixel electrode and the reference potential terminal so as to be interposed therebetween, the resistive element forming a resistance component against electric charges moving between the pixel electrode and the reference potential terminal. | 2016-05-19 |
20160141313 | METHOD FOR MANUFACTURING FLEXIBLE DISPLAY DEVICE - Disclosed is a method for manufacturing a flexible display device. The method includes: providing a substrate, the substrate having a first surface and the second surface opposite to each other; forming a first flexible substrate on the first surface of the substrate and forming the second flexible substrate on the second surface of the substrate in such a way that a force acting from the first flexible substrate to the substrate is equal to, but in opposite direction, a force acting from the second substrate to the substrate; forming a displaying component on a surface of the first flexible substrate that is distant from the substrate; and peeling the first flexible substrate on which the displaying component is formed off the substrate so as to form a flexible display device. The flexible display device manufactured with the method has an enhanced quality. | 2016-05-19 |
20160141314 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, MANUFACTURING METHOD AND DISPLAY DEVICE - A thin film transistor array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes a substrate and a plurality of pixel units arranged on the substrate, each of which includes a display zone and a non-display zone including a thin film transistor and a black matrix that are provided on the substrate, wherein the black matrix is disposed between the substrate and the thin film transistor. | 2016-05-19 |
20160141315 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A display device according to an embodiment includes a plurality of driving blocks including a plurality of gate lines and a gate shorting structure spaced apart from the gate lines by an amount equal to a trimming region; an equipotential line extending from one of the driving blocks to an adjacent driving block, part of which is removed by the amount equal to the trimming region; a gate dummy line extending from at least one of the driving blocks; a plurality of data lines intersecting the gate lines; and an active layer disposed between the gate dummy line and the data lines, wherein some part of the active layer that overlaps the gate dummy line but does not overlap the data lines is removed. | 2016-05-19 |
20160141316 | Low Full-Well Capacity Image Sensor with High Sensitivity - Image sensor pixels having low full-well capacity and high sensitivity for applications such as DIS, qDIS, single/multi bit QIS. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate. Image sensor may also comprise an array of pixels, wherein each pixel comprises: a vertical bipolar structure including an emitter, base, collector configured for storing photocarriers in the base; and a reset transistor coupled to the base, configured to be completely reset of all free carriers using the reset transistor. The emitter may be configured as a pinning layer to facilitate full depletion of the base. Such image sensor pixels may have a full well capacity less than that giving good signal-to-noise ratio (SNR). | 2016-05-19 |
20160141317 | PIXEL ISOLATION REGIONS FORMED WITH DOPED EPITAXIAL LAYER - An image sensor may include isolation regions that are formed in between photodiodes. These isolation regions may prevent cross-talk and improve the performance of the image sensor. The isolation regions may be made of epitaxial silicon. The epitaxial silicon may be grown in trenches formed in a substrate using an etching process. Portions of the substrate may be protected from the etching process with a hard mask layer. Photodiodes may later be implanted in these protected portions of the substrate after the isolation regions have been formed. The epitaxial silicon may be boron-doped or antimony-doped epitaxial silicon with a concentration of boron or antimony between 10 | 2016-05-19 |
20160141318 | METHOD AND SYSTEM FOR ASSEMBLY OF RADIOLOGICAL IMAGING SENSOR - An imaging sensor having a coupling portion consisting of a plurality of resist portions that act as a light guide to direct light from a fiber optic plate to an imaging die layer. The resist portions can be formed through a photolithographic process to define an air gap between adjacent resist portions. The imaging sensor can further include a scintillator layer that can convert ionizing radiation, such as X-rays and gamma rays used in medical imaging, into optical radiation for detection by the imaging die layer. | 2016-05-19 |
20160141319 | SOLID STATE IMAGING DEVICE - A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential. | 2016-05-19 |
20160141320 | Wafer-Level Encapsulated Semiconductor Device, And Method For Fabricating Same - An encapsulated semiconductor device includes a device die with a semiconductor device fabricated thereon. A carrier layer opposite the device die covers the semiconductor device. A dam supports the carrier layer above the device die, the dam being located therebetween. The semiconductor device further includes a first sealant portion for attaching the dam to the device die, and a means for attaching the dam to the carrier layer. The device die, the dam, and the carrier layer form a sealed cavity enclosing the semiconductor device. | 2016-05-19 |
20160141321 | IMAGE SENSOR - An image sensor includes a sensing layer, a filter unit, and a conductive layer. The filter unit is disposed on the sensing layer. The conductive layer surrounds the filter unit, and is disposed on the sensing layer. Therefore, light passing through the filter unit and falling on an adjacent sensing unit is minimized, and the image quality of the image sensor is improved. | 2016-05-19 |
20160141322 | PHOTODIODES FOR AMBIENT LIGHT SENSING AND PROXIMITY SENSING - Ambient light sensing and proximity sensing is accomplished using pairs of stacked photodiodes. Each pair includes a shallow diode with a shallow junction depth that is more sensitive to light having a shorter wavelength and a deeper diode with a deeper junction depth more sensitive to light with longer wavelengths. Photodiodes receiving light passed through cyan, yellow, and magenta filters and light passed without a color filter are used to generate red, green, and blue information through a subtractive approach. The shallow diodes are used to generate lux values for ambient light and the deeper diodes are used for proximity sensing. One or more of the deep diodes may be used in correction to lux determinations of ambient light. | 2016-05-19 |
20160141323 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus having a sensitivity difference between microlens regions hardly be recognized comprises: a plurality of pixels each of which has a photoelectric conversion portion, an optical element arranged above the photoelectric conversion portion, and a microlens arranged above the optical element, wherein the microlenses of the plurality of pixels include a plurality of microlenses of a first microlens structure arranged in a first microlens region, and a plurality of microlenses of a second microlens structure arranged in a second microlens region, the optical elements of the plurality of pixels include a plurality of optical elements of a first optical element structure arranged in a first optical element region, and a plurality of optical elements of a second optical element structure arranged in a second optical element region, and the first microlens region is arranged above a boundary between the first and second optical element regions. | 2016-05-19 |
20160141324 | SEMICONDUCTOR IMAGE SENSOR MODULE, METHOD FOR MANUFACTURING THE SAME AS WELL AS CAMERA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor image sensor module | 2016-05-19 |
20160141325 | Method and Apparatus for Low Resistance Image Sensor Contact - A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line. | 2016-05-19 |
20160141326 | SOLID-STATE IMAGING DEVICE, DRIVING METHOD THEREFOR, AND ELECTRONIC APPARATUS - A pixel in which both phase difference detection and image generation are performed can be implemented with a more simple structure. Each of a plurality of pixels two-dimensionally arranged in a matrix shape includes a first photoelectric conversion unit and a second photoelectric conversion unit both configured to photoelectrically convert light entering via one micro lens. A first reading circuit reads an electric charge generated at the first photoelectric conversion unit and a second reading circuit reads an electric charge generated at the second photoelectric conversion unit. A transistor connects a first electric charge holding unit included in the first reading circuit to a second electric charge holding unit included in the second reading circuit. The present technology is applicable to, for example, a solid-state imaging device that detects a phase difference. | 2016-05-19 |
20160141327 | CMOS IMAGE SENSOR WITH SIGMA-DELTA TYPE ANALOG-TO-DIGITAL CONVERSION - A CMOS image sensor including a plurality of pixels, each including: a photodiode; a sigma-delta modulator of order p, p being an integer greater than or equal to 1, capable of delivering a binary digital signal representative of the illumination level of the photodiode; and a configurable connection circuit enabling to couple the sigma-delta modulator of the pixel to a sigma-delta modulator of another pixel, so that the modulators of the two pixels form with each other a sigma-delta modulator of order greater than p. | 2016-05-19 |
20160141328 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREFOR, AND IMAGING APPARATUS - A solid-state imaging device includes: a first chip including a pixel array in which a plurality of photoelectric conversion portions converting incident light into an electric signal are disposed; a second chip having an area in a plan view less than an area of the first chip in the plan view and electrically and physically connected to the first chip; and a support portion provided to cover an entire region which is not covered with the second chip in a surface of the first chip connected to the second chip and configured to support the first chip so that flatness of the first chip may be maintained. | 2016-05-19 |
20160141329 | LIGHT ABSORPTION APPARATUS - A light absorption apparatus includes a substrate, a light absorption layer above the substrate on a first selected area, a silicon layer above the light absorption layer, a spacer surrounding at least part of the sidewall of the light absorption layer, an isolation layer surrounding at least part of the spacer, wherein the light absorption apparatus can achieve high bandwidth and low dark current. | 2016-05-19 |
20160141330 | METHOD FOR SEMICONDUCTOR SELECTIVE ETCHING AND BSI IMAGE SENSOR - A method of selectively etching a semiconductor device and manufacturing a BSI image sensor device includes etching a doped silicon substrate with an HNA solution for a predetermined time duration to obtain an etching solution having a concentration C | 2016-05-19 |
20160141331 | LIGHT-EMITTING DIODE - A light-emitting diode is provided. The light-emitting diode comprises: a first light-emitting structure, comprising: a first area; a second area; a first isolation path having an electrode isolation layer between the first area and the second area; an electrode contact layer covering the first area; and an electrical connecting structure covering the second area; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and the electrode contact layer covers a sidewall of the first area. | 2016-05-19 |
20160141332 | EMISSIVE DEVICE INCLUDING FIRST AND SECOND ADJACENT PIXELS SHARING THE SAME SEMICONDUCTOR LIGHT-EMITTING STACK - The emissive device includes first and second adjacent pixels ( | 2016-05-19 |
20160141333 | MAGNETO-ELASTIC NON-VOLATILE MULTIFERROIC LOGIC AND MEMORY WITH ULTRALOW ENERGY DISSIPATION - Memory cells, non-volatile logic gates, and combinations thereof have magneto-tunneling junctions (MTJs) which are switched using potential differences across a piezoelectric layer in elastic contact with a magnetostrictive nanomagnet of an MTJ. One or more pairs of electrodes are arranged about the MTJ for supplying voltage across the piezoelectric layer for switching. A permanent magnetic field may be employed to change the positions of the stable magnetic orientations of the magnetostrictive nanomagnet. Exemplary memory cells and universal non-volatile logic gates show dramatically improved performance characteristics, particularly with respect to energy dissipation and error-resilience, over existing methods and architectures for switching MTJs such as spin transfer torque (STT) techniques. | 2016-05-19 |
20160141334 | MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINE SELECT TRANSISTORS AND METHODS THERFOR - A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors. | 2016-05-19 |
20160141335 | Diamond Like Carbon (DLC) in a Semiconductor Stack as a Selector for Non-Volatile Memory Application - Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a trilayer stack of diamond like carbon/silicon/diamond like carbon. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof. | 2016-05-19 |
20160141336 | Field Effect Transistor Constructions And Memory Arrays - In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative material, and a top source/drain region. The stack has a vertical sidewall with a bottom portion along the bottom source/drain region, a middle portion along the conductive gate, and a top portion along the top source/drain region. Third insulative material is along the middle portion of the vertical sidewall. A channel region material is along the third insulative material. The channel region material is directly against the top and bottom portions of the vertical sidewall. The channel region material has a thickness within a range of from greater than about 3 Å to less than or equal to about 10 Å; and/or has a thickness of from 1 monolayer to 7 monolayers. | 2016-05-19 |
20160141337 | MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES - A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair. | 2016-05-19 |
20160141338 | TANDEM-TYPE ORGANIC LIGHT-EMITTING DIODE AND DISPLAY DEVICE - A tandem-type organic light-emitting diode (OLED) and a display device are provided. The tandem-type OLED includes a substrate, a first electrode, a first light-emitting unit, a charge generate layer, a second light-emitting unit and a second electrode. The first electrode is disposed on the substrate, the first light-emitting unit is disposed on the first electrode, the charge generate layer is disposed on the first light-emitting unit is disposed on the first light-emitting unit, the second light-emitting unit is disposed on the charge generate layer, and the second electrode is disposed on the second light-emitting unit. The charge generate layer includes stacked first electron transport layer and active metal layer. Accordingly, the tandem-type OLED with stable performance is obtained and in favor of mass production. | 2016-05-19 |
20160141339 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate extending along a first direction, the substrate comprising a pixel region having a plurality of pixels and a transparent region that is located adjacent to the pixel region, a lower electrode disposed on the substrate in the pixel region, the lower electrode extending along the first direction, a light emitting layer disposed on the lower electrode, the light emitting layer extending along the first direction, and an upper electrode disposed on the light emitting layer in the pixel region, the upper electrode extending along the first direction. The upper electrode exposes the transparent region. | 2016-05-19 |
20160141340 | ORGANIC EL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic EL display device includes a display area, a measurement area provided outside the display area, an organic layer that is formed in the display area and in the measurement area and includes a light-emitting layer, and a conductive film that is formed on the organic layer in the display area and functions as the upper electrode. The conductive film covers the organic layer in the measurement area. | 2016-05-19 |
20160141341 | DISPLAY DEVICE - A sub-pixel is provided in a display area of an organic EL display device. A bank layer surrounds an outer periphery of the sub-pixel. A contact area is positioned in the display area and is adjacent to the sub-pixel through the bank layer. A pixel electrode is provided in the sub-pixel. A common electrode is disposed across the sub-pixel and the contact area. At least a part of an auxiliary conductive layer is positioned in the contact area. A contact hole is provided in the contact area and electrically connects the common electrode and the auxiliary conductive layer. | 2016-05-19 |
20160141342 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS - An array substrate and a manufacturing method thereof, and a display apparatus are provided. The array substrate may include a base substrate, a scan line, a data line arranged to cross each other on the base substrate, pixel units arranged in a matrix and defined by the scan lines and data lines, wherein a thin film transistor, a pixel electrode and a light emitting structure are disposed in the pixel unit, the pixel electrode is disposed above the layer where the thin film transistor is located, the region covered by the pixel electrode includes a region over the thin film transistor; the light emitting structure is disposed above the layer where the thin film transistor is located, and its covered region corresponds to the region covered by the pixel electrode. | 2016-05-19 |
20160141343 | OLED AND FABRICATION METHOD THEREOF, AND DISPLAY APPARATUS - An OLED and a fabrication method thereof, and a display apparatus are provided. The OLED comprises: a base substrate; a first electrode, an organic functional layer and a transparent or semi-transparent second electrode sequentially disposed on the base substrate; and a covering layer provided on a side of the second electrode away from the base substrate. A surface of the covering layer away from the base substrate is uneven. | 2016-05-19 |
20160141344 | LIGHT-EMITTING ELEMENT DISPLAY DEVICE - A light-emitting element display device includes a substrate, one or a plurality of thin film transistors, a light-emitting element, a first electrode, and a second electrode. The substrate includes an insulating material. The thin film transistors are in each pixel of a display area on the substrate. The light-emitting element emits light by current flow in each pixel. The first electrode is between the substrate and the thin film transistors, and overlaps at least two of the thin film transistors when viewed in plan. The second electrode includes a conducting material, and is arranged across the first electrode from the substrate via an insulating film so as to form a capacitor together with the first electrode. | 2016-05-19 |
20160141345 | Light-Emitting Element and Display Device Using Same - A display device includes a plurality of light-emitting elements aligned on a TFT substrate in a formation of a matrix. The plurality of light-emitting elements each have a flat surface portion and including a light-emitting layer, an anode, and a cathode, an insulating layer formed on the TFT substrate and under the light emitting element, and a tilted metal surface provided on a peripheral area surrounding the flat surface portion of the light-emitting element and having a tilt angle with respect to the flat surface portion of the light-emitting element. The tilted metal surface is provided on a surface of a slope of a bank that is provided on the insulation layer, and a width of a cross-section of the bank becomes smaller as the cross section comes farther away from a surface of the TFT substrate. A counter substrate is placed on the TFT substrate. | 2016-05-19 |
20160141346 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes a substrate, an active layer of a thin film transistor formed over the substrate, a gate insulating layer formed over the active layer, a gate electrode of the thin film transistor formed over the gate insulating layer, an interlayer insulating layer formed over the gate electrode and the first electrode, a source electrode and a drain electrode formed over the interlayer insulating layer, a pixel electrode including a first region in direct contact with an upper surface of the interlayer insulating layer and a second region in direct contact with an upper surface of one of the source electrode and the drain electrode, a pixel defining layer covering the source and drain electrodes and including an opening which exposes the first region of the pixel electrode in an area that does not overlap the thin film transistor. | 2016-05-19 |
20160141347 | Organic Light Emitting Display Device - Disclosed herein is an OLED (Organic Light Emitting Display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (Low Temperature Poly-Silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line. A pixel and another pixel adjacent to the pixel connected to a gate line in common, so that it is possible to provide an OLED device with high aperture ratio and high resolution. | 2016-05-19 |
20160141348 | Organic Light-Emitting Diode Display With Enhanced Aperture Ratio - An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode with an anode and cathode. The anodes may be formed from a patterned layer of metal. Thin-film transistor circuitry in the pixels may include transistors such as drive transistors and switching transistors. Data lines may supply data signals to the pixels and horizontal control lines may supply control signals to the gates of the transistors. A switching transistor may be coupled between a voltage initialization line and each anode. The voltage initialization lines and capacitor structures in the thin-film transistor circuitry may be formed using a layer of metal that is different than the layer of metal that forms the anodes. | 2016-05-19 |
20160141349 | ORGANIC LIGHT-EMITTING DIODE DISPLAY HAVING HIGH APERTURE RATIO AND METHOD FOR MANUFACTURING THE SAME - An organic light-emitting diode display can include a substrate in which an emission area and a non-emission area are defined; a first transparent conductive layer, a light shielding layer, a buffer layer and a semiconductor layer sequentially laminated on the non-emission area; a gate electrode superposed on the center region of the semiconductor layer, having a gate insulating layer interposed therebetween; a drain electrode coming into contact with one side of the semiconductor layer, having an interlevel insulating layer covering the gate electrode interposed therebetween, and formed of a second transparent conductive layer and a metal layer laminated thereon; a first storage capacitor electrode disposed under the interlevel insulating layer in the emission area and formed of the first transparent conductive layer; and a second storage capacitor electrode superposed on the first storage capacitor electrode, having the interlevel insulating layer interposed therebetween, and formed of the second transparent conductive layer. | 2016-05-19 |
20160141350 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line. | 2016-05-19 |
20160141351 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device includes a substrate including a plurality of pixel regions each including a light emitting region and a transparent region, a gate electrode in the light emitting region, a first insulating interlayer covering the gate electrode and extending from the light emitting region to the transparent region, a drain electrode on the first insulating interlayer and constituting a transistor in conjunction with the gate electrode, a planarization layer covering the transistor and exposing a top surface of the first insulating interlayer in the transparent region, and a first electrode on the planarization layer. | 2016-05-19 |
20160141352 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a display panel and a stage block. The display panel includes 4m (m is a natural number) number of horizontal lines in which organic light emitting diodes (OLEDs) are arranged. The stage block provides a scan signal and an emission control signal to each of the horizontal lines. An i (i is a natural number equal to or smaller than m) stage block includes a block signal generating unit, an emission control signal generating unit, and a plurality of scan signal generating units. | 2016-05-19 |
20160141353 | DISPLAY PANEL - A display panel is disclosed. The display panel includes a substrate, a plurality of first unit pixel and a plurality of second unit pixel. The substrate includes a first region and a second region extending in a first direction. The plurality of first unit pixels is disposed in the first region of the substrate. The first unit pixel has a first area. The plurality of second unit pixel is disposed in the second region of the substrate. The second unit pixel has a second area which is smaller than the first area. | 2016-05-19 |
20160141354 | Patterned Back-Barrier for III-Nitride Semiconductor Devices - A compound semiconductor device includes a III-nitride buffer and a III-nitride barrier on the III-nitride buffer. The III-nitride barrier has a different band gap than the III-nitride buffer so that a two-dimensional charge carrier gas channel arises along an interface between the III-nitride buffer and the III-nitride barrier. The compound semiconductor device further includes a source and a drain spaced apart from one another and electrically connected to the two-dimensional charge carrier gas channel, a gate for controlling the two-dimensional charge carrier gas channel between the source and the drain, and a patterned III-nitride back-barrier buried in the III-nitride buffer. The patterned III-nitride back-barrier extends laterally beyond the gate towards the drain and terminates prior to the drain so that the patterned III-nitride back-barrier is laterally spaced apart from the drain by a region of the III-nitride buffer. | 2016-05-19 |
20160141355 | ACTIVE DEVICE AND SEMICONDUCTOR DEVICE WITH THE SAME - A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region. The active device is self-isolated by a conductive guarding structure, and the semiconductor device comprising embodied STI-free active devices solves STI edge issues. | 2016-05-19 |
20160141356 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions. | 2016-05-19 |
20160141357 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and a method of making the same. The device includes a semiconductor substrate including a body region having a first conductivity type. The device also includes an array of interconnected trenches extending into the body region from a surface of the substrate. The device further includes a plurality of channel stoppers. Each channel stopper includes a doped region of the first conductivity type located at a side of one or more of the trenches at a position intermediate a top of the trench and a bottom of the trench. | 2016-05-19 |
20160141358 | APPARATUS AND METHODS FOR TRANSCEIVER INTERFACE OVERVOLTAGE CLAMPING - Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure. Additionally, the clamp device includes a first p-type active region and a first n-type active region in the first p-type well region and electrically connected to a first terminal of the clamp device. Furthermore, the clamp device includes a second p-type active region and a second n-type active region in the second p-type well region and electrically connected to a second terminal of the clamp device. The n-type isolation structure is in a p-type region of a semiconductor substrate, and electrically isolates the first and second p-type well regions from the p-type substrate region. The clamp device further includes a blocking voltage tuning structure positioned between the first and second n-type active regions. | 2016-05-19 |
20160141359 | SEMICONDUCTOR STRUCTURE WITH SILICON OXIDE LAYER HAVING A TOP SURFACE IN THE SHAPE OF CONTINUOUS HILLS AND METHOD OF FABRICATING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a substrate, a silicon oxide layer disposed on the substrate, and at least part of a gate electrode covering the silicon oxide layer. A top surface of the silicon oxide layer is in the shape of plural hills. The silicon oxide layer can provide low on-state resistance for the semiconductor structure. | 2016-05-19 |
20160141360 | III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION - Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer. | 2016-05-19 |
20160141361 | NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN - Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions. | 2016-05-19 |
20160141362 | OUTPUT CAPACITANCE REDUCTION IN POWER TRANSISTORS - Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor. In other examples, a planar area component of a body-drain junction may be reduced by forming a spherical cavity at a bottom portion of the body-drain junction and sealing the cavity with a low dielectric constant material. In further examples, a sealed cavity may be formed in an epitaxial region below the body region through formation and removal of selective buried oxide islands. In yet other examples, the output capacitance may be reduced through removal of areas in the drain region of the transistor that do not contribute to the current flow. | 2016-05-19 |
20160141363 | METHOD OF IMPROVING LATERAL BJT CHARACTERISTICS IN BCD TECHNOLOGY - In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BV | 2016-05-19 |
20160141364 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the MOS gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer. | 2016-05-19 |
20160141365 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 2016-05-19 |
20160141366 | Field Effect Transistors and Methods of Forming Same - Semiconductor devices and methods of forming the same are provided. A first gate stack is formed over a substrate, wherein the first gate stack comprises a first ferroelectric layer. A source/channel/drain stack is formed over the first gate stack, wherein the source/channel/drain stack comprises one or more 2D material layers. A second gate stack is formed over the source/channel/drain stack, wherein the second gate stack comprises a second ferroelectric layer. | 2016-05-19 |
20160141367 | SEMICONDUCTOR DEVICES INCLUDING CHANNEL DOPANT LAYER - A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type. The source/drain regions have a second conductivity type. A concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region. The semiconductor device may be used in a sense amplifier of a memory device. | 2016-05-19 |
20160141368 | TALL STRAINED HIGH PERCENTAGE SILICON-GERMANIUM FINS - The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming one or more tall strained silicon germanium (SiGe) fins on a semiconductor on insulator (SOI) substrate. The fins have a germanium (Ge) concentration which may differ from the Ge concentration within the top layer of the SOI substrate. The difference in Ge concentration between the fins and the top layer of the SOI substrate may range from approximately 10 atomic percent to approximately 40 atomic percent. This Ge concentration differential may be used to tailor a strain on the fins. The strain on the fins may be tailored to increase the critical thickness and allow for a greater height of the fins as compared to conventional strained fins of the same SiGe concentration formed from bulk material. | 2016-05-19 |
20160141369 | SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern. Thus, the examples relate to a semiconductor and manufacture device with even doping, and high breakdown voltage obtainable as a result of such doping. | 2016-05-19 |
20160141370 | HIGH ASPECT RATIO TRAPPING SEMICONDUCTOR WITH UNIFORM HEIGHT AND ISOLATED FROM BULK SUBSTRATE - A semiconductor structure having an isolated device region separated from channel defects formed during Aspect Ratio Trapping (ART). The structure includes: an isolated device region of a semiconductor channel separated from a defect region of a semiconductor channel by a barrier layer, the isolated device region is free of formation defects, the defect region includes formation defects; a substrate directly below the defect region of the semiconductor channel; and a dielectric layer adjacent to the defect region, below the barrier layer, and above the substrate. | 2016-05-19 |
20160141371 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region. | 2016-05-19 |
20160141372 | Ga2O3 SEMICONDUCTOR ELEMENT - Provided is a Ga | 2016-05-19 |
20160141373 | SEMICONDUCTOR DEVICES INCLUDING FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME - A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity. | 2016-05-19 |