20th week of 2022 patent applcation highlights part 66 |
Patent application number | Title | Published |
20220157643 | APPARATUS FOR ROTATING SUBSTRATES - Embodiments of the present disclosure generally relate to apparatus for substrate processing, and more specifically to apparatus for rotating substrates and to uses thereof. In an embodiment, an apparatus for rotating a substrate is provided. The apparatus includes a levitatable rotor comprising a plurality of magnets embedded therein, a plurality of gas bearings positioned to levitate the levitatable rotor, and a stator magnetically coupled to the levitatable rotor, the stator for producing a rotating magnetic field. Apparatus for processing a substrate with the apparatus for rotating substrates as well as methods of use are also described. | 2022-05-19 |
20220157644 | SUBSTRATE SUPPORTING ASSEMBLY AND SUBSTRATE PROCESSING APPARATUS - A substrate supporting assembly includes a susceptor plate including at least one substrate seat, and a plurality of gas flow lines for supplying a lifting gas, an acceleration gas, and a deceleration gas to the substrate seat, and at least one satellite on the at least one substrate seat and including an upper surface, and a lower surface where a rotation pattern for receiving a rotational force and a braking force from the acceleration gas and the deceleration gas is provided. The at least one satellite is lifted from the at least one substrate seat by the lifting gas supplied from the at least one substrate seat, is rotated relative to the susceptor plate by the acceleration gas supplied in a forward direction of rotation, to rotate the substrate, and is decelerated or stopped by the deceleration gas supplied in a reverse direction of rotation. | 2022-05-19 |
20220157645 | SUPPORT UNIT AND APPARATUS FOR TREATING SUBSTRATE - Provided is a support unit for supporting a substrate, the support unit including: a heating member configured to transmit thermal energy to a supported substrate; a reflective plate disposed under the heating member and configured to reflect thermal energy generated by the heating member to the substrate; a cooling plate disposed under the reflective plate and formed with a cooling flow path in which a cooling fluid flows; and a gas supply line configured to supply gas to a space between the reflective plate and the cooling plate. | 2022-05-19 |
20220157646 | MANUFACTURING METHOD OF AIR BRIDGE, AIR BRIDGE AND ELECTRONIC DEVICE - A method for manufacturing an air bridge, an air bridge, and an electronic device are disclosed. The method for manufacturing an air bridge includes: applying a first photoresist layer to a substrate; applying a second photoresist layer to the first photoresist layer; exposing, developing, and fixing the second photoresist layer, to form a patterned structure; etching away the first photoresist layer in a specified area through the patterned structure, to form a structure for blocking a deposition material from diffusing to a periphery on the substrate, the specified area including a projection area formed on the first photoresist layer by a top opening of the patterned structure; and depositing a bridge support structure on a surface of the substrate exposed after the first photoresist layer in the specified area is etched away, and forming an air bridge based on the bridge support structure. | 2022-05-19 |
20220157647 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer. | 2022-05-19 |
20220157648 | METHOD AND EQUIPMENT FOR FORMING GAPS IN A MATERIAL LAYER - An equipment includes a supporter and an etching device. The supporter is configured to support a semiconductor device. The semiconductor device includes an etch stop layer, a material layer, and a mask layer. The mask layer has openings to expose portions of the material layer. The etching device is configured to emit a plurality of directional charged particle beams to etch the exposed portions of the material layer for forming gaps in the material layer, in which the etching device has plural ion extraction apertures to emit the directional charged particle beams. A vertical distance between the semiconductor device and the ion extraction apertures is determined in accordance with a profile of each of the gap, each of the directional charged particle beams has two energy peaks at two angles, and the angles are determined in accordance with a profile of each of the gaps and the vertical distance. | 2022-05-19 |
20220157649 | SOURCE/DRAIN ISOLATION STRUCTURE AND METHODS THEREOF - A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region. | 2022-05-19 |
20220157650 | METHOD FOR TRANSFERRING A USE FUL LAYER TO A CARRIER SUBSTRATE - A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature. | 2022-05-19 |
20220157651 | METHOD FOR TRANSFERRING A USEFUL LAYER ONTO A SUPPORT SUBSTRATE - A method for transferring a useful layer to a carrier substrate, includes the following steps: a) providing a donor substrate including a buried weakened plane; b) providing a carrier substrate; c) joining the donor substrate, by its front face, to the carrier substrate along a bonding interface so as to form a bonded structure; d) annealing the bonded structure in order to apply a weakening thermal budget thereto and to bring the buried weakened plane to a defined level of weakening; and e) initiating a splitting wave in the weakened plane by applying a stress to the bonded structure, the splitting wave self-propagating along the weakened plane to result in the useful layer being transferred to the carrier substrate. The splitting wave is initiated when the bonded structure is subjected to a temperature between 150° C. and 250° C. | 2022-05-19 |
20220157652 | INTERCONNECTS HAVING SPACERS FOR IMPROVED TOP VIA CRITICAL DIMENSION AND OVERLAY TOLERANCE - A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element. | 2022-05-19 |
20220157653 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a source/drain structure formed beside the gate structure. The structure also includes a contact structure formed over the source/drain structure. The structure also includes a dielectric structure extending into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure. | 2022-05-19 |
20220157654 | METAL BASED HYDROGEN BARRIER - A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal. | 2022-05-19 |
20220157655 | ELECTROPLATING WITH TEMPORARY FEATURES - Exemplary methods of electroplating may include forming a first mask layer on a semiconductor substrate. The methods may include forming a seed layer overlying the first mask layer. The methods may include forming a second mask layer overlying the seed layer. The methods may include plating an amount of metal on the semiconductor substrate. A portion of the metal may plate over the first mask layer. | 2022-05-19 |
20220157656 | Semiconductor Device with Reduced Contact Resistance and Methods of Forming the Same - Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer. | 2022-05-19 |
20220157657 | SINGULATING INDIVIDUAL CHIPS FROM WAFERS HAVING SMALL CHIPS AND SMALL SEPARATION CHANNELS - Embodiments of the invention include a method of singulating IC chips from a wafer. The method can include receiving the wafer having a substrate formed under active layers. The wafer includes a chip that includes a first portion of the active layers and a first portion of the substrate. A separation trench is formed by using an etch operation to remove a first segment of the active layers and a first segment of the substrate that are beneath a first separation channel of the wafer. The separation trench separates the first portion of the active layers from a remaining portion of the active layers; and separates the first portion of the substrate from a remaining portion of the substrate. The first IC chip is seperated from the wafer by removing a first section of the remaining portion of the substrate that is underneath the first portion of the substrate. | 2022-05-19 |
20220157658 | WAFER MANUFACTURING METHOD AND LAMINATED DEVICE CHIP MANUFACTURING METHOD - A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole. | 2022-05-19 |
20220157659 | WAFER MANUFACTURING METHOD AND LAMINATED DEVICE CHIP MANUFACTURING METHOD - A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, a support substrate fixing step of fixing the wafer to a support substrate, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region, and fixing the device chip to the support substrate. | 2022-05-19 |
20220157660 | WAFER MANUFACTURING METHOD AND LAMINATED DEVICE CHIP MANUFACTURING METHOD - A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region. | 2022-05-19 |
20220157661 | EPITAXIAL GROWTH AND TRANSFER VIA PATTERNED TWO-DIMENSIONAL (2D) LAYERS - Embodiments including apparatus, systems, and methods for nanofabrication are provided. In one example, a method of manufacturing a semiconductor device includes forming a two-dimensional (2D) layer comprising a 2D material on a first substrate and forming a plurality of holes in the 2D layer to create a patterned 2D layer. The method also includes forming a single-crystalline film on the patterned 2D layer and transferring the single-crystalline film onto a second substrate. | 2022-05-19 |
20220157662 | SCALABLE AND FLEXIBLE ARCHITECTURES FOR INTEGRATED CIRCUIT (IC) DESIGN AND FABRICATION - The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile. | 2022-05-19 |
20220157663 | BOT GROUP MESSAGING USING BOT-SPECIFIC VOICE LIBRARIES - A method includes receiving, by a group messaging service, a message including recorded audio and a first group identifier, and determining that the group includes a bot. The method also includes determining whether the bot is a user bot responsive to a user node in the group or a group bot responsive to each of the one or more user nodes, selecting a bot voice library to process the recorded audio, sending, by the group messaging service, the recorded audio to the determined user bot or group bot, processing the recorded audio to produce enhanced text, performing, by the determined user bot or group bot, one or more designated actions corresponding to one of the recorded audio and the enhanced text, and sending, by the determined user bot or group bot, an audio reply to the group messaging service. | 2022-05-19 |
20220157664 | DEVICES WITH ADJUSTED FIN PROFILE AND METHODS FOR MANUFACTURING DEVICES WITH ADJUSTED FIN PROFILE - A method of manufacturing a semiconductor device includes disposing two or more fins each having an initial fin profile on a substrate. A sacrificial oxide layer is grown on a first fin and a second fin of the two or more fins. The sacrificial oxide layer of the first and second fins is etched to trim the fin and to generate a next fin profile for the first and second fins. The growing and etching is repeated to trim the first and second fins such that the number of repetitions for the first fin and the second fin are different. Gate structures are formed over the two or more fins. | 2022-05-19 |
20220157665 | SEMICONDUCTOR DEVICE WITH FIN END SPACER PLUG AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of fins on a substrate, a fin end spacer plug on an end surface of each of the plurality of fins and a fin liner layer, an insulating layer on the plurality of fins, and a source/drain epitaxial layer in a source/drain recess in each of the plurality of fins. | 2022-05-19 |
20220157666 | HYBRID-CHANNEL NANO-SHEET FETS - Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region. | 2022-05-19 |
20220157667 | WAFER MANUFACTURING METHOD AND LAMINATED DEVICE CHIP MANUFACTURING METHOD - A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole. | 2022-05-19 |
20220157668 | WAFER MANUFACTURING METHOD AND LAMINATED DEVICE CHIP MANUFACTURING METHOD - A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a support substrate fixing step of fixing the wafer to a support substrate, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region, and fixing the device chip to the support substrate. | 2022-05-19 |
20220157669 | WAFER MANUFACTURING METHOD AND LAMINATED DEVICE CHIP MANUFACTURING METHOD - A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region. | 2022-05-19 |
20220157670 | METHOD AND APPARATUS FOR MONITORING OPERATING STATUS OF MACHINE, STORAGE MEDIUM, AND ELECTRONIC DEVICE - The present disclosure belongs to the technical field of semiconductors, and provides a method and apparatus for monitoring an operating status of a machine, a storage medium, and an electronic device. The method includes: monitoring a product fabrication process in real time and obtaining a monitoring data set; extracting abnormal data points of a machine based on the monitoring data set; performing screening on the abnormal data points of the machine and obtaining target abnormal data points; presetting a quantity threshold corresponding to the target abnormal data points; and determining, based on a quantity of the target abnormal data points and the quantity threshold, whether to generate an alarm signal. | 2022-05-19 |
20220157671 | PACKAGED RF POWER DEVICE WITH PCB ROUTING - A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed. | 2022-05-19 |
20220157672 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: an insulating substrate including a circuit pattern; a semiconductor device mounted on the insulating substrate and electrically connected to the circuit pattern; a case storing the insulating substrate and the semiconductor device; and an electrode attached to the case, wherein a tip surface of the electrode is jointed to the circuit pattern with solder, the electrode is brought into contact with and pushed against the circuit pattern by the case, and a projection is provided on the tip surface. | 2022-05-19 |
20220157673 | MODULE-TYPE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING MODULE-TYPE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a first main surface on which a semiconductor chip is mounted, a case adhered to a peripheral edge of the substrate to form a recess in which the semiconductor chip is disposed, a cover disposed in the case with a first gap in a direction parallel to the first main surface between the cover and the case such that a second main surface of the cover faces the first main surface, and a first adhesive layer embedded in the first gap. The first adhesive layer has a first protruding portion and/or a second protruding portion, the first and second protruding portions respectively protruding outside and inside the recess from the first gap while being in contact with the inner walls of the case and respectively a third main surface of the cover opposite to the second main surface, and the second main surface. | 2022-05-19 |
20220157674 | SUBSTRATE STRUCTURE - A substrate structure includes a substrate, a first metal layer, a second metal layer, and a third metal layer. The substrate has a first surface and a second surface opposite to each other and at least one through hole. The first metal layer is disposed on the first surface of the substrate. The second metal layer is disposed on the second surface of the substrate. The third metal layer is disposed on an inner wall of the at least one through hole of the substrate and connects the first metal layer and the second metal layer. The third metal layer and a portion of the first metal layer define at least one containing cavity, and the at least one containing cavity is configured to contain solder to fix the substrate structure onto an external circuit. | 2022-05-19 |
20220157675 | SEMICONDUCTOR MODULE - Provided is a semiconductor module including: an insulating circuit board that includes an insulating board and a conductive circuit pattern provided on an upper surface of the insulating board; a semiconductor chip that is provided above the insulating circuit board; a solder portion that bonds the circuit pattern and the semiconductor chip; and one or more temperature gradient adjustment portions configured to be bonded to the insulating circuit board and have at least one surface disposed to face at least one surface of the solder portion. The insulating circuit board is warped in a first direction. At least one of the temperature gradient adjustment portions is disposed at a place where an amount of warpage of the insulating circuit board in the first direction is smaller than an average amount of warpage of the insulating circuit board in the first direction. | 2022-05-19 |
20220157676 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME - Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers. | 2022-05-19 |
20220157677 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - Provided is a package structure and a method of fabricating the same. The package structure includes a die; a first encapsulant, laterally encapsulating the die; a first redistribution structure, disposed on the first encapsulant and the die; a second encapsulant, disposed on the first redistribution structure; an antenna pattern, embedded in the second encapsulant and electrically connected to the first redistribution structure; and a dielectric layer, covering the antenna pattern, wherein an upper surface of the second encapsulant is exposed by the dielectric layer, and a laser mark is formed within the upper surface of the second encapsulant. | 2022-05-19 |
20220157678 | INTEGRATED CIRCUIT PACKAGES WITH CAVITIES AND METHODS OF MANUFACTURING THE SAME - Integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. The housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. The example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment. | 2022-05-19 |
20220157679 | PACKAGE FOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD - An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs. | 2022-05-19 |
20220157680 | Flexible Package Architecture Concept in Fanout - Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL. | 2022-05-19 |
20220157681 | INTEGRATED CIRCUIT PACKAGE WITH V-SHAPED NOTCH CREEPAGE STRUCTURE - A lead frame includes a die pad and electrical leads. An integrated circuit chip is mounted to the die pad. An encapsulating package has a perimeter defined by first, second, third and fourth sidewalls. The electrical leads extend from the opposed first and second sidewalls of the package. At least one sidewall of the opposed third and fourth sidewalls of the package includes a V-shaped concavity functioning to increase a creepage distance between the electrical leads at the opposed first and second sidewalls. | 2022-05-19 |
20220157682 | PACKAGE WITH ELECTRICALLY INSULATED CARRIER AND AT LEAST ONE STEP ON ENCAPSULANT - A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face. | 2022-05-19 |
20220157683 | INTEGRATED CIRCUIT PACKAGE WITH HEAT SINK AND MANUFACTURING METHOD THEREOF - A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material. | 2022-05-19 |
20220157684 | HERMETICALLY SEALED GLASS ENCLOSURE - A hermetically sealed package includes: a heat-dissipating base substrate configured for dissipating heat from the hermetically sealed package; a cap arranged on the heat-dissipating base substrate, the cap and the heat-dissipating base substrate jointly forming at least a part of the package; at least one functional area hermetically sealed by the package; at least one laser bonding line configured for hermetically sealing the package, the laser bonding line having a height perpendicular to a bonding plane of the laser bonding line. | 2022-05-19 |
20220157685 | FATIGUE FAILURE RESISTANT ELETRONIC PACKAGE - A chip package comprises a chip having a first temperature sensor. The first temperature sensor is configured to measure a first temperature of the chip in a localized area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor. The second temperature sensor is configured to measure a second temperature of the chip carrier in a localized area around the second temperature sensor. The chip carrier further includes a localized heater element located near the second temperature sensor and configured to generate heat in response to a detected difference based on comparison of the first temperature and the second temperature such that the detected difference is adjusted in the localized area around the first temperature sensor. | 2022-05-19 |
20220157686 | MOLDED SEMICONDUCTOR PACKAGE WITH DUAL INTEGRATED HEAT SPREADERS - A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described. | 2022-05-19 |
20220157687 | CIRCUIT SUBSTRATE WITH HEAT DISSIPATION BLOCK AND PACKAGING STRUCTURE HAVING THE SAME - A circuit substrate has an open substrate, a heat-dissipation block, multiple high thermal conductivity members, a first dielectric layer, a second dielectric layer, multiple first heat conductive members, and multiple second heat conductive members. The heat-dissipation block is disposed in the open substrate. Multiple high thermal conductivity members are mounted through the heat-dissipation block. The first dielectric layer exposes a part of one of two surfaces of the heat-dissipation block. The second dielectric layer exposes a part of the other surface of the heat-dissipation block. The first heat conductive members are in contact with the heat-dissipation block exposed from the first dielectric layer. The second heat conductive members are in contact with the part of the heat-dissipation block exposed from the second dielectric layer. Therefore, heat can be transferred quickly via the heat-dissipation block and the high thermal conductivity members to improve heat-dissipating capacity of the circuit substrate. | 2022-05-19 |
20220157688 | DIRECT-COOLING FOR SEMICONDUCTOR DEVICE MODULES - In a general aspect, an apparatus can include a metal layer disposed on a surface of the substrate. The apparatus can also include a recess formed in the metal layer and a cooling fin coupled with the metal layer. A portion of the cooling fin can be disposed within the recess. | 2022-05-19 |
20220157689 | PACKAGE STRUCTURE AND METHOD MANUFACTURING THE SAME - A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side. | 2022-05-19 |
20220157690 | THERMAL INTERCONNECT STRUCTURE FOR THERMAL MANAGEMENT OF ELECTRICAL INTERCONNECT STRUCTURE - In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers. | 2022-05-19 |
20220157691 | DIAMOND-BASED THERMAL COOLING DEVICES METHODS AND MATERIALS - Disclosed are novel diamond-based devices, methods, and materials for use in thermal interface cooling, including a freestanding diamond wafer heat spreader, liquefied diamond thermal interface materials coolant and encapsulated nanocrystalline diamond metal heat spreaders. | 2022-05-19 |
20220157692 | PACKAGE STRUCTURES - A package structure includes a semiconductor package, a thermal conductive gel, a thermal conductive film and a heat spreader. The thermal conductive gel is disposed over the semiconductor package. The thermal conductive film is disposed over the semiconductor package and the thermal conductive gel. A thermal conductivity of the thermal conductive film is different from a thermal conductivity of the thermal conductive gel. The thermal conductive film is surrounded by the heat spreader. | 2022-05-19 |
20220157693 | SYSTEMS INCLUDING A VAPOR CHAMBER AS THE HEAT SPREADING SUBSTRATE OF A POWER DEVICE EMBEDDED IN A PCB AND METHODS OF FORMING THE SAME - Embedded cooling systems and methods of forming the same are disclosed. A system may include a PCB stack comprising a first major substrate opposite a second major substrate, a pre-preg layer disposed between the first and second major substrates, a power device stack embedded within the PCB stack and comprising a substrate, a power device coupled to the substrate of the power device stack, and a vapor chamber embedded within at least the pre-preg layer of the PCB stack and the power device stack being coupled to the vapor chamber. | 2022-05-19 |
20220157694 | MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING - An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer. | 2022-05-19 |
20220157695 | Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices - Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width. | 2022-05-19 |
20220157696 | POWER MODULE PACKAGE BASEPLATE WITH STEP RECESS DESIGN - Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate. | 2022-05-19 |
20220157697 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a bendable portion including one or more wiring layers and insulation layers that are alternately stacked. The insulation layers of the bendable portion include a first insulation layer and a second insulation layer. The first insulation layer is located at an inner bent position of the bendable portion when the bendable portion is bent. The second insulation layer is located at an outer bent position of the bendable portion relative to the first insulation layer when the bendable portion is bent. The first insulation layer has a higher elastic modulus than the second insulation layer. | 2022-05-19 |
20220157698 | FLIPCHIP PACKAGE WITH AN IC HAVING A COVERED CAVITY COMPRISING METAL POSTS - A semiconductor package includes an IC having circuitry configured for at least one function with some nodes connected to bond pads, with first metal posts on the bond pads, and dome support metal posts configured in a ring having a top rim defining an inner cavity with solder on the top rim and extending over an area of the inner cavity for providing a solder dome that covers the inner cavity to provide a covered air cavity over a portion of the circuitry. A leadframe includes a plurality of leads or lead terminals. The IC is flipchip attached with a solder connection to the leadframe so that the first metal posts are attached to the leads or the lead terminals. A mold compound provides encapsulation for the semiconductor package except on at least a bottom side of the leads or lead terminals. | 2022-05-19 |
20220157699 | Electronic Molded Package - Example embodiments relate to an electronic package, to an electronic device comprising such a package, and to a lead frame for manufacturing the electronic package. Some examples may particularly relate to electronic packages in which radiofrequency (RF) circuitry is arranged. According to the example embodiments, a width of the clamping portion is substantially larger than the width of the lead end portion, the width of the clamping portion being chosen such that bending of the inner part and/or body part relative to the outer part during the application of the molding compound was substantially prevented thereby having avoided flash and/or bleed of molding compound onto the inner part. | 2022-05-19 |
20220157700 | TWO SIDED BONDABLE LEAD FRAME - A lead frame includes a first side having a first die attach pad that is bondable to a die, and a second side that has a second die attach pad that is bondable to another die. The lead frame includes multiple leads on the edges of the lead frame to connect the die. As part of a no-leads device, such as a quad flat no leads (QFN) or dual flat no-leads (DFN), one of the die attach pads is used in binding to a die, and the other die attach pad is used for thermal dissipation and mounting to a structure such as printed circuit board (PCB). | 2022-05-19 |
20220157701 | PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS - Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars. | 2022-05-19 |
20220157702 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion. | 2022-05-19 |
20220157703 | PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a package device and a manufacturing method thereof. The package device includes a redistribution layer which includes a first dielectric layer, a conductive layer and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern that includes a first conductive pattern, and the first conductive pattern is formed of the conductive layer. | 2022-05-19 |
20220157704 | ELECTRODE ARRANGEMENT, A NEURAL PROBE, AND A METHOD FOR MANUFACTURING AN ELECTRODE ARRANGEMENT - An electrode arrangement comprises: a semiconductor carrier substrate having a first and a second side surface; a first array of electrodes arranged above the first side surface; a second array of electrodes arranged below the second side surface; an electronic circuitry for processing electrical signals recorded by the electrodes; a connecting layer arranged above the electronic circuitry and providing a first connection between a first point and a second point; a first interconnect for electrically connecting the first point to the electronic circuitry; a second interconnect and a first through-substrate via which electrically connect the second point to the electrode in the second array. | 2022-05-19 |
20220157705 | MIXED PAD SIZE AND PAD DESIGN - Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads. | 2022-05-19 |
20220157706 | HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES - Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch. | 2022-05-19 |
20220157707 | THIN SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A thin semiconductor package includes a die paddle and multiple lead fingers made of a metal substrate. A die paddle electroplating layer and a lead finger electroplating layer are formed on the surface of the die paddle and surfaces of the lead fingers, respectively. A die is provided on the die paddle electroplating layer and is electrically connected to the lead finger electroplating layer. The die paddle, the die and the lead fingers are encapsulated by a molding compound. The lower surfaces of the die paddle and the lead fingers are exposed on the bottom surface of the molding compound. The die paddles and the lead fingers are formed by etching the metal substrate instead without using a lead frame. | 2022-05-19 |
20220157708 | VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC SPACERS - Methods for fabricating an IC structure, e.g., for fabricating a metallization stack portion of an IC structure, as well as related semiconductor devices, are disclosed. An example fabrication method includes splitting metal lines that are supposed to be included at a tight pitch in a single metallization layer into two vertically-stacked layers (hence the term “vertical metal splitting”) by using helmets and wrap-around dielectric spacers. Metal lines split into two such layers may be arranged at a looser pitch in each layer, compared to the pitch at which metal lines of the same size would have to be arranged if there were included in a single layer. Increasing the pitch of metal lines may advantageously allow decreasing the parasitic metal-to-metal capacitance associated with the metallization stack. | 2022-05-19 |
20220157709 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure and method for manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a conductive pillar, a second electronic component, and a conductive through via. The conductive pillar is disposed on the first electronic component and has a first surface facing away from the first electronic component. The second electronic component is disposed on the first electronic component. The conductive through via extends through the second electronic component and has a first surface facing away from the first electronic component. The first surface of the conductive through via and the first surface of the conductive pillar are substantially coplanar. | 2022-05-19 |
20220157710 | TWO 2D CAPPING LAYERS ON INTERCONNECT CONDUCTIVE STRUCTURE TO INCREASE INTERCONNECT STRUCTURE RELIABILITY - In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. A first interconnect conductive structure extends through the first interconnect dielectric layer. A first capping layer is arranged over the first interconnect conductive structure, and a second capping layer is arranged over the first capping layer. The first capping layer includes a first two-dimensional material that is different than a second two-dimensional material of the second capping layer. An etch stop layer is arranged over the first interconnect dielectric layer and the second capping layer. The integrated chip further includes a second interconnect dielectric layer arranged over the etch stop layer and a second interconnect conductive structure extending through the second interconnect dielectric layer and the etch stop layer to contact the first interconnect conductive structure. | 2022-05-19 |
20220157711 | INTERCONNECT STRUCTURE - The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure. | 2022-05-19 |
20220157712 | SEMICONDUCTOR DEVICE WITH CARBON HARD MASK AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer. | 2022-05-19 |
20220157713 | SEMICONDUCTOR DEVICE WITH CARBON HARD MASK AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with a carbon hard mask. The semiconductor device includes a substrate, conductive layers positioned on the substrate, a carbon hard mask layer positioned on the conductive layers, an insulating layer including a lower portion and an upper portion, and a conductive via positioned along the upper portion of the insulating layer and the carbon hard mask layer and positioned on one of the adjacent pair of the conductive layers. The lower portion is positioned along the carbon hard mask layer and positioned between an adjacent pair of the conductive layers, and the upper portion is positioned on the lower portion and on the carbon hard mask layer. | 2022-05-19 |
20220157714 | INTEGRATED CIRCUIT INCLUDING SUPERVIA AND METHOD OF MAKING - A method including depositing a first dielectric layer over a first conductive line. The method further includes forming a first opening in the first dielectric layer. The method further includes filling the first opening with a first conductive material to define a second conductive line. The method further includes depositing a second dielectric layer over the first dielectric layer. The method further includes forming a second opening in the second dielectric layer. The method further includes filling the second opening with a second conductive material to define a third conductive line. The method further includes forming a supervia opening in the first dielectric layer and the second dielectric layer. The method further includes filling the supervia opening with a third conductive material to define a supervia, wherein the supervia directly connects to the first conductive line and the third conductive line. | 2022-05-19 |
20220157715 | DEVICES AND METHODS OF VERTICAL INTEGRATIONS OF SEMICONDUCTOR CHIPS, MAGNETIC CHIPS, AND LEAD FRAMES - Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure. | 2022-05-19 |
20220157716 | SEMICONDUCTOR CIRCUIT FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor component for a memory device is provided. The semiconductor component comprises a first active region extending in a first direction; a second active region extending in the first direction; a first conductive layer disposed across the first active region and the second active region, in a second direction substantially perpendicular to the first direction; a second conductive layer extending in the first direction; and a first conductive via connecting the first conductive layer and the second conductive layer. | 2022-05-19 |
20220157717 | SEMICONDUCTOR DEVICE WITH FUSE AND ANTI-FUSE STRUCTURES AND METHOD FOR FORMING THE SAME - The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure. | 2022-05-19 |
20220157718 | SEMICONDUCTOR DEVICE HAVING FUSE ARRAY AND METHOD OF MAKING THE SAME - A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element. | 2022-05-19 |
20220157719 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. | 2022-05-19 |
20220157720 | Integrated Circuit Interconnect Structures with Air Gaps - Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature. | 2022-05-19 |
20220157721 | Butted Contacts and Methods of Fabricating the Same in Semiconductor Devices - A method of forming a semiconductor structure includes first forming a metal gate (MG) over a semiconductor layer, a gate spacer on a sidewall of the MG, and a source/drain (S/D) feature disposed in the semiconductor layer and adjacent to the MG, forming an S/D contact (MD) over the S/D feature, forming a first ILD layer over the MG and the MD, and subsequently patterning the first ILD layer to form an opening. The method further includes forming a metal layer in the opening, such that the metal layer contacts both the MG and the MD, removing a top portion of the metal layer to form a trench, filling the trench with a dielectric layer, and subsequently forming a second ILD layer over the dielectric layer. | 2022-05-19 |
20220157722 | BURIED POWER RAILS WITH SELF-ALIGNED VIAS TO TRENCH CONTACTS - Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact. | 2022-05-19 |
20220157723 | BACKSIDE POWER DISTRIBUTION NETWORK SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad. | 2022-05-19 |
20220157724 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING OXIDATION-RESISTANT CONTACT STRUCTURES AND METHODS OF MAKING THE SAME - A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures, source-level material layers, and a three-dimensional memory array including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack and comprising a respective vertical semiconductor channel and a respective memory film. A vertically alternating sequence of insulating plates and dielectric material plates is laterally surrounded by the alternating stack. A through-memory-level interconnection via structure vertically extends through each plate within the vertically alternating sequence and contacts a center portion of a top surface of one of the lower-level metal interconnect structures. At least one silicon nitride liner prevents or reduces oxidation of the lower-level metal interconnect structures underneath the through-memory-level interconnection via structure. | 2022-05-19 |
20220157725 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having arcuate horizontal boundaries defining additional horizontal widths varying from the first horizontal width proximate the lower portion to a relatively larger horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described. | 2022-05-19 |
20220157726 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width. | 2022-05-19 |
20220157727 | Structure and Method for Bridge Chip Assembly with Capillary Underfill - A method for fabricating a bridge chip assembly for interconnecting two or more IC dies is provided. Each of the IC dies has a first region including first connections having a first pitch and has a second region including second connections or connection pads having a second pitch, the first pitch being greater than the second pitch. The method includes: attaching a non-conductive underfill film on an upper surface of at least the second region of each of the IC dies; bonding the second connections/connection pads of a first IC die to corresponding first connection pads/connections of a bridge chip; and bonding the second connections/connection pads of a second IC die to the bridge chip. The bridge chip assembly includes the bridge chip bonded with the first and second IC dies, and the non-conductive underfill film disposed between the bridge chip and the IC dies. | 2022-05-19 |
20220157728 | SEMICONDUCTOR MEMORY STACKS CONNECTED TO PROCESSING UNITS AND ASSOCIATED SYSTEMS AND METHODS - A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer. | 2022-05-19 |
20220157729 | SEMICONDUCTOR DEVICE HAVING METAL INTERCONNECTS WITH DIFFERENT THICKNESSES - An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer. | 2022-05-19 |
20220157730 | CONNECTION STRUCTURE EMBEDDED SUBSTRATE - A connection structure embedded substrate includes a printed circuit board including a plurality of first insulating layers, and a plurality of first wiring layers disposed on or between the plurality of first insulating layers; and a connection structure embedded in the printed circuit board, and including a plurality of second insulating layers and a plurality of second wiring layers disposed on or between the plurality of second insulating layers. A lowermost second insulating layer of the plurality of second insulating layers includes an organic insulating material, and is in contact with an upper surface of one of the plurality of first insulating layers. | 2022-05-19 |
20220157731 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements. | 2022-05-19 |
20220157732 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure. | 2022-05-19 |
20220157733 | TOPOLOGICAL SEMI-METAL INTERCONNECTS - Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer. | 2022-05-19 |
20220157734 | SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE PLUGS OF DIFFERENT ASPECT RATIOS AND MANGANESE-CONTAINING LINLING LAYER AND METHOD FOR PREPARING THE SAME - The present disclosure provides a semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer and a method for preparing the same. The semiconductor device structure includes a substrate having a pattern-dense region and a pattern-loose region; a first conductive layer disposed over the substrate; a first dielectric layer disposed over the first conductive layer; a first conductive plug and a second conductive plug disposed in the first dielectric layer; wherein the first conductive plug and the second conductive plus comprises copper (Cu) and are separated from the first dielectric layer by the a first lining layer comprising manganese (Mn); wherein the first conductive plug and the second conductive plug have different aspect ratios. | 2022-05-19 |
20220157735 | COPPER INTERCONNECT CLADDING - An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt. | 2022-05-19 |
20220157736 | SEMICONDUCTOR DEVICE HAVING INTERCONNECTION LINES WITH DIFFERENT LINEWIDTHS AND METAL PATTERNS - A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via. | 2022-05-19 |
20220157737 | THREE DIMENSIONAL INTEGRATED SEMICONDUCTOR ARCHITECTURE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device. | 2022-05-19 |
20220157738 | SEMICONDUCTOR WAFER HAVING AN AUXILIARY STRUCTURE POSITIONED IN A SCRIBE LINE REGION, SEMICONDUCTOR CHIP AND METHOD OF FABRICATING A SEMICONDUCTOR WAFER - In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten. The auxiliary structure does not interact with or affect the active device structure in the component positions. | 2022-05-19 |
20220157739 | Selective EMI Shielding Using Preformed Mask - A semiconductor package has a substrate, a first component disposed over the substrate, an encapsulant deposited over the first component, and a second component disposed over the substrate outside the encapsulant. A metal mask is disposed over the second component. A shielding layer is formed over the semiconductor package. The metal mask after forming the shielding layer. The shielding layer is optionally formed on a contact pad of the substrate while a conic area above the contact pad that extends 40 degrees from vertical remains free of the encapsulant and metal mask while forming the shielding layer. Surfaces of the metal mask and encapsulant oriented toward the contact pad can be sloped. The metal mask can be disposed and removed using a pick-and-place machine. | 2022-05-19 |
20220157740 | PACKAGE STRUCTURES WITH BUILT-IN EMI SHIELDING - The present disclosure relates to thin-form-factor semiconductor packages with integrated electromagnetic interference (“EMI”) shields and methods for forming the same. The packages described herein may be utilized to form high-density semiconductor devices. In certain embodiments, a silicon substrate is laser ablated to include one or more cavities and a plurality of vias surrounding the cavities. One or more semiconductor dies may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. A plurality of conductive interconnections are formed within the vias and may have contact points redistributed to desired surfaces of the die-embedded substrate assembly. Thereafter, an EMI shield is plated onto a surface of the die-embedded substrate assembly and connected to ground by at least one of the one or more conductive interconnections. The die-embedded substrate assembly may then be singulated and/or integrated with another semiconductor device. | 2022-05-19 |
20220157741 | METHOD FOR PRODUCING ELECTRONIC COMPONENT DEVICE AND LAMINATED FILM USED THEREFOR - Disclosed is a method for producing an electronic component, the method including: disposing a plurality of electronic components on an adhesive layer of a composite substrate including a support, a temporary fixing material layer, and the adhesive layer with a connection part in contact with the adhesive layer interposed between the adhesive layer and the electronic components; fixing the plurality of electronic components to the composite substrate by curing the adhesive layer; forming a sealing layer sealing the electronic components; obtaining a sealed structure by peeling off the temporary fixing material layer from the adhesive layer; and a forming a circuit surface by grinding the sealed structure from the adhesive layer side. The plurality of electronic components include an IC chip and a chip-type passive component. The passive component is disposed on the adhesive layer by a method including in the following order: disposing a conductor precursor for pattern formation as the connection part on the adhesive layer; placing the passive component on the conductor precursor; and forming a conductive pattern as the connection part by heating the conductor precursor. | 2022-05-19 |
20220157742 | PACKAGE STRUCTURE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING PACKAGE STRUCTURE - A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion. | 2022-05-19 |