20th week of 2022 patent applcation highlights part 69 |
Patent application number | Title | Published |
20220157943 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS OF THE SAME - A semiconductor substrate includes a drift layer of a first layer formed of a single crystal SiC semiconductor and a buffer layer and a substrate layer of a second layer that is formed of a SiC semiconductor which includes a polycrystalline structure and is formed on the surface of the first layer, in which the second layer ( | 2022-05-19 |
20220157944 | WAFER AND METHOD OF MANUFACTURING WAFER - The wafer having a retardation distribution measured with a light having a wavelength of 520 nm, wherein an average value of the retardation is 38 nm or less, wherein the wafer comprises a micropipe, and wherein a density of the micropipe is 1.5/cm | 2022-05-19 |
20220157945 | SIC EPITAXIAL WAFER, MANUFACTURING APPARATUS OF A SIC EPITAXIAL WAFER, FABRICATION METHOD OF A SIC EPITAXIAL WAFER, AND SEMICONDUCTOR DEVICE - The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with Si | 2022-05-19 |
20220157946 | SEMICONDUCTOR FILM - Provided is a α-Ga | 2022-05-19 |
20220157947 | BLACK PHOSPHORUS-TWO DIMENSIONAL MATERIAL COMPLEX AND METHOD OF MANUFACTURING THE SAME - Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded. | 2022-05-19 |
20220157948 | SEMICONDUCTOR EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - Provided is a method of producing a semiconductor epitaxial wafer having enhanced gettering ability. The method of producing a semiconductor epitaxial wafer includes: a first step of irradiating a surface of a semiconductor wafer with cluster ions containing carbon, hydrogen, and nitrogen as constituent elements to form a modified layer that is located in a surface portion of the semiconductor wafer and contains the constituent elements of the cluster ions as a solid solution; and a second step of forming an epitaxial layer on the modified layer of the semiconductor wafer. | 2022-05-19 |
20220157949 | SEMICONDUCTOR DEVICE HAVING BACKSIDE VIA AND METHOD OF FABRICATING THEREOF - Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure. | 2022-05-19 |
20220157950 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a semiconductor layer, a source electrode and a drain electrode that are disposed on the upper surface of the semiconductor layer, a gate electrode disposed on the upper surface of the semiconductor layer and located between the source electrode and the drain electrode, a first insulating film disposed on the gate electrode, and a field plate disposed on the first insulating film, at least part of the field plate overlapping the gate electrode, the field plate including a first metal layer and a second metal layer disposed on the upper surface of the first metal layer, the first metal layer containing gold, the second metal layer containing at least one of tantalum, tungsten, molybdenum, niobium, and titanium. | 2022-05-19 |
20220157951 | HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDCUTOR DEVICES AND MANUFACTURING METHOD THEREOF - A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region. | 2022-05-19 |
20220157952 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first insulating film provided in a trench reaching the second semiconductor layer from above the second semiconductor region via the second semiconductor region and the first semiconductor region, the first insulating film containing a first insulating material; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; a second insulating film provided between a position of 40% of a height of the second electrode from a lower end of the second electrode and a position of an upper end of the second electrode, the second insulating film being provided between the side surface of the second electrode and a fifth insulating film provided between a side surface of the second electrode and the second semiconductor layer, the fifth insulating film containing the first insulating material, the second insulating film containing a second insulating material having a higher dielectric constant than the first insulating material; a third electrode provided above the second electrode, the first insulating film and the second insulating film, the third electrode facing the first semiconductor region via a gate insulating film; an interlayer insulating film provided on the third electrode; and a fourth electrode provided above the interlayer insulating film, wherein the first insulating film in the trench below the position of 40% of the height of the second electrode contains only the first insulating material. | 2022-05-19 |
20220157953 | BIPOLAR JUNCTION TRANSISTOR WITH GATE OVER TERMINALS - Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated. | 2022-05-19 |
20220157954 | SEMICONDUCTOR DEVICE - A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern. | 2022-05-19 |
20220157955 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2. | 2022-05-19 |
20220157956 | FORMING A CAVITY WITH A WET ETCH FOR BACKSIDE CONTACT FORMATION - In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact. | 2022-05-19 |
20220157957 | SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF - A semiconductor structure and a forming method thereof are provided. In one form, a semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, where the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, where on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line. The power rail contact plug is in full contact with the top surface of the power rail line in the longitudinal direction, and a dimension of the power rail contact plug in the longitudinal direction and a contact area between the power rail contact plug and the power rail line are increased, to further help to reduce a resistance of the power rail contact plug and a contact resistance between the power rail line and the power rail contact plug. | 2022-05-19 |
20220157958 | METHOD OF MANUFACTURING TRENCH TYPE SEMICONDUCTOR DEVICE - A method of manufacturing a trench type semiconductor device includes the following steps. First, an epitaxial layer is formed on a substrate, then a trench is formed in the epitaxial layer, and a gate structure is formed in the trench. The gate structure includes an upper gate and a lower gate, and an intermediate insulating portion, and the intermediate insulating portion is located in and above the upper gate. | 2022-05-19 |
20220157959 | SEMICONDUCTOR POWER DEVICES HAVING MULTIPLE GATE TRENCHES AND METHODS OF FORMING SUCH DEVICES - A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure. The gate trench has a bottom surface comprising a first portion at a first level and a second portion at a second level, different from the first level. A method of forming a semiconductor device includes providing a semiconductor layer structure, etching a first gate trench into the semiconductor layer structure, etching a second gate trench into the semiconductor layer structure, and performing an ion implantation into a bottom surface of the second gate trench. The second gate trench is deeper than the first gate trench, and at least a portion of the second gate trench is connected to the first gate trench. | 2022-05-19 |
20220157960 | TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT - A transistor with a shared gate structure includes an active area and a gate. The active area has a body extending in a first direction on a substrate, and a protrusion extending in a second direction perpendicular to the first direction from a central portion of the body in the first direction. The gate is arranged above the active area to overlap a channel area of the active area, and has an inverted pi ( | 2022-05-19 |
20220157961 | FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure. | 2022-05-19 |
20220157962 | INTERFACE LAYER CONTROL METHODS FOR SEMICONDUCTOR POWER DEVICES AND SEMICONDUCTOR DEVICES FORMED THEREOF - A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween. | 2022-05-19 |
20220157963 | Structure and Method for Semiconductor Devices - The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer. | 2022-05-19 |
20220157964 | SEMICONDUCTOR DEVICE - A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film. | 2022-05-19 |
20220157965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure. | 2022-05-19 |
20220157966 | FERROELECTRIC FIELD EFFECT TRANSISTORS HAVING ENHANCED MEMORY WINDOW AND METHODS OF MAKING THE SAME - A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel. | 2022-05-19 |
20220157967 | SEMICONDUCTOR DEVICE STRUCTURE WITH METAL GATE STACK - A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first structure and a second structure. The method further includes replacing the second structure with a third structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first structure and the second sacrificial layers in the third structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first structure and each of the second semiconductor layers in the third structure, respectively. | 2022-05-19 |
20220157968 | ION IMPLANTATION TO REDUCE NANOSHEET GATE LENGTH VARIATION - Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask. | 2022-05-19 |
20220157969 | Inner Spacer Liner - The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features. | 2022-05-19 |
20220157970 | METHOD FOR FABRICATING A DOPED REGION OF A MICROELECTRONIC DEVICE - A method for forming at least one doped region of a transistor includes providing a stack having an insulating layer, an active layer, and a gate pattern having a first lateral flank and removing a first portion of the active layer not overlaid by the gate pattern and extending down to the gate pattern, at the edge of a second portion of the active layer overlaid by the gate pattern, so as to expose an edge of the second portion. The edge extends substantially in a continuation of the lateral flank of the gate pattern. The method also includes forming a first spacer having an L shape and having a basal portion in contact with the insulating layer and a lateral portion in contact with the lateral flank; forming a second spacer on the first spacer; removing the basal portion of the first spacer by selective etching with respect to the second spacer, so as to expose the edge of the second portion; and forming the doped region by epitaxy from the exposed edge. | 2022-05-19 |
20220157971 | SEMICONDUCTOR DEVICE - A semiconductor device including a structure having N gate electrode layers G and (N−1) channel formation region layers CH (where N≥3) alternately juxtaposed on an insulating material layer of a base having the insulating material layer formed on a surface of a conductive substrate. Each of the structure, the channel formation region layer CH, and the gate electrode layer G has a bottom surface, a top surface, and four side surfaces. A second surface of the nth channel formation region layer is connected to a fourth surface of the nth gate electrode layer. A fourth surface of the nth channel formation region layer is connected to a second surface of the (n+1)th gate electrode layer. One of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion. | 2022-05-19 |
20220157972 | FIN-BASED LATERALLY-DIFFUSED METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way. | 2022-05-19 |
20220157973 | Gate Formation with Varying Work Function Layers - A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer. | 2022-05-19 |
20220157974 | LAYOUT TO REDUCE CURRENT CROWDING AT ENDPOINTS - Layout to reduce current crowding at endpoints. At least one example is a semiconductor device comprising: an emitter region defining an inner boundary in the shape of an obround with parallel sides, and the obround having hemispherical ends each having a radius; a base region having a first end, a second end opposite the first end, and base length, the base region disposed within the obround with the base length parallel to and centered between the parallel sides, the first end spaced apart from the first hemispherical end by a first gap greater than the radius, and the second end spaced apart from the second hemispherical ends by a second gap greater than the radius. | 2022-05-19 |
20220157975 | LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT - A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor. | 2022-05-19 |
20220157976 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS - A semiconductor device includes; a semiconductor substrate; an emitter electrode provided on the semiconductor substrate; a gate electrode provided on the semiconductor substrate; a drift layer of a first conduction type provided in the semiconductor substrate; a source layer of the first conduction type provided on an upper surface side of the semiconductor substrate; a base layer of a second conduction type provided on the upper surface side of the semiconductor substrate; a collector electrode provided below the semiconductor substrate; and a two-part dummy active trench including, at an upper part, an upper dummy part not connected with the gate electrode and including, at a lower part, a lower active part connected with the gate electrode and covered by an insulating film, in a trench of the semiconductor substrate, wherein a longitudinal length of the lower active part is larger than a width of the lower active part. | 2022-05-19 |
20220157977 | TRANSISTOR AND METHODS OF FABRICATING A TRANSISTOR - A transistor may include a buffer layer, source and drain contacts on the buffer layer, a barrier layer on the buffer layer, a conductive member on the barrier layer, a dielectric stack, and a gate metal. The barrier layer may be between the source and drain contacts. The conductive member may include a p-doped III-V compound. The dielectric stack may be on the barrier layer and on the conductive member. The dielectric stack may include a first dielectric layer and a second dielectric layer on the first dielectric layer. First and second trenches may extend through the dielectric stack to the conductive member and to the first dielectric layer, respectively. The gate metal may be on the dielectric stack, and may contact the conductive member through the first trench and may contact the first dielectric layer through the second trench. | 2022-05-19 |
20220157978 | p-GaN HIGH ELECTRON MOBILITY TRANSISTOR - A p-GaN high electron mobility transistor is disclosed. The p-GaN high electron mobility transistor includes a substrate, a channel layer located on the substrate, a supply layer laminated on the channel layer, and a doped layer laminated on the supply layer. A doping concentration of the doped layer is gradually distributed, in which the doping concentration in a first doped region close to the supply layer is lower than a doping concentration in a second doped region distant from the supply layer. A gate electrode is located on the doped layer. A source electrode and a drain electrode are respectively electrically connected to the channel layer and the supply layer. | 2022-05-19 |
20220157979 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer. | 2022-05-19 |
20220157980 | NITRIDE SEMICONDUCTOR DEVICE - A field-effect transistor includes a substrate having conductivity and made of gallium nitride, a buffer layer provided on the substrate and made of C-doped GaN, a drift layer provided on the buffer layer and made of undoped GaN, and a channel layer provided on the drift layer, made of undoped AlGaN, and joined to the drift layer by heterojunction. A gate electrode is provided on the channel layer. A source electrode and a drain electrode are each provided in regions on both sides of the gate electrode on the channel layer. | 2022-05-19 |
20220157981 | N-POLAR DEVICES INCLUDING A DEPLETING LAYER WITH IMPROVED CONDUCTIVITY - Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current. | 2022-05-19 |
20220157982 | HIGH VOLTAGE DEVICE OF SWITCHING POWER SUPPLY CIRCUIT AND MANUFACTURING METHOD THEREOF - A high voltage device for use as an up-side switch of a power stage circuit includes: at least one lateral diffused metal oxide semiconductor (LDMOS) device, a second conductivity type isolation region and at least one Schottky barrier diode (SBD). The LDMOS device includes: a well formed in a semiconductor layer, a body region, a gate, a source and a drain. The second conductivity type isolation region is formed in the semiconductor layer and is electrically connected to the body region. The SBD includes: a Schottky metal layer formed on the semiconductor layer and a Schottky semiconductor layer formed in the semiconductor layer. The Schottky semiconductor layer and the Schottky metal layer form a Schottky contact. In the semiconductor layer, the Schottky semiconductor layer is adjacent to and in contact with the second conductivity type isolation region. | 2022-05-19 |
20220157983 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes a plurality of capacitors. | 2022-05-19 |
20220157984 | TRANSISTOR CONTACT AREA ENHANCEMENT - A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD. | 2022-05-19 |
20220157985 | TRANSISTOR HAVING WRAP-AROUND SOURCE/DRAIN CONTACTS AND UNDER-CONTACT SPACERS - Embodiments of the invention are directed to a semiconductor device structure that includes a first channel region over a substrate, a second channel region over the first channel region, and a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is configured such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region. | 2022-05-19 |
20220157986 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; first and second conductors and a third oxide over the second oxide; a second insulator over the first conductor; a third insulator over the second conductor; first and second layers; and fourth to sixth insulators. The sixth insulator includes a region in contact with a top surface of the first insulator. The first layer includes a region in contact with side surfaces of the first and second oxides, a side surface of the first conductor, and the top surface of the first insulator. The second layer includes a region in contact with the side surfaces of the first and second oxides, a side surface of the second conductor, and the top surface of the first insulator. | 2022-05-19 |
20220157987 | Semiconductor Device - An exemplary semiconductor device may include a substrate, an N− epitaxial layer positioned on the substrate, a first P region and a second P region positioned apart from each other on the N− epitaxial layer, a first N+ region positioned within the first P region, a second N+ region positioned within the second P region, and a gate layer positioned between the first P region and the second P region. | 2022-05-19 |
20220157988 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device including an epitaxial layer and a fabrication method thereof are provided. A first well region and a second well region separated from each other respectively extend from a surface of the epitaxial layer into the epitaxial layer. A floating doped region is located in the epitaxial layer and between the first well region and the second well region. The floating doped region is separated from the first well region and the second well region. A first doped region and a second doped region respectively extend from the surface of the epitaxial layer into the first well region and the second well region. A gate structure is located on the epitaxial layer and is adjacent to the first doped region and the second doped region. The gate structure is at least partially overlapped with the floating doped region. | 2022-05-19 |
20220157989 | MOSFET DEVICE WITH SHIELDING REGION AND MANUFACTURING METHOD THEREOF - A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region. | 2022-05-19 |
20220157990 | SEMICONDUCTOR DEVICES - A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type. | 2022-05-19 |
20220157991 | Semiconductor Device and Method - In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor material. | 2022-05-19 |
20220157992 | A SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device with high productivity is provided. The semiconductor device includes a first and a second transistor and a first and a second capacitor. The first and the second transistor include gate electrodes and back gate electrodes. The second transistor is provided in a layer above the first transistor, and the second capacitor is provided in a layer above the first capacitor. One electrode of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and electrically connected to one of a source electrode and a drain electrode of the second transistor. The other electrode of the first capacitor is formed in the same layer as the back gate electrode of the second transistor. | 2022-05-19 |
20220157993 | FLASH MEMORY DEVICE - A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer. | 2022-05-19 |
20220157994 | Latch-Up Prevention - A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region. | 2022-05-19 |
20220157995 | A BIOMIMETIC 2D TRANSISTOR FOR AUDIOMORPHIC COMPUTING - Embodiments relate to a computing device that may be configured as a biomimetic audiomorphic device. The device can include a field effect transistor (FET) having a split-gate architecture with different spacing between the split-gates. Embodiments of the device can include multiple split-gates. Some embodiments include the integration of delay elements and tunable resistor-capacitance (RC) circuits for imitating the interaural time delay neurons. Some embodiments include global back-gating structural features to provide neuroplasticity aspects so as to provide adaptation related changes. | 2022-05-19 |
20220157996 | DISPLAY DEVICE - One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other. | 2022-05-19 |
20220157997 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY DEVICE - Disclosed are a method of manufacturing a thin film transistor, a thin film transistor, a display panel, and a display device. The method includes forming a gate electrode, forming an oxide semiconductor layer at least partially overlapping the gate electrode, and forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein the forming of the oxide semiconductor layer includes forming a first oxide semiconductor layer, and forming a second oxide semiconductor layer on the first oxide semiconductor layer, the second oxide semiconductor layer having a higher energy bandgap than the first oxide semiconductor layer, wherein the forming of the second oxide semiconductor layer is performed by a different process from the forming of the first oxide semiconductor layer, and the forming of the second oxide semiconductor layer includes spraying a precursor solution for the second oxide semiconductor on the first oxide semiconductor layer followed by heat treatment. | 2022-05-19 |
20220157998 | DISPLAY DEVICE - A display device is provided. The display device includes a substrate, a channel layer, a first metal layer, and a second metal layer. The channel layer is disposed on the substrate and includes a first channel layer and a second channel layer. The first metal layer is disposed on the channel layer and includes a first gate and a second gate. The second metal layer is disposed over the first metal layer and includes a first source, a first drain, and a second source. The first gate, the first source, the first drain, and the first channel layer form a first transistor. The second gate, the second source, the first drain, and the second channel layer form a second transistor. The first transistor and the second transistor are connected in parallel. | 2022-05-19 |
20220157999 | SEMICONDUCTOR DEVICE - A memory gate is formed on a semiconductor substrate via an insulating film that is a gate insulator for a memory element. The insulating film includes a first insulating film, a second insulating film on the first insulating film, a third insulating film on the second insulating film, and a fourth insulating film on the third insulating film. The second insulating film is an insulating film having a charge-accumulating function. A bandgap of each of the first insulating film and the third insulating film is larger than that of the second insulating film. The third insulating film is formed of a high dielectric constant material containing a metal element and oxygen. The fourth insulating film is a silicon oxide film or a silicon oxynitride film and is adjacent to the memory gate electrode. | 2022-05-19 |
20220158000 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - Provided is a semiconductor device in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented, the semiconductor device that is particularly useful for power devices. A semiconductor device including at least: a semiconductor layer; a Schottky electrode; and an insulator layer provided between a part of the semiconductor layer and the Schottky electrode, wherein the semiconductor layer contains a crystalline oxide semiconductor, and wherein the insulator layer has a taper angle of 10° or less. | 2022-05-19 |
20220158001 | LASER ASSISTED METALLIZATION PROCESS FOR SOLAR CELL FABRICATION - A method for fabricating a solar cell and the and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. The method can include: providing a solar cell having metal foil having first regions that are electrically connected to semiconductor regions on a substrate at a plurality of conductive contact structures, and second regions; locating a carrier sheet over the second regions; bonding the carrier sheet to the second regions; and removing the carrier sheet from the substrate to selectively remove the second regions of the metal foil. | 2022-05-19 |
20220158002 | SYSTEM AND METHOD FOR EXTENDING THE PRACTICAL CUTOFF WAVELENGTH OF ELECTRO-OPTICAL/INFRARED (EO/IR) SENSORS USING PLASMONIC RESONATORS - A system includes a substrate. The system also includes a detector array disposed over the substrate, where the detector array includes multiple detector pixels. The system further includes multiple plasmonic gratings disposed over top surfaces of the detector pixels, where each plasmonic grating includes multiple convex polyhedrons separated by valleys. Each detector pixel may have a mesa shape, and the convex polyhedrons of the plasmonic gratings may have a smaller size than the mesa shape of the detector pixels. A dimension across a base of each convex polyhedron of the plasmonic gratings may be selected based on a desired resonance wavelength of the plasmonic gratings. | 2022-05-19 |
20220158003 | SOLAR CELL AND METHOD FOR PRODUCING SAME - The present disclosure provides a solar cell and a method for producing same. The solar cell includes: a substrate; a first passivation film, an anti-reflection layer and at least one first electrode formed on a front surface of the substrate; and a tunneling layer, a field passivation layer and at least one second electrode formed on a rear surface. The field passivation layer includes a first field passivation sub-layer and a second field passivation sub-layer; a conductivity of the first field passivation sub-layer is greater than a conductivity of the second field passivation sub-layer, and a thickness of the second field passivation sub-layer is smaller than a thickness of the first field passivation sub-layer; either the at least one first electrode or the at least one second electrode includes a silver electrode, a conductive adhesive and an electrode film that are sequentially formed in a direction away from the substrate. | 2022-05-19 |
20220158004 | METHOD FOR METALLIZING FRONT ELECTRODE OF N-TYPE SOLAR CELL - The present invention relates to a method for metallizing a front electrode of an N-type solar cell, including: treating an N-type crystalline silicon substrate to form a p | 2022-05-19 |
20220158005 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A Semiconductor device includes an insulating layer, an optical waveguide, a first dummy semiconductor film, a second semiconductor film and a third semiconductor film. The optical waveguide is formed on the insulating layer. The first dummy semiconductor film is formed on the insulating layer and is spaced apart from the optical waveguide. The first dummy semiconductor film is formed on the first semiconductor film. The second semiconductor film is integrally formed with the optical waveguide as a single member on the insulating layer. The third semiconductor film is formed on the second semiconductor film. A material of the first dummy semiconductor film is different from a material of the optical waveguide. In plan view, a distance between the optical waveguide and the first dummy semiconductor film in a first direction perpendicular to an extending direction of the optical waveguide is greater than a thickness of the insulating layer. | 2022-05-19 |
20220158006 | DEVICE FOR OPTICAL SENSING AND MANUFACTURING METHOD THEREOF - Disclosed are devices for optical sensing and manufacturing method thereof. In one embodiment, a device for optical sensing includes a substrate, a photodetector and a reflector. The photodetector is disposed in the substrate. The reflector is disposed in the substrate and spaced apart from the photodetector, wherein the reflector has a reflective surface inclined relative to the photodetector that reflects light transmitted thereto to the photodetector. | 2022-05-19 |
20220158007 | SEMICONDUCTOR WAFER, RADIATION DETECTION ELEMENT, RADIATION DETECTOR, AND PRODUCTION METHOD FOR COMPOUND SEMICONDUCTOR MONOCRYSTALLINE SUBSTRATE - Provided is a CdZnTe monocrystalline substrate which has a small leakage current even when a voltage is applied from a low voltage to a high voltage, and which has a lower variation in resistivity with respect to applied voltage changes from 0 to 900 V, and which can maintain a stable resistivity. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by weight or more and 5.0 ppm by weight or less, wherein when a voltage is applied in a range of from 0 to 900 V, the semiconductor wafer has a resistivity for each applied voltage value of 1.0×10 | 2022-05-19 |
20220158008 | Semiconductor Light Receiving Element - Provided is a semiconductor light receiving element which can achieve a high-speed operation without sacrificing light receiving sensitivity while increasing the margin of a manufacturing process. The semiconductor light receiving element according to the present invention is characterized by comprising: a semiconductor layer doped with a first impurity; a semiconductor light absorption layer in which a band gap energy is adjusted to absorb incident light on the semiconductor layer doped with the first impurity; a semiconductor layer on the semiconductor light absorption layer and doped with a second impurity; and a metal electrode contacting side surfaces of the semiconductor layer doped with the second impurity, wherein side surfaces of the metal electrode are surfaces parallel to a growth direction of the semiconductor layer doped with the second impurity. | 2022-05-19 |
20220158009 | SOLAR CELL - The present disclosure provide a solar cell, including: a substrate, an interface passivation layer covering a rear surface of the substrate, and an electrode disposed at a side of the interface passivation layer facing away from the substrate, the interface passivation layer including a first interface passivation sub-layer corresponding to a portion of the interface passivation layer between adjacent electrodes and a second interface passivation sub-layer corresponding to a portion of the interface passivation layer where disposed between the substrate and the electrode; a field passivation layer, at least partially disposed between the interface passivation layer and the electrode; and a conductive enhancement layer, at least partially disposed at a side of the first interface passivation sub-layer away from the substrate to enable carriers in the first interface passivation sub-layer to flow to the electrode, where a resistivity of the conductive enhancement layer is smaller than a resistivity of the field passivation layer. | 2022-05-19 |
20220158010 | BACK-CONTACT SOLAR CELL AND SOLAR CELL MODULE INCLUDING SAME - The present disclosure provides a back-contact solar cell and a solar cell module. The back-contact solar cell includes: a substrate including a light-receiving surface and a back surface opposite to the light-receiving surface, wherein the substrate includes a center region and connecting regions on opposite sides of the center region; positive electrodes and negative electrodes disposed on the back surface of the substrate; auxiliary positive electrodes, disposed on one or both of the light-receiving surface and a side surface of each of the connecting regions, and configured to be electrically coupled to the plurality of positive electrodes; and auxiliary negative electrodes, disposed on one or both of the light-receiving surface and the side surface of each of the connecting regions, and configured to be electrically coupled to the plurality of negative electrodes. | 2022-05-19 |
20220158011 | SOLAR CELL MODULE WITH HOLES AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a transparent solar cell, a photovoltaic system including the transparent solar cell, and a method for manufacturing the transparent solar cell are provided. The transparent solar cell comprises a substrate, an adhesive layer formed on the substrate, a metal layer formed on the adhesive layer, a solar cell layer formed on the metal layer, and a coating layer formed on the solar cell layer. The solar cell layer and the metal layer include a plurality of holes having a predetermined diameter. | 2022-05-19 |
20220158012 | PROTECTION COATING FOR SOLAR CELL WAFERS - A solar module includes solar cells that are encapsulated. A back layer is disposed towards back sides of the solar cells and a transparent layer is disposed towards front sides of the solar cells. A protection coating is formed on a surface of the solar cells. The protection coating can be continuous or have a pattern with cutouts that expose the surface of the solar cells. | 2022-05-19 |
20220158013 | BLOCKING DIODE BOARD FOR ROLLABLE SOLAR POWER MODULE - A blocking diode board (“BDB”) for use with a rollable solar power module (“RSPM”) array is disclosed. The DBD includes a blocking diode, first flat electrical conductor, second flat electrical conductor, first tubular hook, and second tubular hook. | 2022-05-19 |
20220158014 | PHOTOVOLTAIC MODULES - Photovoltaic modules include a front sheet, a back sheet, a photovoltaic layer, a first encapsulant layer, and a second encapsulant layer. The front sheet is made of or includes a composite of a thermoplastic material and a nanoparticle filler dispersed in the thermoplastic material. The thermoplastic material is a poly(methyl methacrylate) or a polycarbonate. The nanoparticle filler may include nanoparticles such as silica nanoparticles, titania nanoparticles, zirconia nanoparticles, zinc oxide nanoparticles, and combinations thereof, for example. The photovoltaic layer is interposed between the front sheet and the back sheet and includes at least one photovoltaic cell. The first encapsulant layer is interposed between the front sheet and the at least one photovoltaic cell. The second encapsulant layer is interposed between the at least one photovoltaic cell and the back sheet. | 2022-05-19 |
20220158015 | SOLAR ARRAY MODULES FOR GENERATING ELECTRIC POWER - A solar power generation module is provided for maximizing the power generated from the module and minimizing the power degradation inflicted by light obstructions. The module includes solar cells arranged in a matrix of N columns and M rows. At least one pair of neighboring rows of solar cells is mechanically and electrically interconnected by single wide polymer conductor stripe that extends over at least two adjacent columns of the at least one pair of neighboring rows. All solar cells in each pair of neighboring rows of a mutual string, are electrically interconnected in series by at least one respective thin wire conductor embedded inside the polymer conductor stripe. At least one solar cell in each string of solar cells is electrically interconnected in parallel to one or two solar cells, situated in a mutual row of an adjacent string, by a parallelly-connection conductive means. | 2022-05-19 |
20220158016 | A LUMINESCENT OPTICAL DEVICE AND A FILM FOR USE WITH SUCH A LUMINESCENT OPTICAL DEVICE - A luminescent optical device based on a luminescent solar collector, LSC, is disclosed. In addition to components forming a LSC for generating electrical energy from solar energy, the luminescent optical device also includes a light source, and optionally one or more sensors, both electrically connected to an energy storage device of the LSC. Under the control of a control unit, the light source may emit light of different wavelengths, for example in response to environmental data measured by the sensor, thereby exciting respective domains containing luminescence material to emit light of different colours. The luminescent optical device may function as a standalone and fully integrated device that is capable of harvesting energy, illuminating itself and displaying various content conveniently and flexibly, for various purposes. | 2022-05-19 |
20220158017 | SOLAR CELL MODULE - A solar cell module includes a plurality of solar cells each having a long axis and a short axis, and including a first electrode disposed on a front surface of a substrate and a second electrode disposed on a back surface of the substrate. The solar cells are disposed along a first direction. The solar cell module further includes a plurality of wiring members connected to the first electrode of a first solar cell and the second electrode of a second solar cell, wherein the plurality of wiring members includes a core layer of metal, and a solder layer formed of a solder material. Further, a ratio of a thickness of the solder layer to a thickness of the core layer is approximately 0.05 to 0.08, and a distance between the first solar cell and the second solar cell is approximately 0.5 mm to 1.5 mm. | 2022-05-19 |
20220158018 | SURFACE TREATMENT OF SOLAR CELLS - Methods of fabricating emitter regions of solar cells using surface treatments, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes treating a surface of a silicon substrate to form a lyophilic area between two lyophobic areas and depositing a liquid phase material containing a silicon material in the lyophilic area to form an emitter region. | 2022-05-19 |
20220158019 | SEMICONDUCTOR PACKAGES WITH SINGLE-PHOTON AVALANCHE DIODES AND PRISMS - A semiconductor package may include a line array of single-photon avalanche diodes (SPADs). The line array of single-photon avalanche diodes may be split between multiple silicon dice. The silicon dice may have a staggered arrangement, with prisms on the package lid redirecting incident light to the silicon dice. The silicon dice may alternate between a first side of the package substrate and a second side of the package substrate. The prisms may alternate between a first structure that redirects incident light to the first side of the package substrate and a second structure that redirects incident light to the second side of the package substrate. The silicon dice may overlap to allow satisfactory alignment between the silicon dice and the prisms. | 2022-05-19 |
20220158020 | SINGLE PHOTON DETECTOR AND SYSTEM FOR MINIMIZING DARK CURRENT - According to an embodiment, a single photon detector configured to reduce a dark current comprises a buffer layer, a light absorption layer, a grading layer, an electric field control layer, and a window layer sequentially formed on a substrate. An active area may be formed in the window layer. A barrier junction may be formed through the window layer up to at least a portion of the light absorption layer, around the active area. | 2022-05-19 |
20220158021 | INTEGRATED CIRCUIT PACKAGE AND SYSTEM USING SAME - Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The integrated circuit package includes first and second active dies. Each of the first and second active dies includes a top contact disposed on the top surface of the die and a bottom contact disposed on a bottom surface of the die. The package further includes a via die having first and second vias that each extends between a top contact disposed on a top surface of the via die and a bottom contact disposed on a bottom surface of the via die, where the bottom contact of the first active die is electrically connected to the bottom contact of the first via of the via die and the bottom contact of the second active die is electrically connected to the bottom contact of the second via of the via die. | 2022-05-19 |
20220158022 | ARRANGEMENT, DEVICE, AND METHOD FOR HEAT TREATING A MULTILAYER BODY - An arrangement for heat treating a multilayer body, which arrangement comprises an energy source with at least one radiant heater for generating heating radiation, a multilayer body, and an intermediate element arranged between the energy source and the multilayer body. According to a first alternative, the intermediate element includes a surface element implemented in the form of a flexible film. According to a second alternative, the intermediate element includes a surface element implemented in the form of a flexible film or a rigid plate, wherein the surface element has a surface facing the energy source, which can be irradiated by the heating radiation and is mechanically supported by a supporting device in the direction toward the energy source. | 2022-05-19 |
20220158023 | LIGHT EMITTING DEVICE - A light emitting device is provided. The light emitting device includes a first semiconductor layer; a second semiconductor layer provided on a bottom surface of the first semiconductor layer; an active layer interposed between the first semiconductor layer and the second semiconductor layer; a dielectric layer provided on a bottom surface of the second semiconductor layer; a plurality of first n-contacts provided on a first etched surface of the first semiconductor layer; and a plurality of first p-contacts and a plurality of second p-contacts provided on the bottom surface of the second semiconductor layer. One first n-contact is disposed along a first edge region of the first semiconductor layer, one first p-contact is closer to the one first n-contact than one second p-contact, and an area of the one first p-contact is greater than an area of each of the second p-contacts. | 2022-05-19 |
20220158024 | N-ZNO/N-GAN/N-ZNO HETEROJUNCTION-BASED BIDIRECTIONAL ULTRAVIOLET LIGHT-EMITTING DIODE AND PREPARATION METHOD THEREFOR - The present invention discloses a bidirectional ultraviolet light emitting diode (UV LED) based on N—ZnO/N—GaN/N—ZnO heterojunction as well as its preparation method. The LED includes: N—ZnO microwires, a N—GaN film, a PMMA protective layer and alloy electrodes; and its preparation method includes the following steps: lay two N—ZnO microwires on the N—GaN film, then spin-coat a PMMA protective layer on the film to fix the N—ZnO microwires until the PMMA protective layer spreads over the N—ZnO microwires, and then place the film on a drying table to solidify the PMMA protective layer; then etch the PMMA protective layer with O | 2022-05-19 |
20220158025 | LIGHT EMITTING DEVICE - A light-emitting device includes an n-side semiconductor layer comprising an n-type contact layer and an intermediate layer located on the n-type contact layer; an active layer located on the intermediate layer; and a p-side semiconductor layer located on the active layer. The intermediate layer includes at least one stacked portion comprising a first layer and a second layer. The first layer is an n-type nitride semiconductor layer comprising an n-type impurity, Al, and Ga. The second layer is a nitride semiconductor layer that includes Al and Ga, has a lower n-type impurity concentration than the first layer, and has a larger thickness than the first layer. An Al composition ratio of the first layer is higher than an Al composition ratio of the second layer. | 2022-05-19 |
20220158026 | LIGHT-EMITTING DIODE - A light-emitting diode is provided. The light-emitting diode includes a P-type semiconductor layer, a N-type semiconductor layer, and a light-emitting stack located therebetween. The light-emitting stack includes a plurality of well layers and a plurality of barrier layers that are alternately stacked, the well layers includes at least one first well layer, at least one second well layer, and third well layers that have different indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of well layers that are closest to the P-type semiconductor layer are the third well layers, and the first well layer is closer to the N-type semiconductor layer than the P-type semiconductor layer. | 2022-05-19 |
20220158027 | ULTRA-WIDEBAND, FREE SPACE OPTICAL COMMUNICATION APPARATUS - Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs. | 2022-05-19 |
20220158028 | LIGHT-EMITTING DEVICE, LIGHT-EMITTING MODULE INCLUDING THE SAME AND DISPLAY APPARATUS INCLUDING THE SAME - A light-emitting device includes a substrate, a first and second mesa structures disposed on the substrate, at least one current blocking element, at least one conductive bridging element, and first and second conductive pads. The conductive bridging element is disposed on the current blocking element, and is electrically connected to the first and second mesa structures. The first and second conductive pads are electrically connected to the first and second mesa structures, respectively. The conductive bridging element has a projection image that is spaced apart from those of the first and second conductive pads in a plan view of the light-emitting device. A light-emitting module including the light-emitting device, and a display apparatus including the light-emitting device are also disclosed. | 2022-05-19 |
20220158029 | SUBSTRATE AND LIGHT EMITTING ELEMENT - A substrate | 2022-05-19 |
20220158030 | METHOD OF MANUFACTURING LIGHT-EMITTING ELEMENT, AND LIGHT-EMITTING ELEMENT ARRAY SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - A method of manufacturing a light-emitting element, and a light-emitting element array substrate and a display device including the same are provided. A method of manufacturing a light-emitting element includes: forming a base substrate including a plurality of protrusions and a rod area which is a remaining area except for the plurality of protrusions; forming a buffer layer on the base substrate; forming a semiconductor structure including a first semiconductor material layer, a light-emitting material layer, and a second semiconductor material layer on the buffer layer; forming a plurality of mask patterns overlapping the rod area on the semiconductor structure; forming element rods by removing the semiconductor structure overlapping the plurality of protrusions using the plurality of mask patterns; forming an insulating film around an outer surface of each of the element rods. and separating the element rods from the buffer layer. | 2022-05-19 |
20220158031 | LIGHT EMITTING DEVICE FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A method of fabricating a light emitting device for a display, the method including the steps of growing a first LED stack on a first growth substrate, the first LED stack including a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, growing a second LED stack on a second growth substrate, the second LED stack including a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, bonding the second LED stack to a first temporary substrate, removing the second growth substrate from the second LED stack, bonding the second LED stack to the first LED stack, and removing the first temporary substrate from the second LED stack. | 2022-05-19 |
20220158032 | LIGHT EMITTING DEVICE AND METHOD OF MAKING THE SAME - A light emitting device for emitting UVC radiation. The device comprises a substrate and a patterned layer. The patterned layer comprises a plurality of mask regions on the substrate. Exposed portions of the substrate are disposed between the mask regions. A plurality of nanostructures are disposed on the exposed portions of the substrate and over the mask regions, the plurality of nanostructures being a single crystal semiconductor and comprising a core tip. An active layer is disposed over the plurality of nanostructures. The active layer is a quantum well structure and comprises at least one material chosen from AIN, AlGaN and GaN. A p-doped layer is disposed over the active layer. Both the active layer and the p-doped layer are conformal to the plurality of nanostructures so as to form an emitter tip over the core tip. | 2022-05-19 |
20220158033 | LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING LIGHT-EMITTING ELEMENT - A light emitting element includes a first light emitting portion and a second light emitting portion. The first light emitting portion includes a first stacked body having a first n-type layer, a first active layer, a first p-type layer, a first tunnel junction layer, and a second n-type layer. The second light emitting portion includes a second stacked body having a third n-type layer, a second p-type layer, a second tunnel junction layer, a fourth n-type layer, a second active layer, a third p-type layer, and a transmissive conductive film. A resistivity of the second n-type layer is higher than a resistivity of the transmissive conductive film. A thickness of the second n-type layer is larger than a thickness of the transmissive conductive film. | 2022-05-19 |
20220158034 | OPTOELECTRONIC SEMICONDUCTOR DEVICE COMPRISING AN INSULATING LAYER AND METHOD OF MANUFACTURING THE OPTOELECTRONIC SEMICONDUCTOR DEVICE - An optoelectronic semiconductor device may include a first and a second semiconductor layer having a first and a second conductivity type. The optoelectronic semiconductor device may include a first contact layer in direct contact with the first semiconductor layer, a first insulating layer formed over the semiconductor layers, and a second current spreading structure electrically connected to the second semiconductor layer. A maximum lateral extension of the second semiconductor layer is greater than a maximum lateral extension of the first semiconductor layer, such that a step structure is formed, and the first insulating layer is formed as a conformal layer over the step structure. A second insulating layer may be arranged between a horizontal surface of the first contact layer and the second current spreading structure. The thickness of the second insulating layer is smaller than the smallest thickness of the first insulating layer over the step structure. | 2022-05-19 |
20220158035 | DISPLAY DEVICE - Some embodiments of the present disclosure provide a display device including a base layer, a first electrode and a second electrode extending along a first direction on the base layer, and spaced apart from each other in a second direction crossing the first direction, and light emitting elements at least partially overlapping the first electrode and at least partially overlapping the second electrode, wherein at least one of the first electrode and the second electrode includes a concavo-convex portion in which at least a portion of one of the light emitting elements overlaps with respect to a third direction that is perpendicular to the first direction and to the second direction. | 2022-05-19 |
20220158036 | DISPLAY DEVICE - According to one embodiment, a display device includes a substrate, an anode electrode, a light emitting element and a reflector plate. The anode electrode is arranged on the substrate. The light emitting element is mounted on the anode electrode. The reflector plate is arranged under the anode electrode, and is arranged to overlap a region where the light emitting element is mounted, in planar view. An anode terminal is arranged on a bottom part and electrically connected to the anode electrode. A cathode terminal is arranged across an entire upper surface on a side opposite to the anode terminal. The anode electrode being smaller than the cathode terminal in a position overlapping the region where the light emitting element is mounted in planar view. | 2022-05-19 |
20220158037 | LIGHT-EMITTING DIODE STRUCTURE FOR IMPROVING BONDING YIELD - A light-emitting diode structure for improving bonding yield is provided, which includes a light-emitting diode, a plurality of contact electrodes, an insulating layer structure, and a plurality of bonding electrodes. One surface of the light-emitting diode includes a mesa structure. The contact electrodes are on the mesa structure. The bonding electrodes are on the insulating layer structure and respectively cover at least one contact electrode. A surface of one of the bonding electrodes facing away from the light-emitting diode has a first platform and a second platform. The second platform is on the first platform. A surface area of a vertical projection of the second platform on the light-emitting diode is smaller than that of the first platform on the light-emitting diode, and said vertical projection of the second platform is within that of the first platform. | 2022-05-19 |
20220158038 | DISPLAY DEVICE - A display device includes: a substrate; a transparent electrode on one surface of the substrate; a reflective electrode on the transparent electrode; a transistor on the reflective electrode; and a light emitting element between the transparent electrode and the reflective electrode. The transistor overlaps the light emitting element. | 2022-05-19 |
20220158039 | LIGHT EMITTING ELEMENT, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE INCLUDING THE LIGHT EMITTING ELEMENT - A light emitting element includes: a light emitting stack pattern including a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked along one direction; and an insulating film surrounding an outer surface of at least one of the first semiconductor layer, the active layer, and the second semiconductor layer. The insulating film including a zinc oxide (ZnO) thin film layer. | 2022-05-19 |
20220158040 | LIGHT-EMITTING DIODE - A light-emitting diode includes a semiconductor light-emitting stack and a distributed Bragg reflector (DBR) structure. The semiconductor light-emitting stack has a first surface and a second surface opposite to each other. The DBR structure is disposed on one of the first surface and the second surface of the semiconductor light-emitting stack, and includes at least one set of first light-transmitting layers and at least one set of second light-transmitting layers stacked on each other in the first direction. The first light-transmitting layers has interface roughness greater than that of the second light-transmitting layers. | 2022-05-19 |
20220158041 | LIGHT EMITTING DEVICE AND LIGHT SOURCE MODULE HAVING THEREOF - A light emitting device including a body having a recess; a light emitting chip disposed in the recess; a first dampproof layer sealing the light emitting chip and extended from a surface of the light emitting chip to a bottom of the recess; a light transmitting layer disposed on the recess; and a second dampproof layer having an open area in which an upper surface of the light transmitting layer is exposed and extended from an outer side area of the upper surface of the light transmitting layer to an upper surface and a side surface of the body. Further, the first dampproof layer and the second dampproof layer include a fluororesin-based material. | 2022-05-19 |
20220158042 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND SEMICONDUCTOR LIGHT EMITTING MODULE - A light emitting device includes a semiconductor light emitting element which emits excitation light having a peak wavelength in a range of 440 to 450 nm and a fluorescent body layer which is provided on the semiconductor light emitting element, is excited by the excitation light from the semiconductor light emitting element, and contains a first fluorescent body and a second fluorescent body which emit first fluorescent light and second fluorescent light. The first fluorescent light has a peak wavelength in a range of 540 to 575 nm, and the second fluorescent light has a peak wavelength in a range of 590 to 605 nm. In mixed color light of the radiation light, the intensity of the radiation light of the semiconductor light emitting element is 1/10 to 1/60 of the intensity of the combined light of the radiation light from the first fluorescent body and the second fluorescent body. | 2022-05-19 |