21st week of 2015 patent applcation highlights part 20 |
Patent application number | Title | Published |
20150137289 | MULTIPLE-BITS-PER-CELL VOLTAGE-CONTROLLED MAGNETIC MEMORY - Voltage controlled magneto-electric tunnel junctions and memory devices are described which provide efficient high speed voltage switching of non-volatile magnetic devices (MeRAM) at high cell densities. A multi-bit-per-cell (MBPC) MeRAM is described which requires only a single transistor to write and read two data bits from the one MBPC MeRAM cell. | 2015-05-21 |
20150137290 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni. | 2015-05-21 |
20150137291 | MAGNETIC MEMORY CELLS AND METHODS OF FORMATION - Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems. | 2015-05-21 |
20150137292 | MAGNETORESISTANCE SENSOR WITH PERPENDICULAR ANISOTROPY - A nanoscale tunnel magneto-resistance (TMR) sensor comprising an in-plane-magnetized reference layer and a free layer comprising interfacial perpendicular anisotropy, wherein the free layer comprises a sensing layer for sensing resistance as a function of applied magnetic field and is tunable to vary the direction of the sensing layer magnetization to be in-plane, canted, or out-of-plane. | 2015-05-21 |
20150137293 | Spin-Transfer Torque Magnetic Random Access Memory (STTMRAM) with Perpendicular Laminated Free Layer - A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy. | 2015-05-21 |
20150137294 | IMAGE SENSOR PACKAGE STRUCTURE AND METHOD - Image sensor package structure and method are provided. The method includes: providing first substrate having upper surface on which image sensing areas and pads are formed; providing second substrate having through holes; forming tape film on upper surface of second substrate to seal each through hole; contacting lower surface of second substrate with upper surface of first substrate to make image sensing areas in through holes; removing portions of tape film and second substrate, wherein remained tape film and second substrate form cavities including sidewalls made of second substrate and caps sealing sidewalls and made of tape film, and remained second substrate also covers pads; removing portions of remained second substrate to expose pads; slicing first substrate to form single image sensor chips including image sensing areas and pads; and electrically connecting pads with circuits on third substrate through wires. Pollution or damage to image sensing areas may be avoided. | 2015-05-21 |
20150137295 | TWO COLOR DETECTOR LEVERAGING RESONANT CAVITY ENHANCEMENT FOR PERFORMANCE IMPROVEMENT - Methods and structures for providing single-color or multi-color photo-detectors leveraging cavity resonance for performance benefits. In one example, a radiation detector ( | 2015-05-21 |
20150137296 | Color Filter Array and Micro-Lens Structure for Imaging System - A color filter array and micro-lens structure for imaging system and method of forming the color filter array and micro-lens structure. A micro-lens material is used to fill the space between the color filters to re-direct incident radiation, and form a micro-lens structure above a top surface of the color filters. | 2015-05-21 |
20150137297 | METHODS OF FORMING IMAGING DEVICE LAYERS USING CARRIER SUBSTRATES - An array of color filter elements may be formed over an array of photodiodes in an integrated circuit for an imaging device using a carrier substrate. The carrier substrate may have a planar surface with a release layer. A layer of color filter material may be applied to the release layer. The carrier substrate may then be flipped and the layer of color filter material may be bonded to the integrated circuit. Heat may be applied to activate the release layer and the carrier substrate may be removed at the interface between the release layer and the color filter material. The layer of color filter material may be patterned either before bonding the layer of color filter material or after the carrier substrate is removed. A layer of microlenses may be formed over the array of color filter elements using a carrier substrate. | 2015-05-21 |
20150137298 | LIGHT DETECTION DEVICE - A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes operating in Geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel. A mounting substrate is configured so that a plurality of electrodes corresponding to the respective channels are arranged on a third principal surface side and so that a signal processing unit for processing output signals from the respective channels is arranged on a fourth principal surface side. In a semiconductor substrate, through-hole electrodes electrically connected to the signal lines are formed for the respective channels. The through-hole electrodes and the electrodes are electrically connected through bump electrodes. | 2015-05-21 |
20150137299 | SOLID STATE IMAGING DEVICE AND MANUFACTURING METHOD FOR SOLID STATE IMAGING DEVICE - There is provided a solid state imaging device according to the embodiment. The solid state imaging device includes an imaging area and an element isolation unit having a light shielding effect. In the imaging area, a plurality of photoelectric conversion elements is two-dimensionally arranged in a matrix in a semiconductor layer. The element isolation unit is embedded so as to surround a light-receiving region of each photoelectric conversion element. A center position of an opening region surrounding the light-receiving region is positioned on the center side of the imaging area than a corresponding center position of the light-receiving region. | 2015-05-21 |
20150137300 | Infrared Sensor Device and Method for Producing an Infrared Sensor Device - An infrared sensor device includes a semiconductor substrate, at least one sensor element that is micromechanically formed in the semiconductor substrate, and at least one calibration element, which is micromechanically formed in the semiconductor substrate, for the sensor element. An absorber material is arranged on the semiconductor substrate in the area of the sensor element and the calibration element. One cavern each is formed in the semiconductor substrate substantially below the sensor element and substantially below the calibration element. The sensor element and the calibration element are thermally and electrically isolated from the rest of the semiconductor substrate by the caverns. The infrared sensor device has high sensitivity, calibration functionality for the sensor element, and a high signal-to-noise ratio. | 2015-05-21 |
20150137301 | MANUFACTURING METHOD FOR SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE - A method for manufacturing a solid-state imaging device comprises a first step of preparing an imaging element including a second principal surface having an electrode arranged thereon, and a photoelectric converter part configured to photoelectrically convert the incident energy line so as to generate a signal charge; a second step of preparing a support substrate, provided with at least one through hole extending in a thickness direction thereof, having a third principal surface; a third step of aligning the imaging element and the support substrate with each other so that the one electrode is exposed out of the one through hole while the second and third principal surfaces oppose each other and joining the imaging element and the support substrate to each other; and a fourth step of embedding a conductive member in the through hole after the third step. | 2015-05-21 |
20150137302 | High Speed Backside Illuminated, Front Side Contact Photodiode Array - The present specification discloses front-side contact back-side illuminated (FSC-BSL) photodiode array having improved characteristics such as high speed of each photodiode, uniformity of the bias voltage applied to different photodiode, low bias voltage, reduced resistance of each photodiode, and an associated reduction in noise. The photodiode array is made of photodiodes with front metallic cathode pads, front metallic anode pad, back metallic cathode pads, n+ doped regions and a p+ doped region. The front metallic cathode pads physically contact the n+ doped regions and the front metallic anode pad physically contacts the p+ doped region. The back metallic cathode pads physically contact the n+ doped region. | 2015-05-21 |
20150137303 | MECHANISMS FOR FORMING MICRO-ELECTRO MECHANICAL DEVICE - Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a substrate and a MEMS sensor over the substrate. The MEMS sensor includes a floating heater disposed over the substrate. The MEMS sensor further includes a heat sink disposed over the substrate and at a side of the floating heater, and the heat sink has an air gap with the floating heater. The MEMS sensor further includes a first plurality of vias formed through the heat sink and thermally connected to the first substrate. | 2015-05-21 |
20150137304 | STRUCTURE AND FABRICATION METHOD OF A HIGH PERFORMANCE MEMS THERMOPILE IR DETECTOR - The invention involves structure and fabrication method of a high performance IR detector. The structure comprises a substrate; a releasing barrier band on the substrate; a thermal isolation chamber constructed by the releasing barrier band; a black silicon-based IR absorber located right above the thermal isolation chamber and the black silicon-based IR absorber is set on the releasing barrier band; a number of thermocouples are set around the lateral sides of the black silicon-based IR absorber. The thermopiles around the black silicon-based IR absorber are electrically connected in series. The cold junctions of the thermopile are connected to the substrate through the first thermal-conductive-electrical-isolated structures as well as the heat conductor under the first thermal-conductive-electrical-isolated structures. The hot junctions of the thermopile are in contact with the IR absorber through the second thermal-conductive-electrical-isolated structures, and the second thermal-conductive-electrical-isolated structures are located above the releasing barrier band. The structure of such detector is simple, and it is easy to implement and can also be monolithicly integrated. Such detector has high responsivity and detection rate, and is CMOS-compatible, thus can be used widely in a safe and reliable manner. | 2015-05-21 |
20150137305 | PROTECTIVE STRUCTURE AND METHOD FOR PRODUCING A PROTECTIVE STRUCTURE - Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode. | 2015-05-21 |
20150137306 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An N type diffusion layer in which a high-side circuit region is disposed is formed from a surface of a P type epitaxial layer covering a surface of a P type semiconductor substrate to reach the surface of the semiconductor substrate. An N type high breakdown voltage isolation region is formed with a prescribed width to surround high-side circuit region. High breakdown voltage isolation region includes a corner portion located along a corner pattern of rectangular high-side circuit region, and a linear portion located along a linear pattern thereof. The concentration of an impurity in an N type diffusion layer of corner portion is set to be higher than the concentration of an impurity in an N type diffusion layer of linear portion. | 2015-05-21 |
20150137307 | Integrated Circuit Assembly with Faraday Cage - An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer. The third electrically conductive interconnect layer forms a second electrically conductive plate below the electrically conductive ring and the region of the semiconductor layer. The plurality of electrically conductive vias electrically couple the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate. The electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device. | 2015-05-21 |
20150137308 | SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET - A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region. | 2015-05-21 |
20150137309 | Methods of Fabricating Isolation Regions of Semiconductor Devices and Structures Thereof - Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device. | 2015-05-21 |
20150137310 | AIR BRIDGE STRUCTURE HAVING DIELECTRIC COATING - A substrate having an air bridge structure with end portions disposed and supported on the substrate and an elevated portion disposed between the end portions is coated with a protective layer. The protective layer is patterned to: leave portions of the protective layer over elevated portion and at least over the end portions of a region under the elevated portion of the air bridge structure; and remove portions over adjacent portions of the substrate. A dielectric material having a thickness greater than the height of the air bridge structure is deposited over the patterned protective layer portions remaining over elevated portion and over the adjacent portions of the substrate, the patterned temporary coating preventing the dielectric material from passing into the region under the elevated portion of the air bridge structure. The dielectric material is patterned to remove portions of the dielectric material over the patterned protective layer remaining over elevated portion while leaving the dielectric material over the adjacent portions of the substrate. The patterned protective layer portions remaining over elevated portion are removed while leaving the dielectric material over the adjacent portions of the substrate. | 2015-05-21 |
20150137311 | Thin Beam Deposited Fuse - A back-end-of-line thin ion beam deposited fuse ( | 2015-05-21 |
20150137312 | METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY - Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps. | 2015-05-21 |
20150137313 | Coil Arrangement with Metal Filling - Devices, methods and production devices that relate to the forming of a coil on a semiconductor substrate are provided. Arranged within the coil is a metal filling, for example with a density of less than 20%. | 2015-05-21 |
20150137314 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member. | 2015-05-21 |
20150137315 | DRAM MIM Capacitor Using Non-Noble Electrodes - A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material. | 2015-05-21 |
20150137316 | SEMICONDUCTOR DEVICE INCLUDING A RESISTOR AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer. | 2015-05-21 |
20150137317 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING A SEMICONDUCTOR WAFER AND METHOD OF PRODUCING A COMPOSITE WAFER - A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer. | 2015-05-21 |
20150137318 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING A SEMICONDUCTOR WAFER AND METHOD OF PRODUCING A COMPOSITE WAFER - A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer, a first semiconductor crystal layer, and a second semiconductor crystal layer above a semiconductor crystal layer forming wafer, wherein the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer are arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer, a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer is contained in the first semiconductor crystal layer and the second semiconductor crystal layer as an impurity, and the concentration of the first atom in the second semiconductor crystal layer is lower than the concentration of the first atom in the first semiconductor crystal layer. | 2015-05-21 |
20150137319 | III NITRIDE SEMICONDUCTOR SUBSTRATE, EPITAXIAL SUBSTRATE, AND SEMICONDUCTOR DEVICE - In a semiconductor device | 2015-05-21 |
20150137320 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region. | 2015-05-21 |
20150137321 | APPARATUS AND METHOD FOR MAGNETIC-FIELD GUIDED METAL-ASSISTED CHEMICAL ETCHING - A magnetic field-guided method of metal-assisted chemical etching comprises immersing a structure that comprises a two-dimensional magnetic pattern layer on a surface thereof in an etchant solution. The magnetic pattern layer sinks into the structure as portions of the structure directly under the magnetic pattern layer are etched. A programmable magnetic field H(t) is applied to the structure during etching to guide the sinking of the magnetic pattern layer, thereby controlling the etching of the structure in three dimensions. | 2015-05-21 |
20150137322 | Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die - A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections. | 2015-05-21 |
20150137323 | METHOD FOR FABRICATING THROUGH SILICON VIA STRUCTURE - A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure. | 2015-05-21 |
20150137324 | STARTUP CIRCUIT AND METHOD FOR AC-DC CONVERTERS - A pattern generator includes and upper chip and one or more lower chips. The upper chip includes an upper substrate and a plurality of conductive plates on the upper substrate. The plurality of conductive plates is arranged as an array. The one or more lower chips include one or more lower substrates and a plurality of driving circuits each on one of the one or more lower substrates and electrically coupled with a corresponding one of the plurality of conductive plates. The upper chip and the one or more lower chips are stacked one over another. | 2015-05-21 |
20150137325 | SEMICONDUCTOR DEVICE HAVING METAL PATTERNS AND PIEZOELECTRIC PATTERNS - Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process. | 2015-05-21 |
20150137326 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer. | 2015-05-21 |
20150137327 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer. | 2015-05-21 |
20150137328 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 2015-05-21 |
20150137329 | COMPONENT HAVING A VIA AND METHOD FOR MANUFACTURING IT - An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer. | 2015-05-21 |
20150137330 | METHOD FOR ESTIMATING THE DIFFUSION LENGTH OF METALLIC SPECIES WITHIN A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE - A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations. | 2015-05-21 |
20150137331 | POLYMERIC MATERIALS IN SELF-ASSEMBLED ARRAYS AND SEMICONDUCTOR STRUCTURES AND METHODS COMPRISING SUCH POLYMERIC MATERIALS - Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures. | 2015-05-21 |
20150137332 | CARRIER FOR A SEMICONDUCTOR LAYER - A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm. | 2015-05-21 |
20150137333 | METHODS OF SELECTIVELY FORMING A MATERIAL USING A PARYLENE COATING AND RELATED SEMICONDUCTOR STRUCTURES - Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures. | 2015-05-21 |
20150137334 | Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV - A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die. | 2015-05-21 |
20150137335 | Managing Parasitic Capacitance and Voltage Handling of Stacked Radio Frequency Devices - Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement. | 2015-05-21 |
20150137336 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, IN-MILLIMETER-WAVE DIELECTRIC TRANSMISSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND IN-MILLIMETER-WAVE DIELECTRIC TRANSMISSION SYSTEM - A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween. | 2015-05-21 |
20150137337 | SEMICONDUCTOR PACKAGE AND LEAD FRAME - A semiconductor package is disclosed, which includes: a die paddle portion; a plurality of conductive portions circumventing the die paddle portion; a power bus bar and a ground bus bar formed around the periphery of the die paddle portion; a semiconductor element attached to the die paddle portion and electrically connected to the conductive portions, the power bus bar, and the ground bus bar by a plurality of bonding wires; and an encapsulant encapsulating the semiconductor element and the bonding wires. The ground bus bar extends outward along the power bus bar and is mutually configured with the power bus bar so as to reduce the loop inductance and resistance of the power bus bar while in use. | 2015-05-21 |
20150137338 | SEMICONDUCTOR ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor assembly is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The base carrier provides a platform for the chip-on-interposer subassembly attachment, whereas the interposer provides primary fan-out routing for the chip. In the method, a buildup circuitry is electrically coupled to the interposer and an optional cover sheet or additional buildup circuitry can be provided on the chip. | 2015-05-21 |
20150137339 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate including a mounting electrode formed on both sides and a wiring; a plurality of first electronic devices mounted on the substrate; a second electronic devices mounted on the substrate; and a via through which the wiring of the substrate and the second electronic devices are connected. | 2015-05-21 |
20150137340 | EMBEDDED PACKAGE SECURITY TAMPER MESH - A secure integrated circuit package is provided. The secure integrated circuit package includes a first substrate having an upper surface and a lower surface. A first plurality of solder balls are arranged in a pattern on the lower surface of the first substrate. A die is coupled to the upper surface of the first substrate. A second plurality of solder balls is coupled to the upper surface of the substrate and arranged in a ring surrounding the die. A mesh substrate including a mesh protection grid is coupled to the second plurality of solder balls. | 2015-05-21 |
20150137341 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads. | 2015-05-21 |
20150137342 | INDUCTOR/TRANSFORMER OUTSIDE OF SILICON WAFER - An integrated circuit package includes an integrated circuit and an interposer layer. The interposer layer is arranged above the integrated circuit and includes an inductor formed at least partially within the interposer layer. The inductor includes a first pair of conductive pillars including a first conductive pillar and a second conductive pillar formed within a first via and a second via, respectively. The first via and the second via are formed through the interposer layer. The inductor further includes a first conductive trace connected across first ends of the first conductive pillar and the second conductive pillar on a first surface of the interposer layer, and a first conductive interconnect structure connected between second ends of the first conductive pillar and the second conductive pillar and the integrated circuit. | 2015-05-21 |
20150137343 | ENHANCED DIE-UP BALL GRID ARRAY AND METHOD FOR MAKING THE SAME - Methods of assembling a ball grid array (BGA) package is provided. One method includes providing a tape substrate that has a first surface and a second surface, attaching a first surface of a stiffener to the first substrate surface, mounting an IC die to the second stiffener surface, mounting a heat spreader to the IC die, and attaching a plurality of solder balls to the second substrate surface. | 2015-05-21 |
20150137344 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device has a circuit board including an insulation layer, a wiring layer formed on one surface of the insulation layer, and a buffer layer formed on the other surface of the insulation layer, a semiconductor element bonded to the wiring layer, a radiator member bonded to the buffer layer of the circuit board, and a resin member to seal the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board. A method for manufacturing the semiconductor device includes bonding the buffer layer of the circuit board to the radiator member, bonding the semiconductor element to the wiring layer of the circuit board, and sealing the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board with resin after the two bonding steps. | 2015-05-21 |
20150137345 | SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER - A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability. | 2015-05-21 |
20150137346 | STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure. | 2015-05-21 |
20150137347 | ADHESIVE COMPOSITION AND SEMICONDUCTOR DEVICE USING SAME - An adhesive composition comprising silver particles containing silver atoms and zinc particles containing metallic zinc, wherein the silver atom content is 90 mass % or greater and the zinc atom content is from 0.01 mass % to 0.6 mass %, with respect to the total transition metal atoms in the solid portion of the adhesive composition. | 2015-05-21 |
20150137348 | ELECTRONIC DEVICE - In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. | 2015-05-21 |
20150137349 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. | 2015-05-21 |
20150137350 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad. | 2015-05-21 |
20150137351 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a die, a conductive post disposed adjacent to the die, and a molding surrounding the conductive post and the die, the molding includes a protruded portion protruded from a sidewall of the conductive post and disposed on a top surface of the conductive post. Further, a method of manufacturing a semiconductor device includes disposing a die, disposing a conductive post adjacent to the die, disposing a molding over the conductive post and the die, removing some portions of the molding from a top of the molding, and forming a recess of the molding above a top surface of the conductive post. | 2015-05-21 |
20150137352 | MECHANISMS FOR FORMING POST-PASSIVATION INTERCONNECT STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer. | 2015-05-21 |
20150137353 | UNDER-BUMP METAL STRUCTURES FOR INTERCONNECTING SEMICONDUCTOR DIES OR PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die. | 2015-05-21 |
20150137354 | PILLAR BUMP FORMED USING SPOT-LASER - A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump. | 2015-05-21 |
20150137355 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric. | 2015-05-21 |
20150137356 | NON-CYANIDE ELECTROLYTIC GOLD PLATING SOLUTION - The present invention provides a non-cyanogen type electrolytic gold plating solution, which can form a plating film capable of maintaining a high hardness even when the plating film is subjected to a heat treatment. A non-cyanogen type electrolytic gold plating solution of the present invention includes: a gold source including an alkaline salt of gold sulfite or ammonium of gold sulfite; and a conductive salt including sulfite and sulfate. The non-cyanogen type electrolytic gold plating solution includes a salt of at least one of iridium, ruthenium, and rhodium in a metal concentration of 1 to 3000 mg/L. Further, the non-cyanogen type electrolytic gold plating solution preferably includes a crystal adjuster. The crystal adjuster is particularly preferably thallium. | 2015-05-21 |
20150137357 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - An inventive semiconductor device includes: a first semiconductor chip; a second semiconductor chip having a front surface opposed to a front surface of the first semiconductor chip; a first electrode region including a first electrode provided between the first semiconductor chip and the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip; and a juncture portion provided between the first semiconductor chip and the second semiconductor chip as surrounding the first electrode region to connect the first semiconductor chip to the second semiconductor chip. | 2015-05-21 |
20150137358 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device according to the present invention includes: a combination object; and a chip having a front surface opposed to a front surface of the combination object. The chip includes: a multi-level wiring structure provided in the front surface of the chip; a connection electrode provided in the multi-level wiring structure and electrically connected to the combination object; an alignment mark set provided in the multi-level wiring structure and electrically isolated from the connection electrode; and an electrically conductive film provided at a higher level than the alignment mark set in association with the multi-level wiring structure to cover the alignment mark set and electrically isolated from the connection electrode. | 2015-05-21 |
20150137359 | METHOD FOR FORMING THROUGH SILICON VIA WITH WAFER BACKSIDE PROTECTION - Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV. | 2015-05-21 |
20150137360 | TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad. | 2015-05-21 |
20150137361 | Through Silicon Via Structure and Method - A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via. | 2015-05-21 |
20150137362 | REWORKABLE EPOXY RESIN AND CURATIVE BLEND FOR LOW THERMAL EXPANSION APPLICATIONS - A curable composition including: an epoxy resin; and an amine curing component including: an aromatic amine curing agent; and a solubilizer including an aliphatic amine, a cycloaliphatic amine, a non-volatile primary alcohol, non-volatile solvent or a mixture thereof. An electronic assembly including: a substrate; an underfill including a cured product of the curable composition on the substrate; and a ball grid array on the underfill is also disclosed. | 2015-05-21 |
20150137363 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate. | 2015-05-21 |
20150137364 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. | 2015-05-21 |
20150137365 | SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES AND METHODS - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. | 2015-05-21 |
20150137366 | REACTIVE BONDING OF A FLIP CHIP PACKAGE - An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process. | 2015-05-21 |
20150137367 | METHOD FOR FORMING TRANSPARENT ELECTRODE AND SEMICONDUCTOR DEVICE MANUFACTURED USING SAME - Provided are a method for forming a transparent electrode and a semiconductor device where the transparent electrode is formed by using the method. The method for forming a transparent electrode includes: forming a transparent electrode by using a transparent material of which resistance state is to be changed from a high resistance state into a low resistance state according to an applied electric field; and performing a forming process of changing the resistance state of the transparent electrode into the low resistance state by applying a voltage to the transparent electrode, so that the transparent electrode has conductivity. Accordingly, it is possible to form the transparent electrode having good ohmic characteristic with respect to the semiconductor layer formed above or below the transparent electrode and high transmittance with respect to the light having a short wavelength in a UV wavelength range as well as the light in visible wavelength range. | 2015-05-21 |
20150137368 | LANDING STRUCTURE FOR THROUGH-SILICON VIA - Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed. | 2015-05-21 |
20150137369 | METHOD OF OPTICAL PROXIMITY CORRECTION FOR MODIFYING LINE PATTERNS AND INTEGRATED CIRCUITS WITH LINE PATTERNS MODIFIED BY THE SAME - A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension. | 2015-05-21 |
20150137370 | ELECTRICALLY CONDUCTIVE DEVICE AND MANUFACTURING METHOD THEREOF - An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube potion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer. | 2015-05-21 |
20150137371 | Nanoscale Interconnects Fabricated by Electrical Field Directed Assembly of Nanoelements - The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting nanorods from carbon nanotubes suspended in an aqueous solution. The assembled nanorods are suitable for use as nanoscale interconnects in CMOS-based devices and sensors. Metallic nanoparticles or carbon nanotubes are assembled into lithographically patterned vias by applying an external electric field. Since the dimensions of nanorods are controlled by the dimensions of vias, the nanorod dimensions can be scaled down to the low nanometer range. The aqueous assembly process is environmentally friendly and can be used to make nanorods using different types of metallic particles as well as semiconducting and metallic nanotubes. | 2015-05-21 |
20150137372 | SELF FORMING BARRIER LAYER AND METHOD OF FORMING - Methods for forming a self-forming barrier layer and the resulting devices are disclosed. Embodiments may include forming a metal line above a substrate, forming a reagent layer above the metal line and the substrate, forming a dielectric layer on the reagent layer, and transforming the reagent layer into a self-forming barrier layer. | 2015-05-21 |
20150137373 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES - Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions. | 2015-05-21 |
20150137374 | COPPER WIRE AND DIELECTRIC WITH AIR GAPS - Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. | 2015-05-21 |
20150137375 | COPPER WIRE AND DIELECTRIC WITH AIR GAPS - Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers. | 2015-05-21 |
20150137376 | Semiconductor Structure and Semiconductor Fabricating Process for the Same - A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer. | 2015-05-21 |
20150137377 | GRAPHENE AND METAL INTERCONNECTS WITH REDUCED CONTACT RESISTANCE - A structure including a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions, a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions, and a metal via comprising a palladium liner extends vertically and electrically connects the first metal line with the second metal line, the via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line. | 2015-05-21 |
20150137378 | Semiconductor Device having Voids and Method of Forming Same - A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening. | 2015-05-21 |
20150137379 | Fan Out Package Structure and Methods of Forming - An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening. | 2015-05-21 |
20150137380 | ELECTRONIC DEVICE INCORPORATING A RANDOMIZED INTERCONNECTION LAYER - An electronic device incorporating a randomized interconnection layer. In one example, the device includes a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern. In another example, a method of fabricating the device includes forming a set of electrodes proximate to a silicon substrate; depositing a heterogeneous layer of elements onto the substrate; etching the heterogeneous layer to form a randomized conductive pattern; and electrically coupling the electrodes to a sensing circuit and the randomized conductive pattern. | 2015-05-21 |
20150137381 | OPTICALLY-MASKED MICROELECTRONIC PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers. | 2015-05-21 |
20150137382 | SELF-ALIGNMENT FOR REDISTRIBUTION LAYER - An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. | 2015-05-21 |
20150137383 | THIN SUBSTRATE AND MOLD COMPOUND HANDLING USING AN ELECTROSTATIC-CHUCKING CARRIER - Thin substrates and mold compound handling is described using an electrostatic-chucking carrier. In one example, a first part of a plurality of silicon chip packages is formed on a front side of a silicon substrate wafer at a first processing station. An a carrier wafer of an electrostatic chuck is attached over the front side of the silicon wafer. The substrate wafer is moved to a second processing station. A second part of the plurality of silicon chip packages are formed on a back side of the silicon wafer at a second processing station. The electrostatic chuck is then released. | 2015-05-21 |
20150137384 | SEMICONDUTOR DEVICE WITH THROUGH-SILICON VIA-LESS DEEP WELLS - Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers. Redistribution layers may be formed on a subset of the contacts and a dielectric layer may be formed on the silicon carrier and formed redistribution layers. Vias may be formed through the dielectric layer to a second subset of the contacts and second redistribution layers may be formed on the dielectric layer. A semiconductor die may be electrically coupled to the second formed redistribution layers and formed vias. The semiconductor die and top surface of the dielectric layer may be encapsulated and the silicon carrier may be thinned to a thickness of the contacts or may be completely removed. | 2015-05-21 |
20150137385 | INTEGRATED CIRCUITS WITH CLOSE ELECTRICAL CONTACTS AND METHODS FOR FABRICATING THE SAME - Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point. | 2015-05-21 |
20150137386 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction. | 2015-05-21 |
20150137387 | INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer. | 2015-05-21 |
20150137388 | SEMICONDUCTOR DEVICES - A semiconductor device includes a first low-k dielectric layer structure including at least one first low-k dielectric layer sequentially stacked on a substrate, a via structure extending through at least a portion of the substrate and the first low-k dielectric layer structure, and a first blocking layer pattern structure spaced apart from the via structure in the first low-k dielectric layer structure. The first blocking layer pattern structure surrounds a sidewall of the first blocking layer structure. | 2015-05-21 |