21st week of 2013 patent applcation highlights part 18 |
Patent application number | Title | Published |
20130126983 | Semiconductor Architecture Having Field-effect Transistors Especially Suitable for Analog Applications - An insulated-gate field-effect transistor ( | 2013-05-23 |
20130126984 | Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer - When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process. | 2013-05-23 |
20130126985 | (110) SURFACE ORIENTATION FOR REDUCING FERMI-LEVEL-PINNING BETWEEN HIGH-K DIELECTRIC AND GROUP III-V COMPOUND SEMICONDUCTOR SUBSTRATE - A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer. | 2013-05-23 |
20130126986 | GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES - A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region. | 2013-05-23 |
20130126987 | PHYSICAL QUANTITY SENSOR AND METHOD OF MAKING THE SAME - A first sealing layer having a frame-like shape and a first contact layer are formed on a back surface of a frame portion of a sensor substrate. The first contact layer is separated from the first sealing layer, extends through a functional member and an insulation layer, and is electrically connected to the functional member and a first base member. A second sealing layer and a second contact layer are formed on a surface of a wiring substrate. The second sealing layer faces the first sealing layer. The second contact layer is separated from the second sealing layer, extends through the insulation layer, and is electrically connected to the second base member. The sealing layers are eutectically bonded to each other. The contact layers are electrically connected to each other, and thereby the first and second base members and the frame portion have the same potential. | 2013-05-23 |
20130126988 | SEMICONDUCTOR SENSOR DEVICE WITH FOOTED LID - A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid. | 2013-05-23 |
20130126989 | Microstructure Device with an Improved Anchor - A microelectromechanical system (MEMS) device includes a substrate and an oxide layer formed on the substrate. A cavity is etched in the oxide layer. A microstructure device layer is bonded to the oxide layer, over the cavity. The microstructure device layer includes a substantially solid microstructure MEMS device formed in the microstructure device layer and suspended over a portion of the cavity. An anchor is formed in the device layer and configured to support the microstructure device, the anchor having an undercut in the oxide layer. The undercut has a length along the anchor that is less than one-half a length of an outer boundary dimension of the microstructure MEMS device. | 2013-05-23 |
20130126990 | SENSOR MANUFACTURING METHOD AND MICROPHONE STRUCTURE MADE BY USING THE SAME - A sensor manufacturing method and a microphone structure produced by using the same. Wherein, thermal oxidation method is used to form a sacrifice layer of an insulation layer on a silicon-on-insulator (SOI) substrate or a silicon substrate, to fill patterned via in said substrate. Next, form a conduction wiring layer on the insulation layer. Since the conduction wiring layer is provided with holes, thus etching gas can be led in through said hole, to remove filling in the patterned via, to obtain an MEMS sensor. Or after etching of the conduction wiring layer, deep reactive-ion etching is used to etch the silicon substrate into patterned via, to connect the substrate electrically to a circuit chip. The manufacturing process is simple and the technology is stable and mature, thus the conduction wiring layer and the insulation layer are used to realize electrical isolation. | 2013-05-23 |
20130126991 | MICROMECHANICAL FUNCTIONAL APPARATUS, PARTICULARLY A LOUDSPEAKER APPARATUS, AND APPROPRIATE METHOD OF MANUFACTURE - A micromechanical functional apparatus, particularly a loudspeaker apparatus, includes a substrate having a top and an underside and at least one circuit chip mounted on the underside in a first cavity. The apparatus further includes a micromechanical functional arrangement, particularly a loudspeaker arrangement, having a plurality of micromechanical loudspeakers mounted on the top in a second cavity. A covering device is mounted above the micromechanical functional arrangement on the top. An appropriate method is implemented to manufacture the micromechanical functional apparatus. | 2013-05-23 |
20130126992 | MEMS Chip Package and Method for Manufacturing an MEMS Chip Package - A MEMS chip package includes a first chip, a second chip, a first coupling element, and a first redistribution layer. The first chip has a first chip surface and a second chip surface, which is opposite the first chip surface. The second chip has a first chip surface and a second chip surface, which is opposite the first chip surface. The first coupling element couples the first chip surface of the second chip to the first chip surface of the first chip, so that a first cavity is defined between the first chip and the second chip. The first redistribution layer is mounted on the second chip surface of the second chip and is configured to provide contact with a substrate. | 2013-05-23 |
20130126993 | ELECTROMECHANICAL TRANSDUCER AND METHOD OF PRODUCING THE SAME - The present invention relates to an electromechanical transducer and a method of producing it, in which the substrate rigidity is maintained to prevent the substrate from being broken during formation of dividing grooves or a film. | 2013-05-23 |
20130126994 | CAPACITIVE PRESSURE SENSOR AND METHOD FOR MANUFACTURING SAME - The capacitive pressure sensor comprises: a substrate functioning as a lower electrode; a first insulating film formed on the substrate; a cavity formed on the first insulating film; a second insulating film formed on the first insulating film to have openings communicated with the cavity and to cover the cavity; a sealing film formed of a conductive material to seal the openings and to extend partially into the cavity through the openings; and an upper electrode formed on the second insulating film to be electrically separated from the sealing film and to overlap the cavity. | 2013-05-23 |
20130126995 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor substrate device includes a plurality of memory elements formed on the top surface of a semiconductor substrate, interlayer insulating films buried between the adjacent memory elements, a protection film formed on sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements, and contacts formed in the interlayer insulating films. The protection film includes a first protection film formed on the sides of each of the memory elements and the top surface of the semiconductor substrate between the adjacent memory elements and a second protection film formed on the first protection film. The first protection film is made of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and the second protection film is made of a boron film or a boron nitride film. | 2013-05-23 |
20130126996 | MAGNETIC MEMORY DEVICE - A magnetic memory device using magnetic resistance is provided. The magnetic memory device may include a magnetic memory layer comprising a plurality of magnetic layers; and a tunnel barrier layer provided between the plurality of magnetic layers; and a stress-generating layer for applying stress to the tunnel barrier layer. | 2013-05-23 |
20130126997 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 2013-05-23 |
20130126998 | RADIATION DETECTORS AND METHODS OF FABRICATING RADIATION DETECTORS - Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 μm to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions. | 2013-05-23 |
20130126999 | RADIATION DETECTORS AND METHODS OF FABRICATING RADIATION DETECTORS - Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps. The method also includes growing a passivation oxide layer on a top of the polished first surface and depositing patterned metal contacts on a top of the passivation oxide layer. The method further includes applying a protecting layer on the patterned deposited metal contacts, etching a second surface of the semiconductor and applying a monolithic cathode electrode on the etched second surface of the semiconductor. The method additionally includes removing the protecting layer from the patterned metal contacts on the first surface, wherein the patterned metal contacts are formed from one of (i) reactive metals and (ii) stiff-rigid metals for producing inter-band energy-levels in the passivation oxide layer. | 2013-05-23 |
20130127000 | Interposer Package For CMOS Image Sensor And Method Of Making Same - An image sensor package and method of manufacture that includes a crystalline handler with conductive elements extending therethrough, an image sensor chip disposed in a cavity of the handler, and a transparent substrate disposed over the cavity and bonded to both the handler and image sensor chip. The transparent substrate includes conductive traces that electrically connect the sensor chip's contact pads to the handler's conductive elements, so that off-chip signaling is provided by the substrate's conductive traces and the handler's conductive elements. | 2013-05-23 |
20130127001 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including a silicon-containing substrate, a photo-sensor chip disposed on the silicon-containing substrate, a plurality of conductive lines electrically connected to the silicon-containing substrate and the photo-sensor chip, an encapsulating layer encapsulating the photo-sensor chip and the conductive lines, and a colloid lens disposed on the encapsulating layer. With the photo-sensor chip stacked on the silicon-containing substrate, a circuit board may have a reduced region that is occupied by the semiconductor package. A method of fabricating the semiconductor package is also provided. | 2013-05-23 |
20130127002 | SOLID STATE IMAGING DEVICE - A CCD image sensor, being a solid state imaging device, has four types of pixels, first to fourth pixels. The first to fourth pixels are arranged in a predetermined pattern. Each of the pixels has a PD and a microlens. Each of the microlens is arranged with its optical axis center eccentric or shifted in a predetermined direction from a center of a light receiving surface of the PD. A part of the microlens overlaps one or more adjacent pixels. | 2013-05-23 |
20130127003 | SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD OF THE SAME AND ELECTRONIC EQUIPMENT - Disclosed herein is a solid-state imaging element including: a transfer section configured to transfer charge generated simultaneously by a photoelectric conversion section in all pixels to a memory section and have a metal gate; and a light-shielding section formed by filling a metal into a groove portion formed by digging an interlayer insulating film around the transfer section. | 2013-05-23 |
20130127004 | Image Sensor Module Package and Manufacturing Method Thereof - An image sensor module includes a substrate, a circuit layer, a flip chip, an insulating layer, and a conducting layer. The substrate has at least one transparent area and defines a first surface and a second surface. The circuit layer is provided on the first surface of the substrate. The flip chip is connected to the circuit layer. The insulating layer substantially encases the flip chip and a part of the circuit layer, wherein the insulating layer has at least one groove at a lateral side of said insulating layer thereof each provided with a metal layer. The conducting layer is provided on a top surface of the insulating layer, wherein the conducting layer is electrically connected to the circuit layer via the metal layer. | 2013-05-23 |
20130127005 | PHOTOVOLTAIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A photovoltaic device and a method of manufacturing the same are disclosed. In one embodiment, the device includes i) a semiconductor substrate, ii) a first conductive semiconductor layer formed on a first region of the semiconductor substrate and iii) a first transparent conductive layer formed on the first conductive semiconductor layer. The device may further include i) a second conductive semiconductor layer formed on a second region of the semiconductor substrate, ii) a second transparent conductive layer formed on the second conductive semiconductor layer and iii) a gap passivation layer interposed between i) the first layers and ii) the second layers, wherein the gap passivation layer has a thickness greater than the sum of the thicknesses of the first layers. | 2013-05-23 |
20130127006 | GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE - A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer. | 2013-05-23 |
20130127007 | TRANSIENT VOLTAGE SUPPRESSOR WITHOUT LEAKAGE CURRENT - A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device. | 2013-05-23 |
20130127008 | THERMALLY EFFICIENT INTEGRATED CIRCUIT PACKAGE - In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits. | 2013-05-23 |
20130127009 | DEFECTED GROUND PLANE INDUCTOR - An spiral inductor ( | 2013-05-23 |
20130127010 | INTEGRATED CIRCUIT INCLUDING A DIFFERENTIAL POWER AMPLIFIER WITH A SINGLE ENDED OUTPUT AND AN INTEGRATED BALUN - An integrated circuit, including, a die with an electronic circuit embedded thereon; wherein the electronic circuit includes a differential power amplifier and pads to electronically interface with the electronic circuit; a packaging encasing the die with contact pins to connect between the integrated circuit and external elements; wires connecting between the pads and the contact pins; a converter that includes capacitors and inductors to combine the outputs from the differential power amplifier to form a single ended output at one of the contact pins; wherein inherent inductance of some of the wires serve as the inductors of the converter. | 2013-05-23 |
20130127011 | Passive Devices For 3D Non-Volatile Memory - Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. | 2013-05-23 |
20130127012 | Semiconductor Devices and Methods of Manufacturing the Same - A method of manufacturing a semiconductor device including forming on a substrate an insulating interlayer through which a capacitor contact is interposed; forming on the insulating interlayer a first upper electrode having an opening through which the capacitor contact is exposed; forming a first dielectric layer pattern on a lateral wall of the opening; forming a lower electrode on the first dielectric layer pattern formed in the opening and the capacitor contact; forming a second dielectric layer pattern on the lower electrode formed in the opening and the first dielectric layer pattern; and forming on the second dielectric layer pattern a second upper electrode so as to fill the opening and to contact the first upper electrode. The semiconductor device may prevent a lower electrode of a capacitor from collapsing. | 2013-05-23 |
20130127013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact. | 2013-05-23 |
20130127014 | HERMETIC PACKAGING OF INTEGRATED CIRCUIT COMPONENTS - A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment. | 2013-05-23 |
20130127015 | Band Gap Improvement In DRAM Capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO | 2013-05-23 |
20130127016 | METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode. | 2013-05-23 |
20130127017 | Bipolar Junction Transistor For Current Driven Synchronous Rectifier - A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-coupled distributed diode. The bipolar transistor involves many N-type collector regions. Each N-type collector region has a central hole so that P-type material from an underlying P-type region extends up into the hole. A collector metal electrode covers the central hole forming a diode contact at the top of the hole. When the distributed diode conducts, current flows from the collector electrode, down through the many central holes in the many collector regions, through corresponding PN junctions, and to an emitter electrode disposed on the bottom side of the IC. The RBJT and distributed diode integrated circuit has emitter-to-collector and emitter-to-base reverse breakdown voltages exceeding twenty volts. The collector metal electrode is structured to contact the collector regions, and to bridge over the base electrode, resulting in a low collector-to-emitter voltage when the RBJT is on. | 2013-05-23 |
20130127018 | Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 2013-05-23 |
20130127019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH SILICON VIA ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed. | 2013-05-23 |
20130127020 | MICRO DEVICE TRANSFER HEAD - A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate. | 2013-05-23 |
20130127021 | METHODS FOR ADHERING MATERIALS, FOR ENHANCING ADHESION BETWEEN MATERIALS, AND FOR PATTERNING MATERIALS, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a base material, and a developable polymer resist material is applied over the grafted polymer brush material. The resist material is at least partially miscible in the grafted polymer brush material. As such, the resist material at least partially dissolves within the grafted polymer brush material to form an intertwined material of grafted polymer brush macromolecules and resist polymer macromolecules. Adhesion between the developable polymer resist and the base material may be thereby enhanced. Also disclosed are related semiconductor device structures. | 2013-05-23 |
20130127022 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 2013-05-23 |
20130127023 | METHOD FOR PRODUCING A GRAPHENE SHEET ON A PLATINUM SILICIDE, STRUCTURES OBTAINED USING SAID METHOD AND USES THEREOF - The invention relates to a method for producing a graphene sheet on a platinum silicide, wherein the platinum silicide is in the form of a layer or a plurality of pins. | 2013-05-23 |
20130127024 | INTEGRATED CIRCUIT CHIPS WITH FINE-LINE METAL AND OVER-PASSIVATION METAL - An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads. | 2013-05-23 |
20130127025 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There are provided a semiconductor package and a manufacturing method thereof, capable of increasing integration by mounting electronic devices on both surfaces of a substrate. The semiconductor package includes a first substrate having mounting electrodes on both surfaces thereof; a plurality of electronic devices mounted on both surfaces of the first substrate; and a second substrate exposed in cavities and bonded to a bottom surface of the first substrate so as to accommodate the electronic devices mounted on the bottom surface of the first substrate in the cavities. | 2013-05-23 |
20130127026 | CONNECTING MATERIAL, METHOD FOR MANUFACTURING CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE - In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material. | 2013-05-23 |
20130127027 | PRE-ENCAPSULATED LEAD FRAMES FOR MICROELECTRONIC DEVICE PACKAGES, AND ASSOCIATED METHODS - Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers. | 2013-05-23 |
20130127028 | THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION - A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset. | 2013-05-23 |
20130127029 | TWO LEVEL LEADFRAME WITH UPSET BALL BONDING SURFACE AND DEVICE PACKAGE - A leadframe, device package, and mode of construction configured to attain a thin profile and improved thermal performance. Leadframes of this invention include a raised die attachment pad arrange above distal ends of leadframe leads. A package will further include a die electrically coupled with an underside surface of the raised die attachment pad, in one example, using ball bonds, the whole sealed in an encapsulant that exposed a bottom portion of the die and a portion of a lead. Two leadframe stacks of such packages are also disclosed as are methods of manufacture. | 2013-05-23 |
20130127030 | SEMICONDUCTOR DEVICE PACKAGING HAVING SUBSTRATE WITH PRE-ENCAPSULATION THROUGH VIA FORMATION - A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided. | 2013-05-23 |
20130127031 | CHIP-CARRIER, A METHOD FOR FORMING A CHIP-CARRIER AND A METHOD FOR FORMING A CHIP PACKAGE - Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity. | 2013-05-23 |
20130127032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened. | 2013-05-23 |
20130127033 | SEMICONDUCTOR DEVICE - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 2013-05-23 |
20130127034 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body. | 2013-05-23 |
20130127035 | THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE - Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and protective layer contacting the polymer layer and covering the cavity. | 2013-05-23 |
20130127036 | NOVEL MECHANISM FOR MEMS BUMP SIDE WALL ANGLE IMPROVEMENT - The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided. | 2013-05-23 |
20130127037 | SEMICONDUCTOR DEVICE BUILT-IN SUBSTRATE - An object of the present invention is to provide a semiconductor device built-in substrate, which can be made thin and can suppress occurrence of warpage. The present invention provides a semiconductor substrate which is featured by including a first semiconductor device serving as a substrate, a second semiconductor device placed on the circuit surface side of the first semiconductor device in the state where the circuit surfaces of the first and second semiconductor devices are placed to face in the same direction, and an insulating layer incorporating therein the second semiconductor device, and which is featured in that a heat dissipation layer is formed at least between the first semiconductor device and the second semiconductor device, and in that the heat dissipation layer is formed on the first semiconductor device so as to extend up to the outside of the second semiconductor device. | 2013-05-23 |
20130127038 | SEMICONDUCTOR DEVICE BONDED BY AN ANISOTROPIC CONDUCTIVE FILM - A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a conductive adhesive layer and an insulating adhesive layer stacked thereon, an amount of reactive monomers in the conductive adhesive layer being higher than an amount of reactive monomers in the insulating adhesive layer. | 2013-05-23 |
20130127039 | Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface - A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking. | 2013-05-23 |
20130127040 | DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY - A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package. | 2013-05-23 |
20130127041 | BALL GRID ARRAY TO PIN GRID ARRAY CONVERSION - Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package. | 2013-05-23 |
20130127042 | Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent. | 2013-05-23 |
20130127043 | MICRO SURFACE MOUNT DEVICE PACKAGING - A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages. | 2013-05-23 |
20130127044 | MICRO SURFACE MOUNT DEVICE PACKAGING - A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of die cavities are formed in a plastic carrier. In some preferred embodiments, the die cavities are formed by laser ablation. A multiplicity of dice are placed on the carrier, with each die being placed in an associated die cavity. Each of the dice preferably has a multiplicity of I/O bumps formed thereon. An encapsulant is applied over the carrier to form an encapsulant layer that covers the dice and fills portions of the cavities that are not occupied by the dice. In some preferred embodiments, the encapsulant is an epoxy material applied by screen printing and the dice are not physically attached to the carrier prior to the application of the encapsulant. In these embodiments, the epoxy encapsulant serves to secure the dice to the carrier. | 2013-05-23 |
20130127045 | MECHANISMS FOR FORMING FINE-PITCH COPPER BUMP STRUCTURES - The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures. | 2013-05-23 |
20130127046 | REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY - Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements. | 2013-05-23 |
20130127047 | CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer. | 2013-05-23 |
20130127048 | DEVICE - A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter. | 2013-05-23 |
20130127049 | Method for Stacking Devices and Structure Thereof - A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure. | 2013-05-23 |
20130127050 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip. | 2013-05-23 |
20130127051 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 2013-05-23 |
20130127052 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 2013-05-23 |
20130127053 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME - Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns. | 2013-05-23 |
20130127054 | STACKED-CHIP PACKAGES IN PACKAGE-ON-PACKAGE APPARATUS, METHODS OF ASSEMBLING SAME, AND SYSTEMS CONTAINING SAME - A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer. | 2013-05-23 |
20130127055 | MECHANISMS OF FORMING DAMASCENE INTERCONNECT STRUCTURES - The mechanisms of forming an interconnect structures described above involves using a reflowed conductive layer. The reflowed conductive layer is thicker in smaller openings than in wider openings. The mechanisms may further involve forming a metal cap layer over the reflow conductive layer, in some embodiments. The interconnect structures formed by the mechanisms described have better electrical and reliability performance. | 2013-05-23 |
20130127056 | SEMICONDUCTOR DEVICES INCLUDING DUAL DAMASCENE METALLIZATION STRUCTURES - A semiconductor device can include a dual-damascene metallization structure that may provide a reduced resistance by providing barrier layers that are different materials. The semiconductor device can include a device layer and a lower conductive layer that can be electrically connected to the device layer. A lower barrier layer can surround the lower conductive layer and an upper conductive layer can be disposed on the lower conductive layer and can be electrically connected to the lower conductive layer. An upper barrier layer can surround the upper conductive layer and can including material that is different from a material included in the lower barrier layer. | 2013-05-23 |
20130127057 | SEED LAYER PASSIVATION - A microfeature workpiece generally includes a first conducting layer, a chemisorbed layer or a monolayer directly on the first conducting layer, and a second conducting layer. The chemisorbed layer or monolayer includes a first material that may be selected from the group consisting of nitrogen-containing compounds, sulfur-containing compounds, and mixtures thereof. | 2013-05-23 |
20130127058 | LINER-FREE TUNGSTEN CONTACT - A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity. | 2013-05-23 |
20130127059 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 2013-05-23 |
20130127060 | UNDER BUMP PASSIVES IN WAFER LEVEL PACKAGING - Under bump passive structures in wafer level packaging and methods of fabricating these structures are described. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology. | 2013-05-23 |
20130127061 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system is provided forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segment of the first bond pad, forming an I/O ring having the first I/O cell, forming an integrated circuit die having the I/O ring, and connecting an external interconnect and the first bond pad. | 2013-05-23 |
20130127062 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 2013-05-23 |
20130127063 | SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE - A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer. | 2013-05-23 |
20130127064 | METHOD AND APPARATUS TO IMPROVE RELIABILITY OF VIAS - In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density. | 2013-05-23 |
20130127065 | CMUT DEVICES AND FABRICATION METHODS - Capacitive micromachined ultrasonic transducer (“CMUT”) devices and fabrication methods are provided. The CMUT devices can include integrated circuit devices utilizing direct connections to various CMOS electronic components. The use of integrated connections can reduce overall package size and improve functionality for use in ultrasonic imaging applications. CMUT devices can also be manufactured on multiple silicon chip layers with each layer connected utilizing through silicon vias (TSVs). External power connections can be provided if high biasing voltages are required. Forward and side looking CMUT arrays can be manufactured for use in a variety of ultrasound technologies. | 2013-05-23 |
20130127066 | Integrated Circuit Including Interconnect Levels - An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area. | 2013-05-23 |
20130127067 | THROUGH SILICON VIA IN N+ EPITAXY WAFERS WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. | 2013-05-23 |
20130127068 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection. | 2013-05-23 |
20130127069 | MATRICES FOR RAPID ALIGNMENT OF GRAPHITIC STRUCTURES FOR STACKED CHIP COOLING APPLICATIONS - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip and a second chip electrically and mechanically coupled by a grid of connectors. The chip stack includes a thermal interface material (TIM) between the first chip and the second chip. The TIM includes nanofibers aligned parallel to mating surfaces of the first and second chips, and a thermosetting polymer that when heated, will reduce the viscosity of the TIM to allow for optimal alignment of the carbon nanofibers. The method includes adding at least one thermosetting polymer to the TIM, dispersing nanofibers into the TIM, and heating the TIM until the thermosetting polymer un-crosslinks. The method further includes applying a magnetic field to align the graphite nanofibers and cooling the TIM until the thermosetting polymer re-crosslinks. | 2013-05-23 |
20130127070 | Stacked Seminconductor Package - Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate including at least one contact pad; an external chip laminate which includes a plurality of semiconductor chips mounted on the substrate, and which is stacked in multi-steps such that the ends at one side of the plurality of semiconductor chips alternately protrude in opposite directions to expose bonding pads which are formed on the up-face surface; at least one internal chip which is disposed in a mounting space formed between the external chip laminate and substrate so as to be electrically connected to the substrate; and a conductive wire electrically connecting the bonding pad of the semiconductor chip and the contact pad of the substrate. | 2013-05-23 |
20130127071 | EPOXY RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an epoxy resin composition for semiconductor encapsulation, including the following components (A) to (F): (A) an epoxy resin; (B) a phenol resin; (C) a curing accelerator; (D) an inorganic filler; (E) a hydrotalcite compound; and (F) a carboxyl group-containing wax having an acid value of 10 to 100 mg KOH/g. | 2013-05-23 |
20130127072 | INTEGRATED AERATION SYSTEM - The integrated aeration system utilizes a water pump for aeration. Ambient air/gas is entrained by a circulating water jet induced by the pump. The circulating water jet enters a sealed tank, The entrained gas is broken into bubbles after the impingement between the jet and a receiving pool occurs, aerating the receiving pool by water jet spray. The entrained gas/air builds up headspace pressure above the water pool, the headspace pressure being measured by a pressure gauge. The trapped air above the water pool is released when the headspace pressure increases to reach a desired value to aerate a separate tank/container as a diffused aeration or any other aeration process. | 2013-05-23 |
20130127073 | METHOD FOR STIRRING A LIQUID AND FOR INJECTING A GAS INTO THIS LIQUID, SUITABLE FOR SHALLOW BASINS - The invention relates to a device for stirring a liquid in a reactor and for injecting a gas into the said liquid in order to form a gas-liquid dispersion, comprising a) a drive device ( | 2013-05-23 |
20130127074 | SYSTEM FOR DECONTAMINATING WATER AND GENERATING WATER VAPOR - A system and method for decontaminating water and generating water vapor includes introducing contaminated water in to a vessel. The water is moved through a series of rotating trays alternately separated by stationary baffles so as to swirl and heat the water to effect the vaporization thereof to produce a vapor having at least some of the contaminants separated therefrom. The vapor is removed from the vessel for condensing apart from the separated contaminants and the remaining water. The vapor may be passed through a turbine connected to an electric generator. Sensors in a controller may be employed to adjust the speed of rotation of the trays or water input into the vessel in response to the sensed conditions. The treated water may be recirculated and reprocessed through the vessel to increase the purification thereof. | 2013-05-23 |
20130127075 | GAS-LIQUID CONTACTING PLATE, GAS-LIQUID CONTACTING LAMINATED BLOCK BODY, GAS-LIQUID CONTACTING LAMINATED STRUCTURE AND GAS PURIFICATION DEVICE - A gas-liquid contacting plate of the present invention in which a treatment liquid flows from an upper side to a lower side direction of a substrate and a part of gas being in contact with the treatment liquid is absorbed into the treatment liquid, includes a downward protruding saw teeth-shaped portion in which a lower end side of the substrate has pitches at predetermined gaps. Further, a pore group for liquid dispersion having a predetermined gap is provided in a plurality of lines, in the substrate. An arrangement thereof is a zigzag arrangement. | 2013-05-23 |
20130127076 | INSULATION FOR A STEAM CARRYING APPARATUS AND METHOD OF ATTACHMENT THEREOF - A steam dispersion system including insulation is disclosed. The steam dispersion system may include a steam dispersion tube with at least one opening defined on an outer surface of the steam dispersion tube and a hollow interior. The insulation covers at least a portion of the steam dispersion tube, the insulation defining an opening aligned with the opening of the steam dispersion tube, wherein the insulation meets 25/50 flame/smoke indexes for UL723/ASTM E-84 and has a thermal conductivity less than about 0.35 Watts/m-K (2.4 in-hr/ft̂2 deg F.). A nozzle defining a throughhole may be placed within the opening of the steam dispersion tube, the throughhole being in fluid communication with the hollow interior of the steam dispersion tube to provide a steam exit. | 2013-05-23 |
20130127077 | SILICONE HYDROGEL LENSES WITH CONVERTIBLE COMFORT AGENTS - The invention provides a silicone hydrogel contact lens including a hydrolyzable polymer. The hydrolyzable polymer can be converted by hydrolysis into a hydrophilic polymer which is capable of imparting the silicone hydrogel contact lens a hydrophilic surface without post-curing surface treatment. | 2013-05-23 |
20130127078 | Photochromic Lens - A cast photochromic lens including a photochromic film and a cast resin, curable by heat or radiation. | 2013-05-23 |
20130127079 | Method for the Production of Polyester Granulates From Highly Viscous Polyester Melts and Also Device for the Production of the Polyester Granulates - The invention relates to a method and device for the direct production of polyester granulate from a highly viscous polyester melt with a polymerisation degree of 132 to 165, as well as the granulates formed thereform. In the method, the highly viscous polyester melt is subjected to a pre-drying and drying/degassing after a hot cutting method. Hot cutting is implemented at water temperatures of 70° C. to 95° C. and with a liquid to solid ratio of 8 to 12:1. | 2013-05-23 |
20130127080 | METHOD AND SYSTEM FOR ENHANCING POLYMERIZATION AND NANOPARTICLE PRODUCTION - The various embodiments herein provide a system and method for enhancing polymerization and nanoparticles production using a disc reactor. The system comprises of a rotating disc comprising a first surface and a second surface arranged longitudinally along a single axis of rotation, a shaft attached to the rotating disc, a ring provided across the first surface and the second surface of the rotating disc, at least one feed inlet for providing a feed solution, a fluid inlet for providing a heat transfer fluid, a fluid outlet for exiting the heat transfer fluid, a product collector for collecting the produced nanoparticles and a product outlet for exiting the produced nanoparticles. The feed solution flows from the first surface to the second surface of the rotating disc due to centrifugal forces and gets accumulated on the product collector and exits from the disc reactor through the product outlet. | 2013-05-23 |
20130127081 | APPLIANCE FOR LOCALIZED HEATING OF A POLYMER MATERIAL SURFACE TO BE REPAIRED BY BLOWING A HOT FLUID INSIDE A CONFINEMENT CHAMBER - The invention provides an appliance for localized heating of a polymer material surface to be repaired by blowing a hot fluid inside a confinement chamber ( | 2013-05-23 |
20130127082 | Manufacturing Method of 3D Patterned Foam Sheet - In a manufacturing method of 3D patterned foam sheet, a foaming material is placed in a foaming mold for a foaming process, and the foaming mold has lines in a predetermined pattern formed on upper and lower walls of the foaming mold, such that after the foaming material is formed, the foaming sheet with the lines in a predetermined pattern can be produced, and matching molds engaged with each other can be used for an extrusion, and the pattern formed on the foam sheet is twisted, and a 3D stylish model with a shape matched to the shape of the mold is formed on the foam sheet. | 2013-05-23 |