21st week of 2012 patent applcation highlights part 22 |
Patent application number | Title | Published |
20120126812 | MAGNETIC RESONANCE IMAGING APPARATUS AND MAGNETIC RESONANCE IMAGING METHOD - First magnetic resonance imaging (MRI) three-dimensional heart image data includes a plurality of two-dimensional heart image data superimposed and having a resolution in at least one direction that is different from that in two other directions. A first axis is detected in the three-dimensional heart image data. A first vector is calculated as passing through the first axis and having at least a predetermined resolution and generated image data on a plane passing through the first axis and the first vector is generated from the first imaging data. A second axis is detected relating to the heart from the generated image data, the second axis being a higher precision axis than the first axis. | 2012-05-24 |
20120126813 | METHOD AND MAGNETIC RESONANCE SYSTEM TO ACQUIRE MR DATA IN A PREDEFINED THREE-DIMENSIONAL VOLUME SEGMENT - In a method and magnetic resonance (MR) apparatus to acquire MR data in a predetermined three-dimensional volume segment of an examination subject, the three-dimensional volume segment is selectively excited with an RF excitation pulse, wherein a magnetic field gradient at the same time is switched. Two phase coding gradients and an additional magnetic field gradient are switched for spatial coding and MR data are acquired depending on this. A frequency range of the RF excitation pulse is set depending on resonance frequencies of at least two substances to be acquired within the volume segment, such that a center frequency of the frequency range is caused to be located between the resonance frequencies. | 2012-05-24 |
20120126814 | PEDIATRIC COIL ASSEMBLY - In order to increase the signal to noise ratio, and thus increase the quality of images produced during pediatric MRI, a pediatric RF coil assembly includes a head coil and a flexible body coil in a single dedicated device shaped and sized for a child. The flexible body coil may be operable to at least partially surround and abut the body of the child located on the pediatric RF coil assembly, while the head coil may at least partially surround and abut the head of the child located on the pediatric RF coil assembly. In order to optimize workflow, the child may be positioned on the pediatric RF coil assembly in a first room and moved to a second room including an MRI system after the child is brought to sleep or sedated in the first room. The pediatric RF coil assembly and the child may be moved to the second room using a handle rotatably attached to the pediatric RF coil assembly, and may be positioned on a patient table of the MRI system when the imaging process is to begin. | 2012-05-24 |
20120126815 | SPINE COIL UNIT - In order to increase the speed at which a user of a magnetic resonance imaging (MRI) system may electrically or optically connect and physically attach a spine coil unit to the MRI system, the spine coil unit includes a connector extending away from a side of a spine coil housing. The spine coil unit is positioned on a patient table of the MRI system and moved along the patient table of the MRI system adjacent to or in physical contact with a corresponding MRI system-side connector. A lever rotatably attached to the spine coil housing may be rotated into a corresponding recess in the MRI system to physically attach and electrically or optically connect the connector of the spine coil housing and/or to positionally fix the spine coil housing relative to the MRI system-side connector. | 2012-05-24 |
20120126816 | METHOD OF MONITORING A HYDROCARBON RESERVOIR - A method of monitoring an extent of a hydrocarbon reservoir ( | 2012-05-24 |
20120126817 | DOWNHOLE SURVEYING UTILIZING MULTIPLE MEASUREMENTS - Certain embodiments described herein provide a measure of the misalignment of multiple acceleration sensors mounted in the downhole portion of a drill string. In certain embodiments, the measure of the misalignment corresponds to a measure of sag which can be used to provide an improved estimate of the inclination of the downhole portion of the drill string and/or the wellbore. Certain embodiments described herein provide an estimate of the magnetic interference incident upon a drilling system using multiple magnetic sensors mounted within a non-magnetic region of the downhole portion of the drilling system. Certain embodiments utilize the magnetic measurements to determine an axial interference resulting from one or more magnetic portions of the downhole portion and to provide an improved estimate of the azimuthal orientation of the downhole portion with respect to the magnetic field of the Earth. | 2012-05-24 |
20120126818 | BATTERY STATUS DETECTION SENSOR - A battery condition detection sensor ( | 2012-05-24 |
20120126819 | DETECTING DEVICE AND METHOD FOR DETECTING BATTERY STORAGE CAPACITY - A detecting device used to detect storage capacity of a battery is connected to a load by a first output terminal and a second output terminal. The detecting device includes a switch unit, a detecting unit, and a control unit. The switch unit is connected between the first and second output terminals. The detecting unit is connected to the first and second output terminals. The detecting unit detects output voltage and current of the battery when the switch is turned on and off and obtains an internal resistance of the battery according to the detected output voltage and current. The control unit controls the switch unit to turn on and off and compares the detected resistance with a reference resistance, and determines the storage capacity of the battery according to the comparison. | 2012-05-24 |
20120126820 | BATTERY PACK BURN-IN TEST SYSTEM AND METHOD - A battery pack burn-in test system comprising first and second interconnection circuits for electrically interconnecting a first and a second battery pack respectively to the system; a data communication bus for coupling to respective battery management integrated circuits (ICs) of the first and second battery packs; and a system management unit coupled to the data communication bus. The system management unit may control a charging of the first battery pack during a burn-in test from a discharging of the second battery pack. | 2012-05-24 |
20120126821 | System and Method for Testing a Radio Frequency Integrated Circuit - In an embodiment, a method of testing a radio frequency integrated circuit (RFIC) includes generating high frequency test signals using the on-chip test circuit, measuring signal levels using on-chip power detectors, and controlling and monitoring the on-chip test circuit using low frequency signals. The RFIC circuit is configured to operate at high frequencies, and an on-chip test circuit that includes frequency generation circuitry configured to operate during test modes. | 2012-05-24 |
20120126822 | SYSTEM AND METHOD FOR EVALUATING A WIRE CONDUCTOR - A method of evaluating an electrically conductive wire segment having an insulated intermediate portion and non-insulated ends includes passing the insulated portion of the wire segment through an electrically conductive brush. According to the method, an electrical potential is established on the brush by a power source. The method also includes determining a value of electrical current that is conducted through the wire segment by the brush when the potential is established on the brush. The method additionally includes comparing the value of electrical current conducted through the wire segment with a predetermined current value to thereby evaluate the wire segment. A system for evaluating an electrically conductive wire segment is also disclosed. | 2012-05-24 |
20120126823 | UNIVERSAL MATE-IN CABLE INTERFACE SYSTEM - The present document describes an assembly for connecting a test unit to a wiring harness or equipment to be tested, and a method for testing using the assembly. The assembly may comprise a test box unit, a generic mate-in interface, and at least one specific mate-in interface. The generic mate-in interface is for connection to the test box unit on one end, and to the at least one specific mate-in interfaces at the other end. The mate-in interfaces are for testing different existing wiring harnesses or equipment. Each one of the generic and specific mate-in interfaces has a specific ID. Information relating to the IDs of the connectors and the contact configuration of each mate-in interface is stored in a database of the test unit for identifying the appropriate test contacts that should be used for testing. | 2012-05-24 |
20120126824 | ANALOG CIRCUIT TEST DEVICE - The invention relates to a test device ( | 2012-05-24 |
20120126825 | SENSOR ASSEMBLY AND METHODS OF MEASURING THE PROXIMITY OF A COMPONENT TO AN EMITTER - A method for measuring a proximity of a component with respect to an emitter is provided. The method includes transmitting at least one microwave signal having a plurality of frequency components within a predefined frequency range to the emitter. At least one electromagnetic field is generated by the emitter from the microwave signal. A load is then induced to the emitter by an interaction between the component and the electromagnetic field, wherein at least one loading signal representative of the loading is reflected within a data conduit from the emitter. Moreover, the loading signal is received by at least one signal processing device. The proximity of the component with respect to the emitter is measured by the signal processing device based on the loading signal. | 2012-05-24 |
20120126826 | Sensor Assembly And Method Of Measuring The Proximity Of A Machine Component To A Sensor - A microwave sensor assembly includes a signal processing device for generating at least one microwave signal that includes a pattern of frequencies and at least one probe coupled to the signal processing device. The probe includes an emitter configured to generate an electromagnetic field from the at least one microwave signal, wherein the emitter is detuned when an object is positioned within the electromagnetic field such that a loading signal is reflected from the emitter to the signal processing device. | 2012-05-24 |
20120126827 | Sensor Assembly And Methods Of Adjusting The Operation Of A Sensor - A microwave sensor probe includes a probe housing, an emitter body coupled to the probe housing, and an emitter coupled to the emitter body. The emitter is configured to generate an electromagnetic field from at least one microwave signal. At least one electromagnetic absorbent member is configured to absorb at least one of a current transmitted through the emitter and an electromagnetic radiation generated by the emitter. | 2012-05-24 |
20120126828 | ELECTROMAGNETIC SENSOR FOR USE IN MEASUREMENTS ON A SUBJECT - A sensor unit for use in measurements on a subject is presented. The sensor unit includes a near field electromagnetic sensor and a flexible signal transmission structure, which are integral with one another by means of at least one common continuous surface. The flexible signal transmission structure is constructed from a first layer including signal connection lines associated with sensor cells near field electromagnetic sensor and a second electrically conductive layer electrically coupled to the electrically conductive material of the sensor. | 2012-05-24 |
20120126829 | METHODS AND SYSTEMS FOR MONITORING COMPONENTS USING A MICROWAVE EMITTER - A method for measuring a proximity of a component with respect to a microwave emitter is provided. The method comprises transmitting at least one microwave signal to the microwave emitter. At least one electromagnetic field is generated by the microwave emitter from the microwave signal. Moreover, the method comprises inducing a loading to the microwave emitter by an interaction between the component and the electromagnetic field, wherein at least one detuned loading signal representative of the loading is reflected within a data conduit from the microwave emitter. The detuned loading signal is received by at least one signal processing device. The signal processing device then measures the proximity of the component with respect to the microwave emitter based on the loading signal. An electrical output is generated by the signal processing device. | 2012-05-24 |
20120126830 | Sensor Assembly And Methods Of Measuring A Proximity Of A Machine Component To A Sensor - A microwave sensor assembly includes a signal generator for generating at least one microwave signal and an emitter coupled to the signal generator. The emitter is configured to generate an electromagnetic field from the at least one microwave signal, wherein the emitter is detuned when an object is positioned within the electromagnetic field such that a loading signal is generated. The microwave sensor assembly also includes a detector coupled to the emitter and to the signal generator. The detector is configured to calculate at least one of an amplitude, a phase, and a power of the loading signal at a primary frequency of the loading signal for use in measuring a proximity of an object to the emitter. | 2012-05-24 |
20120126831 | Sensor Assembly And Microwave Emitter For Use In A Sensor Assembly - A microwave emitter for use in a microwave sensor assembly that includes an emitter body includes a first arm that extends radially outward from the emitter body. The first arm is at least partially non-linear and includes at least one peak and at least one trough. The microwave emitter also includes a second arm that extends radially outward from the emitter body. The second arm includes at least one peak and at least one trough. The first arm and the second arm generate an electromagnetic field when at least one microwave signal is received. | 2012-05-24 |
20120126832 | Sensor Assembly And Methods Of Measuring A Proximity Of A Machine Component To A Sensor - A sensor assembly for use in monitoring a machine component includes a signal processing device and at least one probe. The at least one probe includes an emitter configured to generate an electromagnetic field from at least one microwave signal, wherein the emitter is detuned when a machine component is positioned within the electromagnetic field such that a loading signal is generated. The at least one probe also includes a transmitter coupled to the emitter and configured to wirelessly transmit the loading signal to the signal processing device. | 2012-05-24 |
20120126833 | NON-CONTACT STRESS MEASURING DEVICE - Apparatuses and methods for measuring stress or strain in a conductive material without physical contact with the material are provided. The device comprises an inductor circuit configured to induce an alternating current into the material along a first path; and a detector configured to detect a signal representative of the stress in the material along the first path when current is induced in the material. | 2012-05-24 |
20120126834 | Sensor Element Device and Method for Producing a Molded Body of a Sensor Element Device - A sensor element device for a capacitive contact switch for an operator control device with an operator panel has a molded body of an electrically nonconducting material. The molded body has an upper side that lies against an underside of the control panel in the assembled state. The molded body is transparently formed in certain portions in a direction perpendicular to its upper side as an illuminated indicator and is provided on its upper side with an electrically conductive coating. The electrically conductive coating serves as a capacitive sensor element of the capacitive contact switch and has at least one recess, which has been produced by means of a laser, to form a symbol. | 2012-05-24 |
20120126835 | FUEL SENSOR - An outer electrode projects from an opening, which is formed in an upper inner wall of a fuel passage, into the fuel passage. The fuel passage is adapted to conduct fuel generally in a horizontal direction. The outer electrode includes a fuel chamber in an inside of the outer electrode. An inner electrode is placed in the fuel chamber. A sensing circuit senses an alcohol concentration of the fuel based on an electrical property between the outer electrode and the inner electrode and a fuel temperature, which is sensed with a thermistor. The outer electrode includes a blocking portion and communication holes. The blocking portion limits intrusion of air bubbles, which flow along the upper inner wall of the fuel passage, into the communication holes. | 2012-05-24 |
20120126836 | MICROELECTROMECHANICAL STRUCTURE (MEMS) MONITORING - A MEMS component is monitored to determine its status. Sensors are deployed to sense the MEMS component and produce detection signals that are analyzed to determine the MEMS component state. An indicator device alerts a user of the status, particularly if the MEMS component has failed. Additionally, the MEMS component monitoring system may be practiced as a design structure encoded on computer readable storage media as part of a circuit design system. | 2012-05-24 |
20120126837 | Bumper structure of cleaning robot - A bumper structure of a cleaning robot which detects whether or not an obstacle contacts a bumper and a position of the obstacle, allows the bumper to be simply process and reduces the number of components of the cleaning robot to lower the production costs of the cleaning robot. The bumper structure includes a main body, a bumper installed on the front surface of the main body, a resistance film provided between the main body and the bumper and fixed to the main body, and a metal film provided between the main body and the bumper and fixed to the bumper such that the shape of the metal film is deformed together with the bumper and the metal film comes into contact with the resistance film when at least one obstacle contacts the bumper, so as to measure resistance values. | 2012-05-24 |
20120126838 | ELECTRICAL DEVICE FOR DETECTING MOISTURE - An electrical device for detecting moisture has a detection cable ( | 2012-05-24 |
20120126839 | METHOD AND DEVICE FOR MONITORING THE INSULATION OF UNGROUNDED DC AND AC VOLTAGE NETWORKS - The invention relates to a method and a device for monitoring the insulation of an ungrounded DC and/or AC voltage network. The method comprises the following steps: (a) generating a measurement DC voltage U | 2012-05-24 |
20120126840 | Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment - A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes. | 2012-05-24 |
20120126841 | PROBE APPARATUS AND METHOD FOR CORRECTING CONTACT POSITION - A probe apparatus includes a movable mounting table for supporting an object to be tested; a probe card disposed above the mounting table and having a plurality of probes to come into contact with electrodes of the object; a support body for supporting the probe card; and a control unit for controlling the mounting table. Electrical characteristics of the object are tested based on a signal from a tester by bringing the object and the probes into electrical contact with each other by overdriving the mounting table in a state where a test head is electrically connected with the probe card by a predetermined load. Further, one or more distance measuring devices for measuring a current overdriving amount of the mounting table are provided at one or more locations of the test head or the probe card. | 2012-05-24 |
20120126842 | TEST PROBE - A test probe for testing an object electrically includes a main body, a first probe pin mounted to and protruding out of the main body, and at least one second probe pin coupled to the main body. The at least one second probe pin is changeable from a first state of being folded into the main body to a second state of being unfolded to protrude out of the main body. When the at least one second probe pin is in the first state, the first probe pin is used to contact the object, and when the at least one second probe pin is in the second state, the at least one second probe pin takes the place of the first probe pin in making electrical connection with the object. | 2012-05-24 |
20120126843 | PROBE CARD HOLDING APPARATUS AND PROBER - A probe card holding apparatus which is provided at a prober and holds a probe card includes: a clamp mechanism which clamps a clamp head which is formed at the probe card; a clamp bar which is laid over an opening of the prober in which the probe card is inserted; and an elevator device which is provided at the clamp bar and moves up and down the clamp mechanism. | 2012-05-24 |
20120126844 | CHIP STACK DEVICE TESTING METHOD, CHIP STACK DEVICE REARRANGING UNIT, AND CHIP STACK DEVICE TESTING APPARATUS - A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested. | 2012-05-24 |
20120126845 | CONNECTOR AND SEMICONDUCTOR TESTING DEVICE INCLUDING THE CONNECTOR - A connector includes a first terminal. The first terminal includes a movable portion, and the movable portion has, on its tip side, a contact portion located on a course C of a case assembly. Further, the first terminal includes a fixed portion restricted from moving and located on a base side of the movable portion. The movable portion is elastically deformable to incline toward a side surface of an insertion hole while using the fixed portion as a fixed point. Further, the movable portion includes a hit portion between the contact portion and the fixed portion. The hit portion is located apart from the side surface of the insertion hole, and the hit portion is provided capable of hitting, midway during inclining of the movable portion toward the side surface of the insertion hole, against the side surface of the insertion hole. | 2012-05-24 |
20120126846 | METHOD FOR TESTING A PARTIALLY ASSEMBLED MULTI-DIE DEVICE, INTEGRATED CIRCUIT DIE AND MULTI-DIE DEVICE - The present invention discloses a method of testing a partially assembled multi-die device ( | 2012-05-24 |
20120126847 | POWER SUPPLY MONITOR - Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state. | 2012-05-24 |
20120126848 | MULTI-CHIP STACKED SYSTEM AND CHIP SELECT APPARATUS THEREOF - A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a first ID code and a second seed code according to a first seed code, and an i | 2012-05-24 |
20120126849 | TERMINATION CIRCUIT FOR ON-DIE TERMINATION - In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage. | 2012-05-24 |
20120126850 | Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules - The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC. | 2012-05-24 |
20120126851 | Data-Driven Integrated Circuit Architecture - The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data. | 2012-05-24 |
20120126852 | HIGH-SPEED STATIC XOR CIRCUIT - A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal. | 2012-05-24 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 2012-05-24 |
20120126854 | FREQUENCY REGENERATION CIRCUIT AND FREQUENCY REGENERATION METHOD - A frequency regeneration circuit according to the present invention compares a width of a single pulse of input data with a time width of a 1/n clock cycle defined by a phase difference of multi-phase clock signals (where n is a natural number) in order to regenerate a frequency that is 1/n of a rate of the input data. | 2012-05-24 |
20120126855 | REDUCED TEMPERATURE DEPENDENT HYSTERETIC COMPARATOR - This document discusses, among other things, apparatus and methods for controlling a hysteresis range of a voltage comparator. In an example, an apparatus can include an amplifier having a temperature dependency, a comparator configured to receive first and second currents and to provide an output voltage indicative of a hysteretic comparison of the first and second input voltages, wherein a range of hysteresis of the apparatus is controlled over a range of temperatures. In an example, the amplifier can be configured to receive first and second input voltages and to provide the first and second currents. | 2012-05-24 |
20120126856 | Adjustable Voltage Comparing Circuit and Adjustable Voltage Examining Device - In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved. | 2012-05-24 |
20120126857 | COMMAND BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - A command buffer circuit of a semiconductor apparatus includes a first buffer configured to receive a first command signal and generate a first command control signal, a second buffer configured to receive a second command signal and generate a second command control signal, a second block configured to select and output the first command control signal or the second command control signal in response to a rank control signal, and a control signal generation block configured to generate the rank control signal in response to a single rank signal and a chip select signal. | 2012-05-24 |
20120126858 | LOAD DRIVING APPARATUS - A load driving apparatus for driving a load with a constant current includes a shunt resistor and a driver circuit. A shunt current corresponding to the constant current flows though the shunt resistor. The driver circuit is connected to a first end of the shunt resistor to supply the constant current corresponding to the shunt current to the load. The driver circuit includes a reference voltage source for generating a predetermined reference voltage. The driver circuit adjusts the magnitude of the constant current by performing a feedback-control of the magnitude of the shunt current in such a manner that a first voltage corresponding to the reference voltage and a second voltage corresponding to a voltage at the first end of the shunt resistor become equal to each other. | 2012-05-24 |
20120126859 | LOAD DRIVER WITH CONSTANT CURRENT VARIABLE STRUCTURE - A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state. | 2012-05-24 |
20120126860 | GATE DRIVING CIRCUIT - A highly-reliable gate driving circuit achieved by suppressing the amount of hot-carriers generated in a MOSFET. In the gate driving circuit having NOEMI circuits, same-type NOEMI circuits are connected in series with a p-channel MOSFET constituting a gate charging circuit and an n-channel MOSFET constituting a gate discharging circuit, respectively, so as to suppress the amount of hot-carriers generated in the p-channel MOSFET and the n-channel MOSFET. | 2012-05-24 |
20120126861 | LOAD DRIVING CIRCUIT - A load driving circuit in which the off-time Toff and the fall time Tf can be improved in turn-off operation of the N-channel type MOSFET used as a high side switch. The load driving circuit uses an N-channel type power MOSFET as a high side switch connected between a power supply and a load, including a comparator circuit for comparing a gate voltage of the power MOSFET with a power-supply voltage; and a shut-off circuit for discharging the gate terminal of the power MOSFET in turn-off operation of the power MOSFET, the rate of discharging the gate terminal of the power MOSFET performed with the shut-off circuit being set such that the discharge rate provided if the gate voltage Vg is lower than the power-supply voltage Vp is slower than the rate of discharging the same provided if the gate voltage Vg is higher than the power-supply voltage Vp. | 2012-05-24 |
20120126862 | FREQUENCY DIVIDER WITH PHASE SELECTION FUNCTIONALITY - A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals. | 2012-05-24 |
20120126863 | ELECTRONIC CIRCUIT, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset. | 2012-05-24 |
20120126864 | POWER-ON RESET - This document discusses, among other things, apparatus and methods for providing power-on reset (POR) functionality using an enable circuit. In an example, an apparatus can include a supply input configured to receive a supply voltage, an enable input configured to receive an enable signal, and an inversion network configured to control an enable output using the enable signal. The inversion network can include a delay element configured to delay a first transition of the enable output in response to a rising transition of the supply voltage. | 2012-05-24 |
20120126865 | CLOCK REGENERATION CIRCUIT - A clock regeneration circuit according to an exemplary embodiment of the present invention is characterized in that a phase comparison result of serial data being inputted and a clock signal is shaped with use of the clock signal or another clock signal having a predetermined phase difference from the clock signal, and a phase of the clock signal is controlled with use of the shaped phase comparison result. | 2012-05-24 |
20120126866 | Phase-Locked Loop with Calibration Function and Associated Calibration Method - A phase-locked loop (PLL) includes a charge pump, a frequency divider, a voltage detector, a control module, and a calibration module. When a predetermined current amount and a predetermined frequency dividing amount are provided, the voltage detector measures a voltage associated with an output frequency of the PLL to generate a first reference voltage. When a test current amount and the predetermined frequency dividing amount are provided, the voltage detector again measures the voltage to generate a second reference voltage. When the predetermined current amount and a test frequency dividing amount are provided, the voltage detector again measures the voltage to generate a third reference voltage. The control module estimates a loop gain of the PLL according to the current amounts, the frequency dividing amounts and the reference voltages. The calibration module calibrates the PLL according to the loop gain. | 2012-05-24 |
20120126867 | SIGNAL PATTERN AND DISPERSION TOLERANT STATISTICAL REFERENCE OSCILLATOR - Disclosed is a statistical reference oscillator that includes: a stochastic reference clock generator which receives an input data outputs a reference signal obtained by dividing the received input data at a first frequency division ratio; a frequency divider which divides the frequency of an output signal at a second frequency division ratio and outputs a feedback signal; a frequency detector which outputs a difference signal based on a difference between the reference signal and the feedback signal; and an output signal generator which outputs the output signal based on the difference signal. | 2012-05-24 |
20120126868 | Mechanism for an Efficient DLL Training Protocol During a Frequency Change - An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit. | 2012-05-24 |
20120126869 | TIMING SKEW ERROR CORRECTION APPARATUS AND METHODS - Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result. | 2012-05-24 |
20120126870 | CIRCUIT AND METHOD FOR RAS-ENABLED AND SELF-REGULATED FREQUENCY AND DELAY SENSOR - Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product. | 2012-05-24 |
20120126871 | METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT - A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode. | 2012-05-24 |
20120126872 | Adjusting PLL Clock Source to Reduce Wireless Communication Interference - Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device. | 2012-05-24 |
20120126873 | CONSTANT CURRENT CIRCUIT AND REFERENCE VOLTAGE CIRCUIT - Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors. | 2012-05-24 |
20120126874 | INTEGRATED CIRCUIT - An integrated circuit includes a transfer unit configured to transfer an input signal having a first swing width between a first voltage and a second voltage, a driving unit configured to drive an output terminal to output an output signal having a second swing width in response to the input signal transferred from the transfer unit, and a control unit configured to control the driving unit in response to the output signal. | 2012-05-24 |
20120126875 | SEMICONDUCTOR SWITCH - According to one embodiment, a semiconductor switch includes a power supply section, a driver, and a switch section. The power supply section is configured to generate a first potential higher than a positive power supply potential, and a negative second potential. The driver is connected to the power supply section and configured to output a control signal. A potential of the control signal is set to the first potential at high level and set to the second potential at low level according to a terminal switching signal. The switch section is configured to receive the control signal and switch a connection between terminals. The driver has a first level shifter, a second level shifter and a first circuit. The first level shifter has a first high-side switch and a first low-side switch. The second level shifter has a second high-side switch and a second low-side switch. | 2012-05-24 |
20120126876 | GAIN CONTROL WITH MULTIPLE INTEGRATORS - A method according to one embodiment includes receiving an increment signal at a first integrator when a second integrator overflows; receiving a decrement signal at the first integrator when the second integrator underflows; and incrementing or decrementing a gain applied to an analog signal based on receipt of the increment or decrement signal. A system according to one embodiment includes a first integrator configured to cause incrementing of a gain applied to an analog signal based on receipt of an increment signal when a second integrator overflows, the first integrator being configured to cause decrementing of the gain applied to the analog signal based on receipt of a decrement signal when the second integrator underflows; and the second integrator. | 2012-05-24 |
20120126877 | DEMODULATION MIXING FOR A NEAR FIELD COMMUNICATIONS (NFC) DEVICE - An in-phase, quadrature phase (IQ) mixer for a near field communications (NFC) device is disclosed that includes a signal provider that provides an in-phase (I) mixing signal and a quadrature phase (Q) mixing signal so that the period of the I mixing signal is equal to a period for the Q mixing signal. A controller is configured to control the signal provider so that the average of the I mixing signal over two periods is minimized and the average of the Q mixing signal over two periods is also minimized. The controller is also configured to control the signal provider so that the average propagation delay for the I mixing signal and the Q mixing signal is minimized individually and relative to each other. | 2012-05-24 |
20120126878 | STABLE ON-RESISTANCE SWITCH CIRCUIT - This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current. | 2012-05-24 |
20120126879 | Apparatus and method for controlling power gating in an integrated circuit - A technique for controlling power gating in an integrated circuit is provided. The integrated circuit comprises a block of components to be power gated, and power gating circuitry for selectively isolating the block of components from the source voltage supply in order to achieve such power gating. Voltage regulator circuitry is used to provide a control voltage to the power gating circuitry when performing such power gating operations, the control voltage being settable to any of a plurality of predetermined voltage levels. An adaptive controller receives operating parameter data from either or both of the block of components and the power gating circuitry, that operating parameter data being indicative of leakage current. The adaptive controller then issues a feedback control signal to the voltage regulator circuitry whose value is dependent on the received operating parameter data. The voltage regulator circuitry is then responsive to the feedback control signal to change the control voltage between the plurality of predetermined voltage levels, until the operating parameter data indicates that a desired leakage current has been obtained within the power gating circuitry. Such an approach enables a balance to be achieved between reducing leakage current and reducing wear out of the power gating circuitry. | 2012-05-24 |
20120126880 | IGBT DEVICE WITH BURIED EMITTER REGIONS - An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element. | 2012-05-24 |
20120126881 | MEMS SENSOR USING MULTI-LAYER MOVABLE COMBS - A MEMS sensor comprises a substrate and at least one proof mass having a first plurality of combs, wherein the proof mass is coupled to the substrate via one or more suspension beams such that the proof mass and the first plurality of combs are movable. The MEMS sensor also comprises at least one fixed anchor having a second plurality of combs. The first plurality of combs is interleaved with the second plurality of combs. Each of the combs in the first plurality of combs and the second plurality of combs comprises a plurality of conductive layers electrically isolated from each other by one or more non-conductive layers. Each conductive layer is individually coupled to a respective electric potential such that fringing electric fields are screened to reduce motion of the first plurality of combs along a sense axis due to the fringing electric fields. | 2012-05-24 |
20120126882 | METHOD FOR SUPPRESSING INTERFERENCE - In a method for suppressing interference in a controlled variable in a control circuit, in which the actuating variable is the useful signal, the controlled variable is detected continuously, at two successive sampling instants in each case, the values of the controlled variable are subtracted, and if the absolute amount of the difference deviates by a predefinable setpoint value, at least one control parameter is modified, in such a way that the response of the actuating variable to the interference is minimized. | 2012-05-24 |
20120126883 | VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME - A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed. | 2012-05-24 |
20120126884 | DOUBLE GATED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME - A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on the opposite sidewall of the fin. The device also includes a first lower gate on the sidewall and a second lower gate on the opposite sidewall, wherein the first upper gate is formed above the first lower gate and the second upper gate is formed above the second lower gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first upper gate and second upper gate to preselect the transistors of a fin and then biasing the first lower gate and second lower gate to operate the transistors of the fin. | 2012-05-24 |
20120126885 | DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME - A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin. | 2012-05-24 |
20120126886 | METHOD AND ARRANGEMENT IN A MOBILE COMMUNICATION SYSTEM - The present invention relates to an amplifier circuit where a load modulation is applied to a segmented amplifier. This will reduce the shunt loss since the loss of a segmented amplifier is reduced by allowing each amplifier segment or combination of segments to operate to their full output power capacity, rather than limited to a lower output power which results in a higher shunt loss. Hence, operation to full capacity before adding more segments is made possible by dynamically modulating the load. | 2012-05-24 |
20120126887 | HIGH-EFFICIENCY POWER AMPLIFIER WITH MULTIPLE POWER MODES - In a representative embodiment, a multiple mode power amplifier that is operable in a first power mode and a second power mode. The multiple mode power amplifier comprises a first amplifying unit; a second amplifying unit; a first impedance matching network connected to an output port of the first amplifying unit; a second impedance matching network connected to an output port of the second amplifying unit and to the first impedance matching network; and a third impedance matching network connected to the output ports of the first and the second amplifying units. The third impedance matching network reduces a phase difference between signals amplified by the first and the second amplifying units in the first mode. | 2012-05-24 |
20120126888 | Differential Output Inductor for Class D Amplifier - A circuit includes a first input terminal for receiving a first pulsed voltage and a second input terminal for receiving a second pulsed voltage. The circuit further includes a load and an LC filter. The LC filter includes a coupled inductor pair that includes a first winding and a second winding magnetically coupled to each other. The first winding is coupled between the first input terminal and the load, and the second winding is coupled between the second input terminal and the load. A frequency of a first current flowing through the first winding is increased by the second pulsed voltage applied to the second winding. | 2012-05-24 |
20120126889 | Low Distortion Variable Gain Amplifier (VGA) - In one embodiment, an apparatus an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier, the input node receiving the asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance. | 2012-05-24 |
20120126890 | POWER AMPLIFIER - The invention relates to improving the performance of load modulation power amplifiers through the use of coupled transmission line-based power combiners. Exemplary embodiments disclosed include a power amplifier comprising an input connected to first and second amplifier stages and an output stage configured to combine phase shifted amplified outputs from the first and second amplifier stages and to provide an amplified signal at an output of the power amplifier, wherein the output stage comprises coupled first and second transmission lines connected between the output of the first amplifier stage and an output load connection. | 2012-05-24 |
20120126891 | POWER AMPLIFICATION APPARATUS - A power amplification apparatus includes a first amplifier turned on at a preset low input power; and a second amplifier connected in parallel with the first amplifier and turned off at a low input power due to a relatively low bias current. Output capacitors of the first amplifier and the second amplifier are compensated for by inductors or microstrip lines of dc power supply paths. An output matching circuit of the first amplifier includes a λ/4 transformer. An output matching circuit of the second amplifier has the phase of 0°. Input matching circuits of the first amplifier and the second amplifier include delay compensation circuits. The output matching circuit of the first amplifier, the output matching circuit of the second amplifier, and a final output matching circuit have the same impedance transformation rates. | 2012-05-24 |
20120126892 | REFERENCE VOLTAGE GENERATOR FOR BIASING AN AMPLIFIER - A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage. | 2012-05-24 |
20120126893 | POWER AMPLIFIER, POWER AMPLIFICATION METHOD, AND STORAGE MEDIUM - This invention provides a power amplifier ( | 2012-05-24 |
20120126894 | DIFFERENTIAL AMPLIFIER - A differential amplifier includes first and second current paths, each connected between first and second power supplies (PS) and respectively outputting first and second differential output signals. The first current path includes: first transistor, selectively interconnected between the first PS and a first output terminal, its gate receiving one differential input signal; second transistor, connected between the second PS and the first output terminal, its gate receiving the other differential input signal; and first switch circuit. The second current path includes: third transistor, selectively interconnected between the second PS and a second output terminal, its gate receiving one differential input signal; fourth transistor, connected between the first PS and the second output terminal, its gate receiving the other differential input signal; and second switch circuit. One of the first and second switch circuits is connected to the first PS and the other is connected to the second PS. | 2012-05-24 |
20120126895 | VARIABLE GAIN AMPLIFIER WITH FIXED BANDWIDTH - Provided is a variable gain amplifier. The variable gain amplifier includes an operational amplifier, a variable feedback impedance unit, a variable compensation impedance unit, and a variable current source. The variable feedback impedance unit is connected between an inverting input terminal and output terminal of the operational amplifier, and has a feedback impedance value which varies for gain control. The variable compensation impedance unit is connected to the inverting input terminal, and has a compensation impedance value which varies in response to change of the feedback impedance value for maintaining a constant feedback factor. The variable current source is connected to the inverting input terminal, and supplies an output current, which varies in response to change of the compensation impedance value, to the variable compensation impedance unit. | 2012-05-24 |
20120126896 | OFFSET CANCELLATION FOR CONTINUOUS-TIME CIRCUITS - One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed. | 2012-05-24 |
20120126897 | INPUT COMMON MODE CIRCUIT - A circuit provides a first current corresponding to the differential input Inn and Inp, and a second current corresponding to the common mode input Vcm. The circuit then mirrors the differential current and the common mode current to a third current and a fourth current. Based on the difference between the mirrored differential current and the mirrored common mode current, the circuit pulls up or pulls down these currents to balance the corresponding difference between the differential input and the common mode input. In effect, the circuit adjusts the input common mode voltage to a desired level, without providing an opportunity for it to rise to an unwanted level. | 2012-05-24 |
20120126898 | AMPLIFYING APPARATUS - An amplifying apparatus includes a first amplifier that amplifies an input signal on the basis of a value of a drain voltage and outputs a transmission signal, a distortion compensator that corrects a power amplitude of the input signal on the basis of a difference in power amplitude between the input signal and the transmission signal outputted from the first amplifier, a drain voltage controller that generates the drain voltage on the basis of the power amplitude of the input signal to be corrected, and a drain voltage corrector that corrects the drain voltage on the basis of the difference. | 2012-05-24 |
20120126899 | Power Amplifier with Stabilising Network - A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies. | 2012-05-24 |
20120126900 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip with first and second low noise amplifier for amplifying an inputted signal. The chip is mounted over a wiring substrate which includes first and second electrodes and first, second and third GND electrodes. The wiring substrate includes first and second conductor patterns, wherein the first conductor pattern electrically connects the first and second GND electrodes and surrounds the first and second electrodes in a plan view. The second conductor pattern electrically connects the first conductor pattern and the third GND electrode to each other and is arranged between the first and second electrodes in the plan view. The first conductor pattern extends toward an inside of the semiconductor chip from the first and second GND electrodes in the plan view. | 2012-05-24 |
20120126901 | PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE - A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC. | 2012-05-24 |
20120126902 | HIGH-PRECISION AND LOW-CONSUMPTION QUARTZ OSCILLATOR - A precise, low-consumption low-frequency oscillator includes a low-consumption low-frequency oscillator, operating at a frequency F | 2012-05-24 |
20120126903 | Stabilized Digital Quadrature Oscillator - A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively. | 2012-05-24 |
20120126904 | Oscillators And Methods Of Manufacturing And Operating The Same - Oscillators and methods of manufacturing and operating an oscillator are provided, the oscillators include a base free layer having a variable magnetization direction, and at least one oscillation unit on the base free layer. The oscillation unit may include a free layer element contacting the base free layer and having a width less than a width of the base free layer, a pinned layer element separated from the free layer element, and a separation layer element between the free layer element and the pinned layer element. A plurality of oscillation units may be arranged on the base free layer. | 2012-05-24 |
20120126905 | Assisting FGL oscillations with perpendicular anisotropy for MAMR - A spin transfer oscillator (STO) structure is disclosed that includes two assist layers with perpendicular magnetic anisotropy (PMA) to enable a field generation layer (FGL) to achieve an oscillation state at lower current density for MAMR applications. In one embodiment, the STO is formed between a main pole and write shield and the FGL has a synthetic anti-ferromagnetic structure. The STO configuration may be represented by seed layer/spin injection layer (SIL)/spacer/PMA layer 1/FGL/spacer/PMA layer 2/capping layer. The spacer may be Cu for giant magnetoresistive (GMR) devices or a metal oxide for tunneling magnetoresistive (TMR) devices. Alternatively, the FGL is a single ferromagnetic layer and the second PMA assist layer has a synthetic structure including two PMA layers with magnetic moment in opposite directions in a seed layer/SIL/spacer/PMA assist 1/FGL/spacer/PMA assist 2/capping layer configuration. SIL and PMA assist layers are laminates of (CoFe/Ni)x or the like. | 2012-05-24 |
20120126906 | Relaxation Oscillator - A relaxation oscillator and a method for offset cancellation in a relaxation oscillator. The relaxation oscillator comprises two comparator units, each comparator unit comprising a comparator element and a memory element; and a switch control generator coupled to each of the comparator units; wherein each comparator unit, in a reset state, stores an input-offset voltage on the memory element under the control of the switch control generator such that, in a comparison state, the input-offset voltage is applied to both inputs of the comparator for implementing an offset-free threshold. | 2012-05-24 |
20120126907 | OSCILLATION CIRCUIT - An oscillation circuit has a first inverter connected to an external piezoelectric resonator, a first feedback resistor disposed between input/output terminals of the first inverter, first/second variable capacitive elements connected to input/output of the first inverter, a charging circuit supplying input/output terminal with a reference current to charge the capacitive element, a comparator comparing a charging voltage of input/output with a reference voltage, and a control circuit that, in a calibration operation, at a first time, causes the charging circuit to start supply the reference current to the input terminal or the output terminal, and, at a second time after the first time, generates the control signal for setting a capacitance value of the first or second variable capacitive element so that the charging voltage becomes close to the reference voltage according to a comparison result of the comparator. | 2012-05-24 |
20120126908 | PIEZOELECTRIC VIBRATING REED, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC DEVICE, RADIO-CONTROLLED CLOCK, AND METHOD FOR MANUFACTURING PIEZOELECTRIC VIBRATING REED - This invention is provided a piezoelectric vibrating reed which is capable of decreasing variation in the amount of etching reside as much as possible and suppressing influence of vibration loss on the vibration characteristics as much as possible. A piezoelectric vibrating reed comprising a vibrating section extensive in parallel in a longitudinal direction and a base to which the vibrating section is connected at this proximal end. The base comprises at least a first section and a second section defined from the side of the proximal end of the base long the longitudinal direction. The first section is wider in a transverse direction than the second section. | 2012-05-24 |
20120126909 | DUTY CYCLE TRANSLATOR METHODS AND APPARATUS - Methods and apparatus for translating duty cycle information in duty-cycle-modulated signals to higher frequencies or higher data rates. An exemplary duty cycle translator includes a duty cycle evaluator, a high-speed digital counter, and a comparator. The duty cycle evaluator generates a first digital number representing a duty cycle of a low-frequency input duty-cycle-modulated (DCM) signal. The comparator compares the first digital number to a second digital number generated by the high-speed digital counter, and generates, based on the comparison, an output DCM signal having a higher frequency or data rate than the frequency or data rate of the low-frequency input DCM signal but a duty cycle that is substantially the same as the duty cycle of the low-frequency input DCM signal. | 2012-05-24 |
20120126910 | NONRECIPROCAL DEVICE - According to one embodiment, a nonreciprocal device includes a first component portion serving a circulator and a second component portion serving a circulator. The first component portion includes: a first carrier; a first Y junction-shaped line including three branch lines; first, second and third lines respectively connected to the three branch lines of the first Y junction-shaped line; and fourth and fifth lines. The second component portion includes: a second carrier plate provided on a back surface of the first carrier plate; a second Y junction-shaped line including three branch lines; sixth, seventh and eighth lines respectively connected to the three branch lines of the second Y junction-shaped line, one of the sixth, seventh and eighth lines being connected to one of the first, second and third lines, the other two of the sixth, seventh and eighth lines being respectively connected to the fourth and fifth lines. | 2012-05-24 |
20120126911 | ELECTROMAGNETIC WAVE ISOLATOR - Provided is an electromagnetic wave isolator having at least one microstructured surface, which provides a change in electromagnetic properties across the depth of the microstructured surface. | 2012-05-24 |