21st week of 2016 patent applcation highlights part 58 |
Patent application number | Title | Published |
20160148917 | COOLING DEVICE FOR ELECTRONIC COMPONENTS - A cooling device for electronic components is a combination of substrate (aluminum nitride substrate—thermoelectric elements—aluminum nitride substrate) and utilizing the temperature difference generated by two top and bottom ends of the cooling device to effectively remove the heat generated by the electronic components. This cooling device not only can effectively reduce temperature of the electronic components, but also store the power generated through its thermoelectric effect. | 2016-05-26 |
20160148918 | MEMORY DEVICES WITH CONTROLLERS UNDER MEMORY PACKAGES AND ASSOCIATED SYSTEMS AND METHODS - Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. The controller can manage data stored by the memory packages based on commands from the host. | 2016-05-26 |
20160148919 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a conducting portion, and a sealing resin. The substrate has a main surface and is formed with a recessed portion in the main surface. The conducting portion is formed on the substrate. The sealing resin is disposed in the recessed portion. The conducting portion includes a first wiring layer and a second wiring layer both formed in the recessed portion. The second wiring layer is closer to the main surface than is the first wiring layer in the normal direction of the main surface. | 2016-05-26 |
20160148920 | STACKED MICROELECTRONIC DICE EMBEDDED IN A MICROELECTRONIC SUBSTRATE - Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material. | 2016-05-26 |
20160148921 | CIRCUIT CONFIGURATION AND MANUFACTURING PROCESSES FOR VERTICAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) AND EMI FILTER - A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter. | 2016-05-26 |
20160148922 | DISPLAY APPARATUS - A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate signals in response to the gate control signal provided from the gate control lines, pixels configured to receive data voltages in response to the gate signals, and first and second static electricity prevention parts connected to the gate control lines in parallel configured to discharge a static electricity. Each of the first and second static electricity prevention parts is configured to form current paths, which are smaller in number than a number of the gate control lines, to discharge the static electricity and the static electricity configured to be discharged by the first static electricity prevention part has a polarity different from a polarity of the static electricity configured to be discharged by the second static electricity prevention part. | 2016-05-26 |
20160148923 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode. | 2016-05-26 |
20160148924 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An electrode ( | 2016-05-26 |
20160148925 | SMART SEMICONDUCTOR SWITCH - A semiconductor device may comprise a semiconductor substrate, which is doped with dopants of a first doping type and includes a semiconductor layer adjoining a top surface of the semiconductor substrate, the semiconductor layer being doped with dopants of a second doping type; a MOS transistor being integrated in the first semiconductor region; and a protection circuit electrically connected to a portion of the first semiconductor layer and the gate electrode and being configured to charge the gate electrode dependent on a current passing from the first semiconductor layer to a drain electrode of the MOS transistor. | 2016-05-26 |
20160148926 | INTEGRATED CIRCUIT DEVICE - The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern. | 2016-05-26 |
20160148927 | SWITCHING ELEMENT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the substrate, a first resistor portion formed on the substrate, the first resistor portion connecting the first gate pad and the second gate pad to each other, and a cell region formed on the substrate and connected to the first gate pad. Thus, measurement of the gate resistance value and selection from gate resistances of the switching element can be performed after the completion of the gate-resistor-incorporating-type switching element. | 2016-05-26 |
20160148928 | REVERSE CONDUCTING SEMICONDUCTOR DEVICE - A reverse conducting semiconductor device includes a high-concentration anode layer and a barrier metal layer, the width of the high-concentration anode layer is set larger than the width of contact of the barrier metal layer and the high-concentration anode layer, thereby ensuring that the area of contact between the barrier metal layer and the high-concentration anode layer is constant. | 2016-05-26 |
20160148929 | INTEGRATED CIRCUIT DEVICE - The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern. | 2016-05-26 |
20160148930 | SEMICONDUCTOR DEVICES INCLUDING A STRESSOR IN A RECESS AND METHODS OF FORMING THE SAME - Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region. | 2016-05-26 |
20160148931 | DUAL EPITAXY CMOS PROCESSING USING SELECTIVE NITRIDE FORMATION FOR REDUCED GATE PITCH - A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region. | 2016-05-26 |
20160148932 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film. | 2016-05-26 |
20160148933 | DUAL EPITAXY CMOS PROCESSING USING SELECTIVE NITRIDE FORMATION FOR REDUCED GATE PITCH - A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region. | 2016-05-26 |
20160148934 | SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively. | 2016-05-26 |
20160148935 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH CONTROLLED END-TO-END CRITICAL DIMENSION AND METHOD FOR FORMING THE SAME - A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm. | 2016-05-26 |
20160148936 | CONTACT WRAP AROUND STRUCTURE - A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack. | 2016-05-26 |
20160148937 | SEMICONDUCTOR DEVICE - A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer. | 2016-05-26 |
20160148938 | SEMICONDUCTOR DEVICE HAVING A GATE AND A CONDUCTIVE LINE IN A PILLAR PATTERN - A semiconductor device including a vertical gate and a method for manufacturing the same are disclosed, which prevent a floating body phenomenon, thereby increasing a cell threshold voltage and reducing leakage current, resulting in improved refresh properties of the semiconductor device. The semiconductor device includes a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns arranged along a second direction, formed over a semiconductor substrate; a gate extending in the first direction, arranged along sidewalls of the first pillar patterns, and configured to couple the first pillar patterns; a junction region formed in an upper portion of the pillar patterns; and a conductive line arranged along the sidewalls of the first pillar patterns and provided in a region disposed below the junction region and over the gate. | 2016-05-26 |
20160148939 | STATIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced. | 2016-05-26 |
20160148940 | Cross-Coupled Thyristor SRAM Semiconductor Structures and Methods of Fabrication - A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby. | 2016-05-26 |
20160148941 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device may include semiconductor patterns. The semiconductor device may include insulating layers including first regions surrounding the semiconductor patterns and second regions isolated from each other by island-type first openings and connecting the first regions adjacent to each other. The semiconductor device may include metal layers interposed between the first regions of the stacked insulating layers surrounding the semiconductor patterns, and isolated from each other by line-type second openings overlapping the first openings and the second regions. The semiconductor device may include dielectric patterns partially interposed between the insulating layers and the metal layers and exposed through the second openings. | 2016-05-26 |
20160148942 | FLASH MEMORY UNIT AND MEMORY ARRAY, AND PROGRAMMING, ERASING AND READING METHOD THEREOF - A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate. | 2016-05-26 |
20160148943 | METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY - Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors. | 2016-05-26 |
20160148944 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region. | 2016-05-26 |
20160148945 | METAL WORD LINES FOR THREE DIMENSIONAL MEMORY DEVICES - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions. | 2016-05-26 |
20160148946 | SET OF STEPPED SURFACES FORMATION FOR A MULTILEVEL INTERCONNECT STRUCTURE - A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities. | 2016-05-26 |
20160148947 | MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A memory device includes a stack including gate electrodes vertically stacked on a substrate and having a vertical hole, an active pillar disposed in the vertical hole and providing a vertical channel, a charge storage section interposed between the active pillar and the gate electrodes, a blocking dielectric interposed between the charge storage section and the gate electrodes, a tunnel dielectric interposed between the charge storage section and the active pillar, insulation filling an inner hole of the active pillar, and a fixed charge layer interposed between the filling insulation and the active pillar. Measures are taken to address phenomena in which current would otherwise be adversely affected near an interface between the vertical channel and the filling insulation. | 2016-05-26 |
20160148948 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a core insulating film, a channel film surrounding the core insulating film and extending to a higher level than an upper surface of the core insulating film to have a first end of the channel film exposed over the core insulating film, a channel pad formed over an inner wall of the first end of the channel film exposed over the core insulating film, and a contact plug coupled to the channel pad. | 2016-05-26 |
20160148949 | SEMICONDUCTOR STRUCTURES INCLUDING DIELECTRIC MATERIALS HAVING DIFFERING REMOVAL RATES - Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures. | 2016-05-26 |
20160148950 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, MANUFACTURING METHOD, AND DISPLAY DEVICE - A thin-film transistor array substrate includes a substrate and a plurality of thin-film transistors and a plurality of open areas formed on the substrate in a grid arrangement and also includes a first insulation protection layer, a color filter layer, a pixel electrode, a common electrode, a second insulation protection layer, a via, an insulation layer, and a black matrix arranged on the substrate. The first insulation protection layer is formed on the plurality of thin-film transistors and the plurality of open areas. The thin-film transistors each include a gate and a drain. The pixel electrode is connected through the via to the drain. The black matrix is located on the insulation layer or alternatively on the pixel electrode and the insulation layer to shield the thin-film transistors and the via. A display device and a manufacturing method of the thin-film transistor array substrate are also provided. | 2016-05-26 |
20160148951 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND LIQUID CRYSTAL DISPLAY SCREEN - Embodiments of the present invention disclose an array substrate and a method of manufacturing the same, and a liquid crystal display screen. The array substrate comprises gate lines, data lines arranged to intersect the gate lines, common electrode signal lines, and a plurality of pixels defined by the gate lines and the data lines, wherein each pixel comprises a drive transistor, a pixel electrode connected with one of a source electrode and a drain electrode of the drive transistor while the other one of the source electrode and the drain electrode of the drive transistor is connected with the respective data line, and a common electrode electrically connected with the respective common electrode signal line, and, the common electrode signal lines and the gate lines are formed in the same layer and extend in the same direction as the gate lines, wherein each pixel further comprises a common electrode connection line formed in the same layer as the respective common electrode signal line and extending in a direction of the respective data line, and the common electrode connection line is electrically connected with the respective common electrode signal line and the respective common electrode. Embodiments of the present invention is made so that the pixel resistance value is reduced, reducing the phenomenon of partial green picture in the liquid crystal display screen as a whole. | 2016-05-26 |
20160148952 | ARRAY SUBSTRATE, ITS MANUFACTURING METHOD AND DISPLAY DEVICE - The present disclosure relates to the field of display technology, and provides an array substrate, its manufacturing method and a display device. A signal line on the array substrate includes at least two conductive layers electrically connected to each other. When one of the conductive layers is broken, a signal may be transmitted through the other conductive layer(s). As a result, it is able to improve the reliability of the electrical connection of the signal line, thereby to improve the yield of the display device. Further, the plurality of conductive layers of the signal line is formed simultaneously in an existing process for manufacturing the conductive layer patterns for the array substrate, so it is unnecessary to form the signal line separately, and thereby the manufacturing process is simplified. | 2016-05-26 |
20160148953 | ARRAY SUBSTRATE, RADIATION DETECTOR, AND WIRING SUBSTRATE - According to the embodiment, an array substrate includes a substrate, a plurality of first wirings, a plurality of second wirings, a thin film transistor, a protective layer, and a plurality of connection parts electrically connected to each of the plurality of first wirings and the plurality of second wirings, and including a conductive material having higher corrosion resistance than a material of the plurality of first wirings and the plurality of second wirings. | 2016-05-26 |
20160148954 | MANUFACTURING METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE - The present invention provides an array substrate and a manufacturing method thereof and a display device. The manufacturing method comprises: forming a pattern including a pixel electrode and a source of a thin film transistor on a base substrate through a single patterning process, the pixel electrode is provided in a layer under a layer in which the source is located; forming a pattern including a drain, an active layer, a gate insulation layer and a gate of the thin film transistor through a single patterning process, the active layer covers the source and the drain, and is separated from the gate through the gate insulation layer; and forming a pattern including a passivation layer, a common electrode and a gate line through a single patterning process, the common electrode is a slit electrode and separated from the active layer and the pixel electrode through the passivation layer. | 2016-05-26 |
20160148955 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor array panel according to an exemplary embodiment of the present invention has a first gate insulting layer and a second gate insulating layer disposed on the first gate insulating layer. The gate electrode of the present invention is formed in an opening of the first gate insulating layer with the same height as that of the gate electrode. Therefore, the second gate insulating layer formed on the gate electrode and the first gate insulating layer renders a flat surface without a step. This may reduce or eliminate any defects caused by the step around gate electrodes, such as source electrode and/or drain electrode cracks. | 2016-05-26 |
20160148956 | TFT SUBSTRATES AND THE MANUFACTURING METHOD THEREOF - A TFT substrate and the manufacturing method thereof are disclosed. The method includes: providing a substrate; forming a gate electrode on the substrate; forming a first insulation layer and an active layer on the gate electrode in turn; forming a first black matrix on the active layer; forming a source electrode and a drain electrode on the first black matrix; forming a second insulation layer on the source electrode and the drain electrode; and forming a pixel electrode on the second insulation layer. The pixel electrode is electrically connected to the source electrode or the drain electrode via the second insulation layer. In this way, the masking effect of the display panel assembled by the TFT substrate can be ensured. In addition, the coupling capacitance between the data line and the scanning line may be reduced. | 2016-05-26 |
20160148957 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A liquid crystal display device is disclosed. The liquid crystal display device includes a first substrate, a second substrate opposite of the first substrate, and a TFT layer on the first substrate. The TFT layer includes a gate electrode metal layer, and a source/drain electrode metal layer, where the source/drain electrode metal layer overlaps the gate electrode metal layer. The display device also includes an alignment film layer on a side of the first substrate that faces the second substrate, and on a side of the second substrate that faces the first substrate. The display device also includes at least one protrusion on at least a part of a side of at least one of the gate electrode metal layer and the source/drain electrode metal layer that faces the first substrate, where the protrusion is configured to reflect incident light from a side of the first substrate. | 2016-05-26 |
20160148958 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy. | 2016-05-26 |
20160148959 | Monolithic Integration Techniques for Fabricating Photodetectors with Transistors on Same Substrate - Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues. | 2016-05-26 |
20160148960 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a photoelectric converting layer, a charge accumulating layer, and a light collecting unit are provided. The photoelectric converting layer is formed at a back surface side of a semiconductor substrate. The charge accumulating layer is formed at a front surface side of the semiconductor substrate, and accumulates charges photoelectric-converted by the photoelectric converting layer. The light collecting unit makes light incident to the back surface side of the semiconductor substrate to be collected on the photoelectric converting layer not to be incident to the charge accumulating layer. | 2016-05-26 |
20160148961 | ACTIVE PIXEL SENSOR HAVING A RAISED SOURCE/DRAIN - In some embodiments, the present disclosure relates to an integrated circuit having a device. The device has a first raised source/drain area arranged over a first source/drain region of a substrate, and a second raised source/drain area arranged over a second source/drain region of the substrate. A first gate stack has a dielectric layer positioned over the substrate and an overlying conductive layer. The first gate stack is laterally between the first raised source/drain area and the second raised source/drain area. Sidewall spacers are located over the dielectric layer and laterally between the first gate stack and the first raised source/drain area and the second raised source/drain area. | 2016-05-26 |
20160148962 | THREE LEVEL TRANSFER GATE - A method and device of driving a radiation sensor pixel is disclosed. The sensor pixel comprises a sensing element capable of charge generation as a response to impinging radiation, a floating diffusion node, a transfer gate between the sensing element and the floating diffusion node, and a charge storage device connected to the floating diffusion node via a switch. The method comprises biasing the transfer gate to three or more bias voltages OFF, ON and an intermediate bias between OFF and ON. During the period in which the transfer gate is biased to the intermediate bias, if the sensor reaches saturation, the overflown charges may be collected and part of them stored in the charge storage device, for further analysis and merging. | 2016-05-26 |
20160148963 | MULTI-LAYER EXTRAORDINARY OPTICAL TRANSMISSION FILTER SYSTEMS, DEVICES, AND METHODS - Systems, devices, and methods for an extraordinary optical transmission (EOT) image capture system comprising optical components to capture light corresponding to an object, an EOT filter device to receive the captured light and transmit wavelengths of interest, and an image sensor to receive the wavelengths of interest and capture an image corresponding to the object. The EOT filter device comprising a first EOT film with thickness T | 2016-05-26 |
20160148964 | METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE - Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. | 2016-05-26 |
20160148965 | Detector assembly using vertical wire bonds and compression decals - An imaging sensor includes a first monolithic semiconductor plate having an upper surface and a lower surface; a substantially continuous cathode deposited on the upper surface; an array of anode pads on the lower surface, each anode pad defining an individual pixel; a readout device having an array of readout pads on its upper surface, each readout pad corresponding to a respective anode pad and alignable therewith; and, a plurality of parallel, vertical wire bonds interconnecting the semiconductor plate and the readout device, with each wire connecting one anode pad to its respective readout pad. | 2016-05-26 |
20160148966 | Space-Efficient PCB-Mountable Image Sensor, And Method For Fabricating Same - A space-efficient PCB-mountable image sensor includes a semiconductor substrate having a top surface and a side surface, a bond pad on the top surface, and a conductive layer formed on the side surface and electrically connected to the bond pad. A camera module includes a PCB and a space-efficient PCB-mountable image sensor. A conductive layer of the PCB-mountable image sensor is electrically connected between the bond pad and a contact pad of the PCB. A method for fabricating a space-efficient PCB-mountable image sensor includes forming a trench next to an image sensor on a first side of an image sensor wafer, the image sensor including a bond pad. The method also includes forming a conductive layer spanning the bond pad and at least part of a side wall of the trench, and singulating the image sensor wafer along the trench. | 2016-05-26 |
20160148967 | Bonding Pad on a Back Side Illuminated Image Sensor - A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view. | 2016-05-26 |
20160148968 | SOLID-STATE IMAGE CAPTURING DEVICE AND MANUFACTURING METHOD FOR THE SAME - A solid-state image capturing device according to the present invention includes: a first-conductivity-type well; a first second-conductivity-type diffusion layer that is provided in the first-conductivity-type well and generates carriers upon being irradiated with light; a second second-conductivity-type diffusion layer that is provided in the first-conductivity-type well and stores carriers that are generated in the first second-conductivity-type diffusion layer and are transmitted thereto; and a first first-conductivity-type diffusion layer provided below the second second-conductivity-type diffusion layer, wherein an impurity concentration of the second second-conductivity-type diffusion layer is higher than an impurity concentration of the first second-conductivity-type diffusion layer, and an impurity concentration of the first first-conductivity-type diffusion layer is lower than an impurity concentration of the first-conductivity-type well. | 2016-05-26 |
20160148969 | IMAGE SENSING DEVICE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a method of manufacturing a back side illuminated (BSI) image sensor. The method includes receiving a semiconductive substrate; forming a transistor coupled to a photosensitive element at a front side of the semiconductive substrate; forming a deep trench isolation (DTI) at a back side of the semiconductive substrate; forming a doped layer conformally over the DTI; performing a microwave anneal over the back side; forming a non-transparent material inside the DTI; and forming a color filter over the doped layer. | 2016-05-26 |
20160148970 | IMAGE SENSING DEVICE AND MANUFACTURING METHOD THEREOF - Some embodiments of the present disclosure provide a method of manufacturing a back side illuminated (BSI) image sensor. The method includes receiving a semiconductive substrate; forming a photosensitive element at a front side of the semiconductive substrate; forming a transistor coupled to the photosensitive element; forming a recess at a back side of the semiconductive substrate; forming a first dielectric layer lining to a side portion of the recess and over the back side of the semiconductor substrate; covering a conductive material over the first dielectric layer and filling in the recess; forming a conductive column on top of the recess by patterning the conductive material; and forming a second dielectric layer covering the conductive column and the first dielectric layer. | 2016-05-26 |
20160148971 | METHOD FOR TRANSFERRING A LAYER OF CIRCUITS - A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, this routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate. | 2016-05-26 |
20160148972 | WAFER-LEVEL PACKAGING METHOD OF BSI IMAGE SENSORS HAVING DIFFERENT CUTTING PROCESSES - A wafer-level packaging method of BSI image sensors includes the following steps: S | 2016-05-26 |
20160148973 | LIGHT-EMITTING ELEMENT HAVING AN OPTICAL FUNCTION FILM INCLUDING A REFLECTION LAYER - A light-emitting element includes a light-emitting layer, and an optical function film. The light-emitting layer is configured to include a first plane with a first electrode, a second plane with a second electrode, and a circumferential plane connecting the first and second planes, the second plane being opposing to the first plane, and the light-emitting layer being made of a semiconductor. The optical function film is configured to include a reflection layer being able to reflect light coming from the light-emitting layer, the reflection layer being provided with first and second regions, the first region covering the second plane and the circumferential plane, the second region protruding from the first region to an outside of the light-emitting layer to expose an end plane thereof. | 2016-05-26 |
20160148974 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate including first and second areas; a first contact plug contacted with the substrate through the interlayer dielectric layer of the second area; an anti-peeling layer formed over the interlayer dielectric layer including the first contact plug; a second contact plug contacted with the substrate through the anti-peeling layer and the interlayer dielectric layer in the first area; and a variable resistance pattern contacted with the second contact plug. | 2016-05-26 |
20160148975 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first magnetic layer; a second magnetic layer; a first nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer; and a third magnetic layer disposed between the first magnetic layer and the first nonmagnetic layer, the first magnetic layer including (Mn | 2016-05-26 |
20160148976 | Simultaneous Carbon and Nitrogen Doping of Si in MSM Stack as a Selector Device for Non-Volatile Memory Application - Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on a silicon semiconductor layer doped with both carbon and nitrogen. The metal layer of the selector element can include conductive materials such as carbon, tungsten, titanium nitride, or combinations thereof. | 2016-05-26 |
20160148977 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern. | 2016-05-26 |
20160148978 | RESISTIVE RANDOM ACCESS MEMORY STRUCTURE AND METHOD FOR OPERATING RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory (RRAM) structure including a first transistor, a second transistor and a RRAM cell string is provided. The first transistor and the second transistor are cascaded by electrically connecting a first terminal of the first transistor and the second transistor. The RRAM cell string includes a plurality of memory cells connected with each other and is electrically connected to a second terminal of the first transistor. | 2016-05-26 |
20160148979 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad. | 2016-05-26 |
20160148980 | ORGANIC X-RAY DETECTORS AND RELATED SYSTEMS - Organic x-ray detectors and organic x-ray systems employing the detectors are presented. An Organic x-ray detector has a layered structure that includes a thin film transistor (TFT) array disposed on a substrate, a first electrode disposed on the TFT array, a leakage reduction layer disposed on the first electrode, an absorber layer disposed on the leakage reduction layer, a second electrode disposed on the absorber layer; and a scintillator layer disposed on the second electrode. The leakage reduction layer includes a conjugate polymer and a crosslinkable compound. A process for fabricating an organic x-ray detector is also presented. | 2016-05-26 |
20160148981 | DISPLAY DEVICE, ELECTRO-OPTICAL DEVICE, ELECTRIC EQUIPMENT, METAL MASK, AND PIXEL ARRAY - A display device includes a plurality of pixels, each of the pixels including sub-pixels of a first color, a second color and a third color, the sub-pixels of first and second color are arranged in a column direction, and the sub-pixel of third color is arranged in a row direction with respect to the sub-pixels of first and second colors. The pixels adjacent to each other in the column direction form a set of an even row and a next odd row in an even column, and form a set of an odd row and a next even row in an odd column, in the two sub-pixels of third color, a light emitting layer is continuous and light emitting regions are separated from each other, and the light emitting regions are disposed to be line symmetric with respect to a center line partitioning the two sub-pixels of third color. | 2016-05-26 |
20160148982 | ORGANIC LIGHT-EMITTING DIODE ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the invention disclose an organic light-emitting diode array substrate and a manufacturing method thereof, and a display device. The array substrate comprises: a base substrate, a thin film transistor disposed above the base substrate, an organic light-emitting diode and a filling layer, the organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, wherein, in a light transmissive region of the organic light-emitting diode array substrate, the base substrate, the filling layer and the organic light-emitting layer of the organic light-emitting diode are disposed to be sequentially abutting. | 2016-05-26 |
20160148983 | ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An OLED display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes a substrate and a semiconductor layer formed over the substrate, wherein the semiconductor layer includes a channel and a contact region formed on opposing sides of the channel. The display also includes an insulating layer formed over the semiconductor layer and having a contact hole exposing the contact region, and an OLED formed over the insulating layer, wherein the OLED is electrically connected to the contact region through the contact hole, and wherein at least a portion of the contact hole is formed directly above the contact region. | 2016-05-26 |
20160148984 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a flexible substrate, a driving layer positioned on the flexible substrate and including a thin film transistor, an element layer positioned on the driving layer and including an organic light emitting diode that is connected to the thin film transistor, a thin film encapsulation layer covering the element layer and encapsulating the element layer and the flexible substrate, and a compensation layer positioned between the element layer and the flexible substrate. | 2016-05-26 |
20160148985 | ORGANIC LIGHT EMITTING DIODE DISPLAY - Disclosed herein is an organic light emitting diode display, including a substrate, a first thin film transistor including a first active pattern on the substrate and a first gate electrode on the first active pattern, a data wire on the first gate electrode, a first interlayer insulating layer between the first gate electrode and the data wire, a second interlayer insulating layer positioned the first interlayer insulating layer and the data wire, and an organic light emitting diode positioned on the data wire and connected to the first active pattern. | 2016-05-26 |
20160148986 | TRANSISTOR, ORGANIC LIGHT EMITTING DISPLAY HAVING THE SAME, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY - A transistor including a polysilicon layer on a base substrate and including a channel region, a first ion doping region, a second ion doping region, the channel region being between the first and second ion doping regions, an average size of the grains in the channel region being greater than that of the grains in the first and second ion doping regions, a first gate electrode insulated from and overlapping the channel region, a second gate electrode insulated from the first gate electrode and overlapping the channel region, an inter-insulating layer on the second gate electrode, a source electrode on the inter-insulating layer and connected to the first ion doping region, and a drain electrode on the inter-insulating layer and connected to the second ion doping region. | 2016-05-26 |
20160148987 | OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT - Various embodiments may relate to an optoelectronic component, including an optoelectronic structure, which is designed to provide a first electromagnetic radiation, and a measuring structure, which is designed to measure electromagnetic radiation, wherein the measuring structure has an optically active structure and at least one electro-optical structure. The optically active structure is optically coupled to the optoelectronic structure. The optically active structure is designed to absorb an electromagnetic radiation in such a way that the optically active structure produces a measured signal from the absorbed electromagnetic radiation. The absorbed electromagnetic radiation at least partially includes the first electromagnetic radiation and/or at least one second electromagnetic radiation of an external radiation source. The electro-optical structure is designed in such a way that the electro-optical structure has an adjustable transmittance, such that the fraction of the second electromagnetic radiation incident on the optically active structure can be adjusted. | 2016-05-26 |
20160148988 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting device includes: a first transistor including a source electrode connected to a data line and a gate electrode connected to a scan line; a second transistor including a source electrode connected to a driving voltage and a gate electrode connected to a drain electrode of the first transistor; a capacitor connected between the gate electrode of the second transistor and the source electrode of the second transistor; an organic light emitting diode connected to a drain electrode of the second transistor; and a third transistor connected to the organic light emitting diode and a common voltage. | 2016-05-26 |
20160148989 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device includes a semiconductor on a substrate with a driving channel, an auxiliary storage electrode on the substrate with a storage electrode formed of a same material as the semiconductor and separated therefrom, a first insulating layer covering the semiconductor and the auxiliary storage electrode, a driving gate electrode overlapping the auxiliary storage electrode to define an auxiliary storage capacitor, a second insulating layer covering the driving gate electrode and the first insulating layer, a main storage electrode overlapping the driving gate electrode to define a main storage capacitor, a passivation layer covering the data wire and the second insulating layer, a pixel electrode on the passivation layer, an organic emission layer on the pixel electrode, and a common electrode on the organic emission layer. | 2016-05-26 |
20160148990 | PROCESS-COMPATIBLE DECOUPLING CAPACITOR AND METHOD FOR MAKING THE SAME - Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor. | 2016-05-26 |
20160148991 | PRECISION INTRALEVEL METAL CAPACITOR FABRICATION - A method for fabricating, within an integrated circuit (IC), a capacitor that includes a first plate formed within a recess of a metal layer that includes a second plate of the capacitor is disclosed. The method may include forming the second plate of the capacitor by creating, in a top surface of the metal layer, the recess having at least one side and a bottom and depositing a conformal dielectric film onto the at least one side and the bottom of the recess. The method may also include forming the first plate of the capacitor by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the second plate. | 2016-05-26 |
20160148992 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one. | 2016-05-26 |
20160148993 | REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTORS WITH LOW EFFECTIVE MASS CHANNELS - An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer. | 2016-05-26 |
20160148994 | SEMICONDUCTOR STRUCTURE HAVING FIELD PLATES OVER RESURF REGIONS IN SEMICONDUCTOR SUBSTRATE - A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a first doping region, a first well and a second doping region formed in the substrate; a plurality of first heavily doped regions formed in the first doping region; a plurality of conductors and a plurality of dielectrics formed on the substrate between the first heavily doped regions; a second heavily doped region formed in the first well; a third heavily doped region and a fourth heavily doped region formed in the second doping region; as well as a first gate electrode and a first gate dielectric. The first doping region, the first well, the second heavily doped region and the fourth heavily doped region have a first type of doping. The second doping region, the first heavily doped regions and the third heavily doped region have a second type of doping. | 2016-05-26 |
20160148995 | SEMICONDUCTOR DEVICE - A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate. | 2016-05-26 |
20160148996 | DIODE AND SIGNAL OUTPUT CIRCUIT INCLUDING THE SAME - A diode includes: a p-type semiconductor substrate; an n-type semiconductor layer; a p-type isolation region formed to surround a predetermined region of the n-type semiconductor layer on the p-type semiconductor substrate; an n-type buried layer formed across the p-type semiconductor layer and the n-type semiconductor layer within the predetermined region; an n-type collector wall formed in the n-type semiconductor layer; a p-type anode region and a plurality of n-type cathode regions formed in a diode formation region; and a p-type guard ring formed to surround the diode formation region in a region between the diode formation region of the surface layer of the n-type semiconductor layer and the p-type isolation region. A transistor for reducing a leakage current is formed by the p-type anode region, the p-type guard ring, and an n-type semiconductor between the p-type anode region and the p-type guard ring. | 2016-05-26 |
20160148997 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance. | 2016-05-26 |
20160148998 | FINFET STRUCTURE - A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material. | 2016-05-26 |
20160148999 | CAPACITANCE REDUCTION FOR ADVANCED TECHNOLOGY NODES - After forming source/drain contact trenches to expose source/drain regions, contact liner material layer portions are formed on sidewalls and bottom surfaces of the source/drain contact trenches. Contact material layer portions are then formed over the contact liner material layer portions to fill in the source/drain contact trenches. At least portions of the contact material layer portions and the contact liner material layer portions present on sidewalls of the source/drain contact trenches are removed to provide source/drain contacts with reduced contact capacitance. | 2016-05-26 |
20160149000 | SEMICONDUCTOR WAFER AND METHOD OF PRODUCING SEMICONDUCTOR WAFER - A semiconductor wafer includes first and second superlattice layers. The first superlattice layer includes first unit layers each of which includes first and second layers, the second superlattice layer includes second unit layers each of which includes third and fourth layers, the first layer is made of Al | 2016-05-26 |
20160149001 | GRADED HETEROJUNCTION NANOWIRE DEVICE - A device includes a source region, a drain region, and a semiconductor channel connecting the source region to the drain region. The semiconductor channel includes a source-side channel portion adjoining the source region, wherein the source-side channel portion has a first bandgap, and a drain-side channel portion adjoining the drain region. The drain-side channel portion has a second bandgap different from the first bandgap. | 2016-05-26 |
20160149002 | MEMORY DEVICE CONTAINING STRESS-TUNABLE CONTROL GATE ELECTRODES - A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material. | 2016-05-26 |
20160149003 | Methods of Manufacturing Semiconductor Devices - In methods of manufacturing a semiconductor device, a stress channel layer is formed on a semiconductor substrate. A first ion-implantation process is performed on the semiconductor substrate or the stress channel layer at a temperature ranging from about 100° C. to about 600° C. A gate structure is formed on the stress channel layer. A first source/drain region is formed at an upper portion of the stress channel layer adjacent to the gate structure. | 2016-05-26 |
20160149004 | 3D NAND With Oxide Semiconductor Channel - Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc. | 2016-05-26 |
20160149005 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME, CRYSTAL, AND MANUFACTURING METHOD FOR SAME - A semiconductor device or a crystal that suppresses phase transition of a corundum structured oxide crystal at high temperatures is provided. According to the present invention, a semiconductor device or a crystal structure is provided, including a corundum structured oxide crystal containing one or both of indium atoms and gallium atoms, wherein the oxide crystal contains aluminum atoms at least in interstices between lattice points of a crystal lattice. | 2016-05-26 |
20160149006 | SEMICONDUCTOR STRUCTURES HAVING A GATE FIELD PLATE AND METHODS FOR FORMING SUCH STRUCTURE - A field effect transistor structure having a semiconductor having a source region, a drain region, and a gate contact region disposed between the source region and the drain region; and a gate electrode having a stem section extending from a top section of the gate electrode to, and in Schottky contact with, the gate contact region. The stem section has an upper portion terminating at the top portion of the gate electrode and a bottom portion narrower than the upper portion, the bottom portion terminating at the gee contact region. The bottom portion of the stem has a step between the upper portion of the stem section and the bottom portion of the stem section in only one side of the stem section. The step of the stem section provides an asymmetric field plate for the fled effect transistor. | 2016-05-26 |
20160149007 | METHODOLOGY AND STRUCTURE FOR FIELD PLATE DESIGN - The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer. | 2016-05-26 |
20160149008 | MEMORY DEVICE HAVING BURIED GATE AND METHOD OF FABRICATING THE SAME - A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern. | 2016-05-26 |
20160149009 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a semiconductor substrate, and a gate dielectric film is provided on the semiconductor substrate. A first gate electrode is provided on the gate dielectric film. Lower end portions of side surfaces of the first gate electrode are inclined toward a center of a channel portion. A sidewall film covers the side surfaces of the first gate electrode. A void or a low dielectric material having a dielectric constant lower than that of the sidewall film is located between the lower end portions of the side surfaces of the first gate electrode and the sidewall film. | 2016-05-26 |
20160149010 | VERTICAL CELL-TYPE SEMICONDUCTOR DEVICE HAVING PROTECTIVE PATTERN - According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer. | 2016-05-26 |
20160149011 | POLY SANDWICH FOR DEEP TRENCH FILL - A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner. | 2016-05-26 |
20160149012 | VERY HIGH ASPECT RATIO CONTACT - A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening. | 2016-05-26 |
20160149013 | ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE - An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region. | 2016-05-26 |
20160149014 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved. | 2016-05-26 |
20160149015 | RECESSING RMG METAL GATE STACK FOR FORMING SELF-ALIGNED CONTACT - Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts. | 2016-05-26 |
20160149016 | REPLACEMENT METAL GATE DIELECTRIC CAP - A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate. | 2016-05-26 |