21st week of 2022 patent applcation highlights part 58 |
Patent application number | Title | Published |
20220165603 | SUPPORT SUBSTRATES, METHODS OF FABRICATING SEMICONDUCTOR PACKAGES USING THE SAME, AND METHODS OF FABRICATING ELECTRONIC DEVICES USING THE SAME - Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan. | 2022-05-26 |
20220165604 | MICRO LED ADSORPTION BODY - A micro LED vacuum adsorption body configured to vacuum-adsorb micro LEDs is proposed. More particularly, the micro LED adsorption body is capable of preventing micro LED damage when adsorbing the micro LEDs. | 2022-05-26 |
20220165605 | DEVICE FOR INSPECTING FOR COLOR UNEVENNESS IN FLEXIBLE DISPLAY - A color unevenness inspection system ( | 2022-05-26 |
20220165606 | APPARATUS FOR TREATING SUBSTRATE AND METHOD OF COUPLING SUPPORT UNIT - The present invention provides an apparatus for treating a substrate, including: a process chamber including a first body and a second body which are combined with each other to form a treatment space for treating a substrate is treated therein; a driver which moves the process chamber to an open position or a close position; a support unit which supports a substrate within the treatment space; and a fluid supply unit which supplies a fluid to the treatment space, in which the support unit includes: a support pin coupled to the first body or the second body; and a guide member which is coupled to the support pin and extends in a lateral direction of the support pin to support the substrate. | 2022-05-26 |
20220165607 | ROBOT SYSTEM, AND SLIP DETERMINATION METHOD - A robot system according to one or more embodiments may include a robot, and a control part. The robot may include one or more joints driven by an electric motor, and can hold a wafer by a holding part. The control part gives commands to the robot for control. When the robot holds and transports the wafer with the holding part, the control part performs, based on information about the electric motor, at least one of the following: determining whether slippage has occurred between the holding part and the wafer; and estimating an amount of slippage of the wafer relative to the holding part. | 2022-05-26 |
20220165608 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed. | 2022-05-26 |
20220165609 | METHODS FOR PREPARING A SOI STRUCTURE - Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure. | 2022-05-26 |
20220165610 | DEEP TRENCH INTEGRATION PROCESSES AND DEVICES - Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth. | 2022-05-26 |
20220165611 | Raised Via for Terminal Connections on Different Planes - A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal. | 2022-05-26 |
20220165612 | SELECTIVE PATTERNING OF VIAS WITH HARDMASKS - Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure. | 2022-05-26 |
20220165613 | Selective Deposition of Barrier Layer - Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece. | 2022-05-26 |
20220165614 | Systems And Methods For Workpiece Processing Using Neutral Atom Beams - Plasma processing systems and methods are provided. In one example, a system includes a processing chamber having a workpiece support. The workpiece is configured to support a workpiece. The system includes a plasma source configured to induce a plasma from a process gas in a plasma chamber to generate one or more species of negative ions. The system includes a grid structure configured to accelerate the one or more negative ions towards the workpiece. The grid structure can include a first grid plate, a second grid plate, and one or more magnetic elements positioned between the first grid plate and second grid plate to reduce electrons accelerated through the first grid plate. The system can include a neutralizer cell disposed. downstream of the grid structure configured to detach extra electrons from ions of the one or more species of negative ions to generate energetic neutral species for processing the workpiece. | 2022-05-26 |
20220165615 | METHODS FOR FILLING A GAP AND RELATED SYSTEMS AND DEVICES - Methods and related systems for filling a gap feature comprised in a substrate are disclosed. The methods comprise a step of providing a substrate comprising one or more gap features into a reaction chamber. The one or more gap features comprise an upper part comprising an upper surface and a lower part comprising a lower surface. The methods further comprise a step of subjecting the substrate to a first plasma treatment and subjecting the substrate to a second plasma treatment. Thus the upper surface is inhibited while leaving the lower surface substantially unaffected. Then, the methods comprise a step of selectively depositing a material on the lower surface. | 2022-05-26 |
20220165616 | Interconnect Structure of Semiconductor Device - A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer. | 2022-05-26 |
20220165617 | INTERCONNECT STRUCTURES - A method includes receiving an integrated circuit (IC) layout having a plurality of metal features in a metal layer. The method also includes classifying the plurality of metal features into a first type of metal features and a second type of metal features based on a dimensional criterion, where the first type of the metal features have dimensions greater than the second type of the metal features. The method further includes assigning to the first type of metal features a first metal material, and to the second type of metal features a second metal material, where the second metal material is different from the first metal material. The method additionally includes forming the plurality of metal features embedded within a dielectric layer, where each of the plurality of metal features have the respective assigned metal materials. | 2022-05-26 |
20220165618 | 3D BONDED SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A 3D bonded semiconductor device, which includes a first semiconductor device, a second semiconductor device, an isolation layer, a damascene structure, a barrier layer and a metal layer. The first semiconductor device includes a first substrate and a first conductive pad. The second semiconductor device includes a second substrate and a second conductive pad. The isolation layer covers on a backside of the second semiconductor device. The damascene structure includes a first via hole and a second via hole that respectively land on the first conductive pad and the second conductive pad at the same time, in which a first critical dimension of the first via hole is different from a second critical dimension of the second via hole. The barrier layer forms on the side-walls of the first via hole and the second via hole. The metal layer fills the damascene structure. | 2022-05-26 |
20220165619 | METHOD FOR MANUFACTURING STRUCTURE - Provided is a method of manufacturing a structure that can be easily bonded to a bonding target. The method of manufacturing a structure includes: a conductive layer forming step of forming a conductive layer having conductivity on a part of a surface of an insulating support including at least one surface; a valve metal layer forming step of forming a valve metal layer that covers at least a part of the conductive layer; an anodic oxidation film forming step of forming an anodic oxidation film by performing an anodization treatment on the valve metal layer in a region on the conductive layer using the conductive layer as an electrode; a micropore forming step of forming a plurality of micropores that extend in a thickness direction on the anodic oxidation film; and a filling step of filling the micropores with a conductive material, in which a valve metal layer removing step of removing the valve metal layer having undergone the anodic oxidation film forming step is performed between the anodic oxidation film forming step and the filling step. | 2022-05-26 |
20220165620 | ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE - A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure. | 2022-05-26 |
20220165621 | METHODS OF FORMING THROUGH-SILICON VIAS IN SUBSTRATES FOR ADVANCED PACKAGING - The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power. | 2022-05-26 |
20220165622 | SINGULATION SYSTEMS AND RELATED METHODS - Implementations of a semiconductor substrate singulation process may include applying a fluid jet to a material of a die street of a plurality of die streets included in a semiconductor substrate where the semiconductor substrate may include: a plurality of die separated by the plurality of die streets; and a plurality of die support structures coupled thereto; and singulating the plurality of die and the plurality of die support structures at the plurality of die streets using the fluid jet. The fluid jet may be moved only along a length of the die street. | 2022-05-26 |
20220165623 | VERTICAL FIELD-EFFECT TRANSISTOR DEVICES AND METHODS OF FORMING THE SAME - Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer. | 2022-05-26 |
20220165624 | Gate Structure of a Semiconductor Device and Method of Forming Same - A semiconductor device having a gate structure and a method of forming same are provided. The semiconductor device includes a substrate and a gate structure over the substrate. The substrate has a first region and a second region. The gate structure extends across an interface between the first region and the second region. The gate structure includes a first gate dielectric layer over the first region, a second gate dielectric layer over the second region, a first work function layer over the first gate dielectric layer, a barrier layer along a sidewall of the first work function layer and above the interface between the first region and the second region, and a second work function layer over the first work function layer, the barrier layer and the second gate dielectric layer. The second work function layer is in physical contact with a top surface of the first work function layer. | 2022-05-26 |
20220165625 | UNIVERSAL ELECTRICALLY INACTIVE DEVICES FOR INTEGRATED CIRCUIT PACKAGES - An integrated circuit package may be fabricated with a universal dummy device, instead of utilizing a dummy device that matches the bump layer of an electronic substrate of the integrated circuit package. In one embodiment, the universal dummy device may comprise a device substrate having an attachment surface and a metallization layer on the attachment surface, wherein the metallization layer is utilized to form a connection with the electronic substrate of the integrated circuit package. In a specific embodiment, the metallization layer may be a single structure extending across the entire attachment surface. In another embodiment, the metallization layer may be patterned to enable gap control between the universal dummy device and the electronic substrate. | 2022-05-26 |
20220165626 | FEED-FORWARD RUN-TO-RUN WAFER PRODUCTION CONTROL SYSTEM BASED ON REAL-TIME VIRTUAL METROLOGY - Aspects of the disclosure provide an APC system. The APC system can include a first processing tool that performs a first process on a target wafer, a second processing tool that performs a second process on the target wafer, and a prediction server that includes a prediction model for predicting a characteristic of the target wafer resulting from the first process using real-time data from the first process performed on the target wafer. Parameters of the prediction model can be updated by historical data of previous first processes. The APC system can also include a controller that is coupled to the first and second processing tools. After the first processing tool performs the first process on the target wafer, the controller can instruct the second processing tool to perform an adjusted second process on the target wafer based on the characteristic of the target wafer predicted by the prediction model. | 2022-05-26 |
20220165627 | METHODS AND SYSTEMS FOR COMPONENT ANALYSIS, SORTING, AND SEQUENCING BASED ON COMPONENT PARAMETERS AND DEVICES UTILIZING THE METHODS AND SYSTEMS - A process includes measuring at least one component parameter of a plurality of components with a testing device; and arranging at least a portion of the plurality of components in a sequential order based on the at least one component parameter with an implementation system in at least one of the following: a shipping format and a device implementation of the portion of the plurality of components. A system is disclosed as well. | 2022-05-26 |
20220165628 | MANUFACTURING METHOD OF PACKAGE DEVICE - The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads. | 2022-05-26 |
20220165629 | SILICON CARBIDE SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD OF INSPECTING SILICON CARBIDE SEMICONDUCTOR DEVICE - A portion of a source pad is exposed in an opening of a passivation film. In the exposed portion of the source pad, a wiring region in which a package wiring member is to be bonded and a probe region that is a region different from the wiring region are provided. The probe region has a probe mark of a probe for an energization inspection. An area of the probe mark that overlaps the wiring region is at most 30% of an entire area of the wiring region in a plan view of the silicon carbide semiconductor device. | 2022-05-26 |
20220165630 | SEMICONDUCTOR DEVICE AND POWER CONVERTER - According to an aspect of the first disclosure, a semiconductor device includes a base plate, a case that surrounds a region immediately above the base plate, a semiconductor chip provided in the region, a sealing resin that fills the region and a barrier layer provided on the sealing resin, wherein the barrier layer has a first surface facing the base plate, a second surface opposite to the first surface, and a convex part protruding upward from the second surface, the first surface has a longer distance to the base plate as getting farther from the center, the convex part is provided avoiding the center, and a height of the convex part is greater than a distance in a thickness direction of the barrier layer between a portion of the first surface immediately below the convex part and a portion of the first surface provided at the center. | 2022-05-26 |
20220165631 | SEMICONDUCTOR DEVICE AND POWER CONVERTER - It is an object to provide technology allowing for improvement in productivity of a semiconductor device. A semiconductor device includes: a base plate; an insulating substrate including a ceramic plate integrally bonded to an upper surface of the base plate with no solder layer therebetween and a circuit pattern disposed on an upper surface of the ceramic plate; a semiconductor element mounted on an upper surface of the circuit pattern; a case surrounding the insulating substrate and the semiconductor element over the base plate; an adhesive to adhere a lower portion of the case to an outer peripheral portion of the ceramic plate; and a sealant to seal the interior of the case, wherein the adhesive is in contact with an outer peripheral end of the ceramic plate to an outer peripheral end of the circuit pattern. | 2022-05-26 |
20220165632 | THREE-DIMENSIONAL PACKAGING STRUCTURE AND METHOD FOR FAN-OUT OF BONDING WALL OF DEVICE - Three-dimensional packaging structure for fan-out of bonding wall of device is provided. A first surface of a device is disposed with bond pads and functional area. The device, except for the first surface, is encapsulated with encapsulation material. A first surface of the encapsulation material horizontally connected to the first surface forms a fan-out surface. A wall structure is disposed on the first surface and extends to the fan-out surface. The wall structure partially covers at least one of the bond pads and comprises first opening corresponding to the at least one of the bond pads. Cover plate is bonded with the wall structure to form cavity corresponding to the functional area and comprises at least one second opening in communication with the first opening. A metal interconnection structure is disposed on surface of the cover plate and is electrically connected to the at least one of the bond pads. | 2022-05-26 |
20220165633 | SEMICONDUCTOR STRUCTURE HAVING AN ANTI-ARCING PATTERN DISPOSED ON A PASSIVATION LAYER AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE - A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die. | 2022-05-26 |
20220165634 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer. | 2022-05-26 |
20220165635 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, an interposer on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, the semiconductor devices being electrically connected to the interposer, a dam structure on the interposer extending along a peripheral region of the interposer, the dam structure being spaced apart from the semiconductor devices, and a stress relief on the interposer, the stress relief including an elastic member that fills gaps between the semiconductor devices and the dam structure. | 2022-05-26 |
20220165636 | CIRCUIT BOARD AND METHOD FOR MANUFACTURING ELECTRICAL CONNECTION BOX INCLUDING CIRCUIT BOARD - Provided is a circuit board on which an electronic component including a first terminal and a second terminal that are arranged side by side is to be mounted, the circuit board including: an insulating holding member, a conductive plate, and a signal circuit, in which the conductive plate is held by the holding member, the first terminal is joined to the conductive plate, the signal circuit is formed on a surface of the holding member using conductive nanoink containing a flux, and an end portion of the signal circuit and the second terminal are joined to each other using solder. | 2022-05-26 |
20220165637 | THERMAL SUBSTRATE CONTACT - An integrated circuit includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and which includes a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate. A thermal substrate contact increases the ability to remove heat produced from the integrated circuit transistors out of the integrated circuit. A thermal substrate contact which traverses the oxide layer over a substrate provides a secondary path for heat out of an integrated circuit (or, alternatively, out of a substrate through the integrated circuit) to cool the integrated circuit. | 2022-05-26 |
20220165638 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a wiring substrate; a semiconductor chip mounted on the wiring substrate; a heat release sheet arranged on the semiconductor chip to cover the entire semiconductor chip and having a larger area than an area of the semiconductor chip; and a cover member which covers the semiconductor chip and the heat release sheet and to which the heat release sheet is fixed. The cover member has a first portion facing the semiconductor chip, a flange portion arranged in a periphery of the first portion and bonded and fixed onto the wiring substrate, and a second portion arranged between the first portion and the flange portion. In a plan view of the cover member viewed from the heat release sheet, the heat release sheet is bonded/fixed to the cover member through a bonding member partially arranged between the heat release sheet and the cover member. | 2022-05-26 |
20220165639 | SEMICONDUCTOR DEVICE WITH THERMAL RELEASE LAYER AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first pad positioned above the substrate, and a first redistribution structure including a first redistribution conductive layer positioned on the first pad and a first redistribution thermal release layer positioned on the first redistribution conductive layer. The first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm | 2022-05-26 |
20220165640 | SEMICONDUCTOR MODULE - A semiconductor module may include a first PCB, at least one first semiconductor chip, a heat sink and at least one first TEC. The at least one semiconductor chip is on the first PCB. The heat sink may be configured to surround the first PCB and the at least one semiconductor control chip. The first TEC may be on the first PCB to cool heat from the first PCB. Thus, performances of the semiconductor module may not be deteriorated by the heat. | 2022-05-26 |
20220165641 | SENSOR APPARATUS - Provided is a sensor apparatus that can suppress movement of foreign matter from a Peltier element to a sensor element. The sensor apparatus includes a package substrate, a Peltier element, a circuit substrate, and a sensor element. The package substrate has a recess portion on a side of a first surface and plural terminals on a side of a second surface located on an opposite side of the first surface. The Peltier element is arranged in the recess portion. The circuit substrate is arranged on an opposite side of a bottom surface of the recess portion with the Peltier element sandwiched therebetween. The sensor element is attached to an opposite side of a surface, the surface being opposed to the Peltier element. | 2022-05-26 |
20220165642 | TACTILE REPRESENTATION DEVICE, DISPLAY PANEL AND DISPLAY DEVICE - A tactile representation device is provided. The tactile representation device includes a substrate and a semiconductor temperature control assembly disposed on the substrate. The substrate includes a plurality of deformable regions and a plurality of node regions that are alternately disposed in a first direction, wherein the deformable regions are deformable but the node regions are not deformable. The semiconductor temperature control assembly includes a plurality of semiconductor temperature control units. Each of the semiconductor temperature control units includes a hot terminal electrode, a P-side electrode, an N-side electrode, a P-type semiconductor, and an N-type semiconductor. Each of the hot terminal electrodes is disposed in each of the deformable regions, and each of the P-side electrodes and each of the N-side electrodes are disposed in each of the node regions. | 2022-05-26 |
20220165643 | SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer. | 2022-05-26 |
20220165644 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a base, a conductive pillar at least located in the base, connecting structures and an electrical connection layer. At least one connecting structure is electrically connected to an end of the conductive pillar, the material of the connecting structure is different from that of the conductive pillar, and a total area of an orthographic projection of the connecting structure on the base is less than an area of an orthographic projection of the conductive pillar on the base. The electrical connection layer is electrically connected to an end of the connecting structure distal from the conductive pillar. | 2022-05-26 |
20220165645 | UNIBODY LATERAL VIA - Semiconductor devices are described. In one example, the semiconductor device includes a substrate, a layer of first semiconductor material over the substrate, a layer of second semiconductor material over the layer of first semiconductor material, a first metal contact formed on the layer of first semiconductor material, a second metal contact formed on the layer of second semiconductor material, and a metal via that extends from a backside of the substrate, through the substrate, through the layer of first semiconductor material, and contacts a bottom surface of the first metal contact. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact. | 2022-05-26 |
20220165646 | METHOD FOR MANUFACTURING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed. | 2022-05-26 |
20220165647 | SIGNAL ISOLATOR HAVING ENHANCED CREEPAGE CHARACTERISTICS - Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die. | 2022-05-26 |
20220165648 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor package including a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first surface of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second surface of the semiconductor chip; a conductive post disposed outside the semiconductor chip; a first redistribution structure, which is on the first surface of the semiconductor chip and includes a first redistribution insulation layer supporting the conductive stud and the conductive post; a second redistribution structure, which is on the second surface of the semiconductor chip and includes a second redistribution insulation layer disposed on the adhesive layer; and a first molding layer disposed on the first redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post. | 2022-05-26 |
20220165649 | PRINTED CIRCUIT BOARD - A printed circuit board comprising: a first insulating layer; a first wiring layer disposed on one surface of the first insulating layer; and a bump at least partially disposed in the first insulating layer and connected to the first wiring layer. The bump at least partially protrudes from the other surface of the first insulating layer, opposite to the one surface of the first insulating layer. | 2022-05-26 |
20220165650 | PACKAGING SUBSTRATE AND SEMICONDUCTOR APPARATUS COMPRISING SAME - The embodiment relates to a packaging substrate and a semiconductor apparatus, including an element unit including a semiconductor element; and a packaging substrate electrically connected to the element unit; and it applies a glass substrate as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit. | 2022-05-26 |
20220165651 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package including a first package substrate, a first semiconductor chip on a top surface of the first package substrate, an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip, and a molding layer configured to cover the first package substrate and the first semiconductor chip may be provided. The interposer may include an interposer trench recessed from a bottom surface of the interposer that faces both the top surface of the first semiconductor chip and the top surface of the first package substrate, and an interposer hole penetrating the interposer. The molding layer may include a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer. | 2022-05-26 |
20220165652 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface. | 2022-05-26 |
20220165653 | WIRING SUBSTRATE - A wiring substrate includes a conductor pad, an insulating layer formed on the conductor pad such that the insulating layer is covering the conductor pad and has a through hole, a bump formed on the conductor pad such that the bump is formed in the through hole penetrating through the insulating layer. The conductor pad is formed such that the conductor pad has a connecting surface connected to the bump, a concave part formed on the connecting surface of the conductor pad to the bump, and a convex part formed in the concave part. | 2022-05-26 |
20220165654 | WAFER SYSTEM-LEVEL THREE-DIMENSIONAL FAN-OUT PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF - A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures. | 2022-05-26 |
20220165655 | PACKAGE SUBSTRATE INSULATION OPENING DESIGN - A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer. | 2022-05-26 |
20220165656 | CONNECTION SYSTEM AND METHOD FOR AN OPTIMIZED JOINING PROCESS OF BUSBARS - A connection system for an optimized joining process of busbars, including at least one busbar of a first electronic circuit and at least one busbar of a second electronic circuit. The at least two electronic circuits represent individual components, and the individual components are connectable to one another via the at least one busbar. The at least one of the at least one busbar of the first electronic circuit is mechanically processed. | 2022-05-26 |
20220165657 | SEMICONDUCTOR DEVICES HAVING IMPROVED ELECTRICAL CHARACTERISTICS AND METHODS OF FABRICATING THE SAME - The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer. | 2022-05-26 |
20220165658 | HIGH VOLTAGE DECOUPLING CAPACITOR AND INTEGRATION METHODS - A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers over the first isolation region. The plurality of dielectric layers may include inter layer dielectric (ILD) and inter metal dielectric (IMD) layers. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is arranged over the plurality of dielectric layers, whereby the second conductive layer is a top plate of the capacitor and at least partially overlaps with the first conductive layer. | 2022-05-26 |
20220165659 | Interconnect Structure - A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a source/drain (S/D) feature formed in an interlayer dielectric layer (ILD), a S/D contact via electrically connected to the S/D feature, a metal feature formed over the S/D contact via, and a metal line formed over the metal feature and electrically connected to the S/D contact via. The metal line is formed of a material different from that of the S/D contact via, and the S/D contact via is spaced apart from the metal line. By providing the metal feature, electromigration between the metal line and the contact via may be advantageously reduced or substantially eliminated. | 2022-05-26 |
20220165660 | METHOD OF BACK END OF LINE VIA TO METAL LINE MARGIN IMPROVEMENT - A method of forming a semiconductor structure includes forming a plurality of lower level conductive lines in a first dielectric layer. The plurality of lower level conductive lines includes a first lower level conductive line. The method further includes recessing portions of the first lower level conductive line below a top surface of the first dielectric layer to form a recess, forming a dielectric cap in the recess, depositing a second dielectric layer over the first dielectric layer. Forming a via opening exposes a portion of the second lower level conductive line. The method further includes forming an upper level conductive line and a via in the trench and in the via opening, respectively. The via couples the upper level conductive line to the second lower level conductive line, and the upper level conductive line overlaps with the dielectric cap. | 2022-05-26 |
20220165661 | SELF-ALIGNED VIA STRUCTURES AND METHODS - Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via. | 2022-05-26 |
20220165662 | SEMICONDUCTOR DEVICE WITH AIR GAPS BETWEEN ADJACENT CONDUCTIVE LINES - The present disclosure provides a semiconductor device with air gaps between adjacent conductive lines and a method for forming the semiconductor device. The semiconductor device with air gaps between adjacent conductive lines and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure. | 2022-05-26 |
20220165663 | NON-PLANAR SILICIDED SEMICONDUCTOR ELECTRICAL FUSE - An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses. | 2022-05-26 |
20220165664 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THEREOF - A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes receiving a first integrated circuit component having a seal ring and a fuse structure, wherein the fuse structure is electrically connected to a ground through the seal ring; receiving a second integrated circuit component having a first capacitor; bonding the second integrated circuit component to the first integrated circuit component; electrically connecting the first capacitor to the fuse structure, wherein the first capacitor is electrically connected to the ground through the fuse structure; and blowing the fuse structure after a treatment. | 2022-05-26 |
20220165665 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THEREOF - A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes receiving a first integrated circuit component having a seal ring and a fuse structure, wherein the fuse structure is electrically connected to a ground through the seal ring; receiving a second integrated circuit component having an inductor; bonding the second integrated circuit component to the first integrated circuit component; electrically connecting the inductor to the fuse structure, wherein the inductor is electrically connected to the ground through the fuse structure; and blowing the fuse structure after a treatment. | 2022-05-26 |
20220165666 | LASER-FORMED INTERCONNECTS FOR REDUNDANT DEVICES - A parallel redundant system comprises a substrate, a first circuit disposed over the substrate, a first conductor disposed at least partially in a first layer over the substrate and wire routed to the first circuit, a second circuit disposed over the substrate, the second circuit redundant to the first circuit, a second conductor disposed in a second layer over the substrate and electrically connected to the second circuit, the second conductor disposed at least partially over the first conductor, a dielectric layer disposed at least partially between the first layer and the second layer, and a laser weld electrically connecting the first conductor to the second conductor. | 2022-05-26 |
20220165667 | THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A three-dimensional memory device includes a plurality of row lines stacked alternately with a plurality of interlayer dielectric layers in a vertical direction on a substrate, and each of the plurality of row lines having a projection from a side surface thereof; and a plurality of vias extending in the vertical direction from the substrate, each coupled to the projection of a corresponding row line, and electrically coupling the plurality of row lines to a peripheral circuit defined below the substrate. | 2022-05-26 |
20220165668 | SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE - Disclosed are a semiconductor device and a method for preparing a semiconductor device. The semiconductor device is provided with contact pad structures in contact holes. Each of the contact pad structures is configured to comprise a first contact pad, a second contact pad adaptively covering the first contact pad, and a contact plug located on the second contact pad. The first contact pad is in full contact with an active region in a substrate. In addition, an air gap is formed between the first contact pad and a side wall on a side of the respective contact hole. | 2022-05-26 |
20220165669 | SEMICONDUCTOR DEVICE STRUCTURE, STACKED SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE STRUCTURE - An integrated circuit structure includes a front end of line structure, a front side back end of line structure, and a backside back end of line structure. The front end of line structure includes a device and a power/ground contact connecting the device. The front side back end of line structure disposed over a front side of the front end of line structure. The backside back end of line structure is disposed over a backside of the FEOL structure and includes a power/ground interconnect connecting the power/ground contact. | 2022-05-26 |
20220165670 | SEMICONDUCTOR DEVICE WITH BURIED METAL PAD, AND METHODS FOR MANUFACTURE - A semiconductor device that includes a metal pad buried in the semiconductor substrate that is electrically connected to a metal interconnection structure and electrically isolated from the semiconductor substrate. The semiconductor substrate forms an opening that extends from a back surface to the metal pad. A method for manufacturing a semiconductor device with buried metal pad including depositing, in a recess of a semiconductor substrate, a metal pad, isolating the pad from the substrate, electrically connecting the metal pad to the frontside of the substrate and connecting the metal pad to the backside of the substrate with an opening. A method for stabilizing through-silicon via connections in semiconductor device including electrically coupling a metal interconnection structure to a metal pad submerged in a semiconductor substrate and forming a through-silicon via into the semiconductor substrate that contacts the metal pad. | 2022-05-26 |
20220165671 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded. | 2022-05-26 |
20220165672 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A first semiconductor element (laser diode) and a second semiconductor element (laser diode) are connected to each other in series between a wiring electrically connected to an anode of the first semiconductor element and a wiring electrically connected to a cathode of the second semiconductor element. In this case, each of the first semiconductor element and the second semiconductor element includes a laminated pattern having an emission layer and a plurality of semiconductor layers covering this laminated pattern. | 2022-05-26 |
20220165673 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure including a first die, a second die, a dielectric body, a conductive terminal, a circuit layer and a patterned insulating layer is provided. The second die is disposed on the first die. A second active surface of the second die faces a first active surface of the first die. The dielectric body covers the first die. The conductive terminal is disposed on the dielectric body and opposite to the second die. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first die is electrically connected to the conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. The second die is electrically connected to the first die through the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric body. | 2022-05-26 |
20220165674 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed. | 2022-05-26 |
20220165675 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. | 2022-05-26 |
20220165676 | METHOD AND RELATED STRUCTURE TO AUTHENTICATE INTEGRATED CIRCUIT WITH AUTHENTICATION FILM - The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure. | 2022-05-26 |
20220165677 | FRAME REVEALS WITH MASKLESS LITHOGRAPHY IN THE MANUFACTURE OF INTEGRATED CIRCUITS - Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features. | 2022-05-26 |
20220165678 | SEMICONDUCTOR PACKAGE WITH MARKING PATTERN - A semiconductor package includes; a chip structure including vertically stacked semiconductor chips disposed on a package substrate, a spacer disposed on an uppermost semiconductor chip among the semiconductor chips, an encapsulant covering at least part of the chip structure, and including an upper portion of the encapsulant covering at least part of the spacer, and a marking pattern visually identifiable through an opening in the upper portion of the encapsulant selectively exposing portions of the spacer. | 2022-05-26 |
20220165679 | PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF - A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape. | 2022-05-26 |
20220165680 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion. | 2022-05-26 |
20220165681 | ELECTROMAGNETIC INTERFERENCE SHIELDING DEVICE COMPRISING A FLAME RETARDING, THERMAL INTERFACE MATERIAL COMPOSITE, AND METHOD FOR PREPARATION THEREOF - The present invention provides an EMI shielding device including a flame retarding, thermal interface material composite with a through plane thermal conductivity of no less than 30 W/mK and a dielectric withstanding voltage of no less than 1 kV/mm, where the composite includes at least one dielectric layer of self-aligned, carbon-based materials associated with superparamagnetic particles and at least one layer of fillers including a blend of dielectric heat transfer materials with a thermal or UV curable polymer or phase change polymer. The anisotropic heat transfer carbon-based materials associated with superparamagnetic materials are aligned under a low magnetic field strength of less than 1 Tesla to an orientation that results in a high thermal conductivity direction which can conduct the maximum heat from the adjacent device of the present composite. The present invention also provides a method for preparing the composite. | 2022-05-26 |
20220165682 | SEMICONDUCTOR PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - A semiconductor package structure includes a semiconductor package structure includes a first supporting bar, a second supporting bar and an encapsulant. The second supporting bar is adjacent to the first supporting bar. The first supporting bar and the second supporting bar extend substantially along a first direction. The encapsulant covers the first supporting bar and the second supporting bar. The encapsulant defines a first recess and a second recess recessed from a lower surface of the encapsulant. The first recess extends substantially along a second direction different from the first direction. The second recess is located between the first recess and the second supporting bar. | 2022-05-26 |
20220165683 | ASSEMBLY STRUCTURE AND METHODS FOR MANUFACTURING THE SAME - An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail. | 2022-05-26 |
20220165684 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a circuit structure and a ring-shaped protrusion. The semiconductor substrate has a front surface and a rear surface opposed to each other. The circuit structure is located on the front surface. The ring-shaped protrusion is protruded on the rear surface. | 2022-05-26 |
20220165685 | STRESS MITIGATION STRUCTURE - A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut. | 2022-05-26 |
20220165686 | ROBUST MOLD INTEGRATED SUBSTRATE - An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package. | 2022-05-26 |
20220165687 | PACKAGE WITH ELEVATED LEAD AND STRUCTURE EXTENDING VERTICALLY FROM ENCAPSULANT BOTTOM - A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level. | 2022-05-26 |
20220165688 | ACTIVE PROTECTION CIRCUITS FOR SEMICONDUCTOR DEVICES - Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device. | 2022-05-26 |
20220165689 | PACKAGE STRUCTURE - A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer. | 2022-05-26 |
20220165690 | METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES - A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces. | 2022-05-26 |
20220165691 | PROTECTIVE SURFACE LAYER ON UNDER BUMP METALLURGY FOR SOLDER JOINING - A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer. | 2022-05-26 |
20220165692 | LOW TEMPERATURE BONDED STRUCTURES - Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures. | 2022-05-26 |
20220165693 | SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD - A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad. | 2022-05-26 |
20220165694 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a passivation layer on the substrate, a post-passivation interconnect (PPI) structure on the passivation layer, and a polymer layer covering the PPI structure and the passivation layer. The PPI structure includes a step structure disposed on the passivation layer and around a lower edge of the PPI structure. | 2022-05-26 |
20220165695 | POROUS FLI BUMPS FOR REDUCING BUMP THICKNESS VARIATION SENSITIVITY TO ENABLE BUMP PITCH SCALING - Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure. | 2022-05-26 |
20220165696 | SEMICONDUCTOR PACKAGE - A semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. A pitch of the second bumps is less than that of the first bumps. | 2022-05-26 |
20220165697 | DUAL SOLDER METHODOLOGIES FOR ULTRAHIGH DENSITY FIRST LEVEL INTERCONNECTIONS - An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy. | 2022-05-26 |
20220165698 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another. | 2022-05-26 |
20220165699 | PACKAGE WITH POLYMER PILLARS AND RAISED PORTIONS - The present disclosure is directed to semiconductor packages that include a molding compound having at least one raised portion that extends outward from the package. In some embodiments, the semiconductor packages have a plurality of raised portions, and a plurality of conductive layers are on the plurality of raised portions. The plurality of raised portions and the plurality of conductive layers are utilized to mount the semiconductor packages to an external electronic device (e.g., a printed circuit board (PCB), another semiconductor package, an external electrical connection, etc.). In some embodiments, the semiconductor packages have a single raised portion with a plurality of conductive layers that are on the single raised portion. The single raised portion and the plurality of conductive layers are utilized to mount the semiconductor packages to the external electronic device. The plurality of conductive layers on the plurality of raised portions or the single raised portion may be formed by a laser direct structuring (LDS) process. | 2022-05-26 |
20220165700 | POWER SEMICONDUCTOR MODULE AND POWER CONVERTER - The conductive wire is bonded to the front electrode of the semiconductor device at the bonding section. The first resin member covers at least one end portion of two end portions of the bonding section, the first surface of the front electrode, and the second surface of the conductive wire. The second resin member covers the bent portion of the first resin member. The first resin member has a higher break elongation and a higher break strength than the second resin member. The second tensile elastic modulus of the second resin member is greater than the first tensile elastic modulus of the first resin member. Thereby, the reliability of the power semiconductor module is improved. | 2022-05-26 |
20220165701 | BOND PAD CONNECTION LAYOUT - A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction. | 2022-05-26 |
20220165702 | DEVICE AND METHOD OF FLUIDIC ASSEMBLY OF MICROCHIPS ON A SUBSTRATE - A cell of fluidic assembly of microchips on a substrate, including: a base having its upper surface intended to receive the substrate; a body laterally delimiting a fluidic chamber above the substrate; and a cover closing the fluidic chamber from its upper surface, wherein the body comprises first and second nozzles respectively emerging onto opposite first and second lateral edges of the fluidic chamber, each of the first and second nozzles being adapted to injecting and/or sucking in a liquid suspension of microchips into and/or from the fluidic chamber, in a direction parallel to the mean plane of the substrate. | 2022-05-26 |