21st week of 2022 patent applcation highlights part 60 |
Patent application number | Title | Published |
20220165803 | DISPLAYING BASE PLATE AND FABRICATING METHOD THEREOF, AND DISPLAYING DEVICE - A displaying base plate includes an opening region, an adjacent region surrounding the opening region, and a displaying region surrounding the adjacent region, and the displaying base plate located within the adjacent region includes: a substrate base plate; a flat layer and a passivation layer that are provided on one side of the substrate base plate, wherein the passivation layer is provided on one side of the flat layer that is further away from the substrate base plate, a surface of the one side of the flat layer that is further away from the substrate base plate includes at least an inclined plane adjacent to one side of the opening region, and the flat layer includes a first protrusion provided on the inclined plane; and a first isolating groove that at least partially overlaps with the first protrusion and extends throughout the passivation layer and extends into the first protrusion. | 2022-05-26 |
20220165804 | DISPLAY APPARATUS - A display apparatus includes: a substrate including a first area, a second area, and a third area that is between the first area and the second area; a plurality of first to third display elements respectively arranged in the first to third areas, each of the plurality of first to third display elements including a pixel electrode; and an insulating layer including a plurality of first to third openings that respectively expose at least portions of the pixel electrodes of the plurality of first to third display elements. A number of the plurality of first openings is greater than a number of the plurality of second openings per unit area. In a plan view, an area of the plurality of first openings is greater than an area of the plurality of third openings. | 2022-05-26 |
20220165805 | DISPLAY DEVICE AND METHOD OF PROVIDING THE SAME - A display device includes a display panel including a main portion, a first bent portion and a second bent portion each extending from the main portion, and a corner portion which connects the first bent portion and the second bent portion to each other and is bendable relative to the main portion. The corner portion which is bendable includes a plurality of protrusion patterns partially disconnected from each other and each bendable relative to the main portion, and each of the plurality of protrusion patterns including a display pixel | 2022-05-26 |
20220165806 | DISPLAY DEVICE - An embodiment of a display device includes: a first display area; a second display area including a transmission area; a third display area between the first display area and the second display area; and a plurality of pixel circuits in the third display area and electrically connected to the plurality of third light-emitting elements, respectively. Each of the plurality of pixel circuits includes: a first thin-film transistor including a first semiconductor layer and a first gate electrode overlapping at least a portion of the first semiconductor layer; a second thin-film transistor including a second semiconductor layer including a material different from that of the first semiconductor layer and a second gate electrode overlapping at least a portion of the second semiconductor layer; and a bottom shielding layer below the second semiconductor layer and overlapping at least a portion of the second semiconductor layer on a plane. | 2022-05-26 |
20220165807 | OLED LIGHT-EMITTING DEVICE, DISPLAY DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING OLED LIGHT-EMITTING DEVICE - A first stack-structured light-emitting element includes light-emitting units and a first charge generation layer between the light-emitting units. A second stack-structured light-emitting element includes light-emitting units and a second charge generation layer between the light-emitting units. Each of the first and second charge generation layers consists of one or more charge generation component layers. A first end region of the first charge generation layer and a second end region of the second charge generation layer overlap above the top face of the element separation layer. In the overlap region, an end region of a component layer of the first or second stack-structured light-emitting element configured to block charges of either polarity is interposed between charge generation component layers of the first and second charge generation layers configured to generate charges of the same polarity as the charges to be blocked by the component layer. | 2022-05-26 |
20220165808 | ELECTRONIC DEVICE AND TRANSPARENT DISPLAY HAVING THE SAME - An electronic device includes a transparent substrate, a number of pixel structures and a first trace structure. The transparent substrate includes a transparent region and a trace region. Each of the pixel structures has a sub-pixel structure of first color and a sub-pixel structure of second color. The sub-pixel structure of first color has a light emitting element of first color. The sub-pixel structure of second color has a light emitting element of second color. The first trace structure includes a first main trace, a first auxiliary trace and a second auxiliary trace. The first main trace is disposed in the trace region and surrounds a portion of the transparent region. The first auxiliary trace and the second auxiliary trace are electrically connected to the first main trace, and are electrically connected to the corresponding sub-pixel structure of first color and the corresponding sub-pixel structure of second color, respectively. | 2022-05-26 |
20220165809 | DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A display device comprises a display area and a non-display area, sub-pixels in the display area, each sub-pixel including a first electrode and a second electrode extended in a first direction and light-emitting elements disposed on the first electrode and the second electrode, sub-lines disposed in the non-display area and extended in a second direction, and conductive patterns extended in the first direction, each conductive pattern being connected to at least one of the plurality of sub-lines. The sub-lines comprise first, second, and third sub-lines sequentially disposed from the first sub-line toward the display area. The conductive patterns are disposed in at least one of the sub-pixels closest to the sub-lines. The conductive patterns comprise a first conductive pattern connected to the first sub-line, second conductive patterns connected to the second sub-line, and a third conductive pattern connected to the third sub-line. | 2022-05-26 |
20220165810 | PIXEL ARRANGEMENT STRUCTURE, ORGANIC ELECTROLUMINESCENT DISPLAY PANEL, METAL MASK AND DISPLAY DEVICE - A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, all being not overlapped but being spaced apart. The third sub-pixels have a first symmetry axis and a second symmetry axis that are perpendicular to each other. The first symmetry axis extends through a geometric center of a respective first sub-pixel adjacent to a respective third sub-pixel of the plurality of third sub-pixels, intersects a first edge of the respective third sub-pixel at a first intersection point, and intersects a second edge of the adjacent respective first sub-pixel at a second intersection point. A distance between the first intersection point and the second intersection point is a minimum distance between the respective third sub-pixel and the respective first sub-pixel. The second symmetry axis is similarly configured with respect to a respective second sub-pixel and the respective third sub-pixel. | 2022-05-26 |
20220165811 | DISPLAY PANEL - A display panel may include a substrate, pixels, dummy pixels, and voltage lines. The substrate may include a first transmission region for light transmission and/or sound transmission, a non-display area surrounding the first transmission region, and a display area surrounding the non-display area. The pixels may be arranged on the display area and may emit light. The dummy pixels may be arranged on the non-display area, may include a first dummy pixel, and may emit no light. The voltage lines may transmit voltages to the pixels and the dummy pixels. The voltage lines may include a first voltage line and a second voltage line. The first voltage line may be spaced from the second voltage line, may be aligned with the second voltage line, and may overlap the first dummy pixel. The first transmission region may be positioned between the first voltage line and the second voltage line. | 2022-05-26 |
20220165812 | LIGHT EMITTING DISPLAY PANEL AND LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME - A light emitting display panel includes a first emission area, a second emission area, and a third emission area spaced apart from each other and emitting different colors of light and a photochromic layer surrounding each of the first, second, and third emission areas and disposed in a non-emission area. When the first emission area, the second emission area, and the third emission area emit light, the photochromic layer is in a transparent state. When light of a wavelength band shorter than visible light is incident on the photochromic layer, the photochromic layer is in an opaque state. | 2022-05-26 |
20220165813 | Display Panel, Manufacturing Method thereof and Display Equipment - Disclosed are a display panel, a manufacturing method thereof and display equipment. The display panel comprises a display area, the display area comprises a camera area and a peripheral area surrounding the camera area, the camera area is provided with a transparent first touch control structure, and the first touch control structure is arranged between a substrate and an organic luminescent layer. | 2022-05-26 |
20220165814 | Methods and Configurations for Improving the Performance of Sensors under a Display - An electronic device may include a display and a sensor under the display. The display may include an array of subpixels for displaying an image to a user of the electronic device. At least a portion of the array of subpixels may be selectively removed in a pixel removal region to improve optical transmittance to the sensor through the display. The pixel removal region may include a plurality of pixel free regions that are devoid of thin-film transistor structures, that are devoid of power supply lines, that have continuous open areas due to rerouted row/column lines, that are partially devoid of touch circuitry, that optionally include dummy contacts, and/or have selectively patterned display layers. | 2022-05-26 |
20220165815 | Display Apparatus - According to an exemplary embodiment of the present disclosure, there is provided a display apparatus more stable to penetration of moisture and oxygen, including a panel including a display area, a camera hole area, and a non-display area disposed between the display area and the camera hole area, a light emitting element and a plurality of transistors disposed in the display area on the panel, an encapsulation layer disposed on the light emitting element and the transistors, and at least one camera hole, at least one connection prevention part, and at least one dam disposed in the camera hole area, in which a respective one of the at least one dam is disposed between a respective one of the at least one connection prevention part and a respective one of the at least one camera hole. | 2022-05-26 |
20220165816 | DISPLAY DEVICE - A display device includes a substrate. The substrate includes a display area and a non-display area, and the display area includes an emission area and a non-emission area. A display element layer includes a light emitting element on the emission area of the substrate. A bank is on the display element layer and overlaps the non-display area and the non-emission area of the substrate in a plan view. A color conversion layer is on the display element layer, overlaps the emission area in the plan view, and is to convert a color of light emitted from the light emitting element. An organic insulating layer is on the color conversion layer and the bank. A maximum thickness of the bank is about 4 μm to about 20 μm. An average inclination angle of a first side surface of the bank adjacent to an edge of the substrate in the non-display area based on an upper surface of the substrate is less than or equal to about 45 degrees. | 2022-05-26 |
20220165817 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A display device includes a substrate comprising a display area and a non-display area, a via layer disposed on the substrate, a pixel electrode disposed on the via layer in the display area, and a pixel-defining layer disposed on the pixel electrode and a part of the via layer exposed by the pixel electrode, wherein the pixel-defining layer comprises a first area disposed in the display area and comprising an opening exposing a part of the pixel electrode, and a second area disposed in the non-display area and comprising an end, and wherein the first area comprises a first side surface defining the opening, wherein the second area comprises a second side surface at the end, wherein a first taper angle which is a taper angle of the first side surface is different from a second taper angle which is a taper angle of the second side surface. | 2022-05-26 |
20220165818 | DISPLAY DEVICE - According to one embodiment, a display device includes a base, a driving transistor placed on the base, a first insulating layer placed on the driving transistor, a cathode electrode placed on the first insulating layer, an organic layer including a light-emitting layer placed on the cathode electrode, an anode electrode that covers the organic layer, a second insulating layer placed on the first insulating layer and having an opening superposed on the cathode electrode, and a barrier wall placed on the second insulating layer. The anode electrode is electrically connected to the driving transistor through a first contact hole formed in the first insulating layer and the second insulating layer. | 2022-05-26 |
20220165819 | TRANSPARENT DISPLAY DEVICE - A transparent display device may minimize or reduce coupling occurring between signal lines and apply a repair structure to a scan line. The transparent display device comprises a substrate provided with a transmissive area and a plurality of subpixels disposed between the transmissive areas, first and second anode electrodes provided in each of the plurality of subpixels, a first connection electrode connecting the first anode electrode with the second anode electrode, a driving transistor provided in each of the plurality of subpixels, and a second connection electrode provided below the driving transistor, electrically connecting the driving transistor with the first connection electrode. | 2022-05-26 |
20220165820 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device according to an embodiment of the present invention may include a substrate including a display area and a pad area located on one side of the display area, a pad electrode disposed in the pad area on the substrate, a protective insulating layer disposed on the substrate and the pad electrode to expose at least a part of a top surface of the pad electrode, an inorganic encapsulation layer disposed on the protective insulating layer, and a conductive layer disposed in the pad area between an end of the inorganic encapsulation layer adjacent to the pad electrode and the protective insulating layer. | 2022-05-26 |
20220165821 | Display Device and Method of Manufacturing the Same - Disclosed is a display device and a method of manufacturing the same having improved reliability. In the display device, at least one of a plurality of dielectric films disposed between an oxide semiconductor layer and a light-emitting device includes a lower region disposed on the oxide semiconductor layer and an upper region disposed on the lower region, the upper region including a trap element configured to trap hydrogen, whereby reliability of a thin film transistor including the oxide semiconductor layer is improved. | 2022-05-26 |
20220165822 | DISPLAY PANEL AND DISPLAY APPARATUS - The present disclosure provides a display panel and a display apparatus. The display panel includes at least one opening, and further includes: a substrate; a thin film transistor structure layer; a first inorganic passivation layer; an organic planarization layer on a side of the first inorganic passivation layer distal to the thin film transistor structure layer; and a second inorganic passivation layer on a side of the organic planarization layer distal to the first inorganic passivation layer. The second inorganic passivation layer extends toward the first inorganic passivation layer alone a side of the organic planarization layer proximal to the at least one opening and covers an exposed portion of the organic planarization layer on a side of the organic planarization layer proximal to the at least one opening. | 2022-05-26 |
20220165823 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - An organic EL display ( | 2022-05-26 |
20220165824 | DISPLAY DEVICE - An embodiment of a display device includes a flexible substrate including a polyimide layer and a barrier layer disposed on the polyimide layer. A driving transistor and a second transistor are disposed on the flexible substrate and include a polycrystalline semiconductor layer. A third transistor is disposed on the flexible substrate and includes an oxide semiconductor layer. A light emitting diode is electrically connected to the driving transistor. A bottom shield layer is disposed between the polyimide layer and the polycrystalline semiconductor layer in a cross-sectional view and disposed around a channel of the driving transistor in a plan view. | 2022-05-26 |
20220165825 | DISPLAY DEVICE - A display device is provided. The display device comprises a first base substrate, a first barrier layer disposed on the first base substrate, a second base substrate disposed on the first barrier layer, a first sub-substrate disposed on the second base substrate and comprising at least one dopant selected from a group consisting of: fluorine (F), boron (B), arsenic (As), phosphorus (P), chlorine (Cl), bromine (Br), iodine (I), astatine (At), sulfur (S), selenium (Se), argon (Ar), and tellurium (Te), a second barrier layer disposed on the first sub-substrate, a second buffer layer disposed on the second barrier layer, a first buffer layer disposed on the second buffer layer, at least one transistor disposed on the first buffer layer, and an organic light-emitting diode disposed on the at least one transistor. | 2022-05-26 |
20220165826 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREFOR - According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region. | 2022-05-26 |
20220165827 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a first display region and a second display region, and the second display region includes a transparent display region and a transition display region. Pixel circuits corresponding to light-emitting units of the transparent display region and the transition display region are located in the transition display region, and the pixel circuits located in the transition display region includes a first drive transistor. Along a direction perpendicular to the substrate, an overlapping region is located between the gate transmission structures and a lower electrode disposed on a side, close to the substrate, of a light-emitting unit of the transition display region located above the respective gate transmission structure, a shielding layer connected to a fixed potential is disposed in at least part of the overlapping region to shield from parasitic capacitance between the lower electrode and the gate transmission structure. | 2022-05-26 |
20220165828 | DISPLAY APPARATUS HAVING DRIVING CIRCUIT AND LIGHT EMITTING DEVICE - A display apparatus comprising a driving circuit that includes a storage capacitor and at least one thin film transistor, and a light-emitting device that includes a region disposed outside the driving circuit and a region overlapping with the storage capacitor, each of capacitor electrodes of the storage capacitor being a transparent electrode having a relatively higher transmittance, so that the quality of the image realized on an outer surface of a device substrate which supports the driving circuit and the light-emitting device of each pixel area can be improved. | 2022-05-26 |
20220165829 | DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY APPARATUS - A display substrate comprises a pixel driving circuit and a bottom-emission light-emitting device that are disposed on a base and located in each sub-pixel in a display area. The light-emitting device includes a first electrode electrically connected to the pixel driving circuit. The pixel driving circuit includes a first storage capacitor and a second storage capacitor connected in parallel. The first storage capacitor includes a first storage electrode and a second storage electrode that are disposed oppositely, and the first electrode serves as the first storage electrode. The second storage capacitor includes the second storage electrode and a third storage electrode that are disposed oppositely. The second storage electrode is located between the first storage electrode and the third storage electrode. The first storage electrode is electrically connected to the third storage electrode. The first electrode, the second storage electrode, and the third storage electrode are all transparent electrodes. | 2022-05-26 |
20220165830 | DISPLAY DEVICE - An embodiment of a display device includes a display panel having a flexible characteristic and a rear passivation layer disposed on a rear surface of the display panel and including an opening, wherein a pixel is formed in an area of the display panel corresponding to the opening. The display panel includes: a flexible substrate including a polyimide layer and a barrier layer disposed on the polyimide layer; a driving transistor and a fifth transistor disposed on the substrate and including a polycrystalline semiconductor layer; a light emitting diode receiving an output current of the driving transistor; and a bottom metal layer disposed between the polyimide layer and the polycrystalline semiconductor layer in a cross-sectional view and disposed around a channel of the driving transistor in a plan view. | 2022-05-26 |
20220165831 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - Provided are a display apparatus, of which a display area is expanded for the representation of images in an area where an electronic component is located and in which the degradation in performance of the electronic component is reduced, and a method of manufacturing the display apparatus. The display apparatus includes a substrate, a light-emitting element disposed on the substrate, and a lower metal layer disposed under the light-emitting element. The lower metal layer includes a first surface facing the substrate and including an uneven portion, and a second surface opposite to the first surface. The first surface of the lower metal layer has surface roughness greater than that of the second surface of the lower metal layer | 2022-05-26 |
20220165832 | DISPLAY DEVICE - A display device includes a light emitting element, a first transistor, a second transistor, and a diode. The first transistor may control a driving current flowing to the light emitting element depending on a voltage applied to a gate electrode of the first transistor. The second transistor is electrically connected between the gate electrode of the first transistor and a first electrode of the first transistor. A first electrode of the diode is electrically connected to a first electrode of the second transistor. A second electrode of the diode is electrically connected to the gate electrode of the first transistor. | 2022-05-26 |
20220165833 | DISPLAY PANEL AND DISPLAY APPARATUS - The present disclosure relates to the technical field of display, and discloses a display panel and a display apparatus. The display panel includes a first substrate, a power line arranged on the first substrate, and a drive circuit located at the side, facing away from the first substrate, of the power line and isolated from the power line, an orthographic projection of the power line on the first substrate is at least partially overlapped with an orthographic projection of the drive circuit on the first substrate. | 2022-05-26 |
20220165834 | DISPLAY DEVICE - A display device includes a display panel having a plurality of pixels connected to gate lines and data lines, and a plurality of fingerprint sensors connected to sensing lines and read-out lines. A gate driver provides gate signals to the gate lines and provides sensing signals to the sensing lines. The gate driver includes a first gate signal supply module providing a first gate signal to a first gate line among the gate lines. A first switching element is turned on by a reset enable signal to connect the first gate line and a first sensing line among the sensing lines. | 2022-05-26 |
20220165835 | DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS - Disclosed are a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a plurality of read signal lines, extending on the base substrate in a first direction; a plurality of display signal lines, extending on the base substrate in a second direction, the second direction intersects with the first direction, the plurality of display signal lines and the plurality of read signal lines are arranged on different layers, there is an overlapped region between an orthographic projection of the plurality of display signal lines on the base substrate and an orthographic projection of the plurality of read signal lines; and a shielding layer, located between a layer where the plurality of read signal lines are and a layer where the plurality of display signal lines are, an orthographic projection of the shielding layer on the base substrate at least covers the overlapped region. | 2022-05-26 |
20220165836 | TRANSPARENT DISPLAY DEVICE - A transparent display device may have high transmittance and at the same time have high resolution. The transparent display device comprises a first signal line portion extended in a first direction, including a first sensing scan line, a second sensing scan line, an initialization line and a light emission control line, a second signal line portion extended in a second direction, a transmissive area provided between two adjacent first signal line portions and between two adjacent second signal line portions, and a pixel provided in an intersection area where the first signal line portion and the second signal line portion cross or overlap each other. The light emission control line overlaps the initialization line in at least a partial area. | 2022-05-26 |
20220165837 | TRANSPARENT DISPLAY DEVICE - A transparent display device may minimize coupling occurring between signal lines and apply a repair structure to a scan line. The transparent display device comprises a substrate provided with a transmissive area and a non-transmissive area disposed between the transmissive areas, a reference line extended from the non-transmissive area in a first direction, a first data line disposed at a first side of the reference line, a second data line disposed at a second side of the reference line, a first power line provided between the reference line and the first data line, and a second power line provided between the reference line and the second data line. | 2022-05-26 |
20220165838 | DISPLAY DEVICE - The present inventive concept relates to a display device. A display device according to an exemplary embodiment of the present inventive concept include: a base layer including a plurality of islands in which a pixel is disposed, a plurality of bridges disposed around each of the plurality of islands, a plurality of first wires disposed in a bridge of the plurality of bridges connected to the pixel is disposed; an inorganic insulating layer disposed on the base layer and having an opening exposing a portion of the bridge; and an organic material layer covering the opening, wherein adjacent islands of the plurality of islands are connected to each other through at least the bridge of the plurality of bridges, and the plurality of first wires are disposed on the organic material layer. | 2022-05-26 |
20220165839 | DISPLAY DEVICE - A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction. | 2022-05-26 |
20220165840 | DIELECTRIC THIN FILM, CAPACITOR INCLUDING THE DIELECTRIC THIN FILM, AND METHOD FOR MANUFACTURING THE DIELECTRIC THIN FILM - Provided is a method of preparing a dielectric film having a nanoscale three-dimensional shape and including an oxide, the oxide represented by R | 2022-05-26 |
20220165841 | DYNAMIC RANDOM ACCESS MEMORY CAPACITOR AND PREPARATION METHOD THEREFOR - A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer. | 2022-05-26 |
20220165842 | SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF - Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer. | 2022-05-26 |
20220165843 | GAS DOPANT DOPED DEEP TRENCH SUPER JUNCTION HIGH VOLTAGE MOSFET - A method for manufacturing and a Super Junction MOSFET are disclosed. The Super Junction MOSFET comprises a lightly doped epitaxial layer of a first conductivity type on a heavily doped substrate of the first conductivity type. A deep trench is formed in the epitaxial layer. The deep trench having an insulating layer with a thickness gradient formed on surfaces of the deep trench. One or more regions of the epitaxial layer proximate to sidewalls of the deep trench is doped of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type. Finally, MOSFET device structures are formed in the epitaxial layer. | 2022-05-26 |
20220165844 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug. | 2022-05-26 |
20220165845 | Method for Structuring a Semiconductor Surface and Semiconductor Body Comprising a Semiconductor Surface Having at Least One Structure - In an embodiment a method for structuring a semiconductor surface includes providing the semiconductor surface, wherein the semiconductor surface is part of a GaN-semiconductor layer, irradiating the semiconductor surface with an electron beam in order to produce an irradiated section and anisotropic wet-chemical etching of the semiconductor surface, wherein an etching rate in the irradiated section is less than that in an unirradiated section of the semiconductor surface, and wherein no etching mask is applied to the semiconductor surface before anisotropic wet-chemical etching. | 2022-05-26 |
20220165846 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate, a source/drain contact disposed over the substrate, a first dielectric layer disposed on the source drain contact, an etch stop layer disposed on the first dielectric layer, and a source/drain conductive layer disposed in the etch stop layer and the first dielectric layer. The structure further includes a spacer structure disposed in the etch stop layer and the first dielectric layer. The spacer structure surrounds a sidewall of the source/drain conductive layer and includes a first spacer layer having a first portion and a second spacer layer adjacent the first portion of the first spacer layer. The first portion of the first spacer layer and the second spacer layer are separated by an air gap. The structure further includes a seal layer. | 2022-05-26 |
20220165847 | SEMICONDUCTOR DEVICE WITH DOPED STRUCTURE - The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region. | 2022-05-26 |
20220165848 | SOURCE/DRAIN FEATURES - A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer. | 2022-05-26 |
20220165849 | SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type. | 2022-05-26 |
20220165850 | VERTICAL TRANSPORT CMOS TRANSISTORS WITH ASYMMETRIC THRESHOLD VOLTAGE - A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed over the first set of fins, and a second high-κ metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer. | 2022-05-26 |
20220165851 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a metal plate having a first main surface and a second main surface, the second main surface being opposite to the first main surface, an insulating film provided on a portion of the first main surface of the metal plate, a first conductive layer provided on the insulating film, and a silicon carbide semiconductor chip. The silicon carbide semiconductor chip includes a first electrode and a second electrode on a first surface and a third electrode on a second surface, the second surface being opposite to the first surface. The first surface of the silicon carbide semiconductor chip faces the first main surface of the metal plate, the first electrode is bonded to the first conductive layer with a first bonding material, and the second electrode is bonded to the first main surface of the metal plate with a second bonding material. | 2022-05-26 |
20220165852 | METHODS AND APPARATUS FOR METAL FILL IN METAL GATE STACK - A method of filling a feature in a semiconductor structure includes forming a barrier layer in the feature by one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD); wherein the barrier layer is one of cobalt (Co), molybdenum (Mo), molybdenum nitride (MoN) plus Mo, titanium (Ti), titanium aluminum carbide (TiAlC), or titanium nitride (TiN); and forming a metal layer in the feature and over the barrier layer by one of ALD or CVD; wherein the metal layer is one of aluminum (Al), Co, Mo, ruthenium (Ru), or tungsten (W). | 2022-05-26 |
20220165853 | SYMMETRIC ARRANGEMENT OF FIELD PLATES IN SEMICONDUCTOR DEVICES - The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate. | 2022-05-26 |
20220165854 | P-Type Dipole For P-FET - Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-K dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC). | 2022-05-26 |
20220165855 | CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CONTACT RESISTANCE - Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween. | 2022-05-26 |
20220165856 | GAP SPACER FOR BACKSIDE CONTACT STRUCTURE - Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure include a source feature disposed over a backside source contact, a drain feature disposed over a backside dielectric layer, a plurality of channel members each extending between the source feature and the drain feature, and a gate structure wrapping around each of the plurality of channel members and disposed over the backside dielectric layer. The backside source contact is spaced apart from the backside dielectric layer by a gap. | 2022-05-26 |
20220165857 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a fin-type active region disposed on a substrate and extending in a first horizontal direction, a gate line disposed on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction, the gate line including, a connection protrusion portion including a protrusion top surface at a first vertical level from the substrate, and a main gate portion including a recess top surface extending in the second horizontal direction from the connection protrusion portion, the recess top surface being at a second vertical level lower than the first vertical level, a gate contact disposed on the gate line and connected to the connection protrusion portion, a source/drain region disposed on the fin-type active region and disposed adjacent to the gate line, and a source/drain contact disposed on the source/drain region. | 2022-05-26 |
20220165858 | SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF - Disclosed are a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate, a multilayer semiconductor layer, a dielectric layer, a source and a drain. A gate trench is formed in the multilayer semiconductor layer and the dielectric layer. A gate is formed in the gate trench, and the gate trench includes a first sub-portion of the gate trench formed in the multilayer semiconductor layer and a second sub-portion of the gate trench penetrating the dielectric layer. The second sub-portion of the gate trench includes a second opening located on the surface of the dielectric layer close to the substrate and a third opening on the surface of the dielectric layer away from the substrate. The vertical projection of the third opening on the substrate covers the vertical projection of the second opening on the substrate. | 2022-05-26 |
20220165859 | INTEGRATED CHIP WITH A GATE STRUCTURE OVER A RECESS - The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate. | 2022-05-26 |
20220165860 | SILICIDE BACKSIDE CONTACT - A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer. | 2022-05-26 |
20220165861 | SEMICONDUCTOR DEVICE INCLUDING WORK FUNCTION ADJUSTING METAL GATE STRUCTURE - A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer. | 2022-05-26 |
20220165862 | POWER SEMICONDUCTOR DEVICES HAVING MULTILAYER GATE DIELECTRIC LAYERS THAT INCLUDE AN ETCH STOP/FIELD CONTROL LAYER AND METHODS OF FORMING SUCH DEVICES - A semiconductor device includes a semiconductor layer structure that comprises silicon carbide, a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. A dielectric constant of the capping gate dielectric layer is higher than a dielectric constant of the base gate dielectric layer. | 2022-05-26 |
20220165863 | SPLIT-GATE MOSFET WITH GATE SHIELD - Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches. | 2022-05-26 |
20220165864 | METHOD FOR FORMING A HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region. | 2022-05-26 |
20220165865 | FinFET Device Comprising Plurality of Dummy Protruding Features - A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region. | 2022-05-26 |
20220165866 | HEMT AND METHOD OF FABRICATING THE SAME - An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate. | 2022-05-26 |
20220165867 | GRADIENT-DOPED SACRIFICIAL LAYERS IN INTEGRATED CIRCUIT STRUCTURES - Disclosed herein are gradient-doped sacrificial layers in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include a stack of layers of a first material alternating along an axis with layers of a second material, wherein the first material includes at least one of silicon and germanium, the second material includes silicon and germanium, and a concentration of germanium in an individual layer of the second material increases toward adjacent layers of the first material. | 2022-05-26 |
20220165868 | Isolation Structures of Semiconductor Devices - The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region. | 2022-05-26 |
20220165869 | FIN FIELD EFFECT TRANSISTOR DEVICE STRUCTURE - A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer. | 2022-05-26 |
20220165870 | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE - The present disclosure provides a display substrate and a manufacturing method thereof, and a display device, belongs to the field of display technology. The method includes forming a first thin film transistor, which includes: forming a first gate of the first thin film transistor on a base substrate through a patterning process; forming a first gate insulating layer on a side of the first gate distal to the base substrate; sequentially forming a first semiconductor material layer, a second gate insulating layer and a second gate metal layer on a side of the first gate insulating layer distal to the base substrate, and forming a pattern including an active layer of the first thin film transistor, a pattern of the second gate insulating layer and a second gate of the first thin film transistor through a patterning process. | 2022-05-26 |
20220165871 | Semiconductor Device and Method - In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer. | 2022-05-26 |
20220165872 | HIGH-VOLTAGE SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, a doped isolation region, and at least one isolation pillar. The substrate includes a core layer and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor device is disposed on the substrate, where the first semiconductor device includes a first semiconductor cap layer disposed on the semiconductor barrier layer. The doped isolation region is disposed at one side of the first semiconductor device. At least a portion of the isolation pillar is disposed in the doped isolation region, and the isolation pillar surrounds at least a portion of the first semiconductor device and penetrates the composite material layer. | 2022-05-26 |
20220165873 | HEMT AND METHOD OF FABRICATING THE SAME - An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate. | 2022-05-26 |
20220165874 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes an electron transfer layer formed from a nitride semiconductor, an electron supplying layer formed from a nitride semiconductor having a larger band gap than the electron transfer layer on the electron transfer layer, a first step layer formed from a nitride semiconductor having a smaller band gap than the electron supplying layer on part of the electron supplying layer, a second step layer formed from a nitride semiconductor having a larger band gap than the first step layer on the first step layer, a gate layer including an acceptor impurity and formed from a nitride semiconductor having a smaller band gap than the second step layer on the second step layer, a gate electrode formed on the gate layer, and a source electrode and a drain electrode. The first step layer includes a first extension extending outward from the gate layer in plan view. | 2022-05-26 |
20220165875 | NITRIDE SEMICONDUCTOR APPARATUS - Disclosed herein is a nitride semiconductor apparatus including an electron transit layer including a nitride semiconductor, an electron supply layer that is formed on the electron transit layer and includes a nitride semiconductor with a band gap larger than a band gap of the electron transit layer, a step layer that is formed on part of the electron supply layer and includes a nitride semiconductor with a band gap smaller than the band gap of the electron supply layer, a gate layer that is formed on part of the electron supply layer or part of the step layer and contains acceptor impurities, a gate electrode formed on the gate layer, and a source electrode and a drain electrode that are in contact with the electron supply layer. The step layer includes extension portions extending outside of the gate layer in plan view. The extension portions each include an undoped layer. | 2022-05-26 |
20220165876 | SEMICONDUCTOR POWER DEVICES HAVING GRADED LATERAL DOPING AND METHODS OF FORMING SUCH DEVICES - A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion. | 2022-05-26 |
20220165877 | SEMICONDUCTOR DEVICE - In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer. | 2022-05-26 |
20220165878 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer having a main surface in which a trench is formed, a first-conductivity-type body region formed along a sidewall of the trench in a surface layer portion of the main surface of the semiconductor layer, a second-conductivity-type impurity region formed along the sidewall of the trench in a surface layer portion of the body region, a gate insulating layer formed on an inner wall of the trench, a gate electrode that is embedded in the trench and that faces the body region and the impurity region with the gate insulating layer placed between the gate electrode and the body region and between the gate electrode and the impurity region, a contact electrode that passes through the sidewall of the trench from inside the trench and is drawn out to the surface layer portion of the main surface of the semiconductor layer and is electrically connected to the body region and to the impurity region, and an embedded insulating layer that is interposed between the gate electrode and the contact electrode in the trench and that insulates the gate electrode and the contact electrode. | 2022-05-26 |
20220165879 | Semiconductor Device with Integrated Current Sensor - Described herein is a power semiconductor device and corresponding method of production. The semiconductor device includes: a power device region formed in a semiconductor substrate and including first trenches and second trenches extending lengthwise in parallel with one another with semiconductor mesas between adjacent ones of the trenches, each first trench including a gate electrode at a first potential and each second trench including a field plate at a second potential; and a current sense region formed in the semiconductor substrate. A subset of the first trenches, a subset of the second trenches and a subset of the semiconductor mesas are common to both the current sense region and the power device region. The second trenches are interrupted along opposite first and second sides of the current sense region such that the field plates are interrupted between the power device region and the current sense region. | 2022-05-26 |
20220165880 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench. | 2022-05-26 |
20220165881 | METHOD OF FORMING TRANSISTORS OF DIFFERENT CONFIGURATIONS - The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature. | 2022-05-26 |
20220165882 | STRAINED GATE SEMICONDUCTOR DEVICE WITH DOPED INTERLAYER DIELECTRIC MATERIAL - A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall. | 2022-05-26 |
20220165883 | OXIDE MATERIAL AND SEMICONDUCTOR DEVICE - An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis. | 2022-05-26 |
20220165884 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact. | 2022-05-26 |
20220165885 | Semiconductor Device and Method - In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region. | 2022-05-26 |
20220165886 | SEMICONDUCTOR STRUCTURE AND A MANUFACTURING METHOD THEREOF - A semiconductor structure includes: a substrate; a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence; wherein the first conductive layer includes a first polysilicon layer, a first metal layer and a second polysilicon layer, wherein the first polysilicon layer is adjacent to the substrate and the second polysilicon layer is contiguous to the barrier layer; and wherein the first metal layer is located between the first polysilicon layer and the second polysilicon layer. The gate structure of the embodiments of the application has a straight profile and an excellent electrical performance. | 2022-05-26 |
20220165887 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view. | 2022-05-26 |
20220165888 | High Voltage Gallium Nitride Vertical PN Diode - A vertical gallium nitride (GaN) PN diode uses epitaxial growth of a thick drift region with a very low carrier concentration and a carefully designed multi-zone junction termination extension to achieve high voltage blocking and high-power efficiency. An exemplary large area (1 mm | 2022-05-26 |
20220165889 | WIRING BOARD, ELECTRONIC COMPONENT PACKAGE, AND ELECTRONIC APPARATUS - A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability. | 2022-05-26 |
20220165890 | DETECTOR FOR DETECTING CHARGED PARTICLES OR LIGHT - An embodiment of the present disclosure relates to a detector that includes an AD and detects charged particles or light, and enables speeding up of response of the detector without changing a structure of the AD that limits the response of the detector. A drive circuit of the AD includes a first capacitor and a first resistor. Both the first capacitor and the first resistor are connected in series to the AD in a state where both terminals are set to have the same potential. This configuration reduces the apparent capacitance of the AD and speeds up the response of the entire detector including the drive circuit. | 2022-05-26 |
20220165891 | PHOTO DETECTING DEVICE - A photo detecting device comprising: a substrate; a plurality of photoelectric conversion elements provided to the substrate and configured to output a detection signal corresponding to light with which the photoelectric conversion elements are irradiated; at least one or more light emitting elements provided to the substrate; and a control circuit configured to set a wavelength of light output from the light emitting element by controlling an electric current flowing through the light emitting element. | 2022-05-26 |
20220165892 | METHOD OF MANUFACTURING AN INTEGRATED COMPONENT WITH IMPROVED SPATIAL OCCUPATION, AND INTEGRATED COMPONENT - Disclosed herein is an integrated component formed by a first wafer having first and second trenches defined in a top surface thereof, and a second wafer coupled to the first wafer and formed by a substrate with a structural layer thereon that integrated an electromagnetic radiation detector overlying the second trench. A first cap is coupled to the second wafer, overlies the electromagnetic radiation detector, and serves to define a first air-tight chamber in which the electromagnetic radiation detector is positioned. A stator, a rotor, and a mobile mass are integrated within the substrate and form a drive assembly for driving the mobile mass. The rotor overlies the first trench. A second cap is coupled to the second wafer, overlies the mobile mass, and serving to define a second air-tight chamber in which the mobile mass is positioned. | 2022-05-26 |
20220165893 | Photodetectors Having Optical Grating Couplers Integrated Therein and Related Methods - An integrated device is provided including a substrate; a CQD photodetector on the substrate; and an integrated optical grating contact on the substrate. The integrated optical grating contact is a conductive grating contact and is provided between the substrate and the photodetector. The integrated device further includes a top contact on the photodetector. | 2022-05-26 |
20220165894 | BACK CONTACT SOLAR CELL ASSEMLIES - A back contact solar cell assembly and methods for its manufacture and assembly onto a panel for use in space vehicles are described. The solar cell assembly includes a compound semiconductor multijunction solar cell having a contact at the top surface of the solar cell, a conductive semiconductor element extending from the contact on the top surface to the back surface of the assembly where it forms a first hack contact of a first polarity type, and a second back contact of a second polarity at the back surface of the assembly electrically coupled to the back surface of the solar cell. | 2022-05-26 |
20220165895 | Image sensor and manufacturing method thereof - The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material. | 2022-05-26 |
20220165896 | LIGHT RECEIVING ELEMENT, METHOD OF MANUFACTURING LIGHT RECEIVING ELEMENT, AND IMAGING APPARATUS - A light receiving element ( | 2022-05-26 |
20220165897 | BACKSIDE PROTECTIVE SHEET FOR SOLAR CELL MODULES AND SOLAR CELL MODULE - A backside protective sheet for solar cell modules includes a first layer configured to reflect near-infrared light, a first colored layer arranged closer to a light-receiving surface than the first layer and configured to transmit near-infrared light, and a second colored layer arranged closer to the light-receiving surface than the first colored layer and configured to transmit near-infrared light. | 2022-05-26 |
20220165898 | FLEXIBLE AND LIGHT PHOTOVOLTAIC MODULE - A photovoltaic module includes a transparent first layer forming the front side of the photovoltaic module; a plurality of photovoltaic cells placed side-by-side and electrically connected; a polymer encapsulating assembly able to encapsulate the plurality of photovoltaic cells between a lower portion and an upper portion; a second layer made of a composite material based on polymer resin and on fibres, the encapsulating assembly and the photovoltaic cells being located between the first and second layers, at least the first and second layers defining edges of the photovoltaic module, the plurality of photovoltaic cells being spaced apart by a non-zero distance D | 2022-05-26 |
20220165899 | SPACE SOLAR CELL ARRAY WITH CUSTOM VOLTAGE - A solar cell array comprised of one or more solar cells attached to a substrate, such as a pre-fabricated flex circuit, wherein: the substrate includes one or more insulating layers and one or more conductive layers patterned as one or more conductors for making electrical connections with the solar cells; and the substrate includes one or more decision points for removing or adding electrical continuity to the conductors, for customizing circuits of the solar cells to a desired dimension of the solar cells and a desired output voltage. | 2022-05-26 |
20220165900 | FLAT PANEL DETECTOR AND MEDICAL IMAGE DETECTION DEVICE - The present disclosure provides a flat panel detector and a medical image detection device. The flat panel detector includes a base substrate, wherein the base substrate is divided into a plurality of detection units, each detection unit includes a first absorbing layer and a second absorbing layer, both of which are arranged on the base substrate in a laminating manner, the second absorbing layer is located on one side, away from the base substrate, of the first absorbing layer, and an energy level of rays absorbed by the second absorbing layer is smaller than that of rays absorbed by the first absorbing layer; a voltage supply electrode structure; and an output circuit, electrically connected to the voltage supply electrode structure and configured to output a first detection signal of the first absorbing layer and a second detection signal of the second absorbing layer. | 2022-05-26 |
20220165901 | EXTREME AND DEEP ULTRAVIOLET PHOTOVOLTAIC CELL - An extreme and deep ultra-violet photovoltaic device designed to efficiently convert extreme ultra-violet (EUV) and deep ultra violet (DUV) photons originating from an EUV/DUV power source to electrical power via the absorption of photons creating electrons and holes that are subsequently separated via an electric field so as to create a voltage that can drive power in an external circuit. Unlike traditional solar cells, the absorption of the extreme/deep ultra-violet light near the surface of the device requires special structures constructed from large and ultra-large bandgap semiconductors so as to maximize converted power, eliminate absorption losses and provide the needed mechanical integrity. | 2022-05-26 |
20220165902 | AVALANCHE PHOTODIODE SENSOR AND SENSOR DEVICE - To reduce a variation in the characteristics of avalanche photodiode sensors. An avalanche photodiode sensor includes a first semiconductor region, a second semiconductor region, a low-impurity-concentration region, a first contact region, and a second contact region. The first semiconductor region is disposed on a surface of a semiconductor substrate. The second semiconductor region is disposed below the first semiconductor region and has a different conductivity type from the first semiconductor region. The low-impurity-concentration region is disposed adjacent to the second semiconductor region. The first contact region is disposed on the surface of the semiconductor substrate to be adjacent to the first semiconductor region and has electrodes connected thereto. The second contact region is disposed adjacent to the low-impurity-concentration region and has electrodes connected thereto. | 2022-05-26 |