22nd week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090134882 | DISPOSABLE, PRE-CALIBRATED, PRE-VALIDATED SENSORS FOR USE IN BIO-PROCESSING APPLICATIONS - Disposable, pre-sterilized, and pre-calibrated, pre-validated conductivity sensors are provided. These sensors are designed to store sensor-specific information, such as calibration and production information, in a non-volatile memory chip on the sensor. The sensors are calibrated using 0.100 molar potassium chloride (KCl) solutions at 25 degrees Celsius. These sensors may be utilize with in-line systems, closed fluid circuits, bioprocessing systems, or systems which require an aseptic environment while avoiding or reducing cleaning procedures and quality assurance variances. | 2009-05-28 |
20090134883 | DEVICE AND METHOD FOR TESTING A NOISE IMMUNITY CHARACTERISTIC OF ANALOG CIRCUITS - A method for testing a noise immunity characteristic of an analog circuit of an integrated circuit. The device includes: an analog circuit, an internal stable reference signal source, an internal power supply module connected to the analog circuit and adapted to receive, via first input, a high level voltage supply, the device is characterized by including: a signal modulator that is adapted to provide, during a test period, a noisy signal to a second input of the internal power supply module; whereas the internal power supply module is adapted to output a noisy power supply to the analog circuit, in response to the noisy signal; whereas device is adapted to output an output signal representative of a noise immunity characteristic of the analog circuit. The method includes: providing a high level supply voltage to a first input of an internal power supply module of an integrated circuit and receiving signals from the integrated circuit representative of the performance of the analog circuit. The method is characterized by providing, during a test period, a noisy signal to a second input of the internal power supply module; providing a noisy supply voltage to the analog circuit, by the internal power supply module, in response to the noisy signal; and evaluating a noise immunity characteristic of the analog circuit in response to the received signals. | 2009-05-28 |
20090134884 | Method for determining the layer thickness of a tbc coating of at least one blade of a non-positive-displacement machine, a corresponding tbc layer thickness measuring device for carrying out the method and use of the method and the tbc layer thickness measuring device - A method determines the layer thickness of a TBC coating of at least one blade of a non-positive-displacement machine. To this end, at least one electromagnetic wave is emitted to the surface of the at least one blade, the at least one electromagnetic wave is then at least partially reflected by the at least one blade, and the reflected portion of the at least one electromagnetic wave is received and subsequently processed. In addition, the at least one electromagnetic wave is emitted with a frequency matched to the layer thickness of the TBC coating, and the phase of the at least one electromagnetic wave is compared with the phase of the at least one received electromagnetic wave. The at least one emitted electromagnetic wave undergoes a phase change during reflection and the layer thickness of the TBC coating is determined by the phase comparison. | 2009-05-28 |
20090134885 | Transmission line for dielectric measurement and dielectric measuring device having the transmission line - A transmission line substrate includes at least an insulating layer of a predetermined thickness, a pair of conductor layers arranged in a state of being opposed to each other such that the insulating layer is interposed between the conductor layers, the pair of conductor layers functioning as a high-frequency transmission line, and a fault part formed so as to make the conductor layer on one side disconnected, into which a sample to be measured can be introduced. | 2009-05-28 |
20090134886 | ANGLE-MEASURING DEVICE WITH AN ABSOLUTE-TYPE DISK CAPACITIVE SENSOR - An absolute position measuring device suitable for wide-angle range measurement and providing the advantages of high precision, high resolution, and easy data processing. The measuring device comprises a disk capacitive sensor, a measurement signal processing unit, a data processing unit, and a display unit. The disk capacitive sensor comprises a rough division sensor and a fine division sensor. The pitch point value of the fine division sensor is at least two times higher than two resolutions of the rough division sensor. The rough division sensor and the fine division sensor have the same zero position. The grids of the two rough division and fine division sensors are independent to each other, are free of electric coherence, and are fixed relatively to each other. The grid has an exclusive absolute displacement value within a single pitch measurement range. | 2009-05-28 |
20090134887 | CONTACT SENSOR - A contact sensor is disclosed. The contact sensor includes a main body and at least one conductor. At least one end of the conductor is disposed on the main body and a contact surface is on one side of the conductor for contact the body surface. The surface of the conductor is in the shape of arc. By the contact surface of the conductor, the contact sensor contacts the human body easily without tangling hair. Moreover, there is not need for the present invention to apply any conductive gel on the body surface so that the measurement of physiological signals is easily and conveniently. | 2009-05-28 |
20090134888 | Conductivity test jig, conductivity test apparatus having conductivity test jig, and a method of testing conductivity - The conductivity test jig includes: a jig main body; a holding member; a conductivity test unit; a conductivity member; an air cylinder; a jig main body; and a second air cylinder. The jig main body has a hole for receiving the connector. The holding member holds the connector in the hole. The conductivity test unit is detachably attached to the connector. When the conductivity test unit moves close to the connector, the conductivity member is electrically connected to the terminals of the connector. The air cylinder makes the conductivity test unit contact the connector, and removes the conductivity test unit from the connector. The push-out member is interposed between the connector and the jig main body in an insertion direction of the connector in the hole. The second air cylinder moves the push-out member in the insertion direction. | 2009-05-28 |
20090134889 | MOISTURE SENSOR APPARATUS AND METHOD - A sensor to detect water moisture in soil or other water permeable materials having a capacitive probe or a transmission line acting as a probe, and electronic circuit. The sensor circuit includes a periodic signal generator to produce a carrier wave, which stimulates the transmission line, through a resistive or reactive coupling element. The resistive element also forms a voltage divider with the transmission line, wherein the output of the voltage divider, is demodulated with a simple AM demodulator, such as a peak detector. This demodulated signal is related to the dielectric constant, and thus the moisture of the material surrounding the transmission line. | 2009-05-28 |
20090134890 | METHOD AND STRUCTURE FOR IMPLEMENTING A RESISTOR LADDER - An switching interface is provided for use on a vehicle. In an exemplary embodiment the switching interface comprises a receiver and a switch assembly. The receiver may include an input node; a regulated power supply electrically couple to the input node; and an analog-to-digital (A/D) converter configured to measure a voltage potential between the input node and the receiver ground. The switch assembly may include a first resistor electrically coupled to the receiver input node, the first resistor having a first resistive value; a first switch electrically coupled between the first resistor and a switch assembly ground; a second resistor electrically coupled to the first resistor and the first switch, the second resistor having a second resistive value; and a second switch coupled between the second resistor and the switch assembly ground. The first and second resistive values may be selected such that the switch assembly has a separate switch assembly state for each switch with an associated voltage potential measured between the input node and ground for each of the switch assembly states. | 2009-05-28 |
20090134891 | IC TESTER - An object of the invention is to implement an IC tester wherein an analog test module can be provided at a test head while maintaining flexibility of the test head. The IC tester comprises an analog test module for testing an analog signal against the device under test. The analog test module comprises a main substrate, connected to the device under test, a first sub-substrate connected to the main substrate, the first sub-substrate comprising first analog circuits and first digital circuits electrically connected to the first analog circuits, wherein an analog test is conducted by the first analog circuits, and the first digital circuits, and a second sub-substrate connected to the main substrate, the second sub-substrate comprising second analog circuits and second digital circuits electrically connected to the second analog circuits, wherein an analog test is conducted by the second analog circuits, and the second digital circuits. | 2009-05-28 |
20090134892 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches. | 2009-05-28 |
20090134893 | Test Instrument Probe with MEMS Attenuator Circuit - One or more micromachined (MEMS) switches switch attenuators, such as resistors, into or out of a signal path, such as of a test instrument. The MEMS switches can be fabricated on the same substrate as the attenuators, or the switches or attenuators can be mounted on the same substrate as the others are fabricated. An instrument probe includes attenuators and MEMS switches that are controlled by the instrument and/or by a control circuit in the probe. Optionally, the probe includes reactive elements, such as capacitors, and MEMS switches to compensate for electrical characteristics of the probe and/or probe lead, and the probe or a test instrument automatically sets the MEMS switches to connect appropriate ones of the reactive elements to a signal path within the probe. | 2009-05-28 |
20090134894 | INSPECTION APPARATUS - An inspection apparatus includes a movable mounting table for mounting thereon a target object, a probe card disposed above the mounting table and a control unit for controlling the mounting table. The target object is inspected by bringing a plurality of electrode pads of the target object mounted on the mounting table into contact with a plurality of probes of the probe card with a predetermined contact load by overdriving the mounting table. Further, the mounting table includes a mounting body whose temperature is controllable, a support body for supporting the mounting body, an elevation driving mechanism provided in the support body and pressure sensors provided between the mounting body and the support body to thereby detect the contact load. The control unit controls the elevation driving mechanism in accordance with detection signals from the pressure sensors. | 2009-05-28 |
20090134895 | HIGH PERFORMANCE PROBE SYSTEM - A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads. | 2009-05-28 |
20090134896 | Interface for testing semiconductors - A system that includes an imaging device for effectively positioning a probe for testing a semiconductor wafer. | 2009-05-28 |
20090134897 | APPARATUS AND METHOD FOR LIMITING OVER TRAVEL IN A PROBE CARD ASSEMBLY - Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly. | 2009-05-28 |
20090134898 | Coaxial Spring Probe Grounding Method - The present invention provides a spring probe array for use in a semiconductor test fixture wherein the spring probes provide electrical continuity between a device under test and a test system. The array includes a spring probe retaining device with sockets for supporting spring probes. Fixed within the retaining device are a plurality of signal spring probes and a plurality of ground spring probes. A grounding board is fixed internal and captive to the spring probe retaining device and provides a common grounding connection between coaxial spring probes and adjacent non-coaxial spring probes in the spring probe retaining device. | 2009-05-28 |
20090134899 | PROBE ASSEMBLY WITH MULTI-DIRECTIONAL FREEDOM OF MOTION AND MOUNTING ASSEMBLY THEREFOR - An improved test probe assembly has an improved mounting assembly which provides the test probe multi-directional freedom of movement with respect to a base in order to resist damage frequently caused to the test probe. The improved mounting assembly may, for example, include at least a first resilient mount disposed on the base and having at least a first support and at least a first resilient element. The at least a first resilient element, which may, for example, be at least a first spring, is deflectable when the test probe engages a structure, such as a device under testing (DUT). Accordingly, the improved test probe assembly of the invention can be deflected an infinite number of positions, in order to resist damage caused, for example, by misalignment between the probe and the DUT. | 2009-05-28 |
20090134900 | Test apparatus, pin electronics card, electrical device and switch - Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that receives an output signal of the device under test, and makes judgment concerning pass/fail of the device under test based on the output signal; an internal circuit that exchanges signals between the device under test and the pattern generating section or the judging section; a first transmission line that connects the internal circuit to the device under test; and a first switch that connects the first transmission line to a ground potential in not testing the device under test, and cuts off the first transmission line from the ground potential in testing of the device under test. | 2009-05-28 |
20090134901 | INTEGRATED CIRCUIT DIE STRUCTURE SIMPLIFYING IC TESTING AND TESTING METHOD THEREOF - By adding multiplexing units to selectively transmit signals associated with a functional circuitry of an IC die to test pads, a probe card with less pin counts than the pad number of the IC die can be utilized for testing the functional circuitry. Therefore, the pad number/pad pitch of the IC die is not limited by the pitch of the conventional probe card. A high pin count IC die design is thereby available. | 2009-05-28 |
20090134902 | INTEGRATED CIRCUIT PACKAGE HAVING REVERSIBLE ESD PROTECTION - Methods, systems, and apparatuses are provided for integrated circuit packages and for enabling electrostatic discharge (ESD) testing of the same. A package includes an integrated circuit chip, a substrate, a first electrically conductive trace, and a second electrically conductive trace. The substrate includes a first electrically conductive region and a second electrically conductive region. The first region is coupled to a first ground signal of the chip, and the second region is coupled to a second ground signal of the chip. The first trace is coupled to the first region and the second trace is coupled to the second region. A portion of the first trace is proximate to a portion of the second trace. An electrically conductive material may be deposited to electrically couple the first and second traces to enable ESD protection testing of the package. | 2009-05-28 |
20090134903 | LOOP-BACK TESTING METHOD AND APPARATUS FOR IC - A test system for testing operability of integrated circuits includes: a first IC, for modulating a first signal to generate a first modulated signal and transmitting the first modulated signal, and for receiving a second modulated signal and demodulating the second modulated signal to generate a second signal; a first loop antenna, coupled to the first IC, for receiving the first modulated signal and sending the first modulated signal back to the first IC as the second modulated signal; and a tester circuit coupled to the first IC, for generating the first signal to the first IC, receiving the second signal from the first IC, and comparing the first signal and the second signal to determine the operability of the first IC. | 2009-05-28 |
20090134904 | ANALOG IC HAVING TEST ARRANGEMENT AND TEST METHOD FOR SUCH AN IC - An integrated circuit (IC) comprises a plurality of analog stages ( | 2009-05-28 |
20090134905 | SYSTEM FOR MEASURING SIGNAL PATH RESISTANCE FOR AN INTEGRATED CIRCUIT TESTER INTERCONNECT STRUCTURE - Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I/O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed. | 2009-05-28 |
20090134906 | Resilient Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 2009-05-28 |
20090134907 | Fault Tolerant Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 2009-05-28 |
20090134908 | Multi-Functional Logic Gate Device and Programmable Integrated Circuit Device Using the Same - Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group. | 2009-05-28 |
20090134909 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element is positioned above a transistor material layer deposited on a substrate layer. | 2009-05-28 |
20090134910 | RECONFIGURABLE LOGIC STRUCTURES - Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies. | 2009-05-28 |
20090134911 | Drive method for driving element having capacity impedance, drive device, and imaging device - Three devices such as electric charge-coupled devices are each included in one of three phase impedance circuits composing a 3-phase LC resonance circuit as a device having a capacitive impedance. A driver circuit applies either of a logic level of 0, a high-impedance level or a logic level of 1 to each of nodes Node_A, Node_B and Node_C of the phase impedance circuits so as to result in sequential transitions of a state of resonance among the phase impedance circuits. In an operation to drive the phase impedance circuits, either of the logic level of 0, the high-impedance level and the logic level of 1 is applied to each of the nodes so as to sustain a phase difference of 2π/3 between the phase impedance circuits. In this way, the logical levels and the phases of the logical levels are assigned to the nodes in such a way that the logical levels do not overlap with each other at any timings each corresponding to a point of time. Thus, a driving apparatus for driving the devices each having a capacitive impedance is capable of reducing the power consumption. | 2009-05-28 |
20090134912 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 2009-05-28 |
20090134913 | SIGNAL COMPARISON CIRCUIT - A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison. | 2009-05-28 |
20090134914 | LOW OFFSET COMPARATOR AND OFFSET CANCELLATION METHOD THEREOF - A low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage are configured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage. | 2009-05-28 |
20090134915 | Signal converting apparatus with a relay function wire terminal - A signal converting apparatus with a relay function connector includes a body, a signal converting unit installed in the body and having a signal connecting portion connected to an electronic device for transmitting or receiving a first signal, and at least one first signal line is extended into the body and connected to the signal converting unit. The signal connecting portion is connected to another signal converting apparatus through the first signal line, and a relay function wire terminal is installed in the body and has an end connected to a second signal line. The second signal line is connected to the electronic device or an electric equipment for transmitting/receiving a second signal to/from the electronic device or electric equipment respectively. The relay function wire terminal is connected to a third signal line, and the third signal line is connected to an electric adapter of another signal converting apparatus. | 2009-05-28 |
20090134916 | Charge Domain Filter Circuit - A charge domain filter circuit includes a first signal output portion, a second signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. The second signal output portion outputs a second signal that is sampled at the same time interval as the first signal and at a different time. The adder portion adds the first signal and the second signal together and outputs the result. The second signal output portion is capable of selecting the time to sample the second signal from among a plurality of times. | 2009-05-28 |
20090134917 | VOLTAGE DIVIDER HAVING VARIED OUTPUT LEVELS DEPENDING ON FREQUENCY AND PLL INCLUDING THE SAME - A voltage divider for dividing an input voltage includes a fixed resistor, a variable resistor, an input node and an output node. The fixed resistor has a fixed resistance value independent of an operating frequency, and includes at least one resistance device. The variable resistor has a variable resistance value that varies corresponding to a variation of the operating frequency. The input node receives the input voltage, and the output node outputs an output voltage, which includes the input voltage divided based on the fixed resistance value and the variable resistance value. | 2009-05-28 |
20090134918 | JITTER GENERATOR FOR GENERATING JITTERED CLOCK SIGNAL - A jitter generator for generating a jittered clock signal, includes a jitter control signal generator and a jittered clock generator. The jitter control signal generator is utilized for selecting a digital control code from a plurality of candidate digital control codes at individual time points and respectively outputting a plurality of selected digital control codes. The jittered clock generator is coupled to the jitter control signal generator, and utilized for generating the jittered clock signal. The jittered clock generator dynamically adjusts the jittered clock signal according to the plurality of different digital control codes. | 2009-05-28 |
20090134919 | Input buffer for high-voltage signal application - An input buffer for a high-voltage signal application is provided. The input buffer uses a clamper and an inverter to clamp the output voltage in a proper range even if the input voltage is too high or too low. The proper range of the output voltage is controlled by a voltage source and the ground, so that an electrical device can be triggered safely by the output voltage. | 2009-05-28 |
20090134920 | Semiconductor Device - A semiconductor device in which a transistor can supply an accurate current to a load (EL pixel and signal line) without being influenced by variations is provided. | 2009-05-28 |
20090134921 | SLOPE COMPENSATION METHOD AND CIRCUIT FOR A PEAK CURRENT CONTROL MODE POWER CONVERTER CIRCUIT - A slope compensation method and circuit for a peak current control mode power converter circuit is provided. Since the power converter circuit has a synchronous signal of a driven signal of enabling the first primary switch and the second primary switch, a triangular wave signal is generated. The driven signals of the first and second primary switches determine the ramp up time of the triangular wave signal. The triangular wave signal is added to one of the output DC voltage feedback signal of the corresponding power converter circuit that are used to compare with a current peak value of the voltage feedback signals. Therefore, a high level triangular wave DC voltage feedback signal that is higher than the DC voltage feedback signal is formed, and the switching noises do not effect comparing result of a PWM controller of the power converter circuit. | 2009-05-28 |
20090134922 | Start-up circuit for bias circuit - A start-up circuit for a bias circuit is disclosed. The start-up circuit uses a switch to provide an activating signal to pull the bias circuit out of the null mode. The switch is triggered by a pulse from an external pulse supply or a combined pulse generator. After the pulse, the bias circuit enters a steady operational state and the start-up circuit stops operating. Therefore the start-up circuit has advantages of wide supply range, no standby current, short start-up time and simple circuit topology. | 2009-05-28 |
20090134923 | ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL) - A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL. | 2009-05-28 |
20090134924 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle. | 2009-05-28 |
20090134925 | APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES - A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor. | 2009-05-28 |
20090134926 | MULTI-PHASE NEGATIVE DELAY PULSE GENERATOR - A multi-phase pulse generator provides an even number of pulse signals of same phase difference and pulse signals of higher frequency by applying a negative delay concept. The multi-phase pulse generator includes a first delay block with first unit blocks which have a first negative delay property respectively and of which an even number is ring-coupled; and a second delay block including second unit blocks which have a second negative delay property respectively and of which even number is ring-coupled. The number of the first unit block and the number of the second unit block are the same. A plurality of output nodes is formed based on one-to-one sharing between the first unit block and the second unit block having output signals of different level. Each output node outputs a pulse generated by racing the output signals of different level to each other which are provided from the first unit block and the second unit block connected to the each output node. | 2009-05-28 |
20090134927 | DIGITAL POTENTIOMETER SYSTEM - A system or circuit for simulating a potentiometer, thermistor, or the like. A pulse stream, having a duty cycle which is varied as a changing pulse width or as a differing number of time slices per time period, may be input to the system. The pulse stream to a transistor or switch-like mechanism may allow a controlled connection of a fixed value resistor to a reference voltage or ground to provide various resultant values of impedance or resistance. A measuring circuit connected to the output of the system may determine a value which is of the fixed value resistor divided by the duty cycle of the pulse train effectively controlling the connection of the resistor to ground. One or more additional circuits may be connected in parallel to achieve greater accuracy. | 2009-05-28 |
20090134928 | Attenuator - In the existing technique in which the attenuation characteristic of an attenuator is adjusted by a voltage value, there are problems that a scale of a circuit of the attenuator increases because a new circuit for supplying voltage such as a step-down circuit becomes necessary, and that a thermal noise and a shot noise are mixed in an output signal of the attenuator. To solve the above-mentioned problems, provided is an attenuator comprising a T-type two terminal pair network including first and second circuits connected in series, and a third circuit connected in shunt between these first and second circuits. A shunt capacitor is connected between the first and second circuits independent from the third circuit. | 2009-05-28 |
20090134929 | Level shifter for high-speed and low-leakage operation - The present invention discloses a voltage level shifter capable of interfacing between two circuit systems having different operating voltage swings. The voltage level shifter comprises an input buffer having a low supply voltage for inverting an external input signal to an internal input signal, and an output buffer having a high supply voltage for inverting the internal input signal to an external output signal. The high level of the external input signal is lower than the high level of the external output signal. The voltage level shifter is designed such that the input buffer is operating to achieve a low-leakage and high-speed performance. | 2009-05-28 |
20090134930 | LEVEL SHIFT CIRCUIT - A level shift circuit prevents a through current in an output circuit connected to a high-voltage power supply, thereby reducing power consumption and noise and enabling a high-speed operation. The level shift circuit includes first and second bias generating circuits that supply a gate bias voltage to each of a PMOS transistor as a first transistor and a NMOS transistor as a second transistor. Each of the first and second bias voltage generating circuits includes a series connection of a diode-connected PMOS transistor and a diode-connected NMOS transistor. The discharge of a capacitor to the high-voltage power supply is prevented, and a through current is prevented when an output signal transitions from a high-level to a low-level and vice versa, whereby power consumption and noise can be reduced. | 2009-05-28 |
20090134931 | MULTIPHASE LEVEL SHIFT SYSTEM - Each of n level shifters (LS | 2009-05-28 |
20090134932 | LOW FLICKER NOISE MIXER AND BUFFER - Low flicker noise mixer and buffer. This design employs some native metal oxide semiconductor field-effect transistors (MOSFETs) (e.g., having no threshold voltage) within a passive mixer whose gates are driven using clock signals. These native MOSFETs maybe biased at one half of the power supply voltage to provide a lower noise figure. A cooperatively operating buffer employs appropriately places MOSFETs and resistors to ensure the desired gain. Relatively larger valued resistors can be employed to provide for higher voltage gain, and this can sometimes be accompanied with using a higher than typical power supply voltage. Source followers serve as output buffers and also ensure the required output DC voltage level as well. It is also noted that this design can be implemented using n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) of p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs). | 2009-05-28 |
20090134933 | OUTPUT DRIVER AND METHOD OF OPERATION THEREOF - The method of the present invention for switching an output driver of the type comprising an n-mos transistor and a p-mos transistor configured in a push-pull arrangement operates by directly monitoring the level of the output signal OUT. The method comprises slowly switching off the input to the initially designated active transistor; monitoring the variation in output voltage level in response thereto; and when a desired change in output level is detected the switching the initially designated output transistor on completely and fast. Using this method the parasitic currents in the diodes are much smaller in time and amplitude. | 2009-05-28 |
20090134934 | ELECTRONIC DEVICE - An electronic device includes a power interface for transmitting power, an integrated circuit capable of resetting, and a switch circuit. The switch circuit is connected to the power interface for transmitting the power to the integrated circuit after the integrated circuit is reset and stop transmitting the power to the integrated circuit if the integrated circuit is resetting. | 2009-05-28 |
20090134935 | ANTI-FUSE REPAIR CONTROL CIRCUIT FOR PREVENTING STRESS ON CIRCUIT PARTS - The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal. | 2009-05-28 |
20090134936 | CHARGE PUMP CIRCUIT AND CELL THEREOF - A charge pump cell with an input and output nodes includes a first, second, and third equalization units, and a first, second, and third capacitors. The input node is coupled to the inputs of the first, second and third equalization units, and the output node is coupled to the second equalization unit. One end of the second capacitor is coupled to the control end of the first equalization unit for enabling or disabling the first equalization unit, and also coupled to the output of the third equalization unit. One end of the third capacitor is coupled to the output of the second equalization unit. One end of the first capacitor is coupled to the control ends of the second and third equalization units, and also coupled to the output of the first equalization unit. | 2009-05-28 |
20090134937 | Charge pump circuit - A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit. | 2009-05-28 |
20090134938 | Charge Domain Filter Circuit - A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied. | 2009-05-28 |
20090134939 | Transistor device and method - A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer between semiconductor source and drain layers, the layers being separated by heterosteps; the gate layer having a thickness of less than about 100 Angstroms; and source, gate, and drain electrodes respectively coupled with said source, gate, and drain layers. Separation of the gate by heterosteps, rather than an oxide layer, has very substantial advantages. | 2009-05-28 |
20090134940 | BALANCED AMPLIFIER AND ELECTRONIC CIRCUIT - A balanced amplifier ( | 2009-05-28 |
20090134941 | Negative Resistance Input Amplifier Circuit and Oscillation Circuit - The present invention provides a negative resistance input amplifier including: a microstrip line having one end connected to a collector of a transistor and the other end being open with a length of ¼ of a wavelength λ at a predetermined frequency f; and a microstrip line having one end connected to an emitter of the transistor and the other end grounded with a length of ¼ of the wavelength λ at the predetermined frequency f so that impedance viewed from a base of the transistor becomes negative only at around a target frequency, and an oscillator using the negative resistance input amplifier. | 2009-05-28 |
20090134942 | RADIO FREQUENCY AMPLIFIER WITH CONSTANT GAIN SETTING - Radio frequency amplifier with constant gain setting. A circuitry that includes triple well connected MOSFETs is employed to eliminate body effects therein. The voltage gain as presented herein, being implemented using a ratio of certain elements within the circuitry, is immune to variations in temperature, power supply voltage, and process variations. One implementation employs an array of selectable MOSFETs to allow for more than one gain setting to be provided by the amplifier. Such an amplifier has a variable/selectable gain setting. An appropriately placed MOSFET is employed to provide the desired input impedance (e.g., 50Ω). This design can be implemented using multiple n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) (some of which are triple well connected) and p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs), or alternatively using P-MOSFETs and N-MOSFETs. | 2009-05-28 |
20090134943 | Voltage Control Oscillator - A voltage control oscillator is provided in which a resistance voltage dividing circuit is formed by a switching element so as to arbitrarily change a gain and a reference value of a control voltage, an IC chip area is reduced, and reduction of a noise of an AFC voltage and improvement of C/N are realized. | 2009-05-28 |
20090134944 | CAPACITIVE-DEGENERATION DOUBLE CROSS-COUPLED VOLTAGE-CONTROLLED OSCILLATOR - A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance. | 2009-05-28 |
20090134945 | CLOCK GENERATOR - A clock generator has a ring oscillator which has odd-numbered inverters connected in series, wherein an output of the inverter at a final stage is inputted into the inverter at a first stage to generate and output a clock signal, a frequency divider which receives the clock signal outputted from the ring oscillator, and divides frequency thereof for output, and a heater which is on-off controlled based on the output of the frequency divider and heats the ring oscillator when turned on. | 2009-05-28 |
20090134946 | Oscillation frequency control circuit - Provided is an oscillation frequency control circuit, which corrects its own frequency so that it can hold an oscillation frequency stably even when it does not have an input of a highly stable reference signal but makes a self-run. The oscillation frequency control circuit comprises a voltage-controlled oscillator, a frequency divider, a phase comparator, a loop filter, a detecting circuit for detecting an external reference signal, a PWM circuit for generating pulses, when pulse generating information inputs, to output the pulses to the loop filter, a memory for storing the pulse generating information corresponding to voltage information, a switch for turning ON/OFF the connection between the phase comparator and the loop filter, and a CPU for turning ON the switch, if the level of the external reference signal detected by the detecting circuit is within a proper range, but OFF the switch, if the level is outside of the proper range, thereby to output the pulse generating information stored in the memory, to the PWM circuit. | 2009-05-28 |
20090134947 | Green technology platform for green chip design of MS0-GBQ-AMC-LCO clock, PLL-free SerDes, tire safety, inductorless-PMU & PA on vialess-ESDSL-PCB - The fundamental breakthrough in green technology is the planar EMI-Free Planar Inductor. The EMI-Free Planar Inductor is the backbone of the platform of green technology. The platform of green technology contains the Xtaless ClockChip, Inductorless PMU & PA and ESDS-PCB to provide the green technology for green chip design. Especially for the 4 | 2009-05-28 |
20090134948 | PULSE MODULATION METHOD - A pulse modulation method divides code comprising 4N-bit data into 2-bit units of data. For each pulse signal having a fixed pulse width tw, a code modulated signal is generated by pausing between pulse pause intervals Tr. An adjusted time width of between ½ and 1 times the fixed pulse width tw is taken to be Δt. One of time widths 0, Δt, 2Δt, and 3Δt is added to a fixed pause period tm of time intervals according to a corresponding value of the 2-bit data. If the sum total time TD of the code modulated signal is an interval of at least [(2tw+2tm+3Δt)N+Δt], each pulse pause interval Tr is substituted by a pulse pause interval Tr corresponding to the inverted 2-bit data. An inversion flag signal expresses that inversion information is added to the code modulated signal. | 2009-05-28 |
20090134949 | METHODS AND APPARATUSES FOR INDUCTOR TUNING IN RADIO FREQUENCY INTEGRATED CIRCUITS - An apparatus for matching impedance within a Radio Frequency (RF) integrated circuit is presented. The apparatus includes a first impedance element placed in an RF signal path, an first inductor fabricated on the integrated circuit and connected to the first impedance element, and an adjustable capacitance circuit connected in series with the first inductor and placed between the first inductor and a ground node, where the adjustable capacitance circuit is adjusted to tune the inductance of the first inductor. A method for tuning an inductor is presented. The method includes ascertaining a target inductance value for an inductor in a RF integrated circuit, and determining a capacitance value of an adjustable capacitance circuit so that, when coupled to the inductor, the combined impedance of the adjustable capacitance circuit and the inductor is tuned to the ascertained target inductance value. | 2009-05-28 |
20090134950 | PASSIVE COMPONENT - A passive component is provided with a filter section employing a nonequilibrium input/output system, which has an input side resonator connected to a nonequilibrium input terminal, and an output side resonator coupled with the input side resonator; and a converting section having two double line coupled lines. An output stage of the filter section is connected with an input stage of the converting section through a first capacitor, and an input stage of the filter section is connected with the input stage of the converting section through a second capacitor. Namely, the second capacitor functions as a jump capacitor. The position of an attenuation pole is permitted to be adjusted by a second capacitor in a region low in frequency characteristics. | 2009-05-28 |
20090134951 | BROADBAND RECIPROCAL ACTIVE BALUN STRUCTURE - The present invention relates to the field of electronic devices known as baluns. It concerns an active balun which is broadband and reciprocal. Embodiments of the invention integrate an active splitter balun with an active combiner balun so as to form three transmission lines. A first active coupling is provided between the first and second transmission lines and a second active coupling is provided between the first and third transmission lines. The active couplings are provided by means of amplifier cells distributed along the transmission lines. Embodiments of the invention have configurable means for polarizing the different amplifier cells so as to create a specific coupling direction between the various transmission lines. The device according to the invention can be applied in the field of broadband mixers which are used, notably, in radio transmission and reception circuits. | 2009-05-28 |
20090134952 | POWER HARVESTING SIGNAL LINE TERMINATION - In various embodiments of the invention, a power-harvesting termination circuit may be used to 1) match the impedance of a signal line being terminated, and 2) recover a portion of electrical power from a signal on the signal line and provide the recovered power as an electrical voltage to be used to power other circuits. The power may be harvested at either the receiving device or at the transmitting device. | 2009-05-28 |
20090134953 | Radio frequency devices with enhanced ground structure. - Tunable radio frequency (RF) devices, such as phase shifters and filters, are formed by depositing thin film layers on a substrate and patterning the thin film layers by various lithography techniques. A thin film metal layer is patterned to form a plurality of capacitors and inductors, leaving at least two grounding regions that lie closely adjacent the capacitors and inductors. As patterned portions of the grounding regions are electrically isolated from each other. Performance of the devices are improved by electrically bridging the differential potential grounding regions. | 2009-05-28 |
20090134954 | DIFFERENTIAL BAND-PASS FILTER HAVING SYMMETRICALLY INTERWOVEN INDUCTORS - One embodiment of the invention relates to a dynamically adjustable differential band-pass filter. This band-pass filter includes a first leg that has an input portion and an output portion with a first inductor therebetween. It also includes a second leg in parallel with the first leg, where the second leg has an input portion and an output portion with a second inductor therebetween. The first inductor is symmetrically inter-woven with the second inductor. In some embodiments, the band pass filter is configured to compensate for losses due to the inductors. Other band-pass filters and methods are also disclosed. | 2009-05-28 |
20090134955 | BOOSTED-BIAS TUNABLE FILTER WITH DYNAMIC CALIBRATION - In a signal communication device, a frequency-selective filter has at least one component that is biased by a control signal to establish a center frequency of the frequency-selective filter. A closed-loop bias generator is provided to generate the control signal and to adjust the control signal based, at least in part, on a comparison of the control signal and a reference signal. | 2009-05-28 |
20090134956 | MULTILAYER ELECTRONIC COMPONENT AND MULTILAYER ARRAY ELECTRONIC COMPONENT - A multilayer array electronic component includes a multilayer composite including a helical coil and a capacitor that are defined by stacking a coil conductor, a capacitor conductor, and a ceramic sheet on one another. External electrodes are arranged on the surface of the multilayer composite and electrically connected to the helical coil or the capacitor. A direction identification mark is arranged on the upper surface of the multilayer composite and electrically connected to any of the external electrodes through the helical coil or the capacitor. | 2009-05-28 |
20090134957 | Film bulk acoustic resonator package and method for manufacturing the same - A film bulky acoustic resonator (FBAR) package and a method for manufacturing the package are provided. A top surface of a FBAR on a substrate is entirely covered with a cap and a signal line connected to an external circuit unit is directly attached to a bonding pad of the FBAR through a substrate via-hole formed through the substrate. Since the signal line connected to the external circuit unit is directly attached to the bonding pad of the FBAR through the substrate via-hole formed through the substrate, a process for attaining a signal line connection space of the external circuit unit can be omitted. Therefore, an overall working process can be simplified and the manufacturing cost can be reduced, while improving the production yield. Furthermore, a size of the FBAR can be remarkably reduced. In addition, as described above, when the signal line connected to the external circuit unit is directly attached to the boding pad through a bottom of the substrate, a length of the signal line can be minimized and thus the deterioration of the FBAR, which may be caused during a wafer level packaging process, can be reduced. | 2009-05-28 |
20090134958 | SURFACE ACOUSTIC WAVE FILTER AND SURFACE ACOUSTIC WAVE DUPLEXER - A surface acoustic wave filter which includes a first terminal at the input side, a second terminal at the output side, a plurality of resonators electrically connected between the first and the second terminals, and a piezoelectric substrate provided on the upper surfaces of first and second terminals and the plurality of resonators. The piezoelectric substrate is made to have a thickness that is not thicker than 0.2 mm. The filtering characteristic of surface acoustic wave filter can be improved by taking advantage of the above structure. | 2009-05-28 |
20090134959 | HF TERMINATING RESISTOR HAVING A PLANAR LAYER STRUCTURE - The invention relates to an HF terminating resistor having a planar layer structure which, on a substrate ( | 2009-05-28 |
20090134960 | Linear variable voltage diode capacitor and adaptive matching networks - An integrated variable voltage diode capacitor topology applied to a circuit providing a variable voltage load for controlling variable capacitance. The topology includes a first pair of anti-series varactor diodes, wherein the diode power-law exponent n for the first pair of anti-series varactor diodes in the circuit is equal or greater than 0.5, and the first pair of anti-series varactor diodes have an unequal size ratio that is set to control third-order distortion. The topology also includes a center tap between the first pair anti-series varactor diodes for application of the variable voltage load. In preferred embodiments, a second pair of anti-series varactor diodes is arranged anti-parallel to the first pair of anti-series varactor diodes so the combination of the first pair of anti-series varactor diodes and the second pair of anti-series varactor diodes control second-order distortion as well. | 2009-05-28 |
20090134961 | Apparatus for Monitoring the State of a Protective Device of a Machine - The invention relates to an apparatus ( | 2009-05-28 |
20090134962 | OPENING/CLOSING DEVICE - A plurality of pairs of a movable contact point and a fixed contact point, which are opposite so that they can be contacted with and separated from each other, are provided in parallel and connected in series so that an electrical current flows in the same direction between the movable contact point and the fixed contact point, which are simultaneously closed. Permanent magnets are disposed on lateral sides of the movable contact point and the fixed contact point so that a magnetic field, which extends an arc generated between the contact points in either an upward or downward direction, is formed. | 2009-05-28 |
20090134963 | FLEXIBLE MAGNETIC SHEET SYSTEMS - Flexible magnetic sheets made with high-energy strontium ferrite, such as to decrease thickness with maintaining a strong magnetic energy (over one Megagause-Oersted) as well as flexibility. | 2009-05-28 |
20090134964 | Lead frame-based discrete power inductor - A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil. | 2009-05-28 |
20090134965 | EFFICIENT METHODOLOGY FOR THE DECOUPLING FOR MULTI-LOOP RF COIL GEOMETRIES FOR MAGNETIC RESONANCE IMAGING - A multi-loop RF coil includes a plurality of channels and is formed of a plurality of coil elements. The coil includes a pair of coil elements that at least partially overlap with one another as part of a geometric decoupling scheme between the pair of coil elements. | 2009-05-28 |
20090134966 | Pre-loaded force sensing resistor and method - A force sensing resistor (FSR) includes a substrate having separated electrically conductive traces and another substrate having a resistive layer in which the substrates are subjected to a biasing force such that the substrates contact one another with the resistive layer electrically connecting the traces with a resistance inversely dependent on the biasing force. Upon an external force applied towards a substrate, the substrates contact one another with a total force which is the sum of the forces with the resistive layer electrically connecting the traces with a resistance inversely dependent on the total force. An FSR output which is a function of the resistance is measured. Whether a change in magnitude of the FSR output during a time interval is greater than a threshold is determined. A touch applied on the FSR is detected during the time interval if the change is greater than the threshold. | 2009-05-28 |
20090134967 | RESISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a glazed metal film resistor device excellent in TCR characteristics with using an economical base body containing glass by reducing affection to TCR characteristics caused by glass contained in the base body. The resistor device comprises base body | 2009-05-28 |
20090134968 | SEGMENTING TIME BASED ON THE GEOGRAPHIC DISTRIBUTION OF ACTIVITY IN SENSOR DATA - The invention segments detector input according to the time and the level of activity in different geographic regions of a locality. In one embodiment of the invention the detector input is comprised of video stream from one or more cameras to identify activity in the video. In one embodiment of the invention the detector input is comprised of sensor outputs such as RFID, pressure plates, etc. Various embodiments of the invention include identifying boundaries based on the level of activity. In embodiments of the invention, the boundaries can be used to select time dimensions. In one embodiment, by recognizing time dimensions with distinctive activity patterns, systems can better present overviews of activity over time. | 2009-05-28 |
20090134969 | SYSTEM AND METHOD FOR TRANSMITTING AND RECEIVING INFORMATION ON A NEIGHBORHOOD AREA NETWORK - In accordance with the techniques discussed herein, a device can access data stored by other devices or units on a network. Devices recording data can provide the data to another device for display to a user. A user can then use the information to make decisions about how and when to control energy use. A communications logic unit associated with the radio can format messages including data from a data storage unit. Data can be stored in tables and written to or retrieved by reading or writing part of the table or the entire table. | 2009-05-28 |
20090134970 | IN-VEHICLE ELECTRONIC CONTROL APPARATUS HAVING MONITORING CONTROL CIRCUIT - An in-vehicle electronic control apparatus, having a monitoring control circuit, according to the present invention is configured in such a way that serial interface circuits | 2009-05-28 |
20090134971 | ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - An exemplary electronic device is disclosed herein. The electronic device includes an instruction generator, a main processing unit, a recorder, and a storage unit. The instruction generator is configured for generating control signals in response to user's inputs to the electronic device. The main processing unit is configured for performing corresponding functions according to the control signals. The recorder is configured for reproducing operation information comprising information of the control signals. The storage unit is used for storing the operation information. | 2009-05-28 |
20090134972 | METHOD AND SYSTEM FOR BIOMETRIC KEYBOARD - A method for training a computing system using keyboard biometric information. The method includes depressing two or more keys on a keyboard input device for a first sequence of keys. The method then determines a key press time for each of the two or more keys to provide a key press time characteristic in the first sequence of keys. The method also determines a flight time between a first key and a second key to provide a flight time characteristic in the first sequence of keys, the first key being within the two or more keys. The method includes storing the key press time characteristic and the flight time characteristic for the first sequence of keys, and displaying indications associated with the first sequence of keys on a display device provided on a portion of the keyboard input device. | 2009-05-28 |
20090134973 | Plug & Play and Security Via RFID For Handheld Devices - A system comprises an accessory and a mobile device. The accessory comprises an RFID tag including accessory information. The mobile device comprises an RFID reader reading the RFID tag. The mobile device is configured to operate with the accessory based on the accessory information. A method comprises receiving, by an RFID reader of a mobile device, an RFID signal from an RFID tag associated with an accessory of the mobile device; determining accessory information from the RFID signal; and configuring the mobile device to operate with the accessory based on the accessory information. | 2009-05-28 |
20090134974 | APPARATUS AND METHOD FOR MANAGING RADIO FREQUENCY INDENTIFICATION READER - An apparatus for managing a plurality of RFID readers includes a service policy managing unit that defines demands in the form of service policies to be understood by the plurality of RFID readers, a data processing rule managing unit that generates a data processing rule on the basis of the service policies, a collected data processing unit that receives a plurality of RFID tag data from the plurality of RFID readers, and generates integrated RFID events by applying the data processing rule to the plurality of RFID tag data, and a service report processing unit that provides results corresponding to the integrated RFID events. | 2009-05-28 |
20090134975 | TAG ESTIMATION METHOD AND TAG IDENTIFICATION METHOD FOR RFID SYSTEM - Provided are a tag estimation method and a tag identification method using the same in a RFID system. In the tag estimating method, a reader divides tags in an identifiable area into a predetermined number of groups. Tags are identified by applying a pilot frame L | 2009-05-28 |
20090134976 | APPARATUS AND METHOD FOR PROCESSING DATA IN TRANSMITTING AND RECEIVING END OF RFID SYSTEM - A data receiving and processing system includes: an RF front-end circuit, for receiving an analog signal and generating received data; a processing unit, coupled to the RF front-end circuit, for performing processing on the received data; and a buffering circuit, coupled between the processing unit and the RF front-end circuit, for buffering the received data; wherein data transmitted between the RF front-end circuit and the buffering circuit is serial data, and data transmitted between the buffering circuit and the processing unit is parallel data. | 2009-05-28 |
20090134977 | Method and apparatus for RFID device coexistance - In accordance with exemplary embodiments, a radio frequency identification (RFID) device might employ channel-in-use sensing and time multiplexing transmission to prevent radio systems of RFID devices in close proximity to one another from transmitting while another one of the RFID devices is transmitting so as to reduce, for example, radio interference at the transmitting RFID device. RFID transceivers not transmitting might employ a random back off procedure once a close proximity transmission is detected so that the RFID devices do not repetitively try to seize the channel at approximately the same time. | 2009-05-28 |
20090134978 | STOCK ARTICLE MANAGEMENT SYSTEM - An automatic analyzer transmits information about stock articles used in automatic analyzers provided in a plurality of facilities, respectively, to a management station through a network. The management station manages the stock articles in the plurality of facilities. Each facility includes an information exchanger on which stock articles each appended with an RFID tag are arranged; a first reader/writer exchanging, with the RFID tag, information about the stock articles, when the stock articles are arranged on the information exchanger; a second reader/writer provided in the automatic analyzer, wherein the second reader/writer exchanges, with the RFID tag, information about the stock articles, shares, with the first reader/writer, the information about the stock articles, when the stock articles are mounted on the automatic analyzer; and a processor that processes the information about the stock articles. The management station collectively manages in real time the stock articles in the facilities. | 2009-05-28 |
20090134979 | RADIO FREQUENCY INDENTIFICATION TAG - The disclosed ID tag has a stable internal supply voltage and extends the range of communication with the reader/writer during back scattering communication. An ASK-modulated signal pre-boost circuit to which antenna terminals are coupled is coupled in parallel with a rectifying circuit. In the ASK-modulated signal pre-boost circuit, a switch for back scattering, working as a modulator element, is provided. During back scattering communication, when a back scattering signal “1” is transmitted, only the current flowing in the signal receiving path of the modulation/demodulation unit is wasted by turning the switch for back scattering on. Additional current loss other than the loss for impedance matching can be prevented. | 2009-05-28 |
20090134980 | SYSTEM, TOOLS, AND METHOD FOR GENERATING AND DISPLAYING ELECTRONIC MEMORIAL AND DEDICATION MEDIA, AND ADMINISTRATING COMMUNICATION AND LINKING OF USERS - According to the present invention, there is provided a system and method for generating and displaying electronic notification and memorial media, including display tools for displaying notifications, memorials, and related information, administrative tools for managing the system's operation and the linking of users, communication tools for disseminating related memorial notifications and announcements, broadcast tools for enabling users to participate remotely in memorial and other activities and events, and tribute tools for further memorial activities. While preferably the system and method of the present invention are directed towards applications in the memorial/dedication field, the system and method of the present invention can also be adapted and applied to a broad range of settings and industries, wherever the communication and display of information and notifications is necessary. | 2009-05-28 |
20090134981 | DIRECT AIRCRAFT-TO-AIRCRAFT DATA LINK COMMUNICATION - The present disclosure provides systems and methods for direct communication between aircraft, which may involve receiving tactical and strategic information related to proximate aircraft for improved flight planning. The systems and methods presented herein may be implemented, for example, in a first aircraft having a data link component adapted to process information, a storage component adapted to store information related to the first aircraft, access to a plurality of onboard data sources, and a communication interface component adapted to directly communicate with a second aircraft via a communication link. The first aircraft may include a user interface component adapted to interact with the data link component to retrieve the information related to the second aircraft from the storage component, generate a request message with the information related to the second aircraft, and communicate with the communication interface component to directly transmit the generated request message to the second aircraft via the communication link. | 2009-05-28 |