22nd week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140145226 | POLYMER COMPOSITE, USE OF THE POLYMER COMPOSITE AND OPTOELECTRONIC COMPONENT CONTAINING THE POLYMER COMPOSITE - A polymer composite includes a polymer matrix and ZnO particles distributed in the polymer matrix, wherein the polymer composite is a barrier for compounds containing sulfur. | 2014-05-29 |
20140145227 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode chip includes a semiconductor body including a radiation-generating active region, at least two contact locations electrically contacting the active region, a carrier and a connecting medium arranged between the carrier and the semiconductor body, wherein the semiconductor body includes roughening on outer surfaces facing the carrier, the semiconductor body mechanically connects to the carrier by the connecting medium, the connecting medium locally directly contacts the semiconductor body and the carrier, and the at least two contact locations are arranged on the upper side of the semiconductor body facing away from the carrier. | 2014-05-29 |
20140145228 | OPTOELECTRONIC SEMICONDUCTOR CHIP, METHOD OF FABRICATION AND APPLICATION IN AN OPTOELECTRONIC COMPONENT - An optoelectronic semiconductor chip includes an active layer with a first and a second major face, including a semiconductor material which emits or receives radiation when the semiconductor chip is in operation; a patterned layer including three-dimensional patterns for outcoupling or incoupling radiation and arranged on the first major face in a beam path of the radiation, wherein the patterned layer includes an inorganic-organic hybrid material. | 2014-05-29 |
20140145229 | LIGHT EMITTING DEVICE PACKAGE - A semiconductor device, and more particularly a light emitting device package usable with a lighting apparatus is disclosed. The light emitting device package comprises a package body, a light emitting device located on the package body, the light emitting device emitting light having a first wavelength band, a transparent substrate located over the light emitting device with a distance therebetween, a wavelength conversion layer located on the transparent substrate, wherein the wavelength conversion layer absorbs and converts at least a part of the light having the first wavelength band into light having a second wavelength band, and a color calibration layer located on the wavelength conversion layer, the color calibration layer calibrating color of the wavelength conversion layer. | 2014-05-29 |
20140145230 | ENCAPSULATING SHEET, OPTICAL SEMICONDUCTOR DEVICE, AND PRODUCING METHOD THEREOF - An encapsulating sheet, for encapsulating an optical semiconductor element mounted on a board by a wire-bonding connection, includes an embedding layer for embedding the optical semiconductor element and a wire and a cover layer covering the embedding layer. The embedding layer and the cover layer contain a catalyst containing a transition metal and are prepared from a silicone resin composition that is cured by accelerating a reaction by the catalyst. The ratio of the concentration of the transition metal in the cover layer to that of the transition metal in the embedding layer is 1 or more. The length from an interface between the embedding layer and the cover layer to a portion of the wire that is positioned closest to the cover layer-side is 150 μm or more. | 2014-05-29 |
20140145231 | CONVERSION ELEMENT FOR LIGHT-EMITTING DIODES AND PRODUCTION METHOD - A method of producing a conversion element includes forming a preform from a glass, reshaping the preform into a structured glass fiber using a structuring element, and dividing the glass fiber into conversion elements. | 2014-05-29 |
20140145232 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, LIGHTING INSTRUMENT EMPLOYING THE SAME AND PROCESS FOR PRODUCTION OF THE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm. | 2014-05-29 |
20140145233 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE THEREOF - A light emitting device includes a light emitting structure including a second conduction type semiconductor layer, an active layer, and a first conduction type semiconductor layer, a second electrode layer arranged under the light emitting structure, a first electrode layer having at least portion extending to contact the first conduction type semiconductor layer passing the second conduction type semiconductor layer and the active layer, and an insulating layer arranged between the second electrode layer and the first electrode layer, between the second conduction type semiconductor layer and the first electrode layer, and between the active layer and the first electrode layer, wherein said at least one portion of the first electrode layer contacting the first conduction type semiconductor layer has a roughness. | 2014-05-29 |
20140145234 | Display Device and Manufacturing Method Thereof - A display device in which light leakage in a monitor element portion is prevented without increasing the number of steps and cost is provided. The display device includes a monitor element for suppressing influence on a light-emitting element due to temperature change and change over time and a TFT for driving the monitor element, in which the TFT for driving the monitor element is provided so as not to overlap the monitor element. Furthermore, the display device includes a first light shielding film and a second light shielding film, in which the first light shielding film is provided so as to overlap a first electrode of the monitor element and the second light shielding film is electrically connect to the first light shielding film through a contact hole formed in an interlayer insulating film. The contact hole is formed so as to surround the outer edge of the first electrode of the monitor element. | 2014-05-29 |
20140145235 | SYSTEM AND METHOD FOR LED PACKAGING - System and method for LED packaging. The present invention is directed to optical devices. More specifically, embodiments of the presentation provide LED packaging having one or more reflector surfaces. In certain embodiments, the present invention provides LED packages that include thermal pad structures for dissipating heat generated by LED devices. In particular, thermal pad structures with large surface areas are used to allow heat to transfer. In certain embodiments, thick thermally conductive material is used to improve overall thermal conductivity of an LED package, thereby allowing heat generated by LED devices to dissipate quickly. Depending on the application, thermal pad structure, thick thermal conductive layer, and reflective surface may be individually adapted in LED packages or used in combinations. There are other embodiments as well. | 2014-05-29 |
20140145236 | Functionalization of a Substrate - A method of increasing a work function of an electrode is provided. The method comprises obtaining an electronegative species from a precursor using electromagnetic radiation and reacting a surface of the electrode with the electronegative species. An electrode comprising a functionalized substrate is also provided. | 2014-05-29 |
20140145237 | SUBMINIATURE LED ELEMENT AND MANUFACTURING METHOD THEREOF - Disclosed is a subminiature LED element and a manufacturing method thereof. The subminiature LED element includes a first conductive semiconductor layer, an active layer formed on the first conductive semiconductor layer, and a semiconductor light emission element of a micrometer or nanometer size including a second conductive semiconductor layer formed on the active layer, wherein the outer circumference of the semiconductor light emission element is coated with an insulation film. The manufacturing method includes 1) forming a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer in order on a substrate, 2) etching the first conductive semiconductor layer, the active layer and the second conductive semiconductor layer so that the LED element has a diameter of a nanometer or micrometer level, and 3) forming an insulation film on the outer circumference of the first conductive semiconductor layer, the active layer and the second conductive semiconductor layer and removing the substrate. Therefore, a subminiature LED element of a nanometer or micrometer size may be effectively produced by combining a top-down manner and a bottom-up manner, and light emission efficiency may be improved by preventing a surface defect of the produced subminiature LED element. | 2014-05-29 |
20140145238 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS - Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described. | 2014-05-29 |
20140145239 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer. | 2014-05-29 |
20140145240 | DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICAL SEMICONDUCTOR DEVICES - Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device's effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices. | 2014-05-29 |
20140145241 | SEMICONDUCTOR DEVICE - The present invention implements an equivalent circuit to a semiconductor device for an upper arm by electrically connecting a terminal for E | 2014-05-29 |
20140145242 | Fin-Last FinFET and Methods of Forming Same - Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin. | 2014-05-29 |
20140145243 | GROUP III-NITRIDE-BASED TRANSISTOR WITH GATE DIELECTRIC INCLUDING A FLUORIDE - OR CHLORIDE- BASED COMPOUND - Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N) and a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N). The IC device may further include a gate terminal and a gate dielectric layer disposed between the gate terminal and the barrier layer and/or between the gate terminal and the buffer layer. In various embodiments, the gate dielectric layer may include a fluoride- or chloride-based compound, such as calcium fluoride (CaF | 2014-05-29 |
20140145244 | MEMS DEVICE AND PROCESS FOR RF AND LOW RESISTANCE APPLICATIONS - MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer. | 2014-05-29 |
20140145245 | DEVICE ARCHITECTURE AND METHOD FOR IMPROVED PACKING OF VERTICAL FIELD EFFECT DEVICES - A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill. | 2014-05-29 |
20140145246 | JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE - A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs). | 2014-05-29 |
20140145247 | FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS - A method for fabricating a field effect transistor (FET) device includes forming a plurality of semiconductor fins on a substrate, removing a semiconductor fin of the plurality of semiconductor fins from a portion of the substrate, forming an isolation fin that includes a dielectric material on the substrate on the portion of the substrate, and forming a gate stack over the plurality of semiconductor fins and the isolation fin. | 2014-05-29 |
20140145248 | DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM - FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC). | 2014-05-29 |
20140145249 | Diode Structure Compatible with FinFET Process - An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. | 2014-05-29 |
20140145250 | LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE - A semiconductor device includes a bulk substrate having a plurality of trenches formed therein. The trenches define a plurality of semiconductor fins that are integral with the bulk semiconductor substrate. A local dielectric material is disposed in each trench and between each pair of semiconductor fins among the plurality of semiconductor fins. The semiconductor device further includes an etch resistant layer formed on the local dielectric material. | 2014-05-29 |
20140145251 | METHOD FOR FORMING AN INSULATING TRENCH IN A SEMICONDUCTOR SUBSTRATE AND STRUCTURE, ESPECIALLY CMOS IMAGE SENSOR, OBTAINED BY SAID METHOD - A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material. | 2014-05-29 |
20140145252 | Thin Film Transistor Array Substrate for Digital Photo-Detector - A thin film transistor array substrate for a digital photo-detector is provided. The photo-detector includes a plurality of gate lines to supply a scan signal; a plurality of data lines to output data, the data lines arranged in a direction crossing the gate lines, wherein cell regions are defined by the gate lines and the data lines; a photodiode in each of the cell regions to perform photoelectric conversion; a thin film transistor at each intersection between the gate lines and the data lines to output a photoelectric conversion signal from the photodiode to the data lines in response to a scan signal supplied by the gate lines; and a light-shielding layer over each channel region of the respective thin film transistors. Each light-shielding layer is electrically connected to the respective gate line. | 2014-05-29 |
20140145253 | ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 2014-05-29 |
20140145254 | INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR - An circuit supporting substrate includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer. | 2014-05-29 |
20140145255 | NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND CHANNELS AND METHODS OF FORMING THE SAME - A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device. | 2014-05-29 |
20140145256 | ELECTRONIC DEVICE COMPRISING A CONDUCTIVE STRUCTURE AND AN INSULATING LAYER WITHIN A TRENCH - An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench. | 2014-05-29 |
20140145257 | SEMICONDUCTOR DEVICE HAVING A METAL RECESS - Provided is a semiconductor device (e.g., transistor such as a FinFET or planar device) having a a liner layer and a metal layer (e.g., Tungsten (W)) in a trench (e.g., via CVD and/or ALD). A single chamber (e.g., an extreme fill chamber) will be utilized to separately etch back the liner layer and the metal layer. In general, the liner layer may be etched back further than the metal layer to provide for larger contact and lower resistance. After etching is complete, a bottom-up fill/growth of metal (e.g., W) will be performed (e.g., via CVD in a W chamber or the like) to increase the presence of gate metal in the trench. | 2014-05-29 |
20140145258 | SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF - A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench. | 2014-05-29 |
20140145259 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset. | 2014-05-29 |
20140145260 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 2014-05-29 |
20140145261 | High Voltage Drain-Extended MOSFET Having Extra Drain-OD Addition - An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions. | 2014-05-29 |
20140145262 | HIGH-VOLTAGE LDMOS INTEGRATED DEVICE - The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well. | 2014-05-29 |
20140145263 | Finfet Semiconductor Device Having Increased Gate Height Control - A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region. | 2014-05-29 |
20140145264 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 2014-05-29 |
20140145265 | High Voltage Semiconductor Devices - In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain. | 2014-05-29 |
20140145266 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH TSV BUMPS - A semiconductor integrated circuit is provided. In the semiconductor integrated circuit, each of ESD protection circuitries is disposed between two of TSV bumps arrayed in a matrix, the two being arranged adjacent to each other. First main power lines are disposed to overlap P-channel ESD protection elements. Second main power lines are disposed to overlap N-channel ESD protection elements. The first and second main power lines are arranged orthogonally to each other. | 2014-05-29 |
20140145267 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate, forming spacers on sidewalls of the gate electrodes, depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and the spacers, selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes remains after the selective etch, and forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes. | 2014-05-29 |
20140145268 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer. | 2014-05-29 |
20140145269 | TRANSISTORS AND FABRICATION METHOD - A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a metal layer on the semiconductor substrate. The method also includes forming a silicon layer having at least one layer of graphene-like silicon on the metal layer, and forming a metal oxide layer by oxidizing a portion of the metal layer underneath the silicon layer. Further, the method includes forming a source region and a drain region connecting with the silicon layer. | 2014-05-29 |
20140145270 | STRAIN RELAXATION WITH SELF-ALIGNED NOTCH - A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate. | 2014-05-29 |
20140145271 | STRAIN RELAXATION WITH SELF-ALIGNED NOTCH - A method for fabricating a semiconductor device includes providing one or more gate structures over a strained semiconductor substrate. One or more spacers are formed on the gate structures. One or more notches are formed in the strained semiconductor substrate. The one or more notches are filled to provide strain relaxation in a channel region of the strained semiconductor substrate. | 2014-05-29 |
20140145272 | NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE - A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region. | 2014-05-29 |
20140145273 | INTEGRATED JUNCTION AND JUNCTIONLESS NANOTRANSISTORS - Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor. | 2014-05-29 |
20140145274 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR NFET SEMICONDUCTOR DEVICES AND DEVICES HAVING SUCH GATE STRUCTURES - One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer. | 2014-05-29 |
20140145275 | ULTRASONIC TRANSDUCER AND METHOD OF MANUFACTURING THE SAME - An ultrasonic transducer and a method of manufacturing the same are disclosed. The ultrasonic transducer includes a conductive substrate, a projection which is disposed on the conductive substrate and which forms a cavity therein, a via hole which penetrates the projection and conductive substrate, a first electrode which includes a metal and which fills the via hole, a second electrode which is provided on a bottom of the conductive substrate, a membrane which is provided on the projection and which covers the cavity, and an upper electrode which is provided on the membrane and which contacts the first electrode. | 2014-05-29 |
20140145276 | MEMS MICROPHONE AND METHOD FOR MANUFACTURE - An improved method for manufacturing an MEMS microphone with a double fixed electrode is specified which results in a microphone which likewise has improved properties. | 2014-05-29 |
20140145277 | MAGNETIC DEVICE - A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer. | 2014-05-29 |
20140145278 | Electrostatic Control of Magnetic Devices - A magnetic device includes a first electrode portion, a free layer portion arranged on the first electrode portion, the free layer portion including a magnetic insulating material, a reference layer portion contacting the free layer portion, the reference layer portion including a magnetic metallic layer, and a second electrode portion arranged on the reference layer portion. | 2014-05-29 |
20140145279 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - The present invention relates to a magnetoresistive element including a first magnetic layer, a second magnetic layer, a first nonmagnetic layer, a third magnetic layer. The first magnetic layer includes a magnetic film of Mn | 2014-05-29 |
20140145280 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - Provided is a semiconductor device including: a semiconductor element arranged on a substrate and having two electrodes; a conductive strip in contact with one of the two electrodes; and a dielectric arranged between another one of the two electrodes and the conductive strip, in which the conductive strip has an opening formed therein, the dielectric has a void formed therein, and the opening and the void are connected to each other. | 2014-05-29 |
20140145281 | CONTROLLING OF PHOTO-GENERATED CHARGE CARRIERS - Embodiments related to controlling of photo-generated charge carriers are described and depicted. At least one embodiment provides a semiconductor substrate comprising a photo-conversion region to convert light into photo-generated charge carriers; a region to accumulate the photo-generated charge carriers; a control electrode structure including a plurality of control electrodes to generate a potential distribution such that the photo-generated carriers are guided towards the region to accumulate the photo-generated charge carriers based on signals applied to the control electrode structure; a non-uniform doping profile in the semiconductor substrate to generate an electric field with vertical field vector components in at least a part of the photo-conversion region | 2014-05-29 |
20140145282 | IMAGE SENSOR AND PROCESS THEREOF - An image sensor includes a plurality of color filters and an anti-reflective layer. The color filters are located on a substrate. The anti-reflective layer is located between the substrate and the color filters, and parts of the anti-reflective layer corresponding to at least two of the color filters have different thicknesses. Moreover, an image sensing process including the following steps is also provided. An anti-reflective layer is formed on a substrate. A plurality of color filters is formed on the anti-reflective layer, wherein parts of the anti-reflective layer right below at least two of the color filters have different thicknesses. | 2014-05-29 |
20140145283 | Photodiode with Concave Reflector - A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode. | 2014-05-29 |
20140145284 | PHOTODIODE FOR AN IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A photodiode for an image sensor and a method of fabricating the photodiode are disclosed. The photodiode includes a substrate having a surface defined as a light-incident surface of the photodiode, wherein a plurality of convex structures are provided on the light-incident surface of the photodiode, namely, a non-planar light-incident surface which is capable of reducing the light reflection and hence improving the ability of the photodiode to capture incident light, thereby enabling an image sensor that incorporates the photodiode to have a higher fill factor and a better performance. | 2014-05-29 |
20140145285 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid state imaging device includes a substrate having a plurality of pixels and a plurality of on-chip lenses arranged above the substrate, each on-chip lens having a lens surface formed by subjecting a transparent photosensitive film to exposure using a mask having a gradation pattern and development so that the lens surface serves to correct shading in accordance with the gradation pattern. | 2014-05-29 |
20140145286 | COLORED COMPOSITION, METHOD OF PRODUCING COLOR FILTER USING THE SAME, COLOR FILTER AND SOLID-STATE IMAGING DEVICE - The invention is directed to a colored composition containing a coloring agent and a resin, wherein a content of the coloring agent to a total solid content of the colored composition is 50% by weight or more and a solid content acid value of the resin is more than 80 mg KOH/g, and a method of producing a color filter including forming a first colored layer containing a first colored composition and patterning with dry etching so as to from a through-hole group in the first colored layer, wherein the first colored composition is the colored composition as defined herein. | 2014-05-29 |
20140145287 | SOLID-STATE IMAGE SENSOR - An image sensor includes a first pixel having a first color filter, a first reflection region which reflects light from the first color filter, and a first photoelectric conversion portion arranged in a semiconductor layer and located between the first color filter and the first reflection region, and a second pixel including a second color filter, a second reflection region which reflects light from the second color filter, and a second photoelectric conversion portion arranged in the semiconductor layer and located between the second color filter and the second reflection region. Wavelength corresponding to a maximum transmittance of the first color filter is shorter than wavelength corresponding to a maximum transmittance of the second color filter. An area of the first reflection region is smaller than area of the second reflection region. | 2014-05-29 |
20140145288 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device. | 2014-05-29 |
20140145289 | SCHOTTKY STRUCTURE EMPLOYING CENTRAL IMPLANTS BETWEEN JUNCTION BARRIER ELEMENTS - The present disclosure relates to a Schottky diode having a drift layer and a Schottky layer. The drift layer is predominantly doped with a doping material of a first conductivity type and has a first surface associated with an active region. The Schottky layer is provided over the active region of the first surface to form a Schottky junction. A plurality of junction barrier elements are formed in the drift layer below the Schottky junction, and a plurality of central implants are also formed in the drift layer below the Schottky junction. In certain embodiments, at least one central implant is provided between each adjacent pair of junction barrier elements. | 2014-05-29 |
20140145290 | HIGH-VOLTAGE SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region. | 2014-05-29 |
20140145291 | POWER SEMICONDUCTOR DEVICE - Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer. | 2014-05-29 |
20140145292 | Semiconductor Device With Junction Termination Extension Structure On Mesa And Method Of Fabricating The Same - The invention provides a semiconductor device with a junction termination extension structure on a mesa and a method of fabricating the same. The device comprises: a type-I semiconductor substrate having a first surface and a second surface; a type-I epitaxial layer disposed on the first surface; at least one depression disposed on the type-I epitaxial layer; a mesa-type junction termination extension structure surrounding the at least one depression wherein the mesa-type junction termination extension structure is of type-II; and at least one semiconductor component formed one the depression. | 2014-05-29 |
20140145293 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors. | 2014-05-29 |
20140145294 | WAFER SEPARATION - A method is provided for separation of a wafer into individual ICs. Channels are formed in the one or more metallization layers on a front-side of the wafer along respective lanes. The lanes are located between the ICs and extend between a front-side of the metallization layers and a backside of the substrate. A backside of the substrate is thinned, and laser pulses are applied via the backside of the substrate to change the crystalline structure of the silicon substrate along the lanes. The plurality of portions in the silicon substrate and the channels are configured to propagate cracks in the silicon substrate along the lanes during expansion of the IC wafer. The channels assist to mitigate propagation of cracks outside of the lanes in the metallization layers during expansion of the IC wafer. | 2014-05-29 |
20140145295 | DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION - Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping. | 2014-05-29 |
20140145296 | Semiconductor Device with an Edge Termination Structure Having a Closed Vertical Trench - A semiconductor device includes a semiconductor die having an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The semiconductor device further includes an edge termination structure having a closed vertical trench surrounding the active area. The edge termination structure further includes at least one vertical trench arranged, in a horizontal cross-section, between the closed vertical trench and the active area. The at least one vertical trench includes an insulated side wall forming an acute angle with the outer edge. | 2014-05-29 |
20140145297 | MIM-CAPACITOR AND METHOD OF MANUFACTURING SAME - An integrated circuit includes a support, at least three metal layers above the support, the metal layers having a top metal layer with a top plate and a bottom metal layer with a bottom plate, dielectric material between the top and bottom plates to form a capacitor, and plural oxide layers above the support, such oxide layers including a top oxide layer, each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit by providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate. | 2014-05-29 |
20140145298 | ELECTRODE MANUFACTURING METHOD, FUSE DEVICE AND MANUFACTURING METHOD THEREFOR - The present disclosure relates to an electrode manufacturing method, and a fuse device and manufacturing method therefor. The fuse device includes a fuse element including a phase change material, and a first electrode formed in contact with the fuse element. The phase change material may include doped or undoped chalcogenide. The first electrode may have a sublithographic dimension at a portion where the first electrode contacts the fuse element. When the phase change material has a layer thickness less than or equal to about 30 nm, and a pulse current less than or equal to about 3 mA is applied to the fuse element via the first electrode, the fuse element may undergo a phase change, so as to convert the fuse device into a blow-out state. | 2014-05-29 |
20140145299 | DEEP TRENCH STRUCTURE FOR HIGH DENSITY CAPACITOR - Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed. | 2014-05-29 |
20140145300 | INTEGRATION OF CHIPS AND SILICON-BASED TRENCH CAPACITORS USING LOW PARASITIC SILICON-LEVEL CONNECTIONS - Methods and apparatuses are described for integration of integrated circuit die and silicon-based trench capacitors using silicon-level connections to reduce connection lengths, parasitics and necessary capacitance magnitudes and volumes. A trench capacitor can be fabricated on silicon and mounted on or embedded in a chip or one or more sides of a through silicon interposer (TSI) for silicon-level connections to chip circuitry. Aspect ratio dependent, as opposed to trench diameter or trench depth dependent, trench capacitors formed by a dense array of high aspect ratio trenches with thin, high permittivity dielectric increase capacitance per unit area and volume, resulting in thin, high capacitance trench capacitors having thickness equal to or less than chip thickness. | 2014-05-29 |
20140145301 | SINGLE-CHIP INTEGRATED CIRCUIT WITH CAPACITIVE ISOLATION - An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions. | 2014-05-29 |
20140145302 | MIM CAPACITOR AND FABRICATION METHOD - Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove. | 2014-05-29 |
20140145303 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same, the device including a substrate having a transistor formed thereon; a plurality of lower electrodes formed on the substrate; a first supporter and a second supporter on the plurality of lower electrodes; a dielectric film formed on the lower electrode, the first supporter, and the second supporter; and an upper electrode formed on the dielectric film, wherein the first and second supporters are positioned between the lower electrodes, and the first and second supporters include a first material and a second material. | 2014-05-29 |
20140145304 | STACKABLE HIGH-DENSITY METAL-OXIDE-METAL CAPACITOR WITH MINIMUM TOP PLATE PARASITIC CAPACITANCE - A system including first and second plurality of conductors stacked along a first axis on a substrate. The first axis is perpendicular to a plane on which the substrate lies. In the first and second plurality of conductors, each conductor is connected to an adjacent conductor by one or more first vias arranged along the first axis. The first and second plurality of conductors are arranged in parallel along a second axis (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The first plurality of conductors respectively lie on a plurality of planes (i) perpendicular to the first axis and (ii) parallel to the plane on which the substrate lies. The second plurality of conductors respectively lie on the plurality of planes. Capacitances are formed along the plurality of planes between the first plurality of conductors and the second plurality of conductors. | 2014-05-29 |
20140145305 | Capacitor and Method of Forming a Capacitor - A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode. | 2014-05-29 |
20140145306 | SEMICONDUCTOR DEVICE HAVING GLUE LAYER AND SUPPORTER - A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials. | 2014-05-29 |
20140145307 | Seal Ring Structure with Metal-Insulator-Metal Capacitor - A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring. | 2014-05-29 |
20140145308 | ORDER VACANCY COMPOUND AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an order vacancy compound (OVC) is provided. The method includes the following steps. A trivalent ion, a hexavalent ion and one of a univalent ion and a bivalent ion for an electrodeposition process are provided to form a solar energy absorbing film. The OVC is formed by performing an electrochemical etching process on the solar energy absorbing film. | 2014-05-29 |
20140145309 | Systems For The Recycling of Wire-Saw Cutting Fluid - A process is provided for treating coolant fluid used in wire-saw cutting of semiconductor wafers and which contains silicon-containing impurities. The process comprises changing the properties of the used coolant fluid so that the silicon-containing impurities may be filtered and separated from the coolant fluid to thereby yield a coolant fluid filtrate suitable for use in a wire-saw cutting operation. | 2014-05-29 |
20140145310 | THIN FILM DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING DISPLAY - A method of manufacturing a thin film device, the method includes: forming a functional film having a predetermined pattern on a surface of a first substrate; covering the surface of the first substrate and the functional film with an insulating film; and transferring the insulating film and the functional film from the first substrate to a second substrate. | 2014-05-29 |
20140145311 | METHODS OF FORMING FEATURES IN SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed. | 2014-05-29 |
20140145312 | SEMICONDUCTOR STRUCTURE WITH RARE EARTH OXIDE - A semiconductor structure with a rare earth oxide is provided. The semiconductor structure comprises: a semiconductor substrate ( | 2014-05-29 |
20140145313 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A BOTTOM ANTIREFLECTIVE COATING (BARC) LAYER - This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees. | 2014-05-29 |
20140145314 | SEMICONDUCTOR STRUCTURE WITH BERYLLIUM OXIDE - A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate ( | 2014-05-29 |
20140145315 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, a connection member formed on a top surface of the substrate, a semiconductor package mounted on the connection member, an encapsulation member formed to fill a space between a top portion of the substrate and a bottom portion of the semiconductor package, and a shielding material formed to cover the semiconductor package and the encapsulation member. | 2014-05-29 |
20140145316 | WIRELESS MODULE - A wireless module includes a first board ( | 2014-05-29 |
20140145317 | ELECTRONIC COMPONENT DEVICE - A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective. | 2014-05-29 |
20140145318 | Semiconductor Packages and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package. | 2014-05-29 |
20140145319 | Semicondutor Packages and Methods of Fabrication Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad. | 2014-05-29 |
20140145320 | DIE PACKAGE - An electronic device package including an electronic device within a block of insulating material, for example a QFN package. The paddle may be design to extend beyond the die to allow wirebonding between a region of the paddle and the die. Leads may be extended underneath the die and adhered to the die. | 2014-05-29 |
20140145321 | Power Semiconductor Housing With Contact Mechanism - A housing for a power semiconductor, providing a compartment for installation of a power semiconductor, and including a first and a second terminal. The terminals are for connection of a power semiconductor installed in the compartment, and for leading current to and from the compartment. The housing includes a contact mechanism for bypassing the compartment, the contact mechanism including at least one movable contact arranged for electrically connecting the first and second terminal, the at least one movable contact being movable between a disconnected first position and a connected second position. The contact mechanism further includes a bypass actuator arranged inside the compartment and provided for transforming a pressure from an exploding semiconductor into motion, the bypass actuator is operatively connected to the movable contact and arranged to move the movable contact from the first to the second position when subjected to the pressure of an exploding semiconductor. | 2014-05-29 |
20140145322 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are an electronic component package and a method of manufacturing the same. The electronic component package includes: a substrate; a connection member provided on at least one surface of the substrate; an active element coupled to the substrate by the connection member; and a molding part covering an exposed surface of the active element, wherein the molding part is formed of a first material having a coefficient of thermal expansion of 8 to 15 ppm/° C. and thermal conductivity of 1 to 5 W/m° C. Therefore, warpage may be significantly decreased and heat radiation performance of the active element may be improved, as compared with the case of implementing the molding part using an EMC according to the related art. | 2014-05-29 |
20140145323 | LAMINATION LAYER TYPE SEMICONDUCTOR PACKAGE - Disclosed herein is a lamination layer type semiconductor package, and more particularly, a lamination layer type semiconductor package capable of maintaining a thickness of a package on package structure at a minimum and minimizing a warpage defect by mounting two chips so as to correspond to each other. The lamination layer type semiconductor package includes: an upper package having an upper flip chip mounted on an upper substrate; a lower package having a lower flip chip mounted on a lower substrate and disposed so as to closely adhere the upper flip chip and the lower flip chip to each other; a heat dissipation adhesive member adhesively fixing the upper flip chip and the lower flip chip and dissipating heat generated from the upper flip chip and the lower flip chip; and a molding member molding between the upper substrate and the lower substrate. | 2014-05-29 |
20140145324 | METHOD AND SYSTEM FOR CONTROLLING CHIP WARPAGE DURING BONDING - A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile. | 2014-05-29 |
20140145325 | ELECTRONIC DEVICES WITH EMBEDDED DIE INTERCONNECT STRUCTURES, AND METHODS OF MANUFACTURE THEREOF - An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated. | 2014-05-29 |