22nd week of 2013 patent applcation highlights part 42 |
Patent application number | Title | Published |
20130137222 | Method for Stacking Semiconductor Dies - A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer. | 2013-05-30 |
20130137223 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 2013-05-30 |
20130137224 | MANUFACTURING METHODS FOR LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICES - Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type. | 2013-05-30 |
20130137225 | METHOD AND SYSTEM FOR CARBON DOPING CONTROL IN GALLIUM NITRIDE BASED DEVICES - A method of growing an n-type III-nitride-based epitaxial layer includes providing a substrate in an epitaxial growth reactor, forming a masking material coupled to a portion of a surface of the substrate, and flowing a first gas into the epitaxial growth reactor. The first gas includes a group III element and carbon. The method further comprises flowing a second gas into the epitaxial growth reactor. The second gas includes a group V element, and a molar ratio of the group V element to the group III element is at least 5,000. The method also includes growing the n-type III-nitride-based epitaxial layer. | 2013-05-30 |
20130137226 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device that includes a transistor including an oxide semiconductor is provided. In a manufacturing process of a semiconductor device that includes a bottom-gate transistor including an oxide semiconductor, an insulating film which is in contact with an oxide semiconductor film is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order. The insulating film which is in contact with the oxide semiconductor film refers to a gate insulating film provided under the oxide semiconductor film and an insulating film which is provided over the oxide semiconductor film and functions as a protective insulating film. The gate insulating film and/or the insulating film are/is subjected to dehydration or dehydrogenation treatment by heat treatment and oxygen doping treatment in this order. | 2013-05-30 |
20130137227 | LOGIC AND NON-VOLATILE MEMORY (NVM) INTEGRATION - A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate. | 2013-05-30 |
20130137228 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer. | 2013-05-30 |
20130137229 | MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF - Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase. | 2013-05-30 |
20130137230 | Semiconductor Device with Field Electrode - A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface and forming at least one first trench in the dielectric layer. The at least one first trench extends to the semiconductor body and defines a dielectric mesa region in the dielectric layer. The method further includes forming a second trench in the dielectric mesa region distant to the at least one first trench, forming a semiconductor layer on uncovered regions of the semiconductor body in the at least one first trench and forming a field electrode in the second trench. | 2013-05-30 |
20130137231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. | 2013-05-30 |
20130137232 | METHOD FOR FORMING OXIDE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An oxide semiconductor film is formed over a substrate. A sacrifice film is formed to such a thickness that the local maximum of the concentration distribution of an injected substance injected into the oxide semiconductor film in the depth direction of the oxide semiconductor film is located in a region from an interface between the substrate and the oxide semiconductor film to a surface of the oxide semiconductor film. Oxygen ions are injected as the injected substance into the oxide semiconductor film through the sacrifice film at such an acceleration voltage that the local maximum of the concentration distribution of the injected substance in the depth direction of the oxide semiconductor film is located in the region, and then the sacrifice film is removed. Further, a semiconductor device is manufactured using the oxide semiconductor film. | 2013-05-30 |
20130137233 | HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP - A method for forming a hydrogen barrier liner for a ferro-electric random access memory chip including forming a first dielectric layer over a substrate; forming a gate over the first dielectric layer; forming a first aluminum oxide layer over the gate and the first dielectric layer; forming a second dielectric layer over the first aluminum oxide layer; etching a trench through the second dielectric layer and the first aluminum oxide layer to the gate; forming a hydrogen barrier liner over the second dielectric layer, the hydrogen barrier liner lining the trench and contacting the gate; forming a silicon dioxide layer over the first aluminum dioxide layer, the silicon dioxide layer substantially filling the trench; and substantially removing the silicon dioxide layer leaving a silicon dioxide plug in the trench. | 2013-05-30 |
20130137234 | METHODS FOR FORMING SEMICONDUCTOR DEVICES - Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion. | 2013-05-30 |
20130137235 | MOS TRANSISTOR USING STRESS CONCENTRATION EFFECT FOR ENHANCING STRESS IN CHANNEL AREA - A MOS transistor ( | 2013-05-30 |
20130137236 | Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling - A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions. | 2013-05-30 |
20130137237 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer. | 2013-05-30 |
20130137238 | METHOD FOR FORMING HIGH MOBILITY CHANNELS IN III-V FAMILY CHANNEL DEVICES - Provided is a method of fabricating a semiconductor device. The method includes forming a buffer layer over a surface of a silicon substrate. The method further includes forming openings that extend into the buffer layer. The method includes forming a shallow trench isolation (STI) structures in each of the openings. The method includes removing a predetermined amount of a top surface of the buffer layer relative to a top surface of the STI structures. The method includes forming an insulator layer over the top surface of the buffer layer and forming a channel layer over the insulator layer. | 2013-05-30 |
20130137239 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes: memory cells including a transistor and a capacitor; bit lines; word lines; and sense amplifiers including first and second sense amplifiers, wherein the memory cells includes: a first memory cell group sharing a first auxiliary word line; and a second memory cell group sharing a second auxiliary word line, wherein the word lines includes a first word line coupled to the first auxiliary word line and a second word line coupled to the second auxiliary word line, the first word line is coupled to the first auxiliary word line in a first word line contact region, the second word line is coupled to the second auxiliary word line in a second word line contact region, the bit lines includes first and second bit lines coupled to the first sense amplifier on both sides of the first word line contact region. | 2013-05-30 |
20130137240 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness. | 2013-05-30 |
20130137241 | METHOD FOR THE PREPARATION OF A MULTI-LAYERED CRYSTALLINE STRUCTURE - This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure. | 2013-05-30 |
20130137242 | DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING - Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating, an auxiliary cathode located between the anode and the ionically resistive ionically permeable element, and an insulating shield with an opening in its central region. The insulating shield may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the shield and the ionically resistive ionically permeable element during electroplating. | 2013-05-30 |
20130137243 | SEMICONDUCTOR PROCESS - First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C. | 2013-05-30 |
20130137244 | METHOD AND APPARATUS FOR RECONDITIONING A CARRIER WAFER FOR REUSE - The disclosed subject matter pertains to deposition of thin film or thin foil materials in general, but more specifically to deposition of epitaxial monocrystalline or quasi-monocrystalline silicon film (epi film) for use in manufacturing of high efficiency solar cells. In operation, methods are disclosed which extend the reusable life and to reduce the amortized cost of a reusable substrate or template used in the manufacturing process of silicon and other semiconductor solar cells. | 2013-05-30 |
20130137245 | METHOD FOR MAKING A STRUCTURE COMPRISING AT LEAST ONE MULTI-THICK ACTIVE PART - A method for making a structure comprising an active part comprising at least two layers from a first single crystal silicon substrate, said method comprising the steps of:
| 2013-05-30 |
20130137246 | METHOD OF PRODUCING GROUP III NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE - An object of the present invention is to provide a method for producing a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with Al | 2013-05-30 |
20130137247 | THERMALIZATION OF GASEOUS PRECURSORS IN CVD REACTORS - The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases. | 2013-05-30 |
20130137248 | Doping Carbon Nanotubes and Graphene for Improving Electronic Mobility - A method for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device. | 2013-05-30 |
20130137249 | REMOTE RADICAL HYDRIDE DOPANT INCORPORATION FOR DELTA DOPING IN SILICON - The present invention generally relates to methods of forming substrates using remote radical hydride doping. The methods generally include remotely activating a gas and introducing activated radicals of the gas into a chamber. The activated radicals may be activated hydride radicals of a gas such as diborane (B | 2013-05-30 |
20130137250 | BORON ION IMPLANTATION USING ALTERNATIVE FLUORINATED BORON PRECURSORS, AND FORMATION OF LARGE BORON HYDRIDES FOR IMPLANTATION - Methods of implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. A method of manufacturing a semiconductor device including implanting boron-containing ions using fluorinated boron-containing dopant species that are more readily cleaved than boron trifluoride. Also disclosed are a system for supplying a boron hydride precursor, and methods of forming a boron hydride precursor and methods for supplying a boron hydride precursor. In one implementation of the invention, the boron hydride precursors are generated for cluster boron implantation, for manufacturing semiconductor products such as integrated circuitry. | 2013-05-30 |
20130137251 | Uniform Shallow Trench Isolation Regions and the Method of Forming the Same - A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively. | 2013-05-30 |
20130137252 | PATTERN FORMING METHOD - In a pattern forming method, a pattern having at least either a recess or a protrusion of a curable composition is formed of a curable composition by curing the curable composition into a cured film with a mold having a surface provided with at least either a recess or a protrusion, and separating the mold from the curable composition. The method includes (i) forming a gas generation region containing a gas generator agent so that the gas generation region will be disposed in contact with both the mold and the cured film between the mold and the cured film, (ii) generating a gas from the gas generation region, and (iii) separating the mold from the cured film during or after the step of (ii). | 2013-05-30 |
20130137253 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer provided on the first main surface of the silicon carbide substrate; first silicon carbide regions formed on a surface of the first silicon carbide layer; second and third silicon carbide regions formed on respective surfaces of the first silicon carbide regions; a fourth silicon carbide region formed between facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode electrically connected to the second and third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate. | 2013-05-30 |
20130137254 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device has the following steps. A substrate having a silicon carbide layer of a first conductivity type is prepared. On the silicon carbide layer, a mask layer is formed. By ion implantation from above the mask layer, a well region of a second conductivity type is formed on the silicon carbide layer. At the step of forming the mask layer, the mask layer having an opening with a taper angle, which is an angle formed between a bottom surface and an inclined surface of mask layer, being larger than 60° and not larger than 80° is formed. Thus, a method of manufacturing a semiconductor device, capable of producing a semiconductor device having high degree of integration and high breakdown voltage, can be provided. | 2013-05-30 |
20130137255 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device including an oxide semiconductor which is capable of having stable electric characteristics and achieving high reliability, by a dehydration or dehydrogenation treatment performed on a base insulating layer provided in contact with an oxide semiconductor layer, the water and hydrogen contents of the base insulating layer can be decreased, and by an oxygen doping treatment subsequently performed, oxygen which can be eliminated together with the water and hydrogen is supplied to the base insulating layer. By formation of the oxide semiconductor layer in contact with the base insulating layer whose water and hydrogen contents are decreased and whose oxygen content is increased, oxygen can be supplied to the oxide semiconductor layer while entry of the water and hydrogen into the oxide semiconductor layer is suppressed. | 2013-05-30 |
20130137256 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them. | 2013-05-30 |
20130137257 | Method of Forming a Semiconductor Device by Using Sacrificial Gate Electrodes and Sacrificial Self-Aligned Contact Structures - Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure. | 2013-05-30 |
20130137258 | METHOD FOR FABRICATING BURIED GATES USING PRE LANDING PLUGS - A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. | 2013-05-30 |
20130137259 | Process for Making Contact with and Housing Integrated Circuits - A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages. | 2013-05-30 |
20130137260 | MULTI-STAGE SILICIDATION PROCESS - A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices. | 2013-05-30 |
20130137261 | METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT - A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions. | 2013-05-30 |
20130137262 | TUNGSTEN FILM FORMING METHOD - A tungsten film forming method for forming a tungsten film on a surface of a substrate while heating the substrate in a depressurized atmosphere in a processing chamber includes forming an initial tungsten film for tungsten nucleation on the surface of the substrate by alternately repeating a supply of WF | 2013-05-30 |
20130137263 | ELECTRICALLY ASSISTED CHEMICAL-MECHANICAL PLANARIZATION (EACMP) SYSTEM AND METHOD THEREOF - A novel polishing pad is described. The polishing pad includes a base plate, a main polishing body, a plurality of metal bottom portions, a positive electrode conductive wire and a negative electrode conductive wire. The main polishing body made from a non-conductive material and disposed on the base plate includes a plurality of cavities thereon. The metal bottom portions are disposed in the cavities with each of the cavities having one of the metal bottom portions therein. The positive electrode conductive wire electrically is connected to a positive electrode of a power supply. The negative electrode conductive wire electrically is connected to a negative electrode of the power supply. The positive electrode conductive wire and the negative electrode conductive wire alternatively pass through the base plate and connect to the metal bottom portions respectively. | 2013-05-30 |
20130137264 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer. | 2013-05-30 |
20130137265 | SLURRY, POLISHING LIQUID SET, POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND SUBSTRATE - The polishing liquid according to the embodiment comprises abrasive grains, an additive and water, wherein the abrasive grains include a tetravalent metal element hydroxide, and produce a liquid phase with a nonvolatile content of 500 ppm or greater when an aqueous dispersion with a content of the abrasive grains adjusted to 1.0 mass % has been centrifuged for 50 minutes at a centrifugal acceleration of 1.59×10 | 2013-05-30 |
20130137266 | MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES - Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed. | 2013-05-30 |
20130137267 | Methods for Atomic Layer Etching - Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate. | 2013-05-30 |
20130137268 | METHOD FOR PATTERN FORMATION - According to one embodiment, a method for pattern formation comprises forming a first pattern on a first region of a processed film, forming a reverse material film, having a photosensitive compound, on the processed film so that the reverse material film covers the first pattern, exposing and developing the reverse material film and processing the reverse material film into a second pattern in a second region different from the first region on the processed film, applying etch-back, after exposing and developing the reverse material film, to the reverse material film to expose an upper surface of the first pattern and processing the reverse material film into a third pattern in the first region, and etching the processed film using the second pattern and the third pattern as masks. | 2013-05-30 |
20130137269 | PATTERNING METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE - A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements. | 2013-05-30 |
20130137270 | METHOD FOR FORMING CONTACT HOLE - A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer. | 2013-05-30 |
20130137271 | SILICON-CONTAINING RESIST UNDERLAYER FILM-FORMING COMPOSITION AND PATTERNING PROCESS - The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process. | 2013-05-30 |
20130137272 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device, includes supplying a first etching gas and a second etching gas having a decomposition rate lower than that of the first etching gas from one end of a substrate accommodating region in a process chamber where a plurality of substrates are stacked while exhausting an inside of a process chamber from other end of the substrate accommodating region; and etching a first portion of the plurality of substrate at the one end of the substrate accommodating region using a portion of radicals generated from the first etching gas and second etching gas, and etching a second portion of the plurality of substrates at the other end of the substrate accommodating region using at least a portion of a remaining radicals of the radicals generated from the first etching gas and second etching gas. | 2013-05-30 |
20130137273 | Semiconductor Processing System - The semiconductor processing system includes a reactor chamber that has an upper wall and a lower wall. A hold member is disposed in the reactor chamber to hold a semiconductor substrate in such a way that it faces the lower wall of the reactor chamber. | 2013-05-30 |
20130137274 | SUBSTRATE PROCESSING METHOD - There is provided a substrate processing method to suppress popping while increasing the throughput in a photoresist removing process. The substrate processing method comprises: loading a substrate, which is coated with photoresist into which a dopant is introduced, into a process chamber; heating the substrate; supplying a reaction gas to the process chamber, wherein the reaction gas contains at least oxygen and hydrogen components, and concentration of the hydrogen component ranges from 60% to 70%; and processing the substrate in a state where the reaction gas is excited into plasma. In the heating of the substrate, the substrate may be heated to 220° C. to 300° C. In the heating of the substrate, the substrate may be heated to 250° C. to 300° C. | 2013-05-30 |
20130137275 | METHODS FOR SELECTIVE ETCHING OF A MULTI-LAYER SUBSTRATE - A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum or tungsten layer on a TiN layer on an HfO | 2013-05-30 |
20130137276 | METHOD AND APPARATUS FOR PREVENTING NATIVE OXIDE REGROWTH - A method for combinatorially processing a substrate is provided. The method includes introducing a first etchant into a reactor cell and introducing a fluid into the reactor cell while the first etchant remains in the reactor cell. After initiating the introducing the fluid, contents of the reactor cell are removed through a first removal line and a second removal line, wherein the first removal line extends farther into the reactor cell than the second removal line. A level of the fluid above an inlet to the first removal line is maintained while removing the contents. A second etchant is introduced into the reactor cell while removing the contents through the first removal line and the second removal line. The method includes continuing the introducing of the second etchant until a concentration of the second etchant is at a desired level, wherein the surface of the substrate remains submerged. | 2013-05-30 |
20130137277 | Critical Concentration in Etching Doped Poly Silicon With HF/HNO3 - In some embodiments, the present invention discloses an etchant solution hydrochloric acid and nitric acid to etch doped polysilicon at low etch rates. The doped polysilicon can be doped with Ge, In, B and Ga. Preferably, the concentration of hydrochloric acid can be greater than 1 vol %, and the concentration of nitric acid is greater than 15 vol %. | 2013-05-30 |
20130137278 | TEXTURE-ETCHANT COMPOSITION FOR CRYSTALLINE SILICON WAFER AND METHOD FOR TEXTURE-ETCHING (2) - Disclosed herein is an etching composition for texturing a crystalline silicon wafer, comprising, based on a total amount of the composition: (A) 0.1 to 20 wt % of an alkaline compound; (B) 0.1 to 50 wt % of a cyclic compound having a boiling point of 100° C. or more; (C) 0.000001 to 10 wt % of a fluorine-based surfactant; and (D) residual water. The etching composition can maximize the absorbance of light of the surface of a crystalline silicon wafer. | 2013-05-30 |
20130137279 | Exhaust Unit, Substrate Processing Apparatus, and Method of Manufacturing Semiconductor Device - Provided is a substrate processing apparatus capable of increasing a conductance of an exhaust system while preventing or suppressing an increase in footprint of an apparatus, thereby reducing a pressure thereof. The substrate processing apparatus includes a process container ( | 2013-05-30 |
20130137280 | SELF-ORIENTING ELECTRICAL CONNECTOR - An electrical connector and electronic device for connecting to a complementary electrical connector are provided. The electrical connector comprises a main body containing one or more electrically conducting mediums. The electrical connector also comprises an end piece rotatably connected to the main body at one end of the main body. The end piece has a connecting side for engaging the complementary electrical connector. The end piece is rotatable about an axis of rotation. The connecting side comprises one or more electrical contacts for engaging complementary electrical contacts on the complementary electrical connector. Each electrical contact of the electrical connector is electrically connected to one of the electrically conducting mediums of the main body. The connecting side also comprises a magnet disposed on the connecting side of the end piece for engaging a complementary magnet on the complementary electrical connector. | 2013-05-30 |
20130137281 | CIRCUIT-TERMINAL CONNECTING DEVICE - A circuit-terminal connecting device comprising a first connector having a first housing fixed to a main circuit board and first contacts supported by the first housing to be connected with first circuit-terminals provided on the main circuit board and a second connector having a second housing attached to a flat circuit member and second contacts supported by the second housing to be connected with second circuit-terminals provided on the flat circuit member. The first housing of the first connector fits into a hole formed in the second housing of the second connector so as to create an electrical piling connection between the main circuit board and the flat circuit member wherein the flat circuit member is laid on top of the main circuit board and the first circuit-terminals are electrically connected with the second circuit-terminals through the first and second connectors. | 2013-05-30 |
20130137282 | ELECTRICAL CONNECTOR - An electrical connector is configured to be mounted on a board. The electrical connector includes a housing having a receptacle opening portion for receiving a mating connector; a terminal member disposed in the housing; and a shell member for covering the housing. The terminal member includes a base portion fixed to the housing, an arm portion extending from the base portion toward the receptacle opening portion, a contact portion disposed at a distal end portion of the arm portion, a board connecting portion, and a rotation preventing portion extending from the board connecting portion toward the receptacle opening portion. The shell member includes a shell receiving portion extending toward the base portion. The housing includes an insertion portion disposed between the rotation preventing portion and the shell receiving portion. | 2013-05-30 |
20130137283 | RECEPTACLE CONNECTOR - A receptacle connector adapted to be assembled to a printed circuit board for receiving a plug connector is provided. The receptacle connector includes an insulating base, conductive terminals, a fixing base, and a cover. The insulating base is assembled to a first surface of the printed circuit board and has a recess. The conductive terminals are disposed in the insulating base. Each of the conductive terminals has a contact end. The contact ends are located in the recess. The fixing base is assembled to a second surface of the printed circuit board. The cover is pivoted to the fixing base. The plug connector is adapted for pushing the cover to rotate from a close position to an open position relative to the fixing base. When the cover is at the open position, a receiving space for receiving the plug connector is defined between the cover and the recess. | 2013-05-30 |
20130137284 | CONNECTOR - Provided is a connector lockable a connection with the connection object securely. The connector comprises a housing, an attachment, and a lock portion. The connection object which has a locked portion is inserted to and connected with the connector from the front of the connector. The attachment is attached to the housing and comprises an upper attachment positioned higher than the housing, a lower attachment positioned lower than the housing, and a coupling portion coupling the upper attachment and the lower attachment. The lock portion comprises a locking lug positioned backward of the coupling portion and engaging with the locked portion of the connection object when the connection object connected with the connector is moved in an eject direction opposite to the insertion direction, and a spring portion positioned between the upper attachment and the lower attachment and supporting the locking lug so as to be displaceable in a vertical direction perpendicular to the insertion direction. | 2013-05-30 |
20130137285 | CONNECTOR FOR FLAT CABLES - This connector comprises: a connector housing ( | 2013-05-30 |
20130137286 | HIGH VOLTAGE SAFETY LOCK SENSING - SINGLE SENSOR LINEAR ACTUATOR - A safety lock device for locking a charging connector in a charging receptacle of an electric vehicle is provided. The safety lock device includes a locking pin movable between a first position and a second position, an actuator configured to drive the locking pin between the first position and second position, a sensor configured to measure information used in determining a distance the actuator has driven the locking pin and a control unit electrically connected to the sensor and configured to receive the measured information from the sensor and determine the status of the safety lock based on the measured information received from the sensor. The charging connector and charging receptacle may be part of a Fast Charge coupler. | 2013-05-30 |
20130137287 | ELECTRICAL PLUG CONNECTION, IN PARTICULAR CIRCULAR PLUG CONNECTOR - The invention relates to an electrical plug connection, preferably a circular plug connection having a first circular plug connector and a fastening ring. The fastening ring is rotatably arranged on the first circular plug connector. Furthermore a second circular plug connector, a primary lock and a secondary lock having a locking ring that can be placed onto the second circular plug connector are provided. The secondary lock is formed by the fastening ring and the locking ring being in locking engagement when the first circular plug connector and the second circular plug connector form the plug connection. | 2013-05-30 |
20130137288 | SYSTEMS AND METHODS OF COUPLING ELECTRICAL CONDUCTORS - Systems and methods are provided fir coupling a plurality of electrical conductors, such as wires. A connector is provided including a plurality of bores or channels formed into a preferably unitary connector body, wherein at least a portion of one or more of the bores or channels intersects at least a portion of another of the bores or channels. The bores or channels are preferably formed along bore axes, which may be coplanar. A method according to the present invention includes inserting an insulated electrical conductor into a connector body and rotating a conductive rotational member threaded into a bore or channel formed in a connector body so as to electrically contact the conductive portion of the insulated conductor and at least one other electrically conductive surface. | 2013-05-30 |
20130137289 | HIGH VOLTAGE CONNECTOR - The present invention relates to a high voltage connector in which an interlock terminal and a power connection terminal to which a high voltage is applied are sequentially connected or disconnected by rotation, thereby minimizing the size of the connector and allowing a user to check whether each of the terminals is connected or not. The high voltage connector of the present invention comprises: a plug housing inside which is installed a power connection terminal and an interlock connection plug; a cap housing inserted into the inside of the plug housing, and inside which are installed an interlock connecting tab which is capable of connection with the interlock connection plug, and a power connection terminal tab which is capable of connection with the power connection terminal; and a cover housing installed on the top of the cap housing for connecting or disconnecting the power connection terminal tab and the interlock connecting tab with the power connection terminal and the interlock connection plug by inserting or withdrawing the cap housing from the inside of the plug housing by rotation. | 2013-05-30 |
20130137290 | CARD READER AND ELECTRONIC DEVICE HAVING MOVABLE CARD INSERTION MECHANISM - A card reader is disposed in a case body of an electronic device for connecting an electronic card. The card reader includes an electrical connection socket, at least one guiding member, at least one guiding rail and a cover. The electrical connection socket is disposed in the case body for inserting an electrical connector of the electronic card thereinto. The guiding member is disposed in the case body and provides a guiding slot extending along a guiding direction. The guiding direction is parallel to a direction in which the electrical connector is inserted into the electrical connection socket. The guiding rail includes a sliding portion sliding in the guiding slot and a lower support portion extending from the sliding portion for guiding the electronic card to pass through the insertion hole of the case body. The cover is pivoted to the guiding rail and for closing the insertion hole. | 2013-05-30 |
20130137291 | CABLE IDENTIFICATION USING A UNIQUE SIGNAL CARRIED ON AN UNUSED CONDUCTOR - A cable identification system is provided. The cable identification system includes a multiconductor cable with an electrical connector secured to at least one end. The electrical connector is adapted to connect a plurality of conductors in the cable to a mating connector. The cable identification system further includes a signal generator adapted to connect the electrical connector to the mating connector. The signal generator is configured to select an unused conductor from the plurality of conductors and generate and transmit a unique signal over the selected conductor in the cable. The cable identification system further includes a portable device configured to detect the unique signal when positioned adjacent the cable at any point along the cable. | 2013-05-30 |
20130137292 | CABLE IDENTIFICATION USING A UNIQUE SIGNAL CARRIED ON AN EXTERNAL CONDUCTOR - A cable identification system is provided. The cable identification system includes a cable having a plurality of conductors with an electrical connector secured to at least one end. All but one of the conductors are enclosed in a shield conductor. The remaining additional conductor is positioned external to the outer surface of the shield conductor. The electrical connector is adapted to connect the plurality of conductors to a mating connector. The cable identification system further includes a signal generator adapted to connect the electrical connector to the mating connector. The signal generator is configured to generate and transmit a unique signal over the additional conductor in the cable. The cable identification system further includes a portable device configured to detect the unique signal when positioned adjacent the cable at any point along the cable. | 2013-05-30 |
20130137293 | CONNECTOR FOR PLANAR CABLES - The present invention provides a connector for planar cables, which can reliably electrically connect a planar cable conductor and a mating terminal. The connector ( | 2013-05-30 |
20130137294 | METERSOCKET CONNECTOR - A new connector for attaching conductor wires to a metersocket is disclosed. The design of the connector allows the wires to be laid in along the side of the connector and requires little bending and slack in the wire. Once seated in place, the connector can be secured using a set screw that keeps the conductor wire in place. | 2013-05-30 |
20130137295 | Locking Device for a Connecting Arrangement - A locking device for a connecting arrangement between a connecting piece and a plug-type connector, which connecting piece has, radially on the outside, at least one first undercut region extending in the circumferential direction, which plug-type connector has, radially on the inside, at least one second undercut region which is suitable for corresponding with the first undercut region in an engagement position and can be elastically deformed in the radial direction such that the first undercut region and the second undercut region can be engaged or disengaged. The locking device is suitable for preventing a radial elastic deformation of the plug-type connector at least to such an extent that, in the connecting position, the first undercut region and the second undercut region are fixed in the corresponding engagement position. | 2013-05-30 |
20130137296 | A TELEPHONE OUTLET FOR IMPLEMENTING A LOCAL AREA NETWORK OVER TELEPHONE LINES AND A LOCAL AREA NETWORK USING SUCH OUTLETS - An outlet for coupling at least one data unit to digital data carried over wiring that simultaneously carry a packet-based serial digital data signal and a power signal over the same conductors. The outlet includes: a wiring connector for connecting to the wiring; a transceiver coupled to the wiring connector for transmitting and receiving packet-based serial digital data over the wiring; a LAN connector coupled to the transceiver for bi-directional packet-based data communication with at least one data unit; a bridge or a router coupled between the transceiver and the LAN connector for passing data bi-directionally between the at least one data unit and the wiring; and a single enclosure housing the above-mentioned components. The enclosure is mountable into a standard wall outlet receptacle or wall outlet opening, and the transceiver and the bridge or router are coupled to the wiring connector to be powered from the power signal. | 2013-05-30 |
20130137297 | Docking Station for an Electronic Device having Improved Connector Interface - Disclosed is a docking station for attaching a plurality of external connectors to an electronic device, comprising a connector module for interfacing with the electronic device, a first plug on the connector module, a second plug on the connector module, a first port on the connector module electrically connected to the first plug, a second port on the connector module electrically connected to the second plug, a base member for holding the connector module, a first indexing member on the base member, and a second indexing member on the connector module. | 2013-05-30 |
20130137298 | Docking Station for an Electronic Device with Improved Electrical Interface - Disclosed is a device for attaching a plurality of external connectors to an electronic device having a first and second ports for attaching a first and second external connectors, a first and second plugs positioned to interface with a first and second ports of the electronic device, and a first and second pins positioned to interface with a first and second electrical contact of a third port on the electronic device. | 2013-05-30 |
20130137299 | Coaxial connector grounding inserts - Axially compressible, F-connectors for conventional installation tools for interconnection with coaxial cable include grounding inserts for establishing electrical continuity despite inadequate nut tightening. The connector has a rigid nut, a post penetrating the nut, a tubular body, and an end cap. The conductive post coaxially extends through the connector, linking the nut and body. A post end penetrates the coaxial cable. Internal grounding inserts comprise a circular band coaxially engaging the post and portions on the band engaging the nut. Multiple radially spaced apart spring clips defined around the band grasp a flange portion of the post. The band is seated within a ring groove within the nut, making electrical contact. An alternative insert comprises a tubular band for contacting the post and an integral skirt abutting the nut's internal ring groove and contacting a portion of the socket to which the connector is coupled. | 2013-05-30 |
20130137300 | COAXIAL CABLE CONNECTOR FOR SECURING CABLE BY AXIAL COMPRESSION - A coaxial cable connector including a connector body having a forward end, a rearward end, and a hollow cavity adjacent the forward end, the hollow cavity having an inward facing lip, a first insulator configured to fit within the hollow cavity in such a way that the inward facing lip resists removal of the first insulator from the hollow cavity, the first insulator having a central hole, a center conductor contact having a socket end and a pin end, the socket end located within the connector body toward the rearward end, the pin end passing through the central hole of the first insulator, a spring contact configured to fit into the socket end of the center conductor contact, and a second insulator having a central passageway, the second insulator having a first end and a second end, the first end adjacent the socket end of the center conductor contact. | 2013-05-30 |
20130137301 | ELETRONIC DEVICE HAVING A TRAY FOR PLACING DIGITAL CARD - A tray includes a first slot and a second slot. The first slot is for placing a first digital card including contacts. The second slot is for placing a second digital card including contacts. The second slot is defined in the bottom of the first slot and is smaller than the first slot. An opening is defined on the bottom of the second slot. When the first digital card or the second digital card is placed into the tray, the contacts of the first digital card or the second digital card are exposed through the opening. When the tray is received in a connector of an electronic device, the exposed contacts of the first digital card or the second digital card are electrically connected to the connector of the electronic device. | 2013-05-30 |
20130137302 | EXPANDABLE POWER CONNECTOR - An expandable power connector comprises a frame, a power connector disposed on the frame, and a plurality of module sets lodged in the frame. Wherein, when the module sets are assembled to the frame, a polygonal expandable power connector is contributed. Accordingly, the number of sockets on each module set can be properly arranged. Applicable space between the adjacent sockets is also increased for bulky plugs. Due to the design that each module set with at least one socket is lodged in the frame, a new module set can substitute for the old module set while the socket thereon malfunctions. Therefore, the present invention promotes the convenience of using and maintenance. | 2013-05-30 |
20130137303 | ARRANGEMENT STRUCTURE OF CONNECTING CONDUCTOR CONNECTING INSIDE AND OUTSIDE CONDUCTORS OF MOTOR - An arrangement structure includes: a motor including: a motor main body including a stator and a rotor, the rotor being disposed to be rotatable relative to the stator; a case member configured to store the motor main body; and a connecting conductor configured to electrically connect an inside conductor disposed inside the case member and an outside conductor disposed outside the case member; and a support device fixed to the case member and a frame member of a vehicle, the support device being configured to support the motor on the frame member, wherein the connecting conductor is arranged directly below a fixing portion where the support device is fixed to the case member. | 2013-05-30 |
20130137304 | ELECTRICAL CONNECTOR - An electrical connector is provided, including a housing, an inserting groove, a plurality of terminal-receiving grooves spaced with each other on two sidewalls of the housing and passing through a bottom plate of the housing, and a plurality of electrical terminals integrally formed in the terminal-receiving grooves by an insert molding method. Each electrical terminal includes a U-shaped latch portion. An outer surface of the latch portion protrudes out of a peripheral edge of the sidewall of the housing to prevent from producing the overflow plastic during the process of the insert molding. Moreover, the latch portion disposes a first and a second recesses on two opposite sides thereof. When the electrical connector is combined with a complementary connector, the first and the second recesses of each electrical terminal can form a two-position contact with a complementary terminal of the complementary connector for assuring a stable electrical transmission. | 2013-05-30 |
20130137305 | CONNECTOR - Provided is a connector that can be firmly mounted on the substrate. A plug connector is mounted on a plug substrate while making a metal plate function as a plurality of contacts by an insulting layer formed on the metal plate and a plurality of conductive patterns formed on the insulating layer. A plurality of protrusions that protrude toward the plug substrate are formed on a substrate opposing surface, which is a surface opposite to the plug substrate. The plurality of conductive patterns are formed to respectively overlap the plurality of protrusions. | 2013-05-30 |
20130137306 | PLUG CONNECTOR, RECEPTACLE CONNECTOR AND ELECTRICAL CONNECTOR ASSEMBLY - A plug connector, a receptacle connector and an electrical connector assembly are provided. The plug connector includes a plug housing and a plurality of plug terminals located in the plug housing. Each plug terminal includes a first, second and third contact portions. The receptacle connector includes a receptacle housing and a plurality of receptacle terminals mounted in the receptacle housing. Each receptacle terminal includes a first, second and third side portions. When the plug connector and the receptacle connector are combined together to form the electrical connector assembly, the first, second and third contact portions respectively contact with the first, second and third side portions so that realizing a three-position contact between the plug and receptacle terminals for providing a stable signal transmission. | 2013-05-30 |
20130137307 | PLUG CONNECTOR, RECEPTACLE CONNECTOR AND ELECTRICAL CONNECTOR ASSEMBLY - A plug connector, a receptacle connector and an electrical connector assembly are provided. The receptacle connector includes a receptacle housing and a plurality of receptacle terminals. Each receptacle terminal includes a first and a second wing portions, and a first and a second edge portions. The receptacle housing disposes shoulders respectively corresponding to the first and the second wing portions. The plug connector includes a plug housing and a plurality of plug terminal. Each plug terminal includes a first and a second contact portions. When the plug connector and the receptacle connector are mated together, the plug terminal and the receptacle terminal can realize a two-position contact for providing a stable signal transmission. When pulling out the plug connector, the shoulders of the receptacle housing can block the receptacle terminal to be pulled out thereby ensuring the stable combination of the receptacle terminal and the receptacle housing. | 2013-05-30 |
20130137308 | BOARD-TO-BOARD CONNECTOR - Provided is a board-to-board connector, including a male connector and a female connector. The male connector includes a male housing and a plurality of male terminals. Each male terminal has a U-shaped plug portion. The female connector includes a female housing and a plurality of female terminals. Each female terminal has a first contact portion, a second contact portion and an inserting space. When the male and female terminals are engaged with each other, the flexible end of the male terminal is engaged with the rigid end of the female terminal, and the rigid end of the male terminal is engaged with the flexible end of the female terminal. Accordingly, the male and female terminals are engaged together by combining the rigid with the flexible so that avoiding resulting in the deformation and the damage of the terminals, and further assuring the performance of the board-to-board connector. | 2013-05-30 |
20130137309 | MICRO-CONNECTOR WITH FLATLY DISPOSED PINS - A micro-connector with flatly disposed pins is provided, including a plug unit and a metal shell. The plug unit includes an insulation element, a plug, and a plurality of pins, wherein the plug and a plurality of pins are disposed on opposite sides of the insulation element. The metal ends of the pins penetrate through the inside of the insulation element to extend into the plug for electrical connection. The metal shell is engaged to the insulation element, with extending positioning pins. The insertion direction of the positioning pins forms an angle with the insertion direction of the plug. The angle is preferably between 45°-135° so as to enable easy assembly and good fastening result. | 2013-05-30 |
20130137310 | PLUG CONNECTOR FOR DIFFERENTIAL DATA TRANSMISSION - The plug-in connector shown here is embodied as a round plug-in connector and with its connection side embodied for contacting circuit boards. | 2013-05-30 |
20130137311 | CONNECTOR ASSEMBLY - A connector assembly includes a jack formed on a circuit board and a plug engaging with the jack. The jack includes a main hole and at least one fool-proof hole extending from a periphery of the main hole. The plug includes a main connecting part corresponding to the main hole and at least one fool-proof part extending from a periphery of the main connecting part. When the plug is inserted into the jack, the main connecting part is tightly received in the main hole, and the at least one fool-proof part is tightly received in the at least one fool-proof hole. | 2013-05-30 |
20130137312 | TERMINAL CONNECTOR ASSEMBLY FOR A MEDICAL ELECTRICAL LEAD - An IS-4 terminal connector assembly includes three terminal electrodes positioned over an inner tubular member such that they are radially offset from one another. Each of the terminal ring electrodes are configured such that they can withstand both tensile and cyclical bending loads with minimal compromise in their outer geometry. Additionally, each of the terminal electrodes is configured such that they have both an inner and outer geometry that facilitates adequate insulation between a select terminal electrode and an adjacent conductor. Additionally, each of the terminal ring electrodes is configured such that they facilitate an external approach to staking a cable conductor. | 2013-05-30 |
20130137313 | Electrical Connector and Electrical Equipment Comprising the Same - Electrical connector including at least one electrical power contact having a cross-section larger than 8 mm | 2013-05-30 |
20130137314 | WIRE-TO-BOARD CONNECTOR - Provided is a wire-to-board connector including a plug attached to a wire, and a receptacle mounted on a circuit board. The plug and the receptacle are formed of metal. The plug is fitted into the receptacle to electrically connect the wire to the circuit board. The receptacle has an accommodating portion formed in a tubular shape. The plug has an inserted portion to be inserted into the accommodating portion of the receptacle. The inserted portion includes a body plate and an elastic piece elastically supported in a cantilevered manner by the body plate. The elastic piece of the inserted portion has a free end. The accommodating portion has an engaged portion. When the inserted portion is inserted into the accommodating portion, the free end engages with the engaged portion along with an elastic deformation of the elastic piece, thereby allowing the plug to be fitted into the receptacle. | 2013-05-30 |
20130137315 | CRIMP TERMINAL - A conductor crimp portion ( | 2013-05-30 |
20130137316 | METHODS AND APPARATUS FOR PREVENTING OXIDATION OF AN ELECTRICAL CONNECTION - A malleable wax-based antioxidant is provided for use between two electrical connectors. To form the example antioxidant, a wax-base is melted and particles, such as, for example, zinc particles, are provided in suspension with the melted wax. The suspension is then cooled and formed into a shape by, for example, molding, extrusion, die cutting, or other suitable forming method. The antioxidant remains viscose under normal operating temperatures of the electrical connector to avoid oozing and/or running out of the antioxidant, thus better preventing oxidation of the connector. The particles keep the connections running cool, particularly with aluminum to aluminum connections. | 2013-05-30 |
20130137317 | MARINE VESSEL AND MARINE VESSEL PROPULSION UNIT - A marine vessel includes a hull, a jet pump disposed outside the hull, and an electric motor arranged to drive the jet pump. The jet pump includes a water inlet, a jet nozzle disposed posterior to the water inlet, and a flow path connecting the water inlet and the jet nozzle, and is arranged to jet water, taken in through the water inlet, through the jet nozzle. The electric motor is disposed between the hull and the jet pump. | 2013-05-30 |
20130137318 | FLOATING STRUCTURE HAVING AN UPPER DECK FUEL TANK - A floating structure with an on-deck fuel tank that is surrounded by a cover is provided. In the floating structure, since the fuel tank is covered by the cover, the fuel tank is sealed without being exposed to air, thereby enhancing safety. The fuel tank is configured to store liquefied fuel gas to be used as fuel. The fuel tank is installed on a deck of the floating structure, and the exterior of the fuel tank is surrounded by a cover. | 2013-05-30 |
20130137319 | INFLATABLE STAND UP PADDLEBOARD - An inflatable stand up paddleboard having a top surface for supporting a user and a bottom surface for residing on water. The inflatable stand up paddleboard being characterized as having a front end and back end and a longitudinal axis passing between the front and back ends. The inflatable stand up paddleboard is configured to receive at least one beam for stiffening the inflatable stand up paddleboard positioned substantially parallel to the longitudinal axis. | 2013-05-30 |
20130137320 | PERSONAL FLOTATION APPARATUS - A personal flotation apparatus having a main body member, a primary support member, a head support member, and a foot support member, each made of flexible, buoyant, flotation material. The primary support member, head support member, and foot support member are each connected to the main body member, such that they are substantially perpendicular to the main body member and can provide stability, buoyancy and support in various floating and swimming positions. Some embodiments include multiple main body members to increase stability, buoyancy, support and comfort, and allow for heavier users. | 2013-05-30 |
20130137321 | UNDERWATER FLOATING DEVICE - The present invention relates to an underwater floating device ( | 2013-05-30 |