22nd week of 2017 patent applcation highlights part 43 |
Patent application number | Title | Published |
20170154892 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is an electronic device including a semiconductor memory, The semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers arid a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interpose d between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical, direction; a second stacked structure comprising, a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and the second channel layers to each other; and a first etch stop pattern formed between the first and second stacked structures and at substantially the same level as the first channel connection pattern, wherein the first etch stop pattern includes the same material as the first channel connection pattern and is isolated from the first channel connection pattern, | 2017-06-01 |
20170154893 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode. Between the memory gate electrode and the semiconductor substrate, in a region where the second insulating film is not formed, another silicon dioxide film is embedded. | 2017-06-01 |
20170154894 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a semiconductor device includes: forming a first film including a conductive material above a semiconductor substrate; forming a second film on the first film; forming a third film including a conductive material on the second film; exposing a part of the second film; and wet etching the second film. In the wet etching, a first and second insulation films are deposited on side surfaces of the first and third films, and part of a space between the first and third films is blocked by the first and second insulation films to form an air gap between the first and third films. | 2017-06-01 |
20170154895 | Three-Dimensional Semiconductor Device and Manufacturing Method Therefor - A three-dimensional semiconductor device, comprising a plurality of memory cell transistors and a plurality of select transistors at least partially overlapped in the vertical direction, wherein each select transistor comprises a first drain, an active region and a common source formed in the substrate, distributed along the vertical direction, as well as a metal gate distributed around the active region; wherein each memory cell transistor comprises a channel layer distributed perpendicularly to the substrate surface, a plurality of inter-layer insulating layers and a plurality of gate stack structures alternately stacked along the sidewalls of said channel layer, a second drain located on top of said channel layer; wherein said channel layer and said the first drain are electrically connected. In accordance with the three-dimensional semiconductor memory device and manufacturing method of the present invention, the multi-gate MOSFET is formed beneath the stack structure of the memory cell string including vertical channel to serve as the select transistor, this can improve the control characteristics of the gate threshold voltage, reduce the off-state leakage current, prevent the substrate from over-etching, and effectively improve the reliability of the device. | 2017-06-01 |
20170154896 | ARRAY SUBSTRATE AND DISPLAY DEVICE - An array substrate and a display device, which relates to the field of display technology. The array substrate comprises a base substrate, a plurality of first signal lines and a plurality of second signal lines crossly arranged above the base substrate; the first signal line comprises a first line terminal and a second line terminal, as well as a conducting layer opposite to the second signal line for connecting the first line terminal and the second line terminal, and an insulating layer is arranged between the conducting layer and the second signal line, a plurality of first anti-static structures are arranged at joints of the first line terminal, the second line terminal and the conducting layer respectively. The array substrate and the display device provided by the present invention can reduce interference between the plurality of crossed signal lines. | 2017-06-01 |
20170154897 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy. | 2017-06-01 |
20170154898 | Display Device - A disclosed display device includes a first oxide semiconductor layer and an oxide semiconductor connection wire both formed from an oxide semiconductor material layer over a substrate. The oxide semiconductor connection wire is integrally connected to the first oxide semiconductor layer and has a lower sheet resistance than the first oxide semiconductor layer. The display device also includes a first gate electrode either over the first oxide semiconductor layer or between the first oxide semiconductor layer and the substrate. The display device further includes a first gate insulation layer between the first oxide semiconductor layer and the first gate electrode. | 2017-06-01 |
20170154899 | ARRAY SUBSTRATE AND METHOD OF MOUNTING INTEGRATED CIRCUIT USING THE SAME - An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape. | 2017-06-01 |
20170154900 | INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED SILICON-GERMANIUM PFET IMPLEMENTED IN FINFET TECHNOLOGY - A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed). | 2017-06-01 |
20170154901 | Thin Film Transistor and Display Panel - The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrode and the drain electrode. | 2017-06-01 |
20170154902 | PEELING APPARATUS AND MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE - To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected. Peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film. Liquid is sequentially supplied by a nozzle to a gap between the element formation layer and the peeling layer, which is generated by peeling, so that electric charge generated on surfaces of the element formation layer and the peeling layer is diffused by the liquid. | 2017-06-01 |
20170154903 | METHOD OF FABRICATING CRYSTALLINE ISLAND ON SUBSTRATE - Certain electronic applications, such as OLED display back panels, require small islands of high-quality semiconductor material distributed over a large area. This area can exceed the areas of crystalline semiconductor wafers that can be fabricated using the traditional boule-based techniques. This specification provides a method of fabricating a crystalline island of an island material, the method comprising depositing particles of the island material abutting a substrate, heating the substrate and the particles of the island material to melt and fuse the particles to form a molten globule, and cooling the substrate and the molten globule to crystallize the molten globule, thereby securing the crystalline island of the island material to the substrate. The method can also be used to fabricate arrays of crystalline islands, distributed over a large area, potentially exceeding the areas of crystalline semiconductor wafers that can be fabricated using boule-based techniques. | 2017-06-01 |
20170154904 | MANUFACTURING METHOD OF DISPLAY PANEL - A manufacturing method of a display panel disclosed by the invention includes: providing a substrate, the substrate having a first metal layer disposed thereon, the substrate including a first display region and a first peripheral region, the first metal layer covering the first display region and the first peripheral region; laying a photoresist layer on the first metal layer to form a first half-finished plate; exposing and developing the first half-finished plate to form a second half-finished plate with first and second preset patterns; etching and stripping the second half-finished plate to form a first preset metal wire group on the first display region and form a second preset metal wire group on the first peripheral region. The invention can significantly reduce the occurrence of electrostatic discharge phenomenon during the manufacturing process of a display panel and thus the yield of the display panel can be greatly improved. | 2017-06-01 |
20170154905 | THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL - This disclosure provides a thin film transistor and the preparation method thereof, an array substrate, and a display panel, so as to solve the problem that the active layer is prone to be corroded when a metal oxide thin film transistor is produced by a back channel etching process. The preparation method comprises: forming a gate electrode metal thin film on a base substrate, and allowing the gate electrode metal thin film to form a gate electrode metal layer comprising a gate electrode by a patterning process; forming a gate electrode insulating layer on the gate electrode metal layer; forming an active layer on the gate electrode insulating layer; preparing a metal nanoparticle layer on the active layer, said metal nanoparticle layer being used as an etching protection layer; forming a source and drain electrode metal thin film on the base substrate on which the above processes are finished, and allowing the source and drain electrode metal thin film to form a source and drain electrode metal layer comprising a source electrode and a drain electrode by a patterning process, wherein the source electrode and the drain electrode cover a part of the metal nanoparticle layer; removing or oxidizing the part of the metal nanoparticle layer which is not covered by the source electrode and the drain electrode in an oxygen-containing atmosphere; and forming a passivation layer on the source and drain electrode metal layer. | 2017-06-01 |
20170154906 | OPTICAL SENSOR HAVING TWO TAPS FOR PHOTON-GENERATED ELECTRONS OF VISIBLE AND IR LIGHT - An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate | 2017-06-01 |
20170154907 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device includes pixels each having a photoelectric conversion element for converting incident light to an electric signal, color filters associated with the pixels and having a plurality of color filter components, microlenses converging the incident light through the color filters to the photoelectric conversion elements, a light shielding film disposed between the color filter components of the color filters, and a nonplanarized adhesive film provided between the color filters and the light shielding film. | 2017-06-01 |
20170154908 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGING SYSTEM - A photoelectric conversion device includes a photoelectric conversion unit including a first and second electrodes, a photoelectric conversion layer between the first and second electrodes, and an insulating layer between the photoelectric conversion layer and the second electrodes, an amplifier unit connected to the second electrode and outputs a signal generated in the photoelectric conversion unit, and a reset unit for resetting a voltage of the second electrode. An accumulating operation for accumulating signal charges in the photoelectric conversion unit and a charge removing operation for removing the signal charges from the photoelectric conversion unit are alternately executed in accordance with a voltage applied between the first and second electrodes, and the charge removing operation is executed multiple times between a first accumulating operation and a second accumulating operation which is executed after the first accumulating operation. | 2017-06-01 |
20170154909 | SIGNAL PROCESSING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SIGNAL PROCESSING CIRCUIT - Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed. | 2017-06-01 |
20170154910 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - Disclosed is a solid-state imaging device including: a solid-state imaging element which outputs an image signal according to an amount of light sensed on a light sensing surface; a semiconductor element which performs signal processing with respect to the image signal output from the solid-state imaging element; and a substrate which is electrically connected to the solid-state imaging element and the semiconductor element, in which the semiconductor element is sealed by a molding resin in a state of being accommodated in an accommodation area which is provided on the substrate, and in which the solid-state imaging element is layered on the semiconductor element via the molding resin. | 2017-06-01 |
20170154911 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes a semiconductor substrate including a plurality of photo-sensing devices, a photoelectric conversion device disposed on the semiconductor substrate and absorbing the mixed light of a first color and a second color, and a color filter disposed on one side of the photoelectric conversion device and configured to selectively transmit a mixed light including a third color, and an electronic device including the image sensor is provided. | 2017-06-01 |
20170154912 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2017-06-01 |
20170154913 | SEMICONDUCTOR PACKAGE - A semiconductor package device includes a first semiconductor package including a first package substrate and a semiconductor chip stacked on the first package substrate, and a second semiconductor package stacked on the first semiconductor package. The second semiconductor package includes a second package substrate, an image sensor chip stacked on the second package substrate, and a transparent substrate disposed on the image sensor chip. The first semiconductor chip may include a semiconductor memory device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), and/or an image sensor driver circuit and may transfer, process and/or store signals output from the image sensor chip. | 2017-06-01 |
20170154914 | IMAGING PANEL AND X-RAY IMAGING DEVICE PROVIDED THEREWITH - An aim of the present invention is to provide a technology that increases the aperture ratio of an imaging panel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines and a plurality of data lines. The imaging panel includes, in each of the pixels, a conversion element that converts scintillation light to electric charge, a thin film transistor connected to the gate line, data line, and conversion element, and a metal wiring line connecting to the conversion element and supplying a bias voltage to the conversion element. The metal wiring line is positioned generally parallel to the data line and is closer to the data line that connects to the thin film transistor than approximately the center in the extension direction of the gate line of the conversion element. | 2017-06-01 |
20170154915 | IMAGING PANEL AND X-RAY IMAGING DEVICE - The present invention aims at inhibiting the occurrence of thinning or disconnecting of the bias wiring line in an imaging panel and X-ray imaging device, thereby inhibiting signal delays, signal transmission defects, and the like. A second contact hole electrically connecting an electrode of a photodiode to a bias wiring line penetrates a second interlayer insulating film and photosensitive resin layer. In the second contact hole, an area of a region where the photosensitive resin layer opens is smaller than an area of a region where the second interlayer insulating film opens. | 2017-06-01 |
20170154916 | IMAGING PANEL AND X-RAY IMAGING SYSTEM PROVIDED WITH SAID IMAGING PANEL - An aim of the present invention is to make it possible to achieve stable operation of thin film transistors in an imaging panel of an X-ray imaging system that uses an indirect conversion scheme. An imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and bias wiring line. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and irradiated by scintillation light. The bias wiring line is connected to the photoelectric conversion element and applies a reverse bias voltage to the photoelectric conversion element. The thin film transistor includes a semiconductor active layer and a gate electrode. The gate electrode is formed between the substrate and semiconductor active layer. The bias wiring line includes a portion that overlaps the gate electrode and semiconductor active layer as seen from the radiation direction of the scintillation light. | 2017-06-01 |
20170154917 | METHOD OF FORMING DEEP TRENCH ISOLATION IN RADIATION SENSING SUBSTRATE AND IMAGE SENSOR DEVICE - A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiC | 2017-06-01 |
20170154918 | Back Side Illuminated Image Sensor with Reduced Sidewall-Induced Leakage - Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate. | 2017-06-01 |
20170154919 | MANUFACTURING METHOD OF DISPLAY WITH LIGHTING DEVICES - A manufacturing method of display with lighting devices is disclosed, including providing a tank containing a liquid; disposing a carrying plate with several recessed regions in the tank, and the carrying plate being immersed in the liquid; dropping several lighting devices into the liquid, wherein each of the lighting devices includes two conductive pads, and one of the two conductive pads includes a magnetic material; applying a magnetic field for the lighting devices and the lighting devices will dispose within the recessed regions of the carrying plate; removing the carrying plate with the lighting devices out of the tank, and assembling the lighting devices to an array substrate. | 2017-06-01 |
20170154920 | LIGHT-EMITTING DEVICE - A light-emitting device includes a mounting board, a first wiring, a plurality of light-emitting elements, a first light-transmissive member, and a second wiring. The first wiring includes a plurality of electrodes which are disposed away from each other on the mounting board. The plurality of light-emitting elements is provided on the mounting board and is electrically connected to the first wiring. The first light-transmissive member is disposed above the plurality of light-emitting elements. The second wiring is disposed on a lower surface of the first light-transmissive member and electrically connects between electrodes among the plurality of electrodes of the first wiring. | 2017-06-01 |
20170154921 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DIODE - A light-emitting element includes a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first contact electrode and a second contact electrode located on the light-emitting structure, and respectively making ohmic contact with the first conductive semiconductor layer and the second conductive semiconductor layer; an insulation layer for covering a part of the first contact electrode and the second contact electrode so as to insulate the first contact electrode and the second contact electrode; a first electrode pad and a second electrode pad electrically connected to each of the first contact electrode and the second contact electrode; and a radiation pad formed on the insulation layer, and radiating heat generated from the light-emitting structure. | 2017-06-01 |
20170154922 | LIGHT-EMITTING DEVICE HAVING AN ARRAY OF LIGHT-EMITTING ELEMENTS - A light-emitting device includes a substrate, a first array of light-emitting elements connected in series and arranged along a first straight line on the substrate, a p-electrode disposed on the substrate and connected to the first array, a second array of light-emitting elements connected in series, arranged along a second straight line on the substrate, and connected to the first array, and an n-electrode disposed on the substrate and connected to the second array. The p-electrode has a surface that faces and is substantially parallel to a surface of the n-electrode. | 2017-06-01 |
20170154923 | Magnetic Tunnel Junction Based Logic Circuits - Resistance elements, including Magnetic Tunnel Junction devices are configured as magnetoelectronic (ME) devices. These resistive devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells. | 2017-06-01 |
20170154924 | Magnetic Tunnel Junction Based Reconfigurable Processing System & Components - Resistance elements, including Magnetic Tunnel Junction devices are configured as magnetoelectronic (ME) devices. These resistive devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells. | 2017-06-01 |
20170154925 | METHOD OF FABRICATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES - A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair. | 2017-06-01 |
20170154926 | 3D CROSS-POINT ARRAY AND PROCESS FLOWS - Three-dimensional cross-point array and process flows. In an exemplary embodiment, a method is provided that includes forming stacked layers, performing a first lithography operation on the stacked layers to form cell columns, and performing a second lithography operation on the stacked layers to form first vertical openings that are filled with first conductor layers to form one or more word line connections in a first direction. The method also includes performing a third lithography operation on the stacked layers to form second vertical openings that are filled with second conductor layers to form one or more bit line connections in a second direction. | 2017-06-01 |
20170154927 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a display device including a solar cell so as to use power produced by a solar energy, and a method for manufacturing the same, wherein the display device includes light-emitting areas provided on a lower substrate, and a solar cell layer provided on an upper substrate confronting the lower substrate, and provided to produce power by absorbing light, wherein the light-emitting areas include first to third light-emitting areas, and the solar cell layer includes first to third organic solar cell layers which are disposed to areas corresponding to the first to third light-emitting areas. | 2017-06-01 |
20170154928 | QUANTUM DOT OPTICAL DEVICES WITH ENHANCED GAIN AND SENSITIVITY AND METHODS OF MAKING SAME - Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described. | 2017-06-01 |
20170154929 | ORGANIC PHOTOELECTRONIC DEVICE - An organic photoelectronic device includes a first electrode and a second electrode facing each other, photoelectronic conversion layer between the first electrode and the second electrode and including a first material and a second material providing a p-n junction and an interlayer being adjacent to the first electrode between the first electrode and the photoelectronic conversion layer and including a third material, wherein the first material and the third material are an organic material having each energy bandgap of about 1.7 eV to about 2.3 eV, and an image sensor including the same is provided. | 2017-06-01 |
20170154930 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND HEAD MOUNTED DISPLAY INCLUDING THE SAME - An organic light emitting display device that can prevent non-emission areas from being visible as lattice patterns and a head-mounted display including the organic light emitting display device are provided. The organic light emitting display device includes anode electrodes, banks that define the anode electrodes, organic light-emitting layers that are disposed on the anode electrodes, and color filters that are disposed on the organic light-emitting layers. The banks include a color changing film that changes light emitted from the organic light-emitting layer into a predetermined color and outputs the changed color light. | 2017-06-01 |
20170154931 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device including: a plurality of first electrodes that are respectively patterned according to first, second, and third sub-pixels; a second electrode facing the plurality of first electrodes; a plurality of emission layers between the plurality of first electrodes and the second electrode; a hole transport region between the plurality of first electrodes and the plurality of emission layers; and at least one selected from a first auxiliary layer and a second auxiliary layer. The first auxiliary layer may be between the hole transport region and the first emission layer, the second auxiliary layer may be between the hole transport region and the second emission layer, and at least one selected from the first auxiliary layer and the second auxiliary layer may include a first compound represented by Formula 1: | 2017-06-01 |
20170154932 | DISPLAY UNIT - A display unit includes a plurality of light emitting devices, each of the light emitting devices including a function layer including at least an organic layer is sandwiched between a first electrode and a second electrode, and which have a resonator structure for resonating light by using a space between the first electrode and the second electrode as a resonant section and extracting the light through the second electrode are arranged on a substrate, wherein in the respective light emitting devices, the organic layer is made of an identical layer, and a distance of the resonant section between the first electrode and the second electrode is set to a plurality of different values. | 2017-06-01 |
20170154933 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - The present invention relates to a display panel and a method for manufacturing the same, and a display device. The display panel includes a display region and a non-display region, wherein a photovoltaic cell component is provided in the non-display region and is used to generate electricity when being irradiated by light. The photovoltaic cell component generates electricity when being irradiated by light, and the electricity can be provided to the display panel for the use of display or other functions, thereby supplementing electricity of the power supply, improving the utilization of energy, and prolonging the endurance time of the display panel in a case where the power supply used for providing electricity to the display panel has limited capacity. | 2017-06-01 |
20170154934 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING DISPLAY SUBSTRATE, AND DISPLAY DEVICE INCLUDING DISPLAY SUBSTRATE - A display substrate, a method of manufacturing the same, and a display device including the display substrate disclosed. In one aspect, the display substrate includes a pixel circuit disposed over a base substrate, an insulation layer disposed over the base substrate and overlapping the pixel circuit in the depth dimension of the display substrate, and a pixel electrode disposed over the insulation layer and electrically connected to the pixel circuit. The display substrate also includes a pixel defining layer disposed over the insulation layer, the pixel defining layer formed over a portion of the pixel electrode, and a spacer structure including a first spacer and a second spacer disposed over the first spacer, the first spacer being separated from the pixel circuit and disposed over the insulation layer. | 2017-06-01 |
20170154935 | ORGANIC LIGHT EMITTING DISPLAY PANEL AND METHOD FOR FABRICATING THE SAME - An organic light emitting display panel and a method for fabricating the same are provided by the present invention. The organic light emitting display panel includes: a substrate and a light emitting element layer disposed on the substrate. The light emitting element layer is provided with a plurality of first grooves. The organic light emitting display panel also includes an encapsulation layer disposed on the light emitting element layer, the plurality of first grooves are filled with the encapsulation layer. | 2017-06-01 |
20170154936 | DISPLAY DEVICE - A display device is discussed. The display device according to an embodiment includes a substrate, a display region disposed over the substrate and comprising a plurality of subpixels, and a data pad part disposed in regions other than the display region. The data pad part comprises a data signal line extended from the display region, an insulating film disposed on the data signal line and insulating the data signal line, a data pad electrode disposed on the insulating film and connected to the data signal line through the via hole, and an insulating pattern configured to cover the via hole. The data pad electrode can include at least one electrode hole. | 2017-06-01 |
20170154937 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY APPARATUS, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate includes a thin film transistor including a first gate electrode, an active layer, a source electrode, and a drain electrode. A first conductive layer pattern is on a same layer as the source electrode and the drain electrode and formed of a same material as the source electrode and the drain electrode. An insulating layer is on the first conductive layer pattern and has an opening exposing a patterning cross-section of the first conductive layer pattern. A pixel electrode is on the insulating layer and is coupled to the source electrode or the drain electrode through a contact hole passing through the insulating layer. A diffusion prevention layer covers the patterning cross-section of the first conductive layer pattern and inclined side surfaces of the insulating layer exposed through the opening. | 2017-06-01 |
20170154938 | DISPLAY PANELS AND METHODS FOR FABRICATING THE SAME - A display panel and a method for fabricating the same are provided. The display panel includes: a TFT array substrate; an OLED array disposed on the TFT array substrate, a package layer which covers the OLED array, an upper protection layer covering the package layer, and a lower protection layer. In a first direction, a first projection of the OLED array on the TFT array substrate is located within a second projection of the package layer on the TFT array substrate, and there is a first distance between a boundary of the first projection and a boundary of the second projection. Also in the first direction, the second projection is located within a third projection of the upper protection layer on the TFT array substrate, and there is a second distance between the boundary of the second projection and a boundary of the third projection. | 2017-06-01 |
20170154939 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - An organic light emitting display (OLED) device capable of preventing a pad area of an organic light emitting display panel from being rolled, and a method of fabricating the same, in which the OLED device can include a base film including a display area, and a first pad area provided with first pads, in which the first pad area extends from and protrudes out of a first side of the display area; a plurality of thin film transistors on the base film; and a plurality of organic light emitting diodes on the thin film transistors. | 2017-06-01 |
20170154940 | Light-Emitting Device - There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is μ, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs | 2017-06-01 |
20170154941 | THIN FILM TRANSISTOR SUBSTRATE FOR ORGANIC LIGHT-EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - Provided are a thin film transistor (TFT) substrate and a method of manufacturing the same. A TFT substrate includes: a substrate defining a pixel area, a first TFT including: an oxide semiconductor layer, a first gate electrode on the oxide semiconductor layer, a first source electrode, and a first drain electrode, a second TFT including: a second gate electrode, a polycrystalline semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a first gate insulating layer under the first gate electrode and the second gate electrode, the first gate insulating layer covering the oxide semiconductor layer, a second gate insulating layer under the polycrystalline semiconductor layer, the second gate insulating layer covering the first gate electrode and the second gate electrode, and an intermediate insulating layer on the first gate electrode and the polycrystalline semiconductor layer, the intermediate insulating layer including a nitride layer. | 2017-06-01 |
20170154942 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Discussed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device can include first electrodes that are disposed on a substrate, organic light-emitting layers that are disposed on the first electrodes, banks that overlap edges of the first electrodes and define pixels, light-blocking layers that are disposed on the banks, and resin layers that are disposed between the light-blocking layers and include an adhesive material. A resin transfer pattern that penetrates each of the light-blocking layers from one side to the other side may be formed in the light-blocking layers. The resin layer disposed on one side of each of the light-blocking layers and the resin layer disposed on the other side of the light-blocking layer are connected to each other via the resin transfer pattern. | 2017-06-01 |
20170154943 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof, and a display device, the array substrate ( | 2017-06-01 |
20170154944 | Organic Light Emitting Diode Display - An organic light emitting display in which each pixel has a driving thin film transistor for adjusting the current flowing through an organic light emitting diode based on a voltage applied to a gate electrode, includes the gate electrode of the driving thin film transistor; a signal line adjacent to the gate electrode of the driving thin film transistor; and a first shielding electrode located above the gate electrode of the driving thin film transistor, with a first insulating layer therebetween, wherein the first shielding electrode extends further towards the signal line than the gate electrode of the driving thin film transistor. | 2017-06-01 |
20170154945 | Organic Light Emitting Diode Display - A display device including a substrate comprising a free form active area having pixels defined by scan lines, data lines, and power supply lines, and a bezel area located outside the active area and having power supply routing lines to which a power supply voltage is applied and scan routing lines to which scan pulses are applied; and link lines that are disposed in the bezel area, and that connect the power supply routing lines to the power supply lines and transmit the power supply voltage from the power supply routing lines to the power supply lines, the link lines comprising: a plurality of first link lines; and one or more second link lines that interconnect the first link lines, each of the first link lines comprising one end connected to the power supply routing lines and the other end connected to the power supply lines. | 2017-06-01 |
20170154946 | DISPLAY DEVICE - A display device includes: a display unit in which a plurality of pixels are arranged; and a power supply unit configured to feed a power supply voltage to the pixels through a power feeding line disposed on an outer periphery of the display unit. The pixels each include: an anode formed on a drive circuit layer; an auxiliary wire formed on the drive circuit layer to be spaced apart from the anode; an organic light emitting layer and an electron transport layer that are formed above the anode; and a transparent cathode formed above the electron transport layer. The electron transport layer and the transparent cathode extend from above the anode to above the auxiliary wire. The electron transport layer has a resistance value R | 2017-06-01 |
20170154947 | DISPLAY DEVICE AND ELECTRONIC DEVICE - A display device including a wide display region in which a seam is less likely to be noticed is provided. The display device includes two display panels that overlap with each other. An upper display panel includes a first display region and a region that transmits visible light. A lower display panel includes a second display region and a region that blocks visible light. The second display region overlaps with, on a display surface side, the region that transmits visible light. The region that blocks visible light overlaps with the first display region. At least part of an insulating layer included in the upper display panel is provided in the first display region and not provided in the region that transmits visible light. | 2017-06-01 |
20170154948 | INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA - An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Another conductive structure extends in the peripheral portion on different planes of metallizations and forms a seal ring. | 2017-06-01 |
20170154949 | DIFFUSED RESISTOR - A diffused resistor and method for forming a diffused resistor are provided. The diffused resistor comprises a substrate having a first conductivity type; a first well within the substrate having a second conductivity type; and a second well within the first well having the first conductivity type. The resistor further comprises a first and second contact for coupling the resistor to further circuitry. The first and second contacts are each coupled to both the first well and the second well. | 2017-06-01 |
20170154950 | THREE-DIMENSIONAL METAL RESISTOR FORMATION - A method includes forming an insulating carrier substrate, forming a shallow trench isolation region within the insulating carrier substrate, and forming a plurality of gate recesses on the shallow trench isolation region. The plurality of gate recesses is formed by forming a plurality of dummy gates on the shallow trench isolation region and etching the plurality of dummy gates. The method further includes depositing a metal resistor layer within the plurality of gate recesses. | 2017-06-01 |
20170154951 | SCALABLE FIXED-FOOTPRINT CAPACITOR STRUCTURE - In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a first direction. A first conductor segment among the multiple conductor segments may be biased to a first voltage. The second conductor segment among the multiple conductor segments may be biased to a second voltage. The shielding conductor segment may be biased to the second voltage and is formed at an end of the first conductor segment. In addition to that, the capacitances for the capacitor structure may be adjusted while the footprint of the capacitor structure is fixed. | 2017-06-01 |
20170154952 | Capacitor, Array Of Capacitors, And Device Comprising An Electrode - A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally inner and outer capacitor electrodes. The elevationally inner capacitor electrode comprises a hollow longitudinally-elongated conductive cylinder-like portion and a non-hollow longitudinally-elongated conductive cylinder-like portion electrically coupled with the hollow cylinder-like portion. The non-hollow cylinder-like portion is radially of and extends longitudinally along a longitudinal side surface of the hollow cylinder-like portion. Additional embodiments and aspects are disclosed. | 2017-06-01 |
20170154953 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device includes an impurity region including a p type impurity and disposed within a silicon carbide layer to surround an element region as seen in plan view. The impurity region has a peak concentration of the p type impurity at a position within the silicon carbide layer distant from a first main surface. The peak concentration is not less than 1×10 | 2017-06-01 |
20170154954 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACK - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer. | 2017-06-01 |
20170154955 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a device region on the semiconductor substrate; a planar edge termination region on the semiconductor substrate to surround the device region; and a passivation film covering the edge termination region, wherein the passivation film includes a semi-insulating film directly contacting the semiconductor substrate. | 2017-06-01 |
20170154956 | Method of Manufacturing Superjunction Semiconductor Devices with a Superstructure in Alignment with a Foundation - By using a single trench mask, first and second trenches are formed that extend from a main surface into a semiconductor layer. A foundation is formed that includes first regions in and/or directly adjoining the first trenches. A superstructure is formed in alignment with the foundation by using position information directly obtained from structures formed in the first and/or the second trenches. | 2017-06-01 |
20170154957 | COMPACT CMOS DEVICE ISOLATION - An integrated circuit uses a compact CMOS device isolation scheme which forms a ring of N-well housing PMOS devices to encircle the P-well housing NMOS devices in a circuit block. An N-type buried layer is formed under the P-well and extends partially under the surrounding N-well. The compact CMOS device isolation scheme eliminates the use of a deep N-well ring around the circuit block. Therefore, the circuit blocks of the integrated circuit can be formed with reduced silicon area and the die size for implementing the integrated circuit is reduced. | 2017-06-01 |
20170154958 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region. | 2017-06-01 |
20170154959 | SUPPORT FOR LONG CHANNEL LENGTH NANOWIRE TRANSISTORS - A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging. | 2017-06-01 |
20170154960 | VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS - Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active. | 2017-06-01 |
20170154961 | SEMICONDUCTOR DEVICE INCLUDING A STRAIN RELIEF BUFFER - A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate. | 2017-06-01 |
20170154962 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes providing a substrate, forming an amorphous layer in the substrate, performing a first etching process on the substrate using the amorphous layer as an etch stop layer to form a plurality of first fins, performing a channel stop ion implantation process into the amorphous layer to form an impurity region, and performing an annealing process to activate implanted dopants in the impurity region, wherein the amorphous layer disappears during the annealing process. The method also includes performing a second etching process on a region of the substrate disposed between the first fins to form second fins from the first fins, and forming an isolation region between adjacent second fins by filling at least a portion of an air gap between the second fins with an insulating material. The method prevents dopants of the channel stop implant from diffusing into the channel. | 2017-06-01 |
20170154963 | CONTROLLED DOPING FROM LOW TO HIGH LEVELS IN WIDE BANDGAP SEMICONDUCTORS - The energy of formation of a point defect in a compound semiconductor is a function of the process conditions and the Fermi energy (the energy of the charge carriers). In wide bandgap semiconductors or insulators, the contribution of this energy to the formation energy of charged point defects is significant. For doping for n- or p-type conductivity, the larger the energy gap, the higher the concentration of compensating point defects that is at equilibrium with the system. This is a fundamental problem with wide bandgap materials that will be directly addressed with these capabilities. In this approach, minority carrier injection is used to modify the quasi-Fermi level to control the formation energy of the point defects. Increasing the formation energy of unwanted point defect through an external excitation that leads to excess minority carriers during the growth of the semiconductor device structure leads to a reduction in compensating point defects. | 2017-06-01 |
20170154964 | RADIO FREQUENCY ISOLATION FOR SOI TRANSISTORS - According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. | 2017-06-01 |
20170154965 | Semiconductor Device - A semiconductor device includes a semiconductor substrate including, between a bottom side and a top side, a first trench and a second trench extending in a vertical direction, and a contact groove arranged between the first trench and the second trench. The contact groove has a longitudinal extension in a plane perpendicular to the vertical direction. The longitudinal extension of the contact groove at least partially has a wave-shape. | 2017-06-01 |
20170154966 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer. | 2017-06-01 |
20170154967 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator. | 2017-06-01 |
20170154968 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes. The semiconductor device includes: a substrate including an active region, and a field region directly adjacent to the active region; a first fin-type pattern protruding from the substrate in the active region; a first gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a first portion and a second portion, the first portion intersecting with the first fin-type pattern; a second gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a third portion and a fourth portion, the fourth portion facing the second portion, and the third portion intersecting with the first fin-type pattern and facing the first portion; a first interlayer insulating structure disposed between the first portion and the third portion, being on the substrate, and having a first dielectric constant; and a second interlayer insulating structure disposed between the second portion and the fourth portion, being on the substrate, and having a second dielectric constant which is different from the first dielectric constant. | 2017-06-01 |
20170154969 | SEMICONDUCTOR DEVICE - The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation. | 2017-06-01 |
20170154970 | Buried Bus and Related Method - A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer. | 2017-06-01 |
20170154971 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film. | 2017-06-01 |
20170154972 | GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion. | 2017-06-01 |
20170154973 | Multi-Gate Device and Method of Fabrication Thereof - A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer. | 2017-06-01 |
20170154974 | Semiconductor Device and Method for Producing a Semiconductor Device - A method for producing a semiconductor device includes: depositing a barrier layer on a first surface of a semiconductor body having active regions of a semiconductor device; forming a contact layer that at least partially covers the barrier layer, the barrier layer being configured to prevent a material of the contact layer from diffusing into the semiconductor body; forming a first passivation layer on the contact layer and on exposed surfaces of the barrier layer; in a first etching process, removing the first passivation layer from above the barrier layer so as to uncover sections of the barrier layer; and in a second etching process, removing at least some sections of the barrier layer uncovered by the first etching process | 2017-06-01 |
20170154975 | GRAPHENE TRANSISTOR AND RELATED METHODS - A method and structure for providing high-quality transferred graphene layers for subsequent device fabrication includes transferring graphene onto a hydrophobic surface of a hydrophobic layer and performing a thermal treatment process. In various embodiments, a substrate including an insulating layer is provided, and a hydrophobic layer is formed over the insulating layer. In some examples, a graphene layer is transferred onto the hydrophobic layer. By way of example, the transferred graphene layer has a first carrier mobility. In some embodiments, after transferring the graphene layer, an annealing process is performed, and the annealed graphene layer has a second carrier mobility greater than the first carrier mobility. | 2017-06-01 |
20170154976 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively. | 2017-06-01 |
20170154977 | TRI-GATE FINFET DEVICE - A tri-gate FinFET device includes a fin that is positioned vertically above and spaced apart from an upper surface of a semiconductor substrate, wherein the fin has an upper surface, a lower surface opposite of the upper surface, a first side surface, and a second side surface opposite of the first side surface. The axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the semiconductor substrate, and the first side surface of the fin contacts an insulating material. A gate structure is positioned around the upper surface, the second side surface, and the lower surface of the fin, and a gate contact structure is conductively coupled to the gate structure. | 2017-06-01 |
20170154978 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH EPITAXIAL GROWTH STRUCTURE - Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening. | 2017-06-01 |
20170154979 | Dislocation SMT For FinFet Device - Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process. | 2017-06-01 |
20170154980 | ROBUST GATE SPACER FOR SEMICONDUCTOR DEVICES - After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and planarized such that the top surface of the disposable material layer is formed below the topmost surface of the lower dielectric spacer. An upper dielectric spacer is formed around the gate structure and over the top surface of the disposable material layer. The disposable material layer is removed selective to the upper and lower dielectric spacers and device components underlying the gate structure. Semiconductor surfaces of the gate structure can be laterally sealed by the stack of the lower and upper dielectric spacers. Formation of any undesirable semiconductor deposition on the gate structure can be avoided by the combination of the lower and upper dielectric spacers during a subsequent selective epitaxy process. | 2017-06-01 |
20170154981 | MAKING A DEFECT FREE FIN BASED DEVICE IN LATERAL EPITAXY OVERGROWTH REGION - Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces. | 2017-06-01 |
20170154982 | FINFET WITH EPITAXIAL SOURCE AND DRAIN REGIONS AND DIELECTRIC ISOLATED CHANNEL REGION - A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure. | 2017-06-01 |
20170154983 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced. | 2017-06-01 |
20170154984 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region. | 2017-06-01 |
20170154985 | IE TYPE TRENCH GATE IGBT - In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween. | 2017-06-01 |
20170154986 | STRESS CONTROL ON THIN SILICON SUBSTRATES - Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate. | 2017-06-01 |
20170154987 | NORMALLY-OFF HIGH ELECTRON MOBILITY TRANSISTORS AND FABRICATION METHODS THEREOF - Disclosure includes a normally-off field-effect semiconductor device and the fabrication method thereof. An antigrowth portion is formed on a template. A first semiconductor layer and a second semiconductor layer on the template form two heterojunctions for creating two-dimensional electron gas regions, while a heterojunction-free area defined by the antigrowth portion separate the heterojunctions. A dielectric layer is on the second semiconductor layer and above the antigrowth portion. Two channel electrodes formed on the second semiconductor layer are electrically coupled to the two-dimensional electron gas regions respectively. A gate electrode on the dielectric layer and above the antigrowth portion is used for control of conduction between the channel electrodes. | 2017-06-01 |
20170154988 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE - A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material. | 2017-06-01 |
20170154989 | Methods of Manufacturing Gallium Nitride Devices - Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron to concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others. | 2017-06-01 |
20170154990 | Silicon Germanium P-Channel FinFET Stressor Structure and Method of Making Same - A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET. | 2017-06-01 |
20170154991 | Semiconductor Devices - A semiconductor device may include a pair of active patterns spaced apart from each other in a first direction, a pair of gate electrodes intersecting the pair of the active patterns in a second direction crossing the first direction, gate spacers on sidewalls of the pair of the active patterns, source/drain regions on the pair active patterns between the pair of the gate electrodes, and a spacer protection pattern between the pair of the gate electrodes and between the pair of the active patterns. The spacer protection pattern may be commonly connected to the gate spacers. | 2017-06-01 |