22nd week of 2011 patent applcation highlights part 37 |
Patent application number | Title | Published |
20110129938 | L-FUCOSE ALPHA1-6 SPECIFIC LECTIN - Disclosed is a novel lectin which can bind specifically to an L-fucose α1→6 sugar chain. Also disclosed is use of the lectin. The L-fucose α1→6 specific lectin of the present invention is characterized in that: (1) the lectin is extracted from a basidiomycete or an ascomycete; (2) the lectin has a molecular weight by sodium dodecyl sulfate-polyacrylamide gel electrophoresis (SDS-PAGE) of 4,000 to 40,000; and (3) the lectin has an affinity to an L-fucose α1→6 sugar chain, the affinity being represented by an association constant of 1.0×10 | 2011-06-02 |
20110129939 | PORTABLE ELECTRONIC DEVICE AND METHOD FOR USING THE SAME - A portable electronic device includes at least one function module selected from a group consisting of a wireless communication module, an image capturing module, an audio/video file player module, and an internet module, a halitosis measuring module, and a processor connected to the function module and the halitosis measuring module. The processor controls the function module to work, and detects a level of volatile sulfur compounds (VSCs) in a person's mouth using the halitosis measuring module. | 2011-06-02 |
20110129940 | METHOD AND APPARATUS FOR DESORPTION OF A BLOOD SAMPLE FROM A MEDICAL TEST SHEET - A method for desorption of a blood sample from a dried blood spot on a medical test sheet, for the purpose of biomedical analysis, comprises the steps of: interposing the test sheet inbetween first and second clamping heads; clamping the first and the second clamping heads onto the interposed test sheet; and flushing a desorption area of the clamped test sheet with a sample elution fluid. The clamping heads are transmitting compressive forces to parts of the test sheet. The compressive forces create an imprinted sealing area of the test sheet, which imprinted sealing area has a closed loop shape surrounding a desorption area of the test sheet. The desorption area is contained in a space enveloped by first and second outer surfaces of the first and second clamping heads, respectively, and sealed by the imprinted sealing area. | 2011-06-02 |
20110129941 | Method of Producing Polymeric Particles With Selected Size, Shape, Morphology and Composition - The present invention provides a method and apparatus for producing polymeric particles with pre-designed size, shape, morphology and composition, and more particularly the present invention uses a microfluidic polymerization reactor for producing same. The present invention disclosed herein provides a process for producing polymer particles with pre-selected shapes. The method includes injecting a first fluid comprising a polymerizable constituent with a controlled flow rate into a microfluidic channel and injecting a second fluid with a controlled flow rate into the microfluidic channel in which the second fluid mixes with the first fluid, the second fluid being immiscible with the first fluid so that the first fluid forms into droplets in the microfluidic channel. The microfluidic channel has pre-selected dimensions to give droplets of pre-selected size, morphology and shape. The microfluidic channel is sufficiently long so that the droplets have a sufficiently long residence time in the channel so that they polymerize or otherwise harden into droplets of pre-selected size and shape. | 2011-06-02 |
20110129942 | FLUORESCENCE DETECTING METHOD - An amount of fluorescent labels corresponding to an amount of a detection target substance are caused to bind on a detecting portion. The fluorescent labels are excited, and the amount of the detection target substance is detected based on the intensity of fluorescence emitted due to the excitation. Fine inorganic fluorescent particles which do not become discolored are employed as the fluorescent labels. | 2011-06-02 |
20110129943 | Method for Analyzing Proteins - A method for analyzing proteins makes use of an array of first capture molecules which are specific for peptide epitopes. The proteins to be analyzed or a protein mixture containing the proteins to be analyzed is degraded to peptide fragments corresponding to the peptide epitopes, after which the array of capture molecules is incubated with the peptide fragments. The peptide fragments bound to the capture molecules are then detected. | 2011-06-02 |
20110129944 | WATER-SOLUBLE NANOCRYSTALS AND METHODS OF PREPARING THEM - Disclosed is a water soluble nanocrystal having a core comprising at least one metal M1 selected from an element of subgroup IIb, subgroup VIIa, subgroup VI11a, subgroup 1b, subgroup IV, main group II or main group III of the periodic system of the elements (PSE), at least one element A selected from an element of the main group V or VI of the periodic system of the elements, wherein a capping reagent is attached to the surface of the core of the nanocrystal, and wherein the capping reagent forms a host guest complex with a water soluble host molecule. Also disclosed is a water soluble nanocrystal having a core comprising at least one metal M1 selected from an element of subgroup I1b, subgroup VI1a, subgroup VI11a, subgroup 1b, subgroup IV, main group II or main group III of the periodic system of the elements (PSE), and at least one element A selected from an element of the main group V or VI of the periodic system of the elements, wherein a capping reagent is attached to the surface of the core of the nanocrystal, and wherein the capping reagent is covalently linked to a water soluble host molecule. Also disclosed is a water soluble nanocrystal having a core comprising at least one metal M1 selected from an element of subgroup I1b, subgroup VI1a, subgroup VI11a, subgroup 1b, subgroup IV, main group II or main group III of the periodic system of the elements (PSE), wherein a capping reagent is attached to the surface of the core of the nanocrystal, and wherein the capping reagent forms a host guest complex with a water soluble host molecule. Finally, compositions and uses of such nanocrystals are disclosed. | 2011-06-02 |
20110129945 | SUPERCONDUCTIVITY BASED ON BOSE-EINSTEIN CONDENSATION OF ELECTRON OR ELECTRON-HOLE PAIRS IN SEMICONDUCTORS - The invention describes a method of achieving superconductivity in Group IV semiconductors via the addition of doubly charged impurity atoms to the crystal lattice. The doubly charged impurities function as composite bosons in the semiconductor. Increasing the density of the composite bosons to a level where their wavefunctions overlap, results in the formation of a Bose condensate. The concentration of the doubly charged impurity atoms in the host lattice and the binding energy of the impurities are important factors in determining whether a Bose condensate will form. Doubly charged impurities must be present in the semiconductor at a concentration at which they exhibit overlapping wavefunctions, but still exist within the crystal lattice as bosons. | 2011-06-02 |
20110129946 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 2011-06-02 |
20110129947 | Method For Improving Performance Of A Substrate Carrier - A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier. | 2011-06-02 |
20110129948 | Optical alignment methods for forming LEDs having a rough surface - A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness σ | 2011-06-02 |
20110129949 | METHOD FOR GROWTH OF DILUTE-NITRIDE MATERIALS USING AN ISOTOPE FOR ENHANCING THE SENSITIVITY OF RESONANT NUCLEAR REATION ANALYSIS - In certain desirable embodiments, the present invention relates to the use of | 2011-06-02 |
20110129950 | METHOD OF MANUFACTURING SOLID STATE IMAGING DEVICE, SOLID STATE IMAGING DEVICE, AND CAMERA USING SOLID STATE IMAGING DEVICE - A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer showing an oxidizing property at the time of film formation, the transparent layer being formed on the photo-electric conversion parts and the light-shielding layer. | 2011-06-02 |
20110129951 | PROCESS FOR MANUFACTURING SEALED ORGANIC ELECTROLUMINESCENCE DEVICES - A process for manufacturing sealed organic EL devices includes a step of forming an organic EL layer on a region of an anode-mounted substrate having a substrate and an anode, the region including at least a bonding region in which a sealing member will be bonded and a region which is found inward the bonding region; a step of removing a portion of the organic EL layer which is found at least on the bonding region by applying plasma by a remote plasma method to expose the bonding region; a step of forming a cathode on the organic EL layer to complete an organic EL device; and a step of bonding a sealing member to the exposed bonding region. | 2011-06-02 |
20110129952 | THIN FILM TRANSISTOR SUBSTRATES AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes a color filter layer and a gate line. The color filter layer has a reverse taper shape, which is used to pattern the gate line without a separate mask. Thus, the total number of masks used to manufacture the thin film transistor substrate can be reduced, thereby reducing the manufacturing cost and improving the productivity. | 2011-06-02 |
20110129953 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - A method of manufacturing a nitride semiconductor device is disclosed. The method includes forming a gallium nitride (GaN) epitaxial layer on a first support substrate, forming a second support substrate on the GaN epitaxial layer, forming a passivation layer on a surface of the other region except for the first support substrate, etching the first support substrate by using the passivation layer as a mask, and removing the passivation layer and thereby exposing the second support substrate and the GaN epitaxial layer. | 2011-06-02 |
20110129954 | METHOD FOR MANUFACTURING A PHOTOVOLTAIC CELL STRUCTURE - In the frame of photovoltaic cell manufacturing a silicon compound layer is deposited upon a carrier structure. Manufacturing flexibility is increased on one hand by incorporating ambient air exposure of such silicon compound layer and on the other preventing deterioration of reproducibility by such ambient air exposure by enriching the surface of the addressed silicon compound layer which is to be exposed to ambient air to an oxygen enrichment. | 2011-06-02 |
20110129955 | DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS - A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures. | 2011-06-02 |
20110129956 | WEDGE IMPRINT PATTERNING OF IRREGULAR SURFACE - Patterned substrates for photovoltaic and other uses are made by pressing a flexible stamp upon a thin layer of resist material, which covers a substrate, such as a wafer. The resist changes phase or becomes flowable, flowing away from locations of impression, revealing the substrate, which is subjected to some shaping process, typically etching. Portions exposed by the stamp being are removed, moved, and portions that protected by the resist, remain. A typical substrate is silicon, and a typical resist is a wax. Workpiece textures include extended grooves, discrete, spaced apart pits, and combinations and intermediates thereof. Platen or rotary patterning apparatus may be used. Rough and irregular workpiece substrates may be accommodated by extended stamp elements. Resist may be applied first to the workpiece, the stamp, or substantially simultaneously, in discrete locations, or over the entire surface of either. The resist dewets the substrate completely where desired. | 2011-06-02 |
20110129957 | METHOD OF MANUFACTURING SOLAR CELL - A solar cell manufacturing method is provided. A solar cell manufacturing method according to an exemplary embodiment of the present invention includes: forming a first electrode on a substrate, forming a precursor including copper (Cu), gallium (Ga), and indium (In) on the first electrode, supplying selenium (Se) to the precursor to form a preliminary light absorption layer, depositing at least one of gallium or indium on the preliminary light absorption layer, supplying selenium (Se) to the preliminary light absorption layer deposited with the at least one of gallium and indium to form a light absorption layer and forming a second electrode on the light absorption layer. | 2011-06-02 |
20110129958 | METHOD AND APPARATUS FOR SCRIBING A LINE IN A THIN FILM USING A SERIES OF LASER PULSES - A series of laser pulses in a pulse train, each pulse with a predetermined temporal power shape, scribes a line in a thin film of material on a substrate. The predetermined temporal pulse shape has a fast risetime and fast falltime and a pulse length between 10% power points of less than 10 ns. Scribing a line in the thin film is achieved by placing the series of laser pulse spots on the line to be scribed such that there is some overlapping area between adjacent laser pulse spots along the line. The use of a series of laser pulses with the predetermined pulse shape to scribe a line in the thin film results in a better quality and cleaner scribing process compared to that achieved with a conventional pulse shape. | 2011-06-02 |
20110129959 | CRYSTALLIZATION PROCESSING FOR SEMICONDUCTOR APPLICATIONS - A method and apparatus for forming a crystalline semiconductor layer on a substrate are provided. A semiconductor layer is formed by vapor deposition. A pulsed laser melt/recrystallization process is performed to convert the semiconductor layer to a crystalline layer. Laser, or other electromagnetic radiation, pulses are formed into a pulse train and uniformly distributed over a treatment zone, and successive neighboring treatment zones are exposed to the pulse train to progressively convert the deposited material to crystalline material. | 2011-06-02 |
20110129960 | Method of manufacturing stacked wafer level package - A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes. | 2011-06-02 |
20110129961 | Process to form semiconductor packages with external leads - This invention discloses a process for packaging semiconductor device with external leads. The process includes comprises Step 1: providing a lead frame comprising a plurality of lead frame units connected by a plurality of metal beams, each lead frame unit comprising a die pad and a plurality of leads located on opposite sides of the die pad; adhering a semiconductor chip onto each of the die pad, and providing a plurality of metal connections for electrically connecting each chip to its corresponding leads; Step 2 providing a plastic molding material to enclose the plurality of the lead frame units, the metal beams, the chips, and at least portions of the metal connections; Step 3 removing a portion of the plastic molding material above the metal beams to expose the metal beams and portions of the leads in connection with the metal beams; and Step 4 separating each lead frame unit, forming a plurality of individual semiconductor plastic package components with external leads. | 2011-06-02 |
20110129962 | ENCAPSULATION METHOD FOR PACKAGING SEMICONDUCTOR COMPONENTS WITH EXTERNAL LEADS - This invention discloses a method for packaging a semiconductor device with leads extending outside its encapsulation. The method comprises the following steps: Step 1, providing a lead frame comprising a plurality of lead frame units arranged in two dimensional array, each lead frame unit comprising a die pad and a plurality of leads located along two opposite sides of the die pad, attaching a semiconductor chip onto the die pad and electrically connecting the electrodes on each chip to its corresponding leads; Step 2, Encapsulating the chips, the die pads, and the leads with molding material into a plurality of one dimensional plastic encapsulation bars with the leads of each lead frame unit extending out along two opposite sides of the plastic encapsulation bars connecting to a plurality of tie bars substantially parallel to the plastic encapsulation bars; Step 3, Trimming off the tie bars therefore cutting off the connections between the leads to the tie bars while preserving a portion of the leads extending out of the plastic encapsulation bars; and Step 4, Sawing through the plastic encapsulation bars to form a plurality of individual semiconductor components with leads extending outside its encapsulation. | 2011-06-02 |
20110129963 | Clipless Integrated Heat Spreader Process and Materials - In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips. | 2011-06-02 |
20110129964 | STRUCTURE COMBINING AN IC INTEGRATED SUBSTRATE AND A CARRIER, AND METHOD OF MANUFACTURING SUCH STRUCTURE - The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The IC integrated substrate has a first dielectric layer attached to the carrier. The materials of the carrier and the first dielectric layer are selected to prevent the IC integrated substrate from peeling off the carrier during processing and to allow the IC integrated substrate to naturally separate from the carrier after being cut, through the adhesion between the carrier and the first dielectric layer. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electrical devices using the above structure. | 2011-06-02 |
20110129965 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD - A method for manufacturing a semiconductor package system includes: providing a leadframe, having an open center, with leads adjacent to a peripheral edge of the leadframe; making a die support pad, formed without tie bars, separately from the leadframe; providing a coverlay tape for positioning the support pad centered within the leadframe; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the leads; and connecting a bonding pad on the semiconductor die to one of the leads using a bonding wire. | 2011-06-02 |
20110129966 | SEMICONDUCTOR DEVICE HAS ENCAPSULANT WITH CHAMFER SUCH THAT PORTION OF SUBSTRATE AND CHAMFER ARE EXPOSED FROM ENCAPSULANT AND REMAINING PORTION OF SURFACE OF SUBSTRATE IS COVERED BY ENCAPSULANT - A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device. | 2011-06-02 |
20110129967 | THREE-TERMINAL POWER DEVICE WITH HIGH SWITCHING SPEED AND MANUFACTURING PROCESS - An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device connected in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal connected to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, connected between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal connected to the control terminal; and a Zener diode, connected between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition. | 2011-06-02 |
20110129968 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer. | 2011-06-02 |
20110129969 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer. | 2011-06-02 |
20110129970 | ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material. | 2011-06-02 |
20110129971 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY REDUCING A WIDTH OF OFFSET SPACERS - In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process. | 2011-06-02 |
20110129972 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED ON THE BASIS OF A SIMPLIFIED SPACER REGIME - In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure is provided, which is, in combination with a dielectric cap material, also used as an efficient implantation mask during the implantation of extension and halo regions, thereby increasing the ion blocking capability of the complex gate electrode structure substantially without affecting the sensitive gate materials. | 2011-06-02 |
20110129973 | NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME - A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over the said porous dielectric film, and anisotropically and selectively etching the deposited material. | 2011-06-02 |
20110129974 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming a plurality of buried bit lines in the first trenches, forming a plurality of second trenches to expose at least one sidewall of the buried bit lines by etching the substrate, and forming a plurality of one-sidewall contact plugs which fill the second trenches. | 2011-06-02 |
20110129975 | METHOD FOR FABRICATING SIDE CONTACT IN SEMICONDUCTOR DEVICE USING DOUBLE TRENCH PROCESS - A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench. | 2011-06-02 |
20110129976 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 2011-06-02 |
20110129977 | PLASMA DOPING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate. | 2011-06-02 |
20110129978 | METHOD AND STRUCTURE FOR FORMING FINFETS WITH MULTIPLE DOPING REGIONS ON A SAME CHIP - A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins. | 2011-06-02 |
20110129979 | Method of Manufacturing a Semiconductor Device Having Improved Transistor Performance - In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region. | 2011-06-02 |
20110129980 | CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL - Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability. | 2011-06-02 |
20110129981 | FILLER FOR FILLING A GAP AND METHOD FOR MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE SAME - A filler for filling a gap includes a hydrogenated polysiloxazane having an oxygen content of about 0.2 to about 3 wt %. A chemical structure of the hydrogenated polysiloxazane includes first, second, and third moieties represented by the following respective Chemical Formulas 1-3: | 2011-06-02 |
20110129982 | Method for Forming a Capacitor of a Semiconductor Memory Device - A semiconductor device that is capable of preventing a storage node bunker defect or a defect due to loss of a barrier layer, and a method for forming a capacitor thereof. The semiconductor memory device includes a contact hole formed in an interlayer dielectric layer on a semiconductor substrate; a barrier layer formed on the bottom of the contact hole; a first storage node contact formed of a conductive layer that fills the rest of the contact hole; a second storage node contact formed on the result formed with the first storage node contact so as to be shifted by a given distance from the first storage node contact; an insulation layer formed between the second storage node contacts; a storage electrode connected with the second storage node contact and isolated on a per cell basis; and dielectric layer and plate electrode for covering the storage electrode. | 2011-06-02 |
20110129983 | METHOD FOR FABRICATING A DUAL-ORIENTATION GROUP-IV SEMICONDUCTOR SUBSTRATE - The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (1 1θ)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy. | 2011-06-02 |
20110129984 | METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction. | 2011-06-02 |
20110129985 | METHODS FOR FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES - A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a dielectric layer that is atop a semiconductor substrate. The buffer film layer comprises a material that is oxidation resistant and can be etched selectively to oxide films. The layered structure is patterned with a resist material and etched to form a shallow trench. A thin oxide layer is formed in the trench and the buffer film layer is selectively etched to move the buffer film layer back from the corners of the trench. An isolation material is then used to fill the shallow trench and the buffer film layer is stripped to form an isolation structure. When the structure is etched by subsequent processing step(s), a capped shallow trench isolation structure that covers the shallow trench corners is created. | 2011-06-02 |
20110129986 | NITROGEN-PLASMA SURFACE TREATMENT IN A DIRECT BONDING METHOD - Two plates, each comprising a thin layer of silicon or silicon oxide at a surface thereof, are bonded by subjecting the thin layer of at least one of the plates to a surface treatment step forming a silicon oxynitride superficial thin film with a thickness of less than 5 nm. The thin film is performed with a nitrogen-based plasma generated by an inductively coupled plasma source. Furthermore, a potential difference applied between the plasma and a substrate holder supporting said plate during the surface treatment step is less than 50 V, advantageously less than 15 V and preferably zero. This enables a defect-free bonding interface to be obtained irrespective of a temperature of any heat treatment carried out after a contacting step between the respective thin layers of the two plates. | 2011-06-02 |
20110129987 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a structure and a manufacturing method for efficiently forming a transistor to which tensile strain is preferably applied and a transistor to which compressive strain is preferably applied over the same substrate when stress is applied to a semiconductor layer in order to improve mobility of the transistors in a semiconductor device. Plural kinds of transistors which are separated from a single-crystal semiconductor substrate and include single-crystal semiconductor layers bonded to a substrate having an insulating surface with a bonding layer interposed therebetween are provided over the same substrate. One of the transistors uses a single-crystal semiconductor layer as an active layer, to which tensile strain is applied. The other transistors use single-crystal semiconductor layers as active layers, to which compressive strain using part of heat shrink generated by heat treatment of the base substrate after bonding is applied. | 2011-06-02 |
20110129988 | METHOD OF MAKING MULTIPLE IMPLANTATIONS IN A SUBSTRATE - A method of implanting atoms and/or ions into a substrate, including: a) a first implantation of ions or atoms at a first depth in the substrate, to form a first implantation plane, b) at least one second implantation of ions or atoms at a second depth in the substrate, which is different from the first depth, to form at least one second implantation plane. | 2011-06-02 |
20110129989 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND DEVICE FOR SAME - Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. | 2011-06-02 |
20110129990 | METHOD FOR DOPING NON-PLANAR TRANSISTORS - Methods for doping a non-planar structure by forming a conformal doped silicon glass layer on the non-planar structure are disclosed. A substrate having the non-planar structure formed thereon is positioned in chemical vapor deposition process chamber to deposit a conformal SACVD layer of doped glass (e.g. BSG or PSG). The substrate is then exposed to RTP or laser anneal step to diffuse the dopant into the non-planar structure and the doped glass layer is then removed by etching. | 2011-06-02 |
20110129991 | Methods Of Patterning Materials, And Methods Of Forming Memory Cells - Some embodiments include methods of patterning materials. A mass may be formed over a material, and a first mask may be formed over the mass. First spacers may be formed along features of the first mask, and then the first mask may be removed to leave a second mask corresponding to the first spacers. A pattern of the second mask may be partially transferred into the mass to form an upper portion of the mass into a third mask. The first spacers may be removed from over the third mask, and then second spacers be formed along features of the third mask. The second spacers are a fourth mask. A pattern of the fourth mask may be transferred into a bottom portion of the mass, and then the bottom portion may be used as a mask during processing of the underlying material. | 2011-06-02 |
20110129992 | METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE - A method for fabricating a vertical channel type non-volatile memory device includes repeatedly forming stacks of conductive layers and inter-layer insulation layers over a substrate, and performing an etch process using an etch gas which etches both the conductive layers and the inter-layer insulation layers to form a contact hole exposing the substrate, wherein the etch gas maintains a selectivity between the inter-layer insulation layers and the conductive layers with a ratio of different etching rates ranging from approximately 0.1 to approximately 2. | 2011-06-02 |
20110129993 | Semiconductor device and inspection method therefor - A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block. | 2011-06-02 |
20110129994 | Method of manufacturing a dual face package - A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate. | 2011-06-02 |
20110129995 | MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION - A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated. | 2011-06-02 |
20110129996 | THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER - A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer. | 2011-06-02 |
20110129997 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the present invention includes the following step: a step (S | 2011-06-02 |
20110129998 | CLEANING LIQUID FOR LITHOGRAPHY AND METHOD FOR FORMING WIRING - Provided are a cleaning liquid for lithography that exhibits excellent corrosion suppression performance in relation to tungsten, and excellent removal performance in relation to a resist film or the like, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for lithography according to the present invention includes a quaternary ammonium hydroxide, a water-soluble organic solvent, water, an inorganic salt and an anti-corrosion agent represented by a general formula (1) below. | 2011-06-02 |
20110129999 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device including: an electrode formation step of forming an electrode on one surface of a semiconductor substrate; a through hole formation step of forming a through hole starting from a position on the other surface corresponding to the position of the electrode; a first insulating layer formation step of forming a first insulating layer on at least an inner circumferential surface, a periphery of an opening, and a bottom surface of the through hole; a modifying step of reforming a first portion of the first insulating layer formed on the bottom surface of the through hole; a modified region removal step of removing the modified region; and a conductive layer formation step of forming a conductive layer on the electrode exposed inside the through hole and on the first insulating layer such that the conductive layer is electrically connected with the electrode. | 2011-06-02 |
20110130000 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING COMPOSITIONS FOR ETCHING COPPER - A method of manufacturing a semiconductor device includes preparing a substrate on which a fuze line containing copper is formed. The method further includes cutting the fuze line by emitting a laser beam, and applying a composition for etching copper to the substrate to finely etch a cutting area of the fuze line and to substantially remove at least one of a copper residue and a copper oxide residue remaining near the cutting area. The composition for etching copper includes about 0.01 to about 10 percent by weight of an organic acid, about 0.01 to 1.0 percent by weight of an oxidizing agent, and a protic solvent. | 2011-06-02 |
20110130001 | Substrate Processing Apparatus - A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube. | 2011-06-02 |
20110130002 | Methods and Apparatus for Edge Chamfering of Semiconductor Wafers Using Chemical Mechanical Polishing - Methods and apparatus for processing edge portions of a donor semiconductor wafer include controlling chemical mechanical polishing parameters to achieve chamfering of the edges of the donor semiconductor wafer; and alternatively or additionally flexing the donor semiconductor wafer to present a concave configuration, where edge portions thereof are pronounced as compared to a central surface area thereof, such that the pronounced edge portions of the donor semiconductor wafer are preferentially polished against a polishing surface in order to achieve the chamfering. | 2011-06-02 |
20110130003 | METHOD AND APPARATUS FOR CONFORMABLE POLISHING - Methods and apparatus provide for a conformable polishing head for uniformly polishing a workpiece. The polishing head includes an elastic polishing pad mounted on an elastic membrane that seals a cavity in the polishing head. The cavity is pressurized to expand the membrane and press the polishing pad down on the top surface of the workpiece, such that the polishing pad conforms to the surface and applies a substantially uniform pressure distribution across the workpiece and thereby uniformly removes material across high and low spots on the workpiece. | 2011-06-02 |
20110130004 | METHOD FOR FORMING SIDE CONTACT IN SEMICONDUCTOR DEVICE THROUGH SELF-ALIGNED DAMASCENE PROCESS - A method for fabricating a semiconductor device includes forming a plurality of active regions, each having a first sidewall and a second sidewall, by etching a semiconductor substrate, forming an insulation layer on the first sidewall and the second sidewall, forming an etch stop layer filling a portion of each gap between the active regions, forming a recess exposing the insulation layer formed on any one sidewall from among the first sidewall and the second sidewall, and forming a side contact exposing a portion of any one sidewall from among the first sidewall and the second sidewall by selectively removing a portion of the insulation layer. | 2011-06-02 |
20110130005 | PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY - A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy. | 2011-06-02 |
20110130006 | MASK MATERIAL CONVERSION - The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation. | 2011-06-02 |
20110130007 | IN-SITU CLEAN TO REDUCE METAL RESIDUES AFTER ETCHING TITANIUM NITRIDE - Methods of processing substrates having titanium nitride layers are provided. In some embodiments, a method for processing a substrate having a dielectric layer to be etched, a titanium nitride layer above the dielectric layer, and a patterned photoresist layer above the titanium nitride layer, includes etching a pattern into the titanium nitride layer by exposing the titanium nitride layer to a first plasma comprising a chlorine containing gas to form a hard mask; removing titanium nitride etch residues disposed on one or more surfaces of the process chamber and/or substrate by forming a second plasma in the process chamber from a reactive gas comprising at least one of carbon monoxide or carbon dioxide; and etching the dielectric layer through the hard mask with a third plasma comprising a fluorocarbon gas. | 2011-06-02 |
20110130008 | METHOD TO CONTROL CRITICAL DIMENSION - A method to control a critical dimension is disclosed. First, a material layer and a composite patterned layer covering the material layer are provided. The composite patterned layer has a pattern defining a first critical dimension. Later, an etching gas is used to perform an etching step to etch the composite patterned layer and a pattern-transferring step is carried out so that thereby the underlying material layer has a transferred pattern with a second critical dimension which is substantially smaller than the first critical dimension. | 2011-06-02 |
20110130009 | METHOD AND APPARATUS FOR SURFACE TREATMENT USING A MIXTURE OF ACID AND OXIDIZING GAS - Improved removal of ion-implanted photoresist in a single wafer front-end wet processing station is achieved by combining gaseous ozone and heated sulfuric acid such that a gas/liquid dispersion or foam of ozone in sulfuric acid is applied in a layer to the wafer surface to be treated. | 2011-06-02 |
20110130010 | ETCHING AND CLEANING METHODS AND ETCHING AND CLEANING APPARATUSES USED THEREFOR - A method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a device area, an end face, and a surface peripheral area located outside the device area and between the end face and the device area. Forming a Cu layer on the semiconductor wafer and rotating the wafer in a horizontal plane. Emitting a first liquid from an edge nozzle towards the surface peripheral area which selectively removes a first unnecessary material in the surface peripheral area. Emitting a protecting liquid toward the semiconductor wafer, thereby protecting the device area from the first liquid. An angle of a longitudinal axis of the edge nozzle with respect to a tangent of the semiconductor wafer at a point, where the longitudinal axis of the edge nozzle intersects the end face of the wafer, is set in the range of 0 to 90 degrees in plan view. | 2011-06-02 |
20110130011 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, AND SUBSTRATE PROCESSING APPARATUS - Provided is a method of manufacturing a semiconductor device. The method includes: (a) forming an oxide film having a predetermined thickness on a substrate by alternately repeating: (a-1) forming a layer containing a predetermined element on the substrate by supplying a source gas containing the predetermined element into a process vessel accommodating the substrate and exhausting the source gas from the process vessel; and (a-2) changing the layer containing the predetermined element into an oxide layer by supplying an oxygen-containing gas and an hydrogen-containing gas into the process vessel, wherein inside of the process vessel is under a heated atmosphere having a pressure lower than an atmospheric pressure; and exhausting the oxygen-containing gas and the hydrogen-containing gas from the process vessel; and (b) modifying the oxide film formed on the substrate by supplying the oxygen-containing gas and the hydrogen-containing gas into the process vessel, wherein the inside of the process vessel is under the heated atmosphere having the pressure lower than the atmospheric pressure, and exhausting the oxygen-containing gas and the hydrogen-containing gas from the process vessel. | 2011-06-02 |
20110130012 | RAPID THERMAL PROCESSING BY STAMPING - A rapid thermal processing device and methods are provided for thermal processing of samples such as semiconductor wafers. The device has components including a stamp ( | 2011-06-02 |
20110130013 | Substrate processing method and semiconductor device manufacturing method - A substrate processing method and a semiconductor device manufacturing method in which a stained part does not remain in a finished product even if a residual ion-injected part stays in the finished product. | 2011-06-02 |
20110130014 | ELECTRICAL CONNECTOR WITH IMPROVED CONTACTS ARRANGEMENT - An electrical connector ( | 2011-06-02 |
20110130015 | External Quick Connect Modular Plug for a Wiring Device - The modular electrical wiring device includes an electrical wiring device and an external plug that is electrically coupled by one or more wires to the wiring device. The modular plug is releasably coupled to a connector in a male-female relationship. Both the modular plug and connector include internal contacts for electrically coupling one to the other. The connector is electrically coupled to and directly terminates one or more building wires, which are used to provide power to one or more of the wiring devices. The external plug is removably coupled to the connector to provide electrical power to the wiring device by establishing and electrical pathway from a source of electrical power, through the building wires, the connector and the modular plug to the wiring device. | 2011-06-02 |
20110130016 | External Quick Connect Modular Plug for a Wiring Device - The modular electrical wiring device includes an electrical wiring device and an external plug that is electrically coupled by one or more wires to the wiring device. The modular plug is releasably coupled to a connector in a male-female relationship. Both the modular plug and connector include internal contacts for electrically coupling one to the other. The connector is electrically coupled to and terminates one or more building wires, which are used to provide power to one or more of the wiring devices. The external plug is removably coupled to the connector to provide electrical power to the wiring device by establishing and electrical pathway from a source of electrical power, through the building wires, the connector and the modular plug to the wiring device. | 2011-06-02 |
20110130017 | FLASH MEMORY DEVICE WITH SLIDABLE CONTACT MODULE - A flash memory device includes a circuit board and a contact module slidable with respect to the circuit board. The circuit board includes a plurality of first contacts each having a stiff first contact portion. The contact module includes a slider and a plurality of second contacts fixed to the slider. The slider is slidable with respect to the circuit board along a front-to-rear direction between a first position and a second position. The flash memory device is compatible to USB 2.0 and USB 3.0 receptacle connectors via the slidable contact module. | 2011-06-02 |
20110130018 | DATA CARD WITH ROTATABLE CONNECTOR AND ROTATABLE CONNECTOR FOR DATA CARD - In the field of data cards with a rotatable external port, a data card with a rotatable connector and a rotatable connector for a data card are provided. The data card with a rotatable connector includes a data card body and a rotatable connector, where the rotatable connector includes an external port for connecting with an external device, and the rotatable connector is rotatably connected with the data card body. The data card further includes an antenna set in the rotatable connector. The rotatable connector for a data card includes a rotatable connector body and an external port for connecting with an external device, and includes an antenna therein. Through setting the antenna in the rotatable connector, no matter what angle the data card is rotated, the antenna is always maintained in the same state, so that the antenna can be modulated in advance, so as to eliminate the interference on the performance of the antenna caused by the external device, and ensures stable performance of the antenna. | 2011-06-02 |
20110130019 | ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector comprises a dielectric body, a plurality of terminals, and a metal shell. The dielectric body includes a base and a tongue. The tongue extends forward from the base and supports the plurality of terminals. The metal shell is integrally formed around the dielectric body, and can be formed by bending a metal plate, and includes a top wall, a bottom wall opposite to the top wall, a first side wall, and a second side wall, the four walls defining a rectangular opening. The first side wall includes a lower wall portion and an upper wall portion, both of which are joined at a seam on the first side wall. The lower wall portion has a lower solder leg and the upper wall portion has an upper solder leg and the lower and upper solder legs can be soldered to the circuit board. | 2011-06-02 |
20110130020 | SUBMERSIBLE POTHEAD SYSTEM FOR USE IN A WELL APPLICATION - A technique enables protection of electrical conductors in a submerged environment, such as a wellbore environment. A connector system is deployed at the end of an electric cable to enable connection of the electric cable with a submersible component. The connector system comprises a connector body formed of a moldable material that is molded around at least one conductor of the electric cable. The moldable material insulates and protects the at least one conductor when the connector body is engaged with the submersible component. | 2011-06-02 |
20110130021 | CONNECTION STRUCTURE - A connection structure includes a male terminal housing with first connecting terminals, a female terminal housing with second connecting terminals, isolating plates in the male terminal housing, a connecting member to thereby collectively fix the first connecting terminals and the second connecting terminals at the contacts therebetween for electrical connections between the first connecting terminals and the second connecting terminals, and manipulation permitting means for permitting manipulation of the connecting member for collectively fixing the first connecting terminals and the second connecting terminals at the contacts therebetween respectively, when the male terminal housing and the female terminal housing are mated with each other in a specified mated state. | 2011-06-02 |
20110130022 | CONNECTION STRUCTURE - A connection structure includes a first terminal housing with first connecting terminals, a second terminal housing with second connecting terminals, isolating plates in the first terminal housing, a connecting member to collectively fix the first connecting terminals and the second connecting terminals at the contacts therebetween for electrical connections between the first connecting terminals and the second connecting terminals. The connecting member further includes a metallic elastic member disposed between the head and the isolating plate adjacent to the head to sequentially press the isolating plates in a stacking direction. The isolating plate adjacent to the head includes a recessed portion formed in a surface to contact the elastic member for accommodating one end of the elastic member pressing the isolating plate adjacent to the head. | 2011-06-02 |
20110130023 | Connection structure for a vehicle - A connector has a first terminal housing with first connecting terminals aligned and accommodated therein, a second terminal housing with second connecting terminals aligned and accommodated therein, isolating plates and a connecting member. Each of the first connecting terminals and each of the second connecting terminals are surface-roughened such that a surface facing to other connecting terminal and composing a contact with the other connecting terminal provides a first frictional coefficient. When each of the isolating plates is adjacent to each of the first connecting terminals, each of the isolating plates is integrally fixed to each of the first connecting terminals, and when each of the isolating plates is adjacent to each of the second connecting terminals, each surface of the isolating plates facing to each of the second connecting terminals is surface-roughened to provide a second frictional coefficient. | 2011-06-02 |
20110130024 | KEYLESS HARSH ENVIRONMENT CONNECTOR - A keyless harsh environment connector has a plug unit containing a pin having an outer surface carrying a plurality of axially spaced, annular contacts of gradually decreasing diameter towards a forward end of the pin, and a receptacle unit having a fluid-filled chamber containing a corresponding number of axially spaced, annular contacts of gradually increasing diameter towards a forward end of the receptacle unit, configured for mating engagement with corresponding contacts on the plug pin when the units are mated. A sealing mechanism at a forward end of the chamber seals the chamber when the units are unmated and forms a seal with the plug pin on mating of the units. The plug pin is hollow and extends through an interface between opposing seals at the front end of the receptacle contact chamber during mating. | 2011-06-02 |
20110130025 | CONNECTOR WITH INTERNALLY ACTUATED THREAD SEAL - A novel, reliable, moisture migration preventing cable connector for non-standard port attachment is provided. Such a connector device includes a deformable sealing element that is clear of mating port threads during connector attachment to a cable port, but that deforms upon actuation of a mated thread device rotated around the connector subsequent to cable port attachment. Such deformation allows for the sealing element to enter the open areas of the mated threads thereby preventing the migration of moisture into the cable connector, protecting not only the connector threads, but also the mating port, as well as the internal dielectric and center conductor of the cable itself. A method of providing a signal connection and transfer in a cable system is also encompassed within this invention. | 2011-06-02 |
20110130026 | LEVER-TYPE CONNECTOR - If connection postures of a first and a second housings ( | 2011-06-02 |
20110130027 | SERVER SYSTEM AND SERVER SUITABLE FOR USE IN THE SERVER SYSTEM AND SUITABLE CONNECTION MODULE - A server system includes a server frame with a first side and a second side for insertion of at least one server from the first side of the server frame, at least one connection module for the connection of the at least one server inserted into the server frame from the second side of the server frame opposite the first side, wherein the at least one connection module is arranged transversely with respect to the at least one server, at least one plug connector provided for the server, and at least one additional plug connector provided for the connection module in such a manner that a direct connection between the connection module and the server is produced by the plug connector of the server and the plug connector of the connection module. | 2011-06-02 |
20110130028 | CONNECTION STRUCTURE - A connection structure includes a first terminal housing with first connecting terminals, a second terminal housing with second connecting terminals, isolating plates in the first terminal housing, a connecting member to collectively fix the first connecting terminals and the second connecting terminals at the contacts therebetween for electrical connections between the first connecting terminals and the second connecting terminals. The connection structure is adapted to heat generated at the contacts through the connecting member, the first terminal housing and/or the second terminal housing to an outside of the first terminal housing. | 2011-06-02 |
20110130029 | CARD CONNECTOR - The card connector in which a card receiving space for containing at least a part of a small card incorporating an integrated circuit is formed by a cover member having at least a top board and right and left side walls and a base member having at least a bottom wall, a front wall, and right and left side walls, the card connector includes: a plurality of contacts penetrating the front wall of the base member and being elastically deformably supported by the base member; and a heat dissipating mechanism located behind the plurality of contacts and elastically deformably supported by the base member. The heat dissipating mechanism includes at least one heat dissipating piece having a free end at one end. The heat dissipating mechanism is disposed at a cutoff portion formed at the bottom wall of the base member. | 2011-06-02 |
20110130030 | FLAT CABLE CONNECTOR, HARNESS, AND METHOD FOR MANUFACTURING HARNESS - A body housing supports a plurality of terminals, and an end of a flat cable that includes a conductor-exposed portion is disposed in the body housing. The cover housing is attached to the body housing, and holds the plurality of terminals and a plurality of conductors so as to be sandwiched between the body housing and the cover housing. The terminals are provided with a raised portion that is formed such that a portion of the terminals protrudes, and the plurality of terminals and the plurality of conductors in the conductor-exposed portion are respectively welded together by performing resistance welding with the terminals and the conductors abutting against each other via the raised portion. This enables welding to be performed with a small current with regard to resistance welding of the plurality of terminals of the flat cable connector and the plurality of conductors of the flat cable, thus reducing power consumption during welding, and can also achieve stable welding quality. | 2011-06-02 |
20110130031 | CORD ORGANIZER DEVICE AND METHOD OF USE - The present invention is a cord organizer device that includes a horizontal base surface, spools to receive and control one or more power cords from one or more electrical devices, a plate with a distal end disposed on the top of the spools to label the spools and the power cords, holding clips that are disposed on the sides of the spools to secure the power cords against the horizontal base surface. There is also a cover that is disposed over the spools, the plates and the holding clips to protect and to hide the spools, the plates and the holding clips, a power strip to provide power to the device that is secured by a fastener to the horizontal base surface and a mounting hole to mount the device against a vertical surface. | 2011-06-02 |
20110130032 | ACTIVE COPPER CABLE EXTENDER - Methods and apparatus for reducing distortion in signals propagating through cables at data rates of at least 10 gigabits per second (Gbps) are provided. By connecting such direct attach cables with an active cable extender assembly described herein, data signals may be reshaped, retimed, and/or emphasized in an effort to increase the cable length between network devices while still complying with the signal quality requirements of communication standards, such as the SFF-8431 MSA, the SFF-8461 MSA, and the IEEE 802.3ba CR4/10 standards for Ethernet communications. Copper cable solutions with such increased cable length possible between network devices may provide substantial cost reduction when compared to optical cable solutions. Furthermore, by potentially increasing the signal quality effectively transmitted by a host, solutions utilizing embodiments of the present invention may guarantee host-to-host interoperability. | 2011-06-02 |
20110130033 | CONNECTOR SYSTEM AND SHORTING MEMBER - A connector system includes a first connector and a mating second connector. The first connector includes a housing, at least a first terminal and a plurality of further terminals. The second connector includes a housing, at least a second terminal configured for mating at least with the first terminal of the first connector. The second connector further includes at least one shorting member configured for interconnecting at least one set of at least two further terminals of the first connector. | 2011-06-02 |
20110130034 | COAXIAL CONNECTOR WITH INTEGRATED MOLDED SUBSTRATE AND METHOD OF USE THEREOF - A substrate structure is provided, the substrate structure comprising: a molded substrate located within a connector body of a coaxial cable connector and an electrical structure mechanically connected to the molded substrate. The electrical structure is located in a position that is external to a signal path of a radio frequency (RF) signal flowing through the coaxial cable connector. | 2011-06-02 |
20110130035 | CONNECTOR - A connector that has a high waterproof property, and can be easily assembled. A housing is formed with a through hole for accommodating a contact which is connected to a cable. An elastic sealing member that has a hollow cylindrical shape and is fitted on an outer peripheral surface of the cable is accommodated in a rear portion of the through hole, and an urging member having a hollow cylindrical shape is fitted on an outer peripheral surface of the housing. The urging member is formed with a tapered surface for urging a rear end of the elastic sealing member against the outer peripheral surface of the cable when the urging member is fitted on the outer peripheral surface of the housing. | 2011-06-02 |
20110130036 | ASSEMBLED ELECTRICAL CONNECTOR - The invention discloses an assembled electrical connector, which comprises an insulating housing and at least two sets of electrical conducting terminals. The insulating housing has a main body, a first tongue and a second tongue extending from the main body and perpendicular to the main body, wherein the first tongue is longer than the second tongue, and the second tongue is located at a side of the first tongue in a lengthwise direction. The at least two sets of electrical conducting terminals comprise a first terminal set and a second terminal set, wherein the first terminal set is arranged at a side of the first tongue, and the second terminal set is arranged at a side of the second tongue. Compared with prior art, such a structure can miniaturize the volume of the electrical connector apparently and further miniaturize the volume of an electronic product utilizing the electrical connector. | 2011-06-02 |
20110130037 | CAMERA MODULE SOCKET - A camera module socket for receiving a camera module which plates a metal coating around an outer periphery thereof includes an insulating housing defining a receiving chamber for receiving a lower portion of the camera module, a plurality of conductive terminals received in the insulating housing, a metallic shell encircling the insulating housing, and a shielding cover. The shielding cover has top board which defines a through hole at a middle thereof for allowing a top portion of the camera module exposed therefrom, and a plurality of side boards extended downwardly from side edges of the top board. The shielding cover has at least one elastic arm bent into an inner thereof from the corresponding side board for elastically abutting against the camera module and electrically connected with the metal coating, and at least one resistant tab formed at the corresponding side board for pressing against metallic shell. | 2011-06-02 |