23rd week of 2015 patent applcation highlights part 51 |
Patent application number | Title | Published |
20150155194 | METHOD OF PREPARING HETEROGENEOUS STACKED CO-FIRED CERAMIC FOR USE IN AN ALUMINUM NITRIDE ELECTROSTATIC CHUCK - A method of preparing a heterogeneous stacked co-fired ceramic for use in an aluminum nitride-based electrostatic chuck includes providing a first aluminum nitride blank layer; applying a metal ink to the first aluminum nitride blank layer to form thereon an electrostatic electrode layer by screen printing, wherein the metal ink mainly contains a metal of high melting point; stacking a second aluminum nitride blank layer on the electrostatic electrode layer; laminating the first aluminum nitride blank layer, the electrostatic electrode layer, and the second aluminum nitride blank layer (collectively known as a heterogeneous ceramic) together; and co-firing the laminated heterogeneous ceramic in accordance with a sintering temperature rising curve to prepare the heterogeneous stacked co-fired ceramic characterized by reduced differences in sintering shrinkage ratio between the electrostatic electrode and aluminum nitride blank and enhanced strength and adhesion of the interface between the electrostatic electrode and aluminum nitride blank. | 2015-06-04 |
20150155195 | Wafer Taping Scheme - A method includes setting a first tension value of a laminating tape during a standby mode. A second tension value of the laminating tape is set during taping on a wafer. The second tension value is different from the first tension value. A third tension value of the laminating tape is set after taping. The third tension value is different from the second tension value. | 2015-06-04 |
20150155196 | Transfer Module for Bowed Wafers - A wafer grinding system includes a robot arm having a suction board at one end and a table within reach of the robot arm. An upper surface of the table has a vacuum surface for sucking and holding wafers. A pusher coupled to the robot arm extends about the periphery of the suction board. The pusher flattens wafers against the upper surface of the table, allowing the table to hold by suction wafers that would otherwise be too bowed to be held in that way. Additionally, a table can have a vacuum area that is small in comparison to the wafers, which is another way of increasing the magnitude of wafer bow that can be tolerated. A grinding system can use the reduced vacuum area concept to allow the positioning table to hold bowed wafers and the pusher concept to allow the chuck tables to hold bowed wafers. | 2015-06-04 |
20150155197 | COATING FILM FORMING APPARATUS, COATING FILM FORMING METHOD, AND STORAGE MEDIUM - A coating film forming apparatus includes a substrate holding unit, a ring-shaped member annularly installed along a circumferential direction of the substrate so as to cover an upper side of a peripheral edge portion of the substrate, and a control unit that outputs a control signal so as to perform: positioning the ring-shaped member at a processing position where an air flow flowing above the peripheral edge portion of the substrate is straightened; rotating the substrate at a first revolution number such that a coating liquid supplied to a central portion of the substrate is diffused toward the peripheral edge portion by a centrifugal force; bringing the ring-shaped member to a retreated position where an air flow flowing near a front surface of the substrate is prevented from becoming turbulent; and reducing the revolution number of the substrate to a second revolution number lower than the first revolution number. | 2015-06-04 |
20150155198 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask. | 2015-06-04 |
20150155199 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips. | 2015-06-04 |
20150155200 | Process For Forming And Composite Comprising Conducting Paths Comprising Silver - The invention relates generally to a process ( | 2015-06-04 |
20150155201 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - Provided is a substrate processing apparatus including a substrate processing chamber configured to process a substrate; a gas supply unit configured to alternately supply a first processing gas and a second processing gas to the substrate when processing the substrate; a substrate support unit including a support mechanism configured to support a portion of a back side of the substrate and a support unit configured to support the support mechanism; a heating unit configured to heat the substrate from the back side thereof; a standby chamber configured to accommodate the substrate support unit in standby position; and a control unit configured to control at least one of the gas supply unit and a gas exhaust unit in a manner that an inner pressure of the substrate processing chamber is higher than that of the standby chamber. | 2015-06-04 |
20150155202 | POWER/GROUND LAYOUT FOR CHIPS - Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip. | 2015-06-04 |
20150155203 | POP Structures and Methods of Forming the Same - A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line. | 2015-06-04 |
20150155204 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 2015-06-04 |
20150155205 | PROCESSING METHOD FOR PACKAGE SUBSTRATE - A processing method for a package substrate composed of a substrate, a plurality of device chips mounted on the substrate in a plurality of separate device regions defined by a plurality of crossing division lines, and a sealing layer for sealing the device chips. The processing method includes a cut mark forming step of moving a cutting blade to cut into the package substrate from the side of the substrate in the regions other than the device regions to the depth passing through the sealing layer, thereby forming a cut mark having a predetermined positional relation to the division lines, and a cutting step of cutting the package substrate from the side of the sealing layer along the division lines by using the cutting blade according to the cut mark after performing the cut mark forming step. | 2015-06-04 |
20150155206 | METHOD OF IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE - A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor. | 2015-06-04 |
20150155207 | CMOS CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant. | 2015-06-04 |
20150155208 | Control Fin Heights in FinFET Structures - A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region | 2015-06-04 |
20150155209 | METHOD FOR GENERATING DIE IDENTIFICATION BY MEASURING WHETHER CIRCUIT IS ESTABLISHED IN A PACKAGE STRUCTURE - A package structure is disclosed. The package structure includes a die; a substrate disposed corresponding to the die, wherein the substrate comprises a first dummy pad and a second dummy pad on a first surface of the substrate; and a first solder ball and a second solder ball on a second surface of the substrate and electrically connect the first dummy pad and the second dummy pad respectively. | 2015-06-04 |
20150155210 | SEMICONDUCTOR MANUFACTURING APPARATUSES AND METHODS THEREOF - A semiconductor manufacturing apparatus may include: a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus; a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; and/or an optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region. A semiconductor manufacturing apparatus may include: a bonding head including a heater for heating a chip and bonding the chip onto a circuit board; and/or a cooling block, adjacent to the heater, through which cooling liquid flows. The cooling liquid may be removed from the cooling block while the heater generates heat. The cooling liquid may be supplied to the cooling block while the heater is cooled. | 2015-06-04 |
20150155211 | SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS - A bonding machine for bonding semiconductor elements, the bonding machine including: a support structure for supporting a substrate; a bond head assembly, the bond head assembly including a bonding tool configured to bond a plurality of semiconductor elements to the substrate; an alignment structure including first alignment markings; an alignment element configured to be placed on the alignment structure using the bonding tool, the alignment element including second alignment markings; an imaging system configured to image relative positions of the first alignment markings and corresponding ones of the second alignment markings; and a computer system configured to provide an adjustment to a position of at least one of the bonding tool and the support structure during bonding of ones of the plurality of semiconductor elements to the substrate, the computer being configured to provide the adjustment at least partially based on the relative positions of the first alignment markings and the corresponding ones of the second alignment markings, the adjustment being specific to bonding of the ones of the plurality of semiconductor elements to a corresponding region of the substrate. | 2015-06-04 |
20150155212 | DISPLAY DEVICE AND MANUFACTURING AND TESTING METHODS THEREOF - A display device is disclosed which includes: gate lines and data lines crossing each other to define unit pixel regions in a display area; a pixel electrode in each unit pixel region; a data shorting bar in a non-display area in substantially parallel with the gate lines; a gate shorting bar in the non-display area in substantially parallel with the data lines; gate link lines electrically connecting the gate lines to the gate shorting bar; data link lines electrically connecting the data lines to the data shorting bar; and shield electrodes on at least one of the gate link lines and the data link lines, the shield electrodes including a conductive material that has a higher melting temperature than that of the at least one of the gate link lines and the data link lines. | 2015-06-04 |
20150155213 | Chip Detecting System and Detecting Method - A chip detecting system is disclosed. The system includes a ball grid array (BGA) chip and a circuit board, the BGA chip includes at least two functional pins being located at a corner of the BGA chip, the at least two functional pins are electrically connected to each other, the circuit board is provided with at least two solder pads and at least two testing pads, the at least two functional pins are electrically connected to the at least two solder pads by using solder balls separately, the solder pads are electrically connected to the testing pads separately, and the at least two testing pads are configured to electrically connect to a detector, so as to detect whether a crack exists between the at least two functional pins and the circuit board. | 2015-06-04 |
20150155214 | Multi-Layer Substrate For Semiconductor Packaging - The present invention provides a semiconductor substrate ( | 2015-06-04 |
20150155215 | ELECTRONIC DEVICE WITH FIRST AND SECOND CONTACT PADS AND RELATED METHODS - An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads. | 2015-06-04 |
20150155216 | SEMICONDUCTOR CHIP AND METHOD OF FORMING THE SAME - A semiconductor chip comprising: a substrate; a plurality of pads disposed on the substrate; and a plurality of passivation patterns laterally separated from each other on the substrate, each of the passivation patterns including a plurality of openings, the openings exposing at least one pad of the pads, and the passivation patterns having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate. | 2015-06-04 |
20150155217 | SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device package may comprise: a semiconductor chip element; and/or a supporting structure on which the semiconductor chip element is mounted and comprising an electrical connection element for connecting the semiconductor chip element to an external terminal. The supporting structure may comprise: a first lead frame comprising a heat dissipation element; a second lead frame coupled to the first lead frame; and/or an insulator configured to electrically insulate the first and second lead frames. Each of the first and second lead frames may comprise a mounting region on which the semiconductor chip element is mounted. | 2015-06-04 |
20150155218 | 3DIC Packaging with Hot Spot Thermal Management Features - A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material. | 2015-06-04 |
20150155219 | BACKPLANE FOR DISPLAY DEVICE, AND DISPLAY DEVICE INCLUDING THE SAME - A backplane for a display device and the display device are disclosed. In one aspect, the backplane includes a substrate, an active layer formed over the substrate including a channel region, a source region contacting a first side of the channel region, and a drain region contacting a second side of the channel region. The backplane further includes a gate electrode formed adjacent to the channel region, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. The active layer includes a plurality of heat radiation pins that extend in a direction of the thickness of the active layer. | 2015-06-04 |
20150155220 | THERMALLY INSULATIVE COMPOSITION AND ELECTRONIC DEVICES ASSEMBLED THEREWITH - Provided herein is a thermally insulative composition, which is particularly useful to assemble electronic devices. | 2015-06-04 |
20150155221 | ADHESIVE PATTERN FOR ADVANCE PACKAGE RELIABILITY IMPROVEMENT - The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die. | 2015-06-04 |
20150155222 | SEMICONDUCTOR DIE HAVING IMPROVED THERMAL PERFORMANCE - A semiconductor die having improved thermal performance is disclosed. The semiconductor die includes a substrate having a device layer with a plurality of vias that pass through the substrate and the device layer, wherein individual ones of the plurality of vias have an open space volume of less than around about 70,000 cubic micrometers to around about 20,000 cubic micrometers. In at least one embodiment, the substrate of the semiconductor die is made of silicon carbide (SiC) and the device layer is made of gallium nitride (GaN). | 2015-06-04 |
20150155223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening. | 2015-06-04 |
20150155224 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first metal layer, a barrier metal layer, and a second metal layer. The semiconductor substrate includes a front surface and a back surface. A semiconductor element and an electrode of the semiconductor element are located on the front surface. An opening in the back surface reaches a lower surface of the electrode, and the opening is defined by a side surface and a bottom surface. The first metal layer covers the side surface and the bottom surface. The barrier metal layer covers the first metal layer in the opening The second metal layer is in contact with solder in the opening and is closer to the electrode than parts of the barrier metal layer. The second metal layer is laminated on the barrier metal layer and covers at least a part of the barrier metal layer in the opening | 2015-06-04 |
20150155225 | SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP - A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires. | 2015-06-04 |
20150155226 | MICROELECTRONIC FLIP CHIP PACKAGES WITH SOLDER WETTING PADS AND ASSOCIATED METHODS OF MANUFACTURING - Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non- attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame. | 2015-06-04 |
20150155227 | SEMICONDUCTOR DEVICE - In a multichip thin package requiring a thickness of submillimeter region, it is difficult to thin the package if the chips are mounted over a usual die pad. According to a technique of the present application, in a manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed. | 2015-06-04 |
20150155228 | POWER MODULE AND METHOD FOR MANUFACTURING THE SAME - A power module includes one control IC and a plurality of reverse conducting insulated gate bipolar transistors (RC-IGBTs). The control IC has the functions of a high-voltage IC and a low-voltage IC. The plurality of RC-IGBTs are disposed on three of four sides of the control IC and connected to the control IC through only wires. | 2015-06-04 |
20150155229 | Leadless Semiconductor Package with Optical Inspection Feature - A semiconductor package includes a plurality of bond pads having a first side and a second side opposing the first side, a coating covering the first side of the bond pads, semiconductor dies and electrical conductors attached to the second side of the bond pads, and a molding compound encasing the semiconductor dies and the electrical conductors at the second side of the bonds pads. The molding compound has a first side through which the bond pads protrude and a second side opposing the first side, the first side of the molding compound having a planar surface between adjacent ones of the bond pads. The package further includes a material plated on exposed sidewalls of the bonds pads uncovered by the molding compound and which is detectable by optical inspection. A corresponding method of manufacture is also provided. | 2015-06-04 |
20150155230 | CARRIER-LESS SILICON INTERPOSER USING PHOTO PATTERNED POLYMER AS SUBSTRATE - A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component. | 2015-06-04 |
20150155231 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET. | 2015-06-04 |
20150155232 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines. | 2015-06-04 |
20150155233 | SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME - The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole. | 2015-06-04 |
20150155234 | Interconnect Structure and Method for Forming the Same - Interconnect structures and methods for forming the same are described. A method for forming an interconnect structure may include: forming a low-k dielectric layer over a substrate; forming an opening in the low-k dielectric layer; forming a conductor in the opening; forming a capping layer over the conductor; and forming an etch stop layer over the capping layer and the low-k dielectric layer, wherein the etch stop layer has a dielectric constant ranging from about 5.7 to about 6.8. | 2015-06-04 |
20150155235 | ANTI-FUSE OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE AND SYSTEM EACH INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD FOR FORMING THE ANTI-FUSE - An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved. | 2015-06-04 |
20150155236 | STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 2015-06-04 |
20150155237 | POLYSILICON FUSE, SEMICONDUCTOR DEVICE HAVING POLYSILICON FUSE AND METHOD OF SEVERING POLYSILICON FUSE - In some aspects of the invention, a first polysilicon fuse section for forming a cavity is provided in close proximity to a second polysilicon fuse section for adjusting circuit characteristics. By forming a cavity with the first polysilicon fuse section made to be blown, fused polysilicon is contained in the cavity when the second polysilicon fuse section is blown to make it possible to provide a polysilicon fuse capable of stably maintaining an electrical insulated state. This can provide a polysilicon fuse capable of stably maintaining the electrical insulated state when the fuse is blown, a semiconductor device having the polysilicon fuse and a method of severing the polysilicon fuse. | 2015-06-04 |
20150155238 | MAKING AN EFUSE - A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask. | 2015-06-04 |
20150155239 | Metallic Interconnects Products - One embodiment is a semiconductor device including: at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom; at least one barrier layer disposed over the sidewalls and bottom; a first metallic layer disposed over the at least one barrier layer; a second metallic layer disposed over the first metallic layer; and a metallic filling layer disposed over the second metallic layer; wherein: the first metallic layer is continuous over the sidewalls and bottom, has a thickness in a range from about 10 Å to no more than 40 Å over a sidewall of the at least one opening; and the second metallic layer, and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys containing one or more of these metals. | 2015-06-04 |
20150155240 | METHOD FOR FABRICATING EMI SHIELDING PACKAGE STRUCTURE - An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques. | 2015-06-04 |
20150155241 | WARPAGE REDUCTION IN STRUCTURES WITH ELECTIRCAL CIRCUITRY - To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided. | 2015-06-04 |
20150155242 | INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate. | 2015-06-04 |
20150155243 | Warpage Control in Package-on-Package Structures - A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate. | 2015-06-04 |
20150155244 | GLASS COMPOSITION FOR PROTECTING SEMICONDUCTOR JUNCTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A glass composition for protecting a semiconductor junction is made of fine glass particles prepared from a material in a molten state obtained by melting a raw material which contains at least SiO | 2015-06-04 |
20150155245 | ELECTRICAL COMPONENT TESTING IN STACKED SEMICONDUCTOR ARRANGEMENT - A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component. | 2015-06-04 |
20150155246 | ESD PROTECTION DEVICE - An ESD protection device | 2015-06-04 |
20150155247 | BRIDGE STRUCTURE FOR EMBEDDING SEMICONDUCTOR DIE - A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A bridge structure is also mounted to the substrate, with the semiconductor die fitting within a trench formed in a bottom surface of the bridge structure. The bridge structure may be formed from a semiconductor wafer into either a dummy bridge structure functioning as a mechanical spacer layer, or an IC bridge structure functioning as both a mechanical spacer layer and an integrated circuit semiconductor die. Memory die may also be mounted atop the bridge structure. | 2015-06-04 |
20150155248 | Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor Package - A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief. | 2015-06-04 |
20150155249 | Solder Joint Structure for Ball Grid Array in Wafer Level Package - A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed. | 2015-06-04 |
20150155250 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a first dielectric layer having opposite first and second surfaces and a cavity penetrating the first and second surfaces; a first circuit layer embedded in the first dielectric layer and exposed from the first surface of the first dielectric layer; at least an adhesive member formed in the cavity and adjacent to the first surface of the first dielectric layer; an electronic element disposed on the adhesive member; a second dielectric layer formed on the second surface of the first dielectric layer and in the cavity to encapsulate the adhesive member and the electronic element; a second circuit layer formed on the second dielectric layer; and a plurality of conductive vias formed in the second dielectric layer for electrically connecting the second circuit layer and the electronic element, thereby reducing the package size and cost and increasing the wiring space and flexibility. | 2015-06-04 |
20150155251 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate. | 2015-06-04 |
20150155252 | ALUMINUM COATED COPPER BOND WIRE AND METHOD OF MAKING THE SAME - A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over the surface of the copper core. The ratio of the thickness of the coating layer to the diameter of the copper core is from 0.05 to 0.2 μm. The wire has a diameter in the range of from 100 μm to 600 μm and specified standard deviations of the diameter of the copper core and of the thickness of the coating layer. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding. | 2015-06-04 |
20150155253 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE - A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip. | 2015-06-04 |
20150155254 | SYSTEMS AND METHODS FOR DETERMINING AND ADJUSTING A LEVEL OF PARALLELISM RELATED TO BONDING OF SEMICONDUCTOR ELEMENTS - A bonding machine for bonding semiconductor elements, the bonding machine including: a support structure configured to support a substrate; a bond head assembly, the bond head assembly including a bonding tool configured to bond a plurality of semiconductor elements to the substrate; and a calibration tool including a contact portion configured to be positioned between the bonding tool and the support structure, the contact portion configured to be contacted by each of the bonding tool and the support structure simultaneously during a calibration operation. | 2015-06-04 |
20150155255 | SUBSTRATE BONDING AND BUMP FORMATION OF A SEMICONDUCTOR DEVICE - A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump. | 2015-06-04 |
20150155256 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor package with package-on-package stacking capability is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The interposer provides primary fan-out routing for the chip whereas dual buildup circuitries formed on both opposite sides of the base carrier provides further fan-out routing and are electrically connected to each other by plated through holes to provide the package with stacking capacity. | 2015-06-04 |
20150155257 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region. | 2015-06-04 |
20150155258 | METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE HAVING CONDUCTIVE BUMPS WITH A PLURALITY OF METAL LAYERS - A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate. | 2015-06-04 |
20150155259 | SUBSTRATE OF SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE USING THE SAME - A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier. | 2015-06-04 |
20150155260 | Temporary Bonding Scheme - A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer. | 2015-06-04 |
20150155261 | Chip separation process for photochemical component printing - Parallel transfers of components from donor plates to chip modules can be performed with a single alignment step, after arranging the components to have the correct lateral positions. For example, a dimension of the chip module can be separated to be an integer multiple of a period of the component array on the donor plates. | 2015-06-04 |
20150155262 | SEMICONDUCTOR PACKAGES INCLUDING A MULTI-LAYERED DIELECTRIC LAYER AND METHODS OF MANUFACTURING THE SAME - The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers. | 2015-06-04 |
20150155263 | FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING - A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith. | 2015-06-04 |
20150155264 | TECHNIQUES FOR ADHESIVE CONTROL BETWEEN A SUBSTRATE AND A DIE - Semiconductor devices are described that employ techniques configured to control adhesive application between a substrate and a die. In an implementation, a sacrificial layer is provided on a top surface of the die to protect the surface, and bonds pads thereon, from spill-over of the adhesive. The sacrificial layer and spill-over adhesive are subsequently removed from the die and/or chip carrier. In an implementation, the die includes a die attach film (DAF) on a bottom surface of the die for adhering the die to the cavity of the substrate. The die is applied to the cavity with heat and pressure to cause a portion of the die attach film (DAF) to flow from the bottom surface of the die to a sloped surface of the substrate cavity. | 2015-06-04 |
20150155265 | STACKED MULTI-CHIP INTEGRATED CIRCUIT PACKAGE - A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package. | 2015-06-04 |
20150155266 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads. | 2015-06-04 |
20150155267 | Electronic component with sheet-like redistribution structure - An electronic component comprising an electrically conductive chip carrier comprising an electrically insulating core structure at least partially covered with electrically conductive material, at least one electronic chip each having a first main surface attached to the chip carrier, and a sheet-like redistribution structure attached to a second main surface of the at least one electronic chip and configured for electrically connecting the second main surface of the at least one electronic chip with the chip carrier. | 2015-06-04 |
20150155268 | SEMICONDUCTOR PACKAGE DEVICE - A semiconductor package device, comprising: a package substrate having a first width; first and second semiconductor packages sequentially mounted on the package substrate; and a connection structure connecting the first and second semiconductor packages electrically to each other. The first semiconductor package comprises: a first substrate facing the package substrate and having a second width smaller than the first width; a first semiconductor chip between the first substrate and the package substrate; a conductive structure electrically connecting the first semiconductor chip to the package substrate; and a bonding wire electrically connecting the first substrate to the first semiconductor chip. | 2015-06-04 |
20150155269 | MULTIPLE DIE STACKING FOR TWO OR MORE DIE - A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses. | 2015-06-04 |
20150155270 | Opto-Electronic Module for Emitting Light of Variable Intensity Distribution - The opto-electronic module ( | 2015-06-04 |
20150155271 | Device Including Two Power Semiconductor Chips and Manufacturing Thereof - A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip. | 2015-06-04 |
20150155272 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film. | 2015-06-04 |
20150155273 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device that prevents destruction due to an avalanche breakdown and that has a high tolerance against breakdown by configuring the device so as to have a punch-through breakdown function therein and such that the breakdown voltage of a punch-through breakdown is lower than an avalanche breakdown voltage so that an avalanche breakdown does not occur. | 2015-06-04 |
20150155274 | SEMICONDUCTOR APPARATUS INCLUDING DUMMY PATTERNS - A semiconductor apparatus and system including a semiconductor apparatus may include: a main pattern block having a plurality of main patterns formed to be coupled to a power source and one or more dummy pattern blocks formed around the main pattern block. Any one of the one or more dummy pattern blocks may include a protection part formed to protect the main pattern block. | 2015-06-04 |
20150155275 | Enhancement Mode III-Nitride Switch - According to one exemplary embodiment, an efficient and high speed E-mode N/Schottky switch includes a silicon transistor coupled with a D-mode III-nitride device, where the silicon transistor causes the D-mode III-nitride device to operate in an enhancement mode. The E-mode III-N/Schottky switch further includes a Schottky diode coupled across the silicon transistor so as to improve efficiency, recovery time, and speed of the E-mode III-N/Schottky switch. An anode of the Schottky diode can be coupled to a source of the silicon transistor and a cathode of the Schottky diode can he coupled to a drain of the silicon transistor. The Schottky diode can be integrated with the silicon transistor. In one embodiment the III-nitride device is a GaN device. | 2015-06-04 |
20150155276 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a substrate; circuit units arranged above the substrate, each of the circuit units including a first electrode, a second electrode, a first switching element and a second switching element electrically connected in series between the first electrode and the second electrode, a capacitor electrically connected in parallel to the first switching element and the second switching element between the first electrode and the second electrode, and an AC electrode connected between the first switching element and the second switching element; and a housing that encloses the circuit units. A common potential is applied to the first electrodes of the respective circuit units, a common potential is applied to the second electrodes of the respective circuit units, and the AC electrodes of the respective circuit units are connected to one another. | 2015-06-04 |
20150155277 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion. | 2015-06-04 |
20150155278 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a reservoir capacitor, and the reservoir capacitor includes a plurality of MOS capacitors serially coupled to one another. The plurality of MOS capacitors are arranged in one well. | 2015-06-04 |
20150155279 | Semiconductor Device with Bipolar Junction Transistor Cells - A semiconductor device includes a bipolar junction transistor cell including an emitter region which is at least partly formed between mesas of a semiconductor body. The emitter region extends between a first surface of the semiconductor body and an emitter bottom plane. The transistor cell further includes a collector region and a base region that separates the emitter region and the collector region. | 2015-06-04 |
20150155280 | IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE - A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and beside a traditional FinFET on a bulk substrate, and a design structure on which the subject circuit resides are provided. Buried field effect transistors (FETs) are formed on either side and under the traditional FinFET. The gate of the FinFET becomes the gate of the parallel buried (FETs) and allows self alignment to the underlying sources and drains of the buried FET devices in the bulk semiconductor. | 2015-06-04 |
20150155281 | Semiconductor Device and Method of Forming the Same - A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions. | 2015-06-04 |
20150155282 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4F | 2015-06-04 |
20150155283 | Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors - Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors. | 2015-06-04 |
20150155284 | Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor - Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side. | 2015-06-04 |
20150155285 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region. | 2015-06-04 |
20150155286 | Structure and Method For Statice Random Access Memory Device of Vertical Tunneling Field Effect Transistor - Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel. | 2015-06-04 |
20150155287 | MEMORY DEVICES INCLUDING TWO-DIMENSIONAL MATERIAL, METHODS OF MANUFACTURING THE SAME, AND METHODS OF OPERATING THE SAME - Disclosed are memory devices including a two-dimensional (2D) material, methods of manufacturing the same, and methods of operating the same. A memory device may include a transistor, which includes graphene and 2D semiconductor contacting the graphene, and a capacitor connected to the transistor. The memory device may include a first electrode, a first insulation layer, a second electrode, a semiconductor layer, a third electrode, a second insulation layer, and a fourth electrode which are sequentially arranged. The second electrode may include the graphene, and the semiconductor layer may include the 2D semiconductor. Alternatively, the memory device may include first and second electrode elements, a graphene layer between the first and second electrode elements, a 2D semiconductor layer between the graphene layer and the first electrode element, and a dielectric layer between the graphene layer and the second electrode. | 2015-06-04 |
20150155288 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR STORAGE DEVICE - A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing a part that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug. | 2015-06-04 |
20150155289 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential. | 2015-06-04 |
20150155290 | SEMICONDUCTOR DEVICE - A semiconductor device including a memory cell region including a memory cell in which a floating electrode is disposed above a gate insulating film and a control electrode is stacked above the floating electrode via an interelectrode insulating film, wherein the floating electrode of the memory cell includes a first polysilicon layer containing nitrogen and a second polysilicon layer containing a P-type impurity, and wherein a height of an upper surface of an end of the first polysilicon layer is higher than a height of an upper surface of an element isolation insulating film disposed in the memory cell region. | 2015-06-04 |
20150155291 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A transfer transistor includes a pair of first diffusion regions and a gate electrode layer. The pair of first diffusion regions are formed in a surface of a semiconductor substrate, and are each connected to a contact. The gate electrode layer is formed on the semiconductor substrate via a gate insulating layer and has a pair of openings each surrounding the contact. | 2015-06-04 |
20150155292 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES INCLUDING INTERPOSED FLOATING GATES - Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers. | 2015-06-04 |
20150155293 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 2015-06-04 |