23rd week of 2013 patent applcation highlights part 14 |
Patent application number | Title | Published |
20130140590 | LIGHT-EMITTING DEVICE WITH TEMPERATURE COMPENSATION - The present application provides a light-emitting device comprising a first light-emitting diode group with a first hot/cold factor comprising a plurality of first light-emitting diode units electrically connected to one another; and a temperature compensation element electrically connected to the first light-emitting diode group, and comprising a first resistor and a second resistor; wherein the first resistor has a first temperature coefficient of resistance and the second resistor has a second temperature coefficient of resistance; and the absolute value of the first temperature coefficient of resistance is ten times greater than that of the second temperature coefficient of resistance. | 2013-06-06 |
20130140591 | STRUCTURE AND METHOD FOR LED WITH PHOSPHOR COATING - The present disclosure provides a light emitting diode (LED) apparatus. The LED apparatus includes an LED emitter having a top surface; and a phosphor feature disposed on the LED emitter. The phosphor feature includes a first phosphor film disposed on the top surface of the LED emitter and having a first dimension defined in a direction parallel to the top surface of the LED emitter; a second phosphor film disposed on the first phosphor film and having a second dimension defined in the direction; and the second dimension is substantially less than the first dimension. | 2013-06-06 |
20130140592 | LIGHT EMITTING DIODE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY AND METHODS OF MANUFACTURING SAME - A light emitting diode structure and methods of manufacturing the same are disclosed. In an example, a light emitting diode structure includes a crystalline substrate having a thickness that is greater than or equal to about 250 μm, wherein the crystalline substrate has a first roughened surface and a second roughened surface, the second roughened surface being opposite the first roughened surface; a plurality of epitaxy layers disposed over the first roughened surface, the plurality of epitaxy layers being configured as a light emitting diode; and another substrate bonded to the crystalline substrate such that the plurality of epitaxy layers are disposed between the another substrate and the first roughened surface of the crystalline substrate. | 2013-06-06 |
20130140593 | LIGHT EMITTING DIODE - A light emitting diode including a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode electrically is connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and aligned side by side, and a cross section of each of the three-dimensional nano-structure is M-shaped. | 2013-06-06 |
20130140594 | LIGHT EMITTING DIODE - A light emitting diode including a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer is provided. A surface of the substrate away from the active layer is configured as the light emitting surface. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order. A first electrode electrically is connected with the first semiconductor layer. A second electrode is electrically connected with and covers a surface of the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and the light emitting surface, and a cross section of each of the three-dimensional nano-structure is M-shaped. | 2013-06-06 |
20130140595 | LIGHT EMITTING DIODE - A light emitting diode including a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode is electrically connected with and covers the first surface of the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and the light emitting surface, and a cross section of each of the three-dimensional nano-structure is M-shaped. | 2013-06-06 |
20130140596 | LIGHT EMITTING DIODE - A light emitting diode including a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode covers the entire surface of the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and aligned side by side, and a cross section of each of the three-dimensional nano-structure is M-shaped. | 2013-06-06 |
20130140597 | Organic Light Emitting Device and Manufacturing Method Thereof - In an organic light emitting device and a method of manufacturing the organic light emitting device, reflective layers are formed on pixel definition layers to prevent the generation of an open edge defect (or a non-transfer defect) in forming light emitting layers. The organic light emitting device includes a base, first electrodes patterned and formed on the base, light emitting layers formed on the first electrodes, and a second electrode formed on the light emitting layers. Pixel definition layers are formed between the patterned first electrodes, and reflective layers are disposed in the pixel definition layers. | 2013-06-06 |
20130140598 | METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP, AND OPTOELECTRONIC SEMICONDUCTOR CHIP - A method for producing an optoelectronic semiconductor chip is specified, comprising the following steps: providing an n-conducting layer ( | 2013-06-06 |
20130140599 | TEXTILE-TYPE ORGANIC LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A textile-type organic light-emitting device and a method of manufacturing the textile-type organic light-emitting device are provided. The light-emitting device includes a textile-type first electrode; an organic light-emitting material layer formed on a surface of the textile-type first electrode; and a second electrode formed on the organic light-emitting material layer, the second electrode being transparent. | 2013-06-06 |
20130140600 | SEMICONDUCTOR NANOPARTICLE-CONTAINING MATERIALS AND LIGHT EMITTING DEVICES INCORPORATING THE SAME - In various embodiments, the present invention provides a light emitting device cap configured for location on a light emitting device comprising or consisting essentially of a primary light source. The cap defines a well region within which is received a population of semiconductor nanoparticles such that the semiconductor nanoparticles are in optical communication with the primary light source of the light emitting device when the cap is located on the light emitting device. There is further provided a light emitting device comprising or consisting essentially of a primary light source and such a cap, as well as methods for fabricating such a cap and device. | 2013-06-06 |
20130140601 | Recessed Channel Negative Differential Resistance-Based Memory Cell - The disclosed recessed thyristor-based memory cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode is connected to the bit line and cathode is connected to the word line. The disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. The disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell assists in improving the data retention of the cell and extends the time needed between cell refresh. | 2013-06-06 |
20130140602 | Power Semiconductor Package with Conductive Clip - According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively. | 2013-06-06 |
20130140603 | POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate. | 2013-06-06 |
20130140604 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed. | 2013-06-06 |
20130140605 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure - A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device. | 2013-06-06 |
20130140606 | COMPLEMENTARY LOGIC DEVICE USING SPIN INJECTION - A complementary logic device includes: an insulating layer formed on a substrate; a source electrode formed of a ferromagnetic body on the insulating layer; a gate insulating film; a gate electrode formed on the gate insulating film and controlling a magnetization direction of the source electrode; a channel layer formed on each of a first side surface and a second side surface of the source electrode and transmitting spin-polarized electrons from the source electrode; a first drain electrode formed on the first side surface of the source electrode; and a second drain electrode formed on the second side surface of the source electrode, wherein a magnetization direction of the first drain electrode and a magnetization direction of the second drain electrode are antiparallel to each other. Therefore, not only characteristics of low power and high speed but also characteristics of non-volatility and multiple switching by spin may be obtained. | 2013-06-06 |
20130140607 | DEVICES AND METHODS RELATED TO A GALLIUM ARSENIDE SCHOTTKY DIODE HAVING LOW TURN-ON VOLTAGE - Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes. | 2013-06-06 |
20130140608 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGE-PICKUP APPARATUS - In a photoelectric conversion device, groups of unit pixels are arranged in a well, where each of the unit pixels includes photoelectric conversion elements, an amplifier transistor, and transfer transistors. The photoelectric conversion device includes a line used to supply a voltage to the well, a well-contact part used to connect the well-voltage-supply line to the well, and transfer-control lines used to control the transfer transistors. The transfer-control lines are symmetrically arranged with respect to the well-voltage-supply line in respective regions of the unit-pixel groups. | 2013-06-06 |
20130140609 | MATRIX CHARGE-TRANSFER IMAGE SENSOR WITH ASYMMETRIC GATE - The invention relates to image sensors, more particularly but not exclusively to scanning sensors with signal integration (or TDI sensors, for ‘Time Delay Integration linear sensors’). The adjacent pixels along a column each comprise an alternation of at least one photodiode and one storage gate adjacent to the photodiode. The gates comprise a main body and, on the upstream side in the direction of the transfer of the charges but not on the downstream side, a series of narrow fingers extending from the main body toward the upstream side, the ends of the fingers on the upstream side being adjacent to a photodiode situated upstream of the gate, the narrow fingers being separated from one another by doped insulating regions of the first type of conductivity, with a higher doping and preferably deeper than the surface regions, connected, as they are, to the reference potential of the active layer, these insulating regions being interposed between the main body of the gate and the photodiode. These fingers induce a directionality on the charge transfer. | 2013-06-06 |
20130140610 | SOLID-STATE IMAGING DEVICE AND CAMERA - A solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element. | 2013-06-06 |
20130140611 | PRESSURE SENSOR HAVING NANOSTRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a pressure sensor having a nanostructure and a method for manufacturing the same. More particularly, it relates to a pressure sensor having a nanostructure attached on the surface of the pressure sensor and thus having improved sensor response time and sensitivity and a method for manufacturing the same. The pressure sensor according to the present disclosure having a nanostructure includes: a substrate; a source electrode and a drain electrode arranged on the substrate with a predetermined spacing; a flexible sensor layer disposed on the source electrode and the drain electrode; and a nanostructure attached on the surface of the flexible sensor layer and having nanosized wrinkles. | 2013-06-06 |
20130140612 | FIELD-EFFECT TRANSISTOR HAVING BACK GATE AND METHOD OF FABRICATING THE SAME - A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body. | 2013-06-06 |
20130140613 | SOI-BASED CMOS IMAGERS EMPLOYING FLASH GATE/CHEMISORPTION PROCESSING - A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide later is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer. | 2013-06-06 |
20130140614 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film. | 2013-06-06 |
20130140615 | SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS - Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures include a tunneling barrier material positioned between a ferromagnetic storage material and a pinned ferromagnetic material in contact with an antiferromagnetic material and a multiferroic material in contact with the ferromagnetic storage material, wherein the antiferromagnetic material, the ferromagnetic storage material, and the pinned ferromagnetic material are located between a first electrode and a second electrode. | 2013-06-06 |
20130140616 | Integrated Circuit Including a Power Transistor and an Auxiliary Transistor - In one embodiment of an integrated circuit, the integrated circuit includes a power transistor with a power control terminal, a first power load terminal and a second power load terminal. The integrated circuit further includes an auxiliary transistor with an auxiliary control terminal, a first auxiliary load terminal and a second auxiliary load terminal. The first auxiliary load terminal is electrically coupled to the power control terminal. The integrated circuit further includes a capacitor with a first capacitor electrode, a second capacitor electrode and a capacitor dielectric layer. The capacitor dielectric layer includes at least one of a ferroelectric material and a paraelectric material. The first capacitor electrode is electrically coupled to the auxiliary control terminal. | 2013-06-06 |
20130140617 | SEMICONDUCTOR DEVICE - A semiconductor device capable of high-speed operation. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is supplied with a first signal. One of a source and a drain of the second transistor is supplied with a first potential. A gate of the second transistor is supplied with a second signal. A first electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor. A second electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor. In a first period, the first signal is low and the second signal is high. In a second period, the first signal is high and the second signal is either low or high. | 2013-06-06 |
20130140618 | VERTICAL TRANSISTORS - A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed. | 2013-06-06 |
20130140619 | High Performance Dielectric Stack for DRAM Capacitor - A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value. | 2013-06-06 |
20130140620 | Flash Memory and Manufacturing Method Thereof - The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same. | 2013-06-06 |
20130140621 | FLASH MEMORY - A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1V 10-year extrapolated retention window at 125° C. and excellent 10 | 2013-06-06 |
20130140622 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced. | 2013-06-06 |
20130140623 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer. | 2013-06-06 |
20130140624 | Semiconductor Structure and Method for Forming The Semiconductor Structure - The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer. | 2013-06-06 |
20130140625 | Field-Effect Transistor and Method of Making - The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor. | 2013-06-06 |
20130140626 | Field-Effect Device and Manufacturing Method Thereof - Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region. | 2013-06-06 |
20130140627 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes. | 2013-06-06 |
20130140628 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar. | 2013-06-06 |
20130140629 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate. | 2013-06-06 |
20130140630 | TRENCH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A trench Schottky diode and a manufacturing method thereof are provided. The manufacturing method includes the following steps. Firstly, a semiconductor substrate is provided. A multi-trench structure including a wide trench and a plurality of narrow trenches is formed in the semiconductor substrate, a gate oxide layer is formed on a surface of the multi-trench structure, and a polysilicon structure is formed over the gate oxide layer and the first oxide layer. The polysilicon structure is etched to partially expose the first oxide layer and the gate oxide layer on a bottom surface of the wide trench. The semiconductor substrate, the polysilicon structure and the gate oxide layer are partially exposed by a photolithography and etching process. A metal sputtering layer is formed. Afterwards, the metal sputtering layer is etched to expose a part of the second oxide layer. | 2013-06-06 |
20130140631 | SEMICONDUTOR ISOLATION STRUCTURE AND METHOD OF MANUFACTURE - A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described. | 2013-06-06 |
20130140632 | Lateral Transistor Component and Method for Producing Same - A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone. | 2013-06-06 |
20130140633 | EDGE TERMINATION FOR SUPER JUNCTION MOSFET DEVICES - In one embodiment, a Super Junction metal oxide semiconductor field effect transistor (MOSFET) device can include a substrate and a charge compensation region located above the substrate. The charge compensation region can include a plurality of columns of P type dopant within an N type dopant region. In addition, the Super Junction MOSFET can include a termination region located above the charge compensation region and the termination region can include an N− type dopant. Furthermore, the Super Junction MOSFET can include an edge termination structure. The termination region includes a portion of the edge termination structure. | 2013-06-06 |
20130140634 | METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION - A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts. | 2013-06-06 |
20130140635 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening. | 2013-06-06 |
20130140636 | STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS - A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers. | 2013-06-06 |
20130140637 | Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same - A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure. | 2013-06-06 |
20130140638 | HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT - Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout. | 2013-06-06 |
20130140639 | HIGH GATE DENSITY DEVICES AND METHODS - A semiconductor device with an isolation feature is disclosed. The semiconductor device includes a plurality of gate structures disposed on a semiconductor substrate, a plurality of gate sidewall spacers of a dielectric material formed on respective sidewalls of the plurality of gate structures, an interlayer dielectric (ILD) disposed on the semiconductor substrate and the gate structures, an isolation feature embedded in the semiconductor substrate and extended to the ILD and a sidewall spacer of the dielectric material disposed on sidewalls of extended portion of the isolation feature. | 2013-06-06 |
20130140640 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 2013-06-06 |
20130140641 | METAL GATE FEATURES OF SEMICONDUCTOR DIE - A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio. | 2013-06-06 |
20130140642 | ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT - An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use. | 2013-06-06 |
20130140643 | INTEGRATED HIGH-K/METAL GATE IN CMOS PROCESS FLOW - A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench. | 2013-06-06 |
20130140644 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device involves process for forming gate insulating films of different thickness on a semiconductor substrate, depositing films that constitute a gate electrode, removing the gate insulating films having different thickness formed on an impurity diffusion region surface of a transistor including the gate electrode, and doping impurities into a portion where the gate insulating film is removed. | 2013-06-06 |
20130140645 | SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment. | 2013-06-06 |
20130140646 | TRANSISTOR WITH REDUCED DEPLETION FIELD WIDTH - Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode. | 2013-06-06 |
20130140647 | III-V METAL-OXIDE-SEMICONDUCTOR DEVICE - A hafnium oxide layer, between a III-V semiconductor layer and a metal oxide layer is used to prevent interaction between the III-V semiconductor layer and the metal oxide layer. | 2013-06-06 |
20130140648 | ELECTROCHEMICAL TRANSISTOR - The object of the invention is to provide a three-terminal switch (electrochemical transistor) capable of achieving sharp on-off operation. | 2013-06-06 |
20130140649 | TRANSIENT DEVICES DESIGNED TO UNDERGO PROGRAMMABLE TRANSFORMATIONS - The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level examples of transient electronics are provided. | 2013-06-06 |
20130140650 | MEMS Devices and Methods for Forming the Same - A method includes forming a Micro-Electro-Mechanical System (MEMS) device on a front surface of a substrate. After the step of forming the MEMS device, a through-opening is formed in the substrate, wherein the through-opening is formed from a backside of the substrate. The through-opening is filled with a dielectric material, which insulates a first portion of the substrate from a second portion of the substrate. An electrical connection is formed on the backside of the substrate. The electrical connection is electrically coupled to the MEMS device through the first portion of the substrate. | 2013-06-06 |
20130140651 | MICROELECTROMECHANICAL SYSTEMS (MEMS) RESONATORS AND RELATED APPARATUS AND METHODS - Devices having piezoelectric material structures integrated with substrates are described. Fabrication techniques for forming such devices are also described. The fabrication may include bonding a piezoelectric material wafer to a substrate of a differing material. A structure, such as a resonator, may then be formed from the piezoelectric material wafer. | 2013-06-06 |
20130140652 | MAGNETIC PRESSURE SENSOR - A magnetic pressure sensor is provided that includes a semiconductor body with a top side and a back side, a Hall sensor formed on the top side of the semiconductor body, a spacer connected to the semiconductor body, whereby the spacer has a recess in the center, and a membrane covering the recess, whereby the membrane has a first material and has a ferromagnetic substance. The ferromagnetic substance concentrates a magnetic flux density of a source formed outside the ferromagnetic material, and the spacer is formed as a circumferential wall and has a second material and the second material is different from the first material in at least one element. | 2013-06-06 |
20130140653 | MEMS DEVICE ETCH STOP - The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric layer above the substrate, an etch stop layer above the dielectric layer, and two anchor plugs above the dielectric layer, the two anchor plugs each contacting the etch stop layer or a top metal layer disposed above the dielectric layer. The device further comprises a MEMS structure layer disposed above a cavity formed between the two anchor plugs and above the etch stop layer from release of a sacrificial layer. | 2013-06-06 |
20130140654 | Low Frequency CMUT with Vent Holes - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. | 2013-06-06 |
20130140655 | MEMS ACOUSTIC TRANSDUCER AND METHOD FOR FABRICATING THE SAME - A MEMS acoustic transducer is provided, which includes a substrate, a MEMS chip, and a housing. The substrate has a first opening area and a lower electrode layer disposed over a surface of the substrate, wherein the first opening area includes at least one hole allowing acoustic pressure to enter the MEMS acoustic transducer. The MEMS chip is disposed over the surface of the substrate, including a second opening area and an upper electrode layer partially sealing the second opening area, wherein the upper electrode layer and the lower electrode layer, which are parallel to each other and have a gap therebetween, form an induction capacitor. The housing is disposed over the MEMS chip or the surface of the substrate creating a cavity with the MEMS chip or the substrate. In addition, a method for fabricating the above MEMS acoustic transducer is also provided. | 2013-06-06 |
20130140656 | MEMS Microphone And Method For Producing The MEMS Microphone - The invention relates to a method for producing a microphone, in which a transducer element (WE) is mounted on a carrier (TR); a cover is arranged over the transducer element (WE) and the carrier (TR) such that the transducer element (WE) is enclosed between the cover and the carrier (TR); a first sound inlet opening (SO | 2013-06-06 |
20130140657 | MAGNETIC MEMORY DEVICES INCLUDING FREE MAGNETIC LAYER HAVING THREE-DIMENSIONAL STRUCTURE - Magnetic memory devices including a free magnetic layer having a three-dimensional structure, include a switching device and a magnetic tunnel junction (MTJ) cell connected thereto. The MTJ cell includes a lower magnetic layer, a tunnel barrier layer, and a free magnetic layer, which are sequentially stacked. A portion of the free magnetic layer protrudes in a direction away from an upper surface of the tunnel barrier layer. | 2013-06-06 |
20130140658 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element includes a layered structure and a negative thermal expansion material layer. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a magnetic layer having a positive magnetostriction constant. The magnetization direction is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. | 2013-06-06 |
20130140659 | FLUX-CLOSED STRAM WITH ELECTRONICALLY REFLECTIVE INSULATIVE SPACER - Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free magnetic layer through an electrically insulating and electronically reflective layer. An electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic element from a reference magnetic layer. | 2013-06-06 |
20130140660 | MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY - In a perpendicular magnetization domain wall motion MRAM in which the magnetizations of both ends of a magnetization free layer are pinned by magnetization pinned layers, the increase of a write current due to leakage magnetic field from the magnetization pinned layer is prevented. A first displacement is present between a first boundary line and a first vertical line, where a curve portion, which crosses a first magnetization free layer, of an outer circumferential line of a first magnetization pinned layer is the first boundary line, a segment which links a center of a magnetization free region and a center of a first magnetization pinned region is a first segment, and a segment, which is a vertical line of the first segment, and which comes in contact with the first boundary line is the first vertical line. | 2013-06-06 |
20130140661 | PEROVSKITE MANGANESE OXIDE THIN FILM AND MANUFACTURING METHOD THEREFOR - A perovskite manganese oxide thin film formed on a substrate that allows a first order phase transition and has A-site ordering. The thin film contains Ba and a rare earth element in the A sites of a perovskite crystal lattice and has an (m10) orientation for which m=2n, and 9≧n≧1. A method for manufacturing the film includes forming in a controlled atmosphere using laser ablation an atomic layer or thin film that assumes a pyramidal structure having oxygen-deficient sites in a plane containing the rare earth element and oxygen; and filling the oxygen-deficient sites with oxygen. The controlled atmosphere has an oxygen partial pressure controlled to a thermodynamically required value for creating oxygen deficiencies and contains a gas other than oxygen, and has a total pressure that is controlled to a value at which the A sites have a fixed compositional ratio. | 2013-06-06 |
20130140662 | PHOTODIODE DEVICE FOR IMPROVING THE DETECTIVITY AND THE FORMING METHOD THEREOF - A method for forming the photodiode device is provided. The method comprises providing a substrate, then a transparent conductive film is formed on the substrate. A conductive polymer is formed on the transparent conductive film. A photoactive layer is formed on the conductive polymer. A charge blocking layer is formed on the photoactive layer. Finally, a cathode metal is formed on the charge blocking layer. | 2013-06-06 |
20130140663 | IMAGE SENSOR AND IMAGE CAPTURE APPARATUS - An image sensor in which each pixel includes a first sub-pixel including a first semiconductor layer, a second sub-pixel including a second semiconductor layer having a polarity different from a polarity of the first semiconductor layer, a third semiconductor layer having a polarity equal to the polarity of the first semiconductor layer, and a microlens, and which includes a plurality of pixels in which the first semiconductor is included in the second semiconductor layer, and the second semiconductor layer is included in the third semiconductor layer, wherein a center of gravity position of a light-receiving surface defining the first semiconductor layer is different from a center of gravity position of a light-receiving surface defining both the first semiconductor layer and the second semiconductor layer. | 2013-06-06 |
20130140664 | FLIP CHIP PACKAGING STRUCTURE - The present invention discloses a flip chip packaging structure which is applied to a process of a compact camera module (CCM), and the structure thereof comprises an image sensor component, at least one connection member, a circuit board and an insulating plate. The image sensor component is electrically connected with the circuit board via an electrical-conduction of the connection body. Hence, by disposing the insulating plate between the image sensor component and the circuit board, the present invention not only can provide a thermal insulating protection to the image sensor component but also use enough space to execute a surface mount technology (SMT), so as to simplify the flip chip process and to increase the yield of manufacture. | 2013-06-06 |
20130140665 | SOLID STATE IMAGE PICKUP DEVICE AND CAMERA - A solid state image pickup device which can prevent color mixture by using a layout of a capacitor region provided separately from a floating diffusion region and a camera using such a device are provided. A photodiode region is a rectangular region including a photodiode. A capacitor region includes a carrier holding unit and is arranged on one side of the rectangle of the photodiode region as a region having a side longer than the one side. In a MOS unit region, an output unit region including an output unit having a side longer than the other side which crosses the one side of the rectangle of the photodiode region is arranged on the other side. A gate region and the FD region are arranged between the photodiode region and the capacitor region. | 2013-06-06 |
20130140666 | SELF-ALIGNED IMPLANTS TO REDUCE CROSS-TALK OF IMAGING SENSORS - A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region. | 2013-06-06 |
20130140667 | LOCALIZED CARRIER LIFETIME REDUCTION - A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate. | 2013-06-06 |
20130140668 | Forming Structures on Resistive Substrates - A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices. | 2013-06-06 |
20130140669 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. | 2013-06-06 |
20130140670 | STRUCTURE AND METHOD FOR REDUCTION OF VT-W EFFECT IN HIGH-K METAL GATE DEVICES - A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices. | 2013-06-06 |
20130140671 | COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THREE-DIMENSIONALLY FORMED COMPONENTS - The present invention relates to a compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology. | 2013-06-06 |
20130140672 | VARIABLE INDUCTOR AND SEMICONDUCTOR DEVICE USING SAME - A variable inductor includes a spiral inductor, a loop conductor, and a switch for opening or short-circuiting an end of the loop conductor. The loop conductor is formed in a direction perpendicular to the spiral inductor and is used for adjusting the inductance value of the spiral inductor by opening or short-circuiting the end of the loop conductor by the switch. | 2013-06-06 |
20130140673 | MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING - A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other. | 2013-06-06 |
20130140674 | SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line. | 2013-06-06 |
20130140675 | Method for ALD Deposition Rate Enhancement - A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO | 2013-06-06 |
20130140676 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx | 2013-06-06 |
20130140677 | CAPACITOR STRUCTURES FOR SEMICONDUCTOR DEVICE - A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors. | 2013-06-06 |
20130140678 | INSULATOR LAYER BASED MEMS DEVICES - The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die. | 2013-06-06 |
20130140679 | SEMICONDUCTIVE CERAMIC SINTERED COMPACT - There is provided a semiconductive ceramic sintered compact that has a conductivity high enough to attain static electricity removal and antistatic purposes and, at the same time, has excellent mechanical properties or stability over time. The semiconductive ceramic sintered compact includes a main phase and a conductive phase present between the main phases, wherein the main phase is a ceramic sintered phase including Al | 2013-06-06 |
20130140680 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an active region located in an upper portion of a semiconductor substrate; a through-hole electrode penetrating the substrate, and made of a conductor having a thermal expansion coefficient larger than that of a material for the substrate; and a stress buffer region located in the upper portion of the substrate and sandwiched between the through-hole electrode and the active region. The stress buffer region does not penetrate the substrate and includes a stress buffer part made of a material having a thermal expansion coefficient larger than that of the material for the substrate and an untreated region where the stress buffer part is not present. The stress buffer part is located in at least two locations sandwiching the untreated region in a cross section perpendicular to a surface of the substrate and passing through the through-hole electrode and the active region. | 2013-06-06 |
20130140681 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 2013-06-06 |
20130140682 | BURIED WORD LINE AND METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - A buried word line includes a substrate having thereon a recessed trench, an insulating layer on a bottom surface and a sidewall of the recessed trench, and a lining layer in the recessed trench. The lining layer has a cleaned surface that is cleaned by a cleaning solution comprising HF or H3PO4. A tungsten layer is selectively deposited on the cleaned surface of the lining layer. | 2013-06-06 |
20130140683 | Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die - In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path. | 2013-06-06 |
20130140684 | Semiconductor Device Assembly Utilizing a DBC Substrate - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 2013-06-06 |
20130140685 | Electronic Device and a Method for Fabricating an Electronic Device - The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier. | 2013-06-06 |
20130140686 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar. | 2013-06-06 |
20130140687 | SEMICONDUCTOR DEVICE - According to one embodiment, provided is a semiconductor device including a lower layer wiring, and an upper layer wiring that is drawn in the same direction as a direction in which the lower layer wiring is drawn. Intermediate wirings include at least a first intermediate wiring and a second intermediate wiring. Conductors include at least a plurality of first conductors connecting between the lower layer wiring and the first intermediate wiring, a plurality of second conductors connecting between the upper layer wiring and the second intermediate wiring, and a plurality of third conductors which connect between the first intermediate wiring and the second intermediate wiring, and are less in number than the first conductors or the second conductors on a drawn side of the lower layer wiring and the upper layer wiring. | 2013-06-06 |
20130140688 | Through Silicon Via and Method of Manufacturing the Same - The present invention discloses a through silicon via and method of manufacturing the same comprising the steps of providing a substrate, forming a plurality of through silicon via (TSV) holes in said substrate, forming a seed layer on the surface of said substrate and said a plurality of TSV holes, forming a patterned mask on said substrate, wherein said patterned mask comprises a plurality of first openings corresponding to said TSV holes and a plurality of second openings adjacent to or surrounding said a plurality of first openings, forming a material layer on said substrate, wherein said material layer is filled into said TSV holes and said first openings to form a plurality of through silicon vias, and said material layer is filled into said second openings to form a plurality of dummy bumps. | 2013-06-06 |
20130140689 | Bump-on-Trace Structures in Packaging - A package component includes a metal trace on a top surface of the package component, and an anchor via underlying and in contact with the metal trace. The anchor via is configured not to conduct currents flowing through the metal trace. | 2013-06-06 |