23rd week of 2018 patent applcation highlights part 57 |
Patent application number | Title | Published |
20180158708 | METHOD FOR AUTOMATIC SENDING CASSETTE POD - A system for sending a cassette pod is provided. The system includes a processing machine having a load port for receiving the cassette pod. The system further includes a manipulating apparatus positioned above the processing machine. The manipulating apparatus includes an intermediate module having a stage and a driving mechanism connected to the stage to change the position of the stage. The manipulating apparatus further includes a conveyor module having a gripper assembly for grasping the cassette pod. | 2018-06-07 |
20180158709 | SUBSTRATE TREATMENT APPARATUS - A substrate treatment apparatus includes a lower electrode, an upper electrode, a first AC power supply that is connected to the upper electrode and supplies AC power at a first frequency, a second AC power supply that is connected to the upper electrode and supplies AC power at a second frequency which is lower than the first frequency, an internal electrode provided in the lower electrode, a filter circuit connected to the internal electrode, and a DC power supply connected to the internal electrode via the filter circuit. The filter circuit includes a first filter circuit that becomes low impedance with respect to AC power at the first frequency compared to AC power at the second frequency, and a second filter circuit that becomes low impedance with respect to AC power at the second frequency compared to AC power at the first frequency. | 2018-06-07 |
20180158710 | HIGH-TECH TEMPERATURE CONTROL DEVICE FOR SEMICONDUCTOR MANUFACTURING FACILITY - The present invention relates to a high-tech temperature control device for a semiconductor manufacturing facility and, more specifically, to a high-tech temperature control device for an electrostatic chuck, which supports a wafer and maintains the temperature in a semiconductor wafer processing process. It is possible to very precisely control a temperature of an electrostatic chuck by maintaining temperatures and a mixing flow rate of a heating heat medium and a cooling heat medium constant and adjusting a mixing ratio. Meanwhile, the heat medium after heating and cooling is collected and reused, thereby efficiently using energy. | 2018-06-07 |
20180158711 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes an electrostatic chuck and a lifter pin. The electrostatic chuck has a mounting surface on which a target object is mounted and a back surface opposite to the mounting surface, and a through hole formed through the mounting surface and the back surface. The lifter pin is at least partially formed of an insulating member and has a leading end accommodated in the through hole. The lifter pin vertically moves with respect to the mounting surface to vertically transfer the target object. A conductive material is provided at at least one of a leading end portion of the lifter pin which corresponds to the through hole and a wall surface of the through hole which faces the lifter pin. | 2018-06-07 |
20180158712 | Method for Bonding Thin Semiconductor Chips to a Substrate - A method for bonding thin chips to a target substrate is described herein. According to an example method, an adhesive tape is provided with thinned chips attached thereto. The chips are transferred to a carrier substrate by one or more tape-to-tape transfer steps. The carrier is then diced into separate carrier-and-chip assemblies, which can be handled by existing tools designed for handling chips of regular thickness. The fact that the thinning step is separate from the carrier attachment may lead to reduced thickness variation of the chips. The use of tape-to-tape transfer steps allows for attaching either the front or the back side of the chips to the carrier. The use of an individual carrier per chip allows for treating the thinned chip as if it were a standard chip. | 2018-06-07 |
20180158713 | ELEMENT CHIP MANUFACTURING METHOD - Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma. | 2018-06-07 |
20180158714 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus and technique, capable of processing substrates regardless of the types of substrates, include a loadlock chamber accommodating a first support part and a second support part for supporting a wafer; a first transfer mechanism including first tweezers configured to transfer the substrate into or out of the loadlock chamber through a first side of the loadlock chamber; a second transfer mechanism including second tweezers configured to transfer the substrate into or out of the loadlock chamber through a second side of the loadlock chamber; and a reactor where the substrate is processed. The first support part includes first support mechanisms spaced apart by a first distance along a direction perpendicular to an entering direction of the first tweezers or the second tweezers, and the second support part includes second support mechanisms spaced apart by a second distance smaller than the first distance. | 2018-06-07 |
20180158715 | SUBSTRATE SUPPORTING PIN, SUBSTRATE SUPPORTING DEVICE AND SUBSTRATE ACCESS SYSTEM - The disclosure provides a substrate supporting pin, a substrate supporting device and a substrate access system. The substrate supporting pin is used to support a substrate and includes a rod body. A supporting end of the rod body is provided with a rotating member that is able to roll along a surface of the substrate. Compared to the prior art, the disclosure can reduce or eliminate the damage of the substrate. | 2018-06-07 |
20180158716 | PAD RAISING MECHANISM IN WAFER POSITIONING PEDESTAL FOR SEMICONDUCTOR PROCESSING - An assembly used in a process chamber for depositing a film on a wafer. A pedestal assembly includes a pedestal movably mounted to a main frame. A lift pad rests upon the pedestal and moves with the pedestal assembly. A raising mechanism separates the lift pad from the pedestal, and includes a hard stop fixed to the main frame, a roller attached to the pedestal assembly, a slide moveably attached to the pedestal assembly, a lift pad bracket interconnected to the slide and a pad shaft extending from the lift pad, and a lever rotatably attached to the lift pad bracket. The lever rests on the roller when not engaged with the upper hard stop. When the pedestal assembly moves upwards, the lever rotates about a pin when engaging the upper hard stop and roller, and separates the lift pad from the pedestal by a process rotation displacement. | 2018-06-07 |
20180158717 | WAFER EDGE LIFT PIN DESIGN FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A wafer edge lift pin of an apparatus for manufacturing a semiconductor device is described. The wafer edge lift pin includes a top section containing a notch portion having a horizontal upwardly facing surface for supporting a wafer and a vertically sloped surface for lateral confinement of the wafer, wherein the notch portion is horizontally swept away from the wafer along a radius, a base section below the top section, the base section having a diameter that is greater than a diameter of the top section across the notch portion, and a bottom section having a diameter that is smaller than the diameter of the base section. The apparatus includes a process chamber where the wafer is processed, a chuck assembly on which the wafer is loaded, and a plurality of at least three wafer edge lift pins for moving the wafer up and down. | 2018-06-07 |
20180158718 | SEMICONDUCTOR DEVICE HAVING AIR GAP SPACERS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region. | 2018-06-07 |
20180158719 | METHOD FOR DIRECT BONDING OF SUBSTRATES INCLUDING THINNING OF THE EDGES OF AT LEAST ONE OF THE TWO SUBSTRATES - A method for direct bonding between at least a first and a second substrate, each of the first and second substrates containing a first and a second main surface, the method including: a first thinning of the edges of the first substrate over at least one portion of the circumference of the first substrate, at the first main surface of the first substrate; and placing the second main surface of the first substrate in contact with the second main surface of the second substrate such that a bonding wave propagates between the first and second substrates, securing the first and second substrates to one another by direct bonding such that portions of the second main surface of the first substrate located below the thinned portions of the first main surface of the first substrate are secured to the second substrate. | 2018-06-07 |
20180158720 | METHOD OF SEPARATING THE MAIN PART OF A SEMICONDUCTOR SUBSTRATE FROM THE FUNCTIONAL LAYER BUILT ON IT - A process separates a main body of a semiconductor substrate from a functional layer. The method includes the steps of implanting ions into a semiconductor substrate through a top surface of the semiconductor substrate to form an ion damage layer underneath the top surface of the semiconductor substrate. After the ions are implanted into the semiconductor substrate, a functional layer is formed on the top surface of the semiconductor substrate. The main body of the semiconductor substrate is then separated from the functional layer. The method also includes forming the functional layer on the semiconductor substrate after ion implanting and then separating the functional layer from the main body of the substrate at the ion damage layer. This method avoids bonding in SOI and can thus reduce process steps and cost. | 2018-06-07 |
20180158721 | HIGH RESISTIVITY SILICON-ON-INSULATOR STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer. | 2018-06-07 |
20180158722 | STRUCTURE OF DUAL DAMASCENE STRUCTURES HAVING VIA HOLE AND TRENCH - A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature. | 2018-06-07 |
20180158723 | DUAL PHOTORESIST APPROACH TO LITHOGRAPHIC PATTERNING FOR PITCH REDUCTION - Methods of lithographic patterning a dielectric layer. A first resist layer is formed on a hardmask layer, and a second resist layer is formed on the first resist layer. The second resist layer is patterned to form a first opening, which is transferred from the second resist layer to the first resist layer. The second resist layer is removed from the first resist layer after the first opening is transferred from the second resist layer to the first resist layer. The first resist layer is patterned to form a second opening laterally displaced in the first resist layer from the first opening. The first resist layer is comprised of a metal oxide photoresist that is removable selective to the hardmask layer. The hardmask layer and the dielectric layer may be subsequently patterned using first resist layer. | 2018-06-07 |
20180158724 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. The method also includes forming a first mask layer covering a sidewall of the second composite structure and a surface portion of the first composite structure and exposing at least another surface portion of the first composite structure. In addition, the method includes forming a second mask layer, on a surface portion of the second composite structure and spaced apart from the first mask layer by a first annular opening. Further, the method includes etching a top first layer of the first composite layers and a top first layer of the second composite layers. | 2018-06-07 |
20180158725 | METHOD AND SYSTEM FOR FABRICATION SEMICONDUCTOR DEVICE - A method for fabrication a semiconductor device and a system utilizing the same are provided. In the method for fabrication the semiconductor device, at first, a semiconductor structure having a metal conducting structure is provided. Next, a dielectric layer is deposited over the metal conducting structure. Then, an etching process is performed on the dielectric layer by using a fluorine-containing gas so as to form an opening, in which fluorine-containing compounds are formed on a surface of the opening during the etching process. And then, a pre-cleaning process is performed by using UV radiation so as to remove the fluorine-containing compounds. After the pre-cleaning process is performed, a cleaning process is performed to clean the surface of the opening. | 2018-06-07 |
20180158726 | Method and Structure for Interconnection - A semiconductor structure includes a first dielectric layer disposed over a substrate; a first metal feature and a second metal feature embedded in the first dielectric layer and spaced from each other; an etch stop layer disposed between the first and second metal features and on sidewalls of the first dielectric layer; a second dielectric layer disposed over the etch stop layer and between the first and second metal features; and an air gap surrounded by the second dielectric layer and disposed between the first and second metal features. | 2018-06-07 |
20180158727 | SEMICONDUCTOR DEVICE WITH CONTACT PLUG - The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner. | 2018-06-07 |
20180158728 | MEMORY DEVICE AND METHOD OF FORMING THEREOF - A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element. | 2018-06-07 |
20180158729 | FINFET DEVICE AND METHOD OF FORMING THE SAME - Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween. | 2018-06-07 |
20180158730 | SEMICONDUCTOR DEVICES - A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench, The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer, The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench. | 2018-06-07 |
20180158731 | METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY - A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip. | 2018-06-07 |
20180158732 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor structure includes a substrate, a hole which includes a top hole and a bottom hole in communication with each other in the substrate, and a filler in the top hole and the bottom hole, wherein the top hole tapers toward the bottom hole, and a side surface of the top hole and a side surface of the bottom hole form an obtuse angle. | 2018-06-07 |
20180158733 | INTEGRATED CIURCUIT PRODUCT HAVING A THROUGH-SUBSTRATE-VIA (TSV) AND A METALLIZATION LAYER THAT ARE FORMED AFTER FORMATION OF A SEMICONDUCTOR DEVICE - An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material. | 2018-06-07 |
20180158734 | METHOD OF SEPARATING ELECTRONIC DEVICES HAVING A BACK LAYER AND APPARATUS - A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed along the second major surface. The method includes placing the wafer onto a carrier substrate. The method includes singulating the wafer through the spaces to form singulation lines after the placing the wafer on the carrier substrate, wherein singulating comprises stopping in proximity to the layer of material. The method includes applying a pressure to the entire wafer thereby separating the layer of material in the singulation lines, wherein applying the pressure comprises using a fluid. The method provide a way to batch separate layers of material disposed on wafers after singulating the wafers. | 2018-06-07 |
20180158735 | PARTITIONED WAFER AND SEMICONDUCTOR DIE - A wafer includes a first set of dies and a second set of dies. The wafer further includes a scribe line separating the first set of dies from the second set of dies, wherein the scribe line has a first width. The wafer further includes a plurality of trenches between adjacent dies of the first set of dies and connected to the scribe line, wherein the plurality of trenches has a second width less than the first width, and a depth of each trench of the plurality of trenches is less than a thickness of the wafer. | 2018-06-07 |
20180158736 | METHOD FOR FABRICATING AUTO-ALIGNED INTERCONNECTION ELEMENTS FOR A 3D INTEGRATED CIRCUIT - Method for fabricating transistors for an integrated 3D circuit, comprising:
| 2018-06-07 |
20180158737 | INTEGRATION METHOD FOR FINFET WITH TIGHTLY CONTROLLED MULTIPLE FIN HEIGHTS - A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin. | 2018-06-07 |
20180158738 | SEMICONDUCTOR DEVICE STRUCTURE - A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer. | 2018-06-07 |
20180158739 | STACKED SHORT AND LONG CHANNEL FINFETS - An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell. | 2018-06-07 |
20180158740 | DISPLAY ELEMENT MANUFACTURING METHOD AND MANUFACTURING APPARATUS - The display element manufacturing apparatus has a transporting part, which transports a substrate in a first direction, a first alignment system, which detects fiducial marks, a second alignment system, which is arranged at a prescribed distance from the first alignment system in the first direction and detects fiducial marks, calculating parts, which detect the fiducial marks and calculate the expansion/contraction of the substrate in the first direction or the transport speed of the substrate, and a processing part, which processes a prescribed position of the substrate based on at least one of the expansion/contraction of the substrate in the first direction or the transport speed of the substrate and the fiducial marks. | 2018-06-07 |
20180158741 | DISPLAY DEVICE - A display device includes a display area, a peripheral area, a pad portion, a bending area, a first crack detection circuit, and a first crack detection line. The display area includes pixels and data lines. The peripheral area is disposed outside the display area. The pad portion is disposed in the peripheral area. The bending area is disposed in the peripheral area. The bending area is bendable or in a bent state. The first crack detection circuit is disposed between the display area and the pad portion. The first crack detection circuit includes switches. The first crack detection line includes a first curved portion disposed in the bending area. The first crack detection line is connected between the pad portion and the first crack detection circuit. | 2018-06-07 |
20180158742 | THROUGH-SILICON VIA BASED SEMICONDUCTOR PACKAGE - Provided is a semiconductor package. The semiconductor package comprises: a device substrate having a device pattern formed thereon; a cap substrate overlying the device substrate and comprising a first cavity area; a base substrate underlying the device substrate and comprising a second cavity area formed in the position corresponding to the first cavity area and at least one first through-silicon via that outputs, to the outside, an electrical signal provided from the device pattern or transmits, to the device pattern, an electrical signal provided from the outside; and a circuit substrate underlying the base substrate and electrically connected with the first through-silicon via to process an electrical signal for the device pattern. | 2018-06-07 |
20180158743 | Resin Molding and Sensor Device - A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit board. The resin is adhered and integrated with the circuit board. A resin leakage suppression layer including a material having a higher thermal conductivity than that of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin. | 2018-06-07 |
20180158744 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region. | 2018-06-07 |
20180158745 | SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL INCLUDING LONG VIA LINES - The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved. | 2018-06-07 |
20180158746 | CHIP PACKAGE - A chip package may include a first polymer layer and a first semiconductor chip in the first polymer layer. The first semiconductor chip may include a first semiconductor device and a first semiconductor substrate supporting the first semiconductor device. The first semiconductor chip may also have a first contact pad coupled to the first semiconductor device. The first semiconductor chip may further include a first conductive interconnect on the first contact pad. The chip package may also include a second polymer layer on the first polymer layer and across an edge of the first semiconductor chip. The chip package may further include a first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and across the edge of the first semiconductor chip. | 2018-06-07 |
20180158747 | HEAT SINK - A graphite heat sink includes plate-shaped fin portions formed of a graphite material, a base portion contacting lower ends of the plate-shaped fin portions and a joining portion between the plate-shaped fin portions and the base portion, in which the plate-shaped fin portions have a thermal conductivity of | 2018-06-07 |
20180158748 | HEAT DISSIPATION APPARATUS FOR SEMICONDUCTOR MODULE - A heat dissipation apparatus for a semiconductor module according to an exemplary embodiment of the present invention includes: a heatsink which is provided to be in surface-to-surface contact with a semiconductor module; a duct unit which includes a pair of wall members which extends perpendicularly to an edge of the other surface of the heatsink and a quadrangular box member which is formed in a quadrangular box shape opened at both ends thereof, in which two sides of the opened ends of the quadrangular box member are connected to the wall members, respectively, and any one surface, among surfaces for constituting the quadrangular box shape, is formed to be inclined; and an intake fan which is provided at the other end of the quadrangular box member, in which a vent hole is formed in the inclined lateral surface of the quadrangular box member. | 2018-06-07 |
20180158749 | Package Structure for Heat Dissipation - A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material. | 2018-06-07 |
20180158750 | CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME - Provided are chip-on-film package and display device including the same. The chip-on-film package comprises: a base film; a driving chip which is disposed on a surface of the base film; and a heat radiating member which is disposed on the driving chip and comprises a first heat radiating pad portion, a second heat radiating pad portion separated from the first heat radiating pad portion in a first direction, a connecting portion disposed between the first heat radiating pad portion and the second heat radiating pad portion, and one or more protrusions extending from the first heat radiating pad portion or the second heat radiating pad portion along an oblique direction in the first direction, wherein the connecting portion at least partially overlaps the driving chip. | 2018-06-07 |
20180158751 | SEMICONDUCTOR DEVICE PACKAGES WITH DIRECT ELECTRICAL CONNECTIONS AND RELATED METHODS - Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. | 2018-06-07 |
20180158752 | SEMICONDUCTOR STORAGE DEVICES - A semiconductor storage device includes a circuit substrate. The circuit substrate includes a main body and a connection tab connected to a side of the main body. The a main body includes a first chip mounting region and a second chip mounting region. A first semiconductor chip of a first type is mounted on the first chip mounting region. A second semiconductor chip of a second type is mounted on the second chip mounting region. The first type of the first semiconductor chip is different from the second type of the second semiconductor chip. The circuit substrate further includes a first thermal via in the connection tab and comprising a conductive material. | 2018-06-07 |
20180158753 | HEAT DISSIPATING STRUCTURE AND MANUFACTURE - A heat dissipating structure includes a heat source; a heat dissipating part disposed to oppose to the heat source; a concave portion formed in at least one of opposing surfaces of the heat source and the heat dissipating part; and a heat conducting structure comprising a filler layer of thermoplastic material disposed between the heat source and the heat dissipating part and contacting with the opposing surfaces of the heat source and the heat dissipating part, and an assembly of carbon nanotubes that are distributed in the thermoplastic material, oriented perpendicularly to the surfaces of the filler layer, contacting, at both ends, with the opposing surfaces of the heat source and the heat dissipating part, and limited its distribution in the opposing surfaces by the concave portion. | 2018-06-07 |
20180158754 | HIGH POWER THERMALLY CONDUCTIVE RADIO FREQUENCY ABSORBERS - Radio frequency (“RF”) absorbing devices used as RF termination devices or free space absorbers, for example, are formed with a planar wafer made of an inorganic thermally conductive material. The planar wafer has a first surface and a second surface opposite the first surface. A metallized resistive film is disposed on the first surface. A metallized reflective heat sink is disposed on the second surface. | 2018-06-07 |
20180158755 | THERMAL MITIGATION CONTROL RETAINING CLIP - A retaining clip adapted to be applied to secure and/or compress e.g., a heat sink element, to one or more assemblies of an electronic device may include a first planar region having a first end (e.g., a top end), and a second end, e.g., opposite or distal to the first end (e.g., a bottom end); a second planar region on the second end of the first planar region; a third planar region on the first end of the first planar region; a V-shape bend on an end of the third planar region; and an L-shape bend on an end of the second planar region. | 2018-06-07 |
20180158756 | INTEGRATED CIRCUIT WITH INTEGRALLY FORMED MICRO-CHANNEL OSCILLATING HEAT PIPE - A miniaturized oscillating heat pipe (OHP) embedded within an integrated circuit (IC) is provided. The miniaturized oscillating heat pipe (OHP) integrally formed within an integrated circuit (IC) is fabricated to form a monolithic IC device using silicon (or similar future semiconductors) fabrication techniques. The OHP is operable to transfer high local heat fluxes within the IC device to more accessible locations on the IC device for heat rejection to an available heat sink. | 2018-06-07 |
20180158757 | METHOD FOR ELECTRICALLY CONTACTING A COMPONENT BY GALVANIC CONNECTION OF AN OPEN-PORED CONTACT PIECE, AND CORRESPONDING COMPONENT MODULE - The invention relates to a method for electrically contacting a component ( | 2018-06-07 |
20180158758 | Leadframe and method of manufacturing the same - A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer. | 2018-06-07 |
20180158759 | CHIP PACKAGE AND A WAFER LEVEL PACKAGE - Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer. | 2018-06-07 |
20180158760 | LEAD FRAME - A lead frame includes a plurality of leads formed from a metal plate having a front side and a back side, a first resin member, and a second resin member. The leads have side faces thereof fixed with the first resin member. Faces serving as internal connectors of the leads are uncovered on the side of the front-side surface of the first resin member, and faces serving as external connectors of the leads are uncovered on the side of the back-side surface of the first resin member. The second resin member is formed on the front-side surface of the first resin member to be at a level higher than the faces serving as the internal connectors, and has openings for leaving the faces serving as the internal connectors uncovered. | 2018-06-07 |
20180158761 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE - A semiconductor device has a configuration in which a high-side module portion and a low-side module portion overlap each other. The semiconductor device further includes a control-side frame extending across the high-side module portion and the low-side module portion, and having a high-side integrated circuit and a low-side integrated circuit placed thereon. The high-side integrated circuit of the high-side module portion and the low-side integrated circuit of the low-side module portion are placed on one main surface of the control-side frame. At a boundary between the high-side module portion and the low-side module portion, the control-side frame is bent such that the high-side semiconductor chip and the low-side semiconductor chip face each other. | 2018-06-07 |
20180158762 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a first surface, a first electrode and a second electrode provided on the first surface, a wiring electrically connected to the first electrode at the first surface, a first metal layer on the first surface and directly contacting the second electrode, a thickness of the first metal layer in a direction orthogonal to the first surface being greater than a height of a topmost portion of the wiring in the first direction from the first surface, and a resin package contacting the semiconductor chip, the first metal layer, at least a portion of the wiring, and a first portion of the first surface and leaving a second portion of the first surface exposed. | 2018-06-07 |
20180158763 | SEMICONDUCTOR DEVICE AND METERING APPARATUS - A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing signal of a frequency according to a oscillation frequency of the oscillation circuit, and a frequency correction section that corrects a frequency of the timing signal based on temperature data; and a discrete device that includes at least one of a temperature sensing device that detects a peripheral temperature, that supplies the detected temperature as temperature data to the frequency correction section, and that is provided as a separate body to the semiconductor chip, or a capacitor that is electrically connected to both the oscillator and the oscillation circuit and that is provided as a separate body to the semiconductor chip, wherein the oscillator, the semiconductor chip and the discrete device are contained within a single package. | 2018-06-07 |
20180158764 | 3D CHIP ASSEMBLIES USING STACKED LEADFRAMES - A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets. | 2018-06-07 |
20180158765 | INTEGRATED CIRCUIT PACKAGE COMPRISING LEAD FRAME - An integrated circuit package comprises a lead frame including a plurality of leads and a current conductor forming an electrically conductive path that connects at least two leads of the plurality of leads. The package also comprises a semiconductor die comprising an integrated circuit and having first and second opposing surfaces, the first surface being proximate to the current conductor. Each of the at least two leads comprises a groove to locally space the lead away from the semiconductor die in a direction perpendicular to the first surface, in which the groove comprises at least that part of the lead that overlaps the edge of the semiconductor die. | 2018-06-07 |
20180158766 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad. | 2018-06-07 |
20180158767 | METHOD OF FORMING A MOLDED SUBSTRATE ELECTRONIC PACKAGE AND STRUCTURE - An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body. | 2018-06-07 |
20180158768 | Semiconductor Device and Method of Forming a 3D Interposer System-In-Package Module - A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate. | 2018-06-07 |
20180158769 | MODIFYING EXECUTION FLOW IN SAVE-TO-RETURN CODE SCENARIOS - A computer-implemented method includes, in a code transformation system, identifying save-to-return code instructions, function call code instructions, comparison code instructions, and exceptional code instructions. The function call code instructions are associated with the save-to-return code instructions. The comparison code instructions are associated with the save-to-return code instructions. The exceptional code instructions are associated with the comparison code instructions. A predefined proximity range based on a predefined proximity value as well as a proximity eligibility indicator are determined. The proximity eligibility indicator denotes whether the save-to-return code instructions and the comparison code instructions are within the predefined proximity range. Responsive to the proximity eligibility indicator denoting the save-to-return code instructions and the comparison code instructions are within the predefined proximity range, one or more execution flow relationships between the function call code instructions and the exceptional code instructions are created. A corresponding computer program product and computer system are also disclosed. | 2018-06-07 |
20180158770 | METHODS OF MAKING WIRING SUBSTRATE FOR STACKABLE SEMICONDUCTOR ASSEMBLY AND MAKING STACKABLE SEMICONDUCTOR ASSEMBLY - The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon. | 2018-06-07 |
20180158771 | SEMICONDUCTOR DEVICE - It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands. | 2018-06-07 |
20180158772 | CAPACITOR MOUNTING STRUCTURE - A mounting structure includes a silicon die, an interposer, a substrate, and a capacitor. The capacitor includes a multilayer body, a first outer electrode provided on one end surface of the multilayer body, a second outer electrode provided on another end surface of the multilayer body, and a third outer electrode provided on side surfaces of the multilayer body, and a portion of the capacitor at the first outer electrode side is embedded within the interposer. The first outer electrode is connected to a power supply terminal of the silicon die through a via of the interposer. The second outer electrode is connected to a power supply pattern on the substrate. The third outer electrode is connected to a ground pattern within the interposer. | 2018-06-07 |
20180158773 | SEMICONDUCTOR DEVICE INCLUDING A BIT LINE - A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern. | 2018-06-07 |
20180158774 | FABRICATION METHOD OF SEMICONDUCTOR SUBSTRATE - A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body. | 2018-06-07 |
20180158775 | HIGH Q FACTOR INDUCTOR STRUCTURE - A three-dimensional (3-D) inductor is incorporated in a substrate. The 3-D inductor has a first connector plate, a second connector plate, a third connector plate, a first terminal plate, and a second terminal plate. Four multi-via walls connect the various plates, wherein each multi-via wall includes a first group of at least three individual via columns, each of which connects two plates together. | 2018-06-07 |
20180158776 | Integrated Circuit Having a High Cell Density - An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line. | 2018-06-07 |
20180158777 | REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE - An integrated circuit (IC) package with improved performance and reliability is disclosed. The IC package includes an IC die and a routing structure. The IC die includes a conductive via having a peripheral edge. The routing structure includes a conductive structure coupled to the conductive via. The conductive structure may include a cap region, a routing region, and an intermediate region. The cap region may overlap an area of the conductive via. The routing region may have a first width and the intermediate region may have a second width along the peripheral edge of the conductive via, where the second width may be greater than the first width. | 2018-06-07 |
20180158778 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES - Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. | 2018-06-07 |
20180158779 | Semiconductor Device and Method of Forming an Integrated SIP Module with Embedded Inductor or Package - A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant. | 2018-06-07 |
20180158780 | MOLDING STRUCTURE FOR WAFER LEVEL PACKAGE - A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices. | 2018-06-07 |
20180158781 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt. | 2018-06-07 |
20180158782 | ELECTRONIC CIRCUIT PACKAGE HAVING HIGH COMPOSITE SHIELDING EFFECT - Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a magnetic mold resin that covers the surface of the substrate so as to embed the electronic component therein, the magnetic mold resin comprising a composite magnetic material containing a thermosetting resin material and a magnetic filler; and a laminated film including at least a metal film and a magnetic film, the laminated film covering at least an top surface of the magnetic mold resin. The metal film is connected to the power supply pattern, and the magnetic film has a higher effective permeability than that of the magnetic mold resin. | 2018-06-07 |
20180158783 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer. | 2018-06-07 |
20180158784 | FABRICATION METHOD OF ELECTRONIC PACKAGE HAVING EMBEDDED PACKAGE BLOCK - A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost. | 2018-06-07 |
20180158785 | PACKAGING STRUCTURES FOR METALLIC BONDING BASED OPTO-ELECTRONIC DEVICE AND MANUFACTURING METHODS THEREOF - The present disclosure proposes a packaging structure for a metallic bonding based opto-electronic device and a manufacturing method thereof. According to the embodiments, the packaging structure for an opto-electronic device may comprise an opto-electronic chip and a packaging base. The opto-electronic chip comprises: a substrate having a first substrate surface and a second substrate surface opposite to each other; an opto-electronic device formed on the substrate; and electrodes for the opto-electronic device which are formed on the first substrate surface. The packaging base has a first base surface and a second base surface opposite to each other, and comprises conductive channels extending from the first base surface to the second base surface. The opto-electronic chip is stacked on the packaging base in such a manner that the first substrate surface faces the packaging base, and the electrodes formed on the first substrate surface of the opto-electronic chip are bonded with corresponding conductive channels in the packaging base. | 2018-06-07 |
20180158786 | RADIO FREQUENCY (RF) INDUCTIVE SIGNAL COUPLER AND METHOD THEREFOR - A reference circuit includes an integrated circuit (IC) formed on a semiconductor substrate including a first spiral inductor and a second spiral inductor. The first spiral inductor is formed from a first metal layer over the substrate. The second spiral inductor is formed from a second metal layer. The second spiral inductor is offset from the first spiral inductor and includes a first portion overlapping the first spiral inductor. A first capacitor includes a first terminal coupled to receive a radio frequency (RF) signal and a second terminal coupled to a first terminal of the first spiral inductor, and second capacitor includes a first terminal coupled to a second terminal of the first spiral inductor. | 2018-06-07 |
20180158787 | INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME - An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided | 2018-06-07 |
20180158788 | MIXED STRUCTURE METHOD OF LAYOUT OF DIFFERENT SIZE ELEMENTS TO OPTIMIZE THE AREA USAGE ON A WAFER - A semiconductor wafer device that comprises a round wafer with a large surface area and a low cost per unit area is disclosed. The semiconductor wafer device comprises mixed size elements, such that a plurality of large devices are manufactured on the wafer, as well as a plurality of small devices are manufactured on the wafer. The small devices act as fill in elements for the wafer, as the plurality of large devices do not efficiently fill in the wafer. Typically, the large devices comprise strap or interposer devices and the small devices comprise chip devices. The chip devices attach to small RFID antennas and the interposer devices attach to larger structures, such as high frequency tags where the strap/interposer can act as a bridge from the center of an antenna coil to the outside. | 2018-06-07 |
20180158789 | Semiconductor Device and Method - A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures. | 2018-06-07 |
20180158790 | SOLDER PARTICLE - Disclosed is a solder particle including a plastic core; a copper-free metal layer which is formed on an external surface of the plastic core; and a solder layer which is formed on the copper-free metal layer and contains not less than 85 wt % tin. Thus, it is possible to provide a solder particle with a copper-free metal layer, which is excellent in strength and conductivity and prevents or minimizes generation of a void during a reflow process or the like. | 2018-06-07 |
20180158791 | FAN-OUT SEMICONDUCTOR PACKAGE MODULE - A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate. | 2018-06-07 |
20180158792 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIP WITH LARGE AND SMALL IRREGULARITIES ON UPPER AND LOWER SIDE SURFACE PORTIONS THEREOF - A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the semiconductor chip to be covered by an encapsulating resin, and an area having small irregularities is formed on a lower side surface of the semiconductor chip, thereby improving adhesive strength between the semiconductor chip and the encapsulating resin and preventing penetration of moisture from outside. | 2018-06-07 |
20180158793 | Method and Apparatus for forming Contacts on an Integrated Circuit Die using a Catalytic Adhesive - A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB. | 2018-06-07 |
20180158794 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap. The inner peripheral end of a bottom of the conductive cap is disposed at a side close to the inner periphery of the insulating coating member relative to the outer peripheral end of the insulating coating member. The bottom has a shape in which the distance between the main surface and itself decreases continuously from its outer peripheral end toward its inner peripheral end. | 2018-06-07 |
20180158795 | SEMICONDUCTOR DEVICE - In order to inhibit defective connection between a bump of a semiconductor chip and an electrode pad of a substrate, a semiconductor device includes a substrate provided on a surface with a plurality of electrode pads | 2018-06-07 |
20180158796 | BONDING APPARATUS, BONDING SYSTEM, BONDING METHOD AND STORAGE MEDIUM - There is provided a bonding apparatus for bonding substrates together, which includes: a first holding part configured to adsorptively hold a first substrate by vacuum-drawing the first substrate on a lower surface of the first substrate; a second holding part provided below the first holding part and configured to adsorptively hold a second substrate by vacuum-drawing the second substrate on an upper surface of the second substrate; a pressing member provided in the first holding part and configured to press a central portion of the first substrate; and a plurality of substrate detection parts provided in the first holding part and configured to detect a detachment of the first substrate from the first holding part. | 2018-06-07 |
20180158797 | STRUCTURES AND METHODS TO ENABLE A FULL INTERMETALLIC INTERCONNECT - A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process. | 2018-06-07 |
20180158798 | Fan-Out Package Structure, And Manufacturing Method Thereof - The method of fabricating a fan-out package structure comprises: S | 2018-06-07 |
20180158799 | MULTI-CHIP PACKAGE CAPABLE OF TESTING INTERNAL SIGNAL LINES - A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires. | 2018-06-07 |
20180158800 | APPARATUS AND METHOD OF POWER TRANSMISSION SENSING FOR STACKED DEVICES - Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator. | 2018-06-07 |
20180158801 | METHODS OF MANUFACTURING ELECTRONIC DEVICES FORMED IN A CAVITY AND INCLUDING A VIA - A method of manufacturing an electronic device formed in a cavity may include, on a first substrate having a bottom surface and a top surface, forming a first side wall of a certain height along a periphery on the bottom surface to surround an electronic circuit disposed on the bottom surface; forming a via communicating between the bottom surface and the top surface, forming of the via including stacking a first stop layer and a second stop layer sequentially on a portion of the bottom surface of the first substrate corresponding to the via and etching the first substrate to form a through-hole corresponding to the via, a rate of etching the first substrate being greater than that of the first stop layer and a rate of etching the first stop layer being greater than that of the second stop layer; forming a second side wall of a certain height along a periphery on a top surface of the second substrate; and aligning and bonding the first side wall and the second side wall. | 2018-06-07 |
20180158802 | Semiconductor Device and Method - A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components. | 2018-06-07 |
20180158803 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip. | 2018-06-07 |
20180158804 | Integrated Circuit Package For Assembling Various Dice In A Single IC Package - An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate. | 2018-06-07 |
20180158805 | METHOD FOR MAKING AN LED MODULE AND MODULE MADE THEREOF - An LED module includes a substrate, a first conductive element formed on a top face of the substrate, wherein the first conductive element has a feature to bear at least 0.3 Amps of electrical current passing therethrough and conductive islands formed on a top face of substrate and one of which is electrically connected to the first conductive element. An insulation film is formed on a top face of the first conductive element and at least one second conductive element is formed on the substrate to be electrically connected to remainder of the conductive islands and crosses over the first conductive element at portions where the first conductive element having the insulation film formed thereon. An LED chip is mounted on the top face of the substrate to electrically connect to the first conductive element, the conductive islands and the second conductive element. | 2018-06-07 |
20180158806 | MANUFACTURING METHOD OF DISPLAY - A manufacturing method of a display including the following steps is provided. Firstly, a back plate, a first transfer platform and a second transfer platform are provided, wherein a plurality of first light-emitting devices are disposed on the first transfer platform, and a plurality of second light-emitting devices are disposed on the second transfer platform. Secondly, a plurality of first bonding layers are formed at a plurality of first positions of the back plate. Then, the first transfer platform and the back plate are correspondingly docked, so that the first light-emitting devices are bonded on the first positions through the first bonding layers. After that, a plurality of second bonding layers are formed at a plurality of second positions of the back plate. Finally, the second transfer platform and the back plate are correspondingly docked, so that the second light-emitting devices are bonded on the second positions through the second bonding layers. | 2018-06-07 |
20180158807 | LED MODULE AND METHOD FOR FABRICATING THE SAME - Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips. | 2018-06-07 |