23rd week of 2017 patent applcation highlights part 63 |
Patent application number | Title | Published |
20170162472 | Power Semiconductor Module and Manufacturing Method of Power Semiconductor Module - An object of the present invention is to provide a power semiconductor module that can secure a satisfactory cooling without expanding the size of a case component. In the power semiconductor module according to the present invention, a frame case includes a front surface, a back surface, and a pair of side surfaces and formed with an opening part in at least one of the front surface and the back surface. A metal base is inserted into the opening part of the frame case. A frame case is provided with a joining part FW to which the peripheral part of the metal base and the peripheral part of the opening part of the frame case are joined. A first concaved part and a second concaved part are formed respectively in each of a pair of side surfaces of the frame case. Each of the concaved parts is prolonged toward an inner side of the frame case from the side surfaces, and includes a bottom surface formed facing the joining part FW side in an intermediate position of the thickness direction of each of the side surfaces. | 2017-06-08 |
20170162473 | SYSTEMS AND METHODS FOR THERMAL CONTROL OF INTEGRATED CIRCUITS - A system includes a carrier defining a plurality of channels. The system includes an integrated circuit (IC) die having a first side and having a second side opposite the first side. The second side of the IC die is coupled to the carrier. The system includes a die attach layer between the carrier and the second side of the IC die. The die attach layer defines one or more openings that enable a fluid to flow from the carrier to the second side of the IC die. | 2017-06-08 |
20170162474 | COOLING MODULE AND ELECTRONIC DEVICE - The cooling module includes a heat sink for cooling a power component of an ultrasonic source and a resonance tube arranged between the ultrasonic source and the heat sink. The cooling module is designed to guide a stream of air flowing through the resonance tube in a circumferential predefined direction (e.g., in a direction along an inner circumference of the resonance tube). The electronic device includes a power component and a heat sink provided for cooling, the heat sink of the cooling module being designed and arranged for cooling the power component. | 2017-06-08 |
20170162475 | HEAT EXCHANGER METHODS, APPARATUSES AND SYSTEMS WITH A MANIFOLD STRUCTURE - Methods, apparatuses and systems associated with a heat exchanger for cooling an IC package are disclosed herein. In embodiments, a heat exchanger may include a base plate having a bottom side to be thermally coupled to the IC package, and a fin side, wherein the fin side is to include a plurality of fins to dissipate thermal energy emanated from the IC package. The heat exchanger may further include a manifold structure disposed on top of the base plate, having one or more layers, to regulate a coolant fluid flow to cool the plurality of fins, wherein the one or more layers are to include a plurality of channels and ports complementarily organized to distribute the coolant fluid flow to the plurality of fins tailored to a thermal energy emanation pattern of the integrated circuit package. Other embodiments may be described and/or claimed. | 2017-06-08 |
20170162476 | Connector block with two sorts of through connections, and electronic device comprising a connector block - An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip. | 2017-06-08 |
20170162477 | LEAD FRAME AND LIGHT EMITTING DIODE PACKAGE HAVING THE SAME - A lead frame for an LED package includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes separated first and second connecting surfaces. Top surfaces of the bonding electrode, the first connecting electrode, and the second connecting electrode are exposed, and support and electrically connect with light emitting chips. LED packages can be mounted on the lead frame and electrically connect with each other. The conductive layout of the lead frame further permits installation of a zener diode which can be connected to the LED packages in series or in parallel. | 2017-06-08 |
20170162478 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present disclosure provides a semiconductor device and a semiconductor device manufacturing method that may prevent positional displacement of an electronic component mounted on a lead frame. Namely, a semiconductor device includes a lead frame, and an electronic component that has a protruding or recessed structure at a bonding face that bonds to the lead frame and is bonded to the lead frame, in a state in which a portion of the lead frame is fitted together with the protruding or recessed structure. | 2017-06-08 |
20170162479 | SEMICONDUCTOR DEVICE WITH FRAME HAVING ARMS AND RELATED METHODS - A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms. | 2017-06-08 |
20170162480 | SEMICONDUCTOR DEVICE - A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of the device has a projecting terminal sealed in the package, to one surface of which a back surface of the chip is bonded, and the other surface of which is partially exposed from a bottom surface of the package as a first terminal. A lead separate from the island is sealed in the package and has one surface electrically connected with the second pad, and another surface exposed from the package bottom surface as a second terminal capable of electrical connection between the second pad and outside. A mass center of the chip is away from a center of the package, the projecting terminal is as large as the lead, and solder under the device spreads to the island projecting terminal. | 2017-06-08 |
20170162481 | SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE - Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces. | 2017-06-08 |
20170162482 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element and an electrically conductive member. The semiconductor element is configured to allow an electric current to flow from a first electrode to a second electrode and prevent an electric current flowing from the second electrode to the first electrode. The electrically conductive member is joined with the second electrode via a solder joint layer. Surface of the second electrode in contact with the solder joint layer mainly comprises nickel, and surface of the electrically conductive member in contact with the solder joint layer mainly comprises copper. The solder joint layer comprises first and second compound layers. The first compound layer is located at an interface with, the second electrode and comprises nickel-tin based intermetallic compound. The second compound layer is located at an interface with the electrically conductive member and comprises copper-tin based intermetallic compound. | 2017-06-08 |
20170162483 | ELECTRONIC PACKAGES FOR FLIP CHIP DEVICES - Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an encapsulant. The plurality of leads are interdigitated and are at different voltage potentials | 2017-06-08 |
20170162484 | THERMALLY CONDUCTIVE SHEET AND SEMICONDUCTOR DEVICE - A thermally conductive sheet of the present invention includes a thermosetting resin (A), and an inorganic filler material (B) which is dispersed in the thermosetting resin (A). In the thermally conductive sheet according to the present invention, the volume resistivity of the cured product of the thermally conductive sheet, which is measured one minute later after an applied voltage of 1000 V is applied thereto on the basis of JIS K 6911 and at a temperature of 175° C., is greater than or equal to 1.0×10 | 2017-06-08 |
20170162485 | SEMICONDUCTOR DEVICE - [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad | 2017-06-08 |
20170162486 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method includes the steps of: preparing a lead frame including a plurality of die pads, and preparing a plurality of semiconductor chips; disposing each of the semiconductor chips on a respective one of the die pads; forming a sealing resin to cover the die pads and the semiconductor chips; and attaching a heat dissipation plate to the die pads by pressing the heat dissipation plate against the die pads via a resin sheet which is an adhesive layer after the sealing resin is formed. | 2017-06-08 |
20170162487 | CHIP ON FILM PACKAGE - A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip. | 2017-06-08 |
20170162488 | PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE - Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate. | 2017-06-08 |
20170162489 | Flat No-Lead Packages with Electroplated Edges - A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the hack side of the terminals each include a contact region which lacks the plating layer. | 2017-06-08 |
20170162490 | SEMICONDUCTOR DEVICE, PACKAGE, AND VEHICLE - A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector. | 2017-06-08 |
20170162491 | Chip-size, double side connection package and method for manufacturing the same - A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection. | 2017-06-08 |
20170162492 | IC Carrier of Semiconductor Package and Manufacturing Method Thereof - The present invention discloses an IC Carrier of a semiconductor package and its manufacturing method. The IC Carrier of the semiconductor package includes a dielectric layer and a patterned conductor layer. The dielectric layer has at least one opening groove. The patterned conductor layer is embedded in the dielectric layer, wherein a part of the patterned conductor layer is as a conductive pillar, which has two exposed ends, and a part of the patterned conductor layer is as a conductive wire, which only has one exposed end. | 2017-06-08 |
20170162493 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate. | 2017-06-08 |
20170162494 | METHOD FOR FABRICATING PACKAGE STRUCTURE - A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a surface exposed from the first surface of the dielectric layer; a plurality of conductive posts embedded in the dielectric layer and electrically connected to the first circuit layer and having one ends exposed from the second surface of the dielectric layer; a second circuit layer formed on the second surface of the dielectric layer and electrically connected the ends of the conductive posts exposed from the second surface of the dielectric layer; and a plurality of protruding elements formed on the surface of the first circuit layer exposed from the first surface of the dielectric layer, thereby providing a large contact area so as to strengthen bonding between a semiconductor chip and the first circuit layer of the package structure. | 2017-06-08 |
20170162495 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED PAD ON LAYERED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core. | 2017-06-08 |
20170162496 | TRENCH SILICIDE WITH SELF-ALIGNED CONTACT VIAS - A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions. | 2017-06-08 |
20170162497 | METAL VIA STRUCTURE - A filled metal via having an adhesive layer configured on bottom is disclosed. The adhesive layer enhances bonding force between the filled metal via and a bottom element. Further, stacked metal vias can be made to save spaces to enhance circuit density for an electronic system. | 2017-06-08 |
20170162498 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated. | 2017-06-08 |
20170162499 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER READABLE RECORDING MEDIUM - A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions. | 2017-06-08 |
20170162500 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer. | 2017-06-08 |
20170162501 | CRACK STOP LAYER IN INTER METAL LAYERS - Devices and methods for forming a device are presented. The method includes providing a substrate prepared with interlevel dielectric (ILD) layers having interconnect levels. Each of the ILD layers has a metal level dielectric which includes one or more metal lines and a via level dielectric which includes one or more via contacts. A crack stop layer is formed within one of the via level dielectric of one of the ILD layers. The crack stop layer prevents crack formation in the ILD layer or crack propagation to underlying ILD layer. | 2017-06-08 |
20170162502 | Semiconductor Devices and Methods of Forming Same - Embodiments of the present disclosure include a semiconductor device and methods of forming the same. A representative embodiment includes a method of forming a semiconductor device that includes a first conductive feature over a substrate, a dielectric layer over the conductive feature, and an opening through the dielectric layer to the first conductive feature. The method further includes selectively forming a first capping layer over the first conductive feature in the opening, and a second conductive feature on the first capping layer. | 2017-06-08 |
20170162503 | MOS ANTIFUSE WITH VOID-ACCELERATED BREAKDOWN - A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown. | 2017-06-08 |
20170162504 | Metal Line Structure and Method - A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line. | 2017-06-08 |
20170162505 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer. | 2017-06-08 |
20170162506 | Interconnect Structure and Method of Forming Same - An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer. | 2017-06-08 |
20170162507 | Semiconductor Structures For Assembly In Multi-Layer Semiconductor Devices Including At Least One Semiconductor Structure - A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided. | 2017-06-08 |
20170162508 | STRAIN ENGINEERING DEVICES USING PARTIAL DEPTH FILMS IN THROUGH-SUBSTRATE VIAS - Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall. | 2017-06-08 |
20170162509 | HIGH DENSITY INTERCONNECT DEVICE AND METHOD - Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards. | 2017-06-08 |
20170162510 | SEMICONDUCTOR DEVICE WITH EMBEDDED SEMICONDUCTOR DIE AND SUBSTRATE-TO-SUBSTRATE INTERCONNECTS - A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate. | 2017-06-08 |
20170162511 | DIELECTRIC/METAL BARRIER INTEGRATION TO PREVENT COPPER DIFFUSION - An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound. | 2017-06-08 |
20170162512 | Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition - A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench. | 2017-06-08 |
20170162513 | NON-OXIDE BASED DIELECTRICS FOR SUPERCONDUCTOR DEVICES - A method of forming a superconductor device is provided. The method includes depositing a non-oxide based dielectric layer over a substrate, depositing a photoresist material layer over the non-oxide based dielectric layer, irradiating and developing the photoresist material layer to form a via pattern in the photoresist material layer, and etching the non-oxide based dielectric layer to form openings in the non-oxide based dielectric layer based on the via pattern. The method further comprises stripping the photoresist material layer, and filling the openings in the non-oxide based dielectric with a superconducting material to form a set of superconducting contacts. | 2017-06-08 |
20170162514 | SEMICONDUCTOR PACKAGE WITH ANTENNA - A semiconductor package includes a substrate, a plurality of pin pads, a radio frequency (RF) pad, a semiconductor component, at least one surface mount device (SMD) component, a mold compound, a printed circuit board (PCB) antenna and a conductive solder. The RF pad is used to receive or transmit an RF signal on the top side of the substrate. The SMD component is mounted on the RF pad. The mold compound on the top side of the substrate covers the semiconductor component and the SMD component. The PCB antenna is located on the mold compound. Wherein, the conductive solder and the SMD component are stacked between the RF pad and a feeding structure of the PCB antenna. | 2017-06-08 |
20170162515 | SEMICONDUCTOR PACKAGES INCLUDING A SHIELDING PART AND METHODS FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include arranging a conductive elastic plate over a package substrate including through slits disposed along edges of a chip mounting region and a conductive guard rails providing a concave trench shape, and bending the conductive elastic plate. Edge portions of the conductive elastic plate may be inserted into the trenches of the conductive guard rails and supported by the conductive guard rails by a force trying to stretch by the elastic restoring force of the wing portions of the conductive elastic plate. | 2017-06-08 |
20170162516 | SEMICONDUCTOR PACKAGES INCLUDING SIDE SHIELDING PARTS - A method of fabricating a semiconductor package is provided. The method includes providing a package substrate strip including chip mounting regions, bridge regions connecting the chip mounting regions to each other, and through slits disposed between the chip mounting regions. A side shielding part including a lower portion filling the through slits and an upper portion upwardly extending from the lower side shielding part to protrude from the package substrate strip is formed. Semiconductor chips are mounted on the chip mounting regions. Mold patterns are formed on the package substrate strip to cover the semiconductor chips and to expose a top surface of the side shielding part. A top shielding part is formed on the mold patterns to contact the side shielding part. | 2017-06-08 |
20170162517 | PACKAGING FOR HIGH SPEED CHIP TO CHIP COMMUNICATION - Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping. | 2017-06-08 |
20170162518 | Protection Structure for Semiconductor Device Package - A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring. | 2017-06-08 |
20170162519 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor package, and a semiconductor package resulting therefrom, that comprises attaching at least one semiconductor die to a metal plate, encapsulating the at least one semiconductor die on the metal plate using an encapsulant, and dicing the metal plate and the encapsulant. | 2017-06-08 |
20170162520 | LEAD FRAME, ELECTRONIC COMPONENT DEVICE, AND METHODS OF MANUFACTURING THEM - A lead frame includes a terminal part having a first side surface formed in a concave curve shape on a lower side from an upper end of the terminal part, and a second side surface formed in a concave curve shape on a lower side from a lower end of the first side surface. The concave curve shape of each of the first and second side surfaces has a depth in a surface direction of the terminal part. A boundary part of the first side surface and the second side surface becomes a protrusion protruding outward. The depth of the concave curve shape of the second side surface is larger than that of the first side surface. A distance between an upper end and a lower end of the second side surface is longer than a distance between an upper end and the lower end of the first side surface. | 2017-06-08 |
20170162521 | WAFER PROCESSING METHOD - Disclosed herein is a wafer processing method including a stacked member removing step of applying a laser beam having an absorption wavelength to a stacked member through a protective film along each division line formed on the front side of a wafer, thereby performing ablation to remove the stacked member present on each division line, a dividing step of applying an external force to the wafer to divide the wafer into individual device chips along each division line where a modified layer is previously formed, and a plasma etching step of supplying an etching gas in a plasma state to the wafer from the front side thereof after performing the stacked member removing step or after performing the dividing step, thereby removing damage due to the ablation in the stacked member removing step. | 2017-06-08 |
20170162522 | STRESS RELIEF IN SEMICONDUCTOR WAFERS - Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer. | 2017-06-08 |
20170162523 | PACKAGE SUBSTRATE - A package substrate is disclosed. The package substrate includes a molding layer, a redistribution structure, and a build-up structure. The redistribution structure is embedded in the molding layer with a surface exposed by the molding layer. The build-up structure is formed on the bottom surface of the molding layer. An inner stress caused by a CTE difference between different materials in the package substrate is reduced by forming at least one groove which is arranged around the periphery of the redistribution structure onto the top surface of the molding layer, thereby improving the problem of the redistribution structure cracking in the prior art. | 2017-06-08 |
20170162524 | Antennas and Waveguides in InFO Structures - A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with the metal ring, encapsulating the device die and the metal ring in an encapsulating material. The method further includes filling a dielectric material into a space encircled by the metal ring, and forming a second metal plate covering the dielectric material and the metal ring, with an opening formed in the second metal plate. A plurality of redistribution lines is formed, with one of the redistribution lines overlapping a portion of the opening. The first metal plate, the metal ring, the second metal plate, and the dielectric material in combination form an antenna or a waveguide. The redistribution line forms a signal-coupling line of the passive device. | 2017-06-08 |
20170162525 | HIGH FREQUENCY SEMICONDUCTOR AMPLIFIER - A high frequency semiconductor amplifier includes an input circuit, a first semiconductor element, first bonding wires, an interstage circuit, second bonding wires, a second semiconductor element, third bonding wires, an output circuit, fourth bonding wires and a package. The input circuit includes a first DC blocking capacitor, an input transmission line, a first input pad part, and a first bias circuit. The interstage circuit includes a second DC blocking capacitor, an interstage transmission line, a first output pad part, and a second bias circuit, a microstrip line divider, and a second input pad part. The output circuit includes a second output pad part, a microstrip line combiner, a third DC blocking capacitor, an output transmission line, and a fourth bias circuit. The first and second semiconductor elements, the input circuit, the interstage circuit, and the output circuit are bonded to the package. | 2017-06-08 |
20170162526 | METHOD TO IMPROVE CMP SCRATCH RESISTANCE FOR NON PLANAR SURFACES - A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond. | 2017-06-08 |
20170162527 | ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof. | 2017-06-08 |
20170162528 | Semiconductor Device - A semiconductor device includes a semiconductor chip including a semiconductor substrate, an element formed in an element forming region of the semiconductor substrate, and a through-via penetrating across a front surface and a rear surface of the semiconductor substrate while avoiding the element forming region of the semiconductor substrate to form a conductive path between the front surface and the rear surface; a circuit component mounted on a circuit component connection surface at the same side as the front surface of the semiconductor substrate of the semiconductor chip; and an external connection members formed on the rear surface of the semiconductor substrate. | 2017-06-08 |
20170162529 | ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE - In order to easily inspect a dispersion state of conductive particles in such an anisotropic conductive film that the conductive particles are dispersed even at high density, linear lines including no conductive particle in a plan view of an anisotropic conductive film including an insulating adhesive layer and conductive particles dispersed in the insulating adhesive layer are allowed to exist at predetermined intervals. Specifically, the conductive particles are disposed in a lattice so as to be arranged in a first arrangement direction and a second arrangement direction, and the disappearance lines are inclined relative to the first arrangement direction or the second arrangement direction. | 2017-06-08 |
20170162530 | Packaged IC with Solderable Sidewalls - A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal. | 2017-06-08 |
20170162531 | COMPOSITION FOR ANISOTROPIC CONDUCTIVE FILM, ANISOTROPIC CONDUCTIVE FILM, AND CONNECTION STRUCTURE USING THE SAME - An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic conductive film including a binder resin; a curable alicyclic epoxy compound; a curable oxetane compound; a quaternary ammonium catalyst; and conductive particles, wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1: | 2017-06-08 |
20170162532 | Edge Interconnect Packaging of Integrated Circuits for Power Systems - Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules. | 2017-06-08 |
20170162533 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer. | 2017-06-08 |
20170162534 | CHIP ATTACH FRAME - A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads. | 2017-06-08 |
20170162535 | TRANSIENT INTERFACE GRADIENT BONDING FOR METAL BONDS - A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the Cu-Cu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears. | 2017-06-08 |
20170162536 | NANOWIRES FOR PILLAR INTERCONNECTS - An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate. | 2017-06-08 |
20170162537 | ADHESIVE BONDING COMPOSITION AND WAFER-TO-WAFER BONDED ASSEMBLY PREPARED FROM THE SAME - A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a phosphor capable of producing light when exposed to radiation (typically X-rays). The material is particularly suitable for bonding components at ambient temperature in situations where the bond joint is not accessible to an external light source. An associated method includes: placing a polymerizable adhesive composition, including a photoinitiator and energy converting material, such as a down-converting phosphor, in contact with at least two components to be bonded to form an assembly; and, irradiating the assembly with radiation at a first wavelength, capable of conversion (down-conversion by the phosphor) to a second wavelength capable of activating the photoinitiator, to prepare items such as inkjet cartridges, wafer-to-wafer assemblies, semiconductors, integrated circuits, and the like. | 2017-06-08 |
20170162538 | METHOD FOR APPLYING A BONDING LAYER - A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate. | 2017-06-08 |
20170162539 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition. | 2017-06-08 |
20170162540 | WAFER-LEVEL CHIP-SCALE PACKAGE WITH REDISTRIBUTION LAYER - A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The WLCSP further includes a passivation layer formed over the semiconductor structure and the first bonding pad, exposing portions of the first bonding pad. The WLCSP further includes a conductive redistribution layer formed over the passivation layer and the portions of the first bonding pad exposed by the passivation layer. The WLCSP further includes a planarization layer formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. The WLCSP further includes an under-bump-metallurgy (UBM) layer formed over the planarization layer and a conductive bump formed over the UBM layer. | 2017-06-08 |
20170162541 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA. | 2017-06-08 |
20170162542 | Packages with Thermal Management Features for Reduced Thermal Crosstalk and Methods of Forming Same - An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour lid over the first die stack and second die stack. The contour lid includes a first thermal conductive portion over the first die stack, a second thermal conductive portion over the second die stack, and a thermal barrier portion between the first thermal conductive portion and the second thermal conductive portion. The thermal barrier portion includes a low thermal conductivity material. | 2017-06-08 |
20170162543 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip adjacent a second semiconductor chip. The first semiconductor chip includes a first surface and a second surface. The second semiconductor chip includes a third surface and a fourth surface. The third surface faces the second surface. A first through-electrode and a second through-electrode are between the first and second surfaces. A third through-electrode is between the third surface and the fourth surface and is connected to the first through-electrode. A fourth through-electrode is between the third surface and the fourth surface and is connected to the second through-electrode. An end of the first through-electrode has a first magnetic polarity on the second surface, and an end of the second through-electrode has a second magnetic polarity opposite to the first magnetic polarity on the second surface. | 2017-06-08 |
20170162544 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device, enhanced with process capability and reliability by way of flow control of an adhesive material to fix semiconductor chips. The semiconductor device includes a first semiconductor chip including a first surface and a second surface opposite to each other, a flow regulating structure formed at the first surface of the first semiconductor chip, and a second semiconductor chip mounted on the first surface of the first semiconductor chip. The second semiconductor chip overlaps at least a portion of the flow regulating structure. | 2017-06-08 |
20170162545 | STACKED SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a vertical direction. The thermal-mechanical bumps are disposed in bump layers between the semiconductor dies. Fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations. | 2017-06-08 |
20170162546 | SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS - Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. | 2017-06-08 |
20170162547 | Solid State Light Fixtures Suitable for High Temperature Operation Having Separate Blue-Shifted-Yellow/Green and Blue-Shifted-Red Emitters - Solid state light fixtures include a plurality of blue-shifted-yellow/green light emitting diode (“LED”) packages and a plurality of blue-shifted-red LED packages, where the solid state light fixture emits light having a correlated color temperature of between 1800 K and 5500 K, a CRI value of between 80 and 99, a CRI R9 value of between 15 and 75, and a Qg value of between 90 and 110 when the blue-shifted-yellow/green LED packages and the blue-shifted-red LED packages are operating at steady-state operating temperatures of at least 80° C. | 2017-06-08 |
20170162548 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM HAVING THE SAME - The present invention provides a light emitting device comprising a first light emitting portion that emits white light at a color temperature of 6000K or more and a second light emitting portion that emits white light at a color temperature of 3000K or less, which include light emitting diode chips and phosphors and are independently driven. The present invention has an advantage in that a light emitting device can be diversely applied in a desired atmosphere and use by realizing white light with different light spectrums and color temperatures. Particularly, the present invention has the effect on health by adjusting the wavelength of light or the color temperature according to the circadian rhythm of humans. | 2017-06-08 |
20170162549 | ELECTRONIC ASSEMBLIES - The electronic assemblies described in this specification are characterized by a non-planar low-temperature co-fired ceramic substrate on which an electronic device is mounted. | 2017-06-08 |
20170162550 | Interconnect Structures For Assembly Of Semiconductor Structures Including At Least One Integrated Circuit Structure - A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corres ponding method for fabricating a semiconductor structure is also provided. | 2017-06-08 |
20170162551 | Semiconductor Device and Method of Manufactures - A semiconductor device and method of manufacture is provided. A reflowable material is placed in electrical connection with a through via, wherein the through via extends through an encapsulant. A protective layer is formed over the reflowable material. In an embodiment an opening is formed within the protective layer to expose the reflowable material. In another embodiment the protective layer is formed such that the reflowable material is extending away from the protective layer. | 2017-06-08 |
20170162552 | LASER LIFT-OFF ON ISOLATED III-NITRIDE LIGHT ISLANDS FOR INTER-SUBSTRATE LED TRANSFER - A laser liftoff process is provided. A device layer can be provided on a transfer substrate. Channels can be formed through the device layer such that devices comprising remaining portions of the device layer are laterally isolated from one another by the channels. The transfer substrate can be bonded to a target substrate through an adhesion layer. Surface portions of the devices can be removed from an interface region between the transfer substrate and the devices by irradiating a laser beam through the transfer substrate onto the devices. The laser irradiation decomposes the III-V compound semiconductor material. The channels provide escape paths for the gaseous products (such as nitrogen gas) that are generated by the laser irradiation. The transfer substrate is separated from a bonded assembly including the target substrate and remaining portions of the devices. The devices can include a III-V compound semiconductor material. | 2017-06-08 |
20170162553 | LED DISPLAY WITH WAVELENGTH CONVERSION LAYER - A display and method of manufacture are described. The display may include a substrate including an array of pixels with each pixel including multiple subpixels, and each subpixel within a pixel is designed for a different color emission spectrum. An array of micro LED device pairs are mounted within each subpixel to provide redundancy. An array of wavelength conversion layers comprising phosphor particles are formed over the array of micro LED device pairs for tunable color emission spectrum. | 2017-06-08 |
20170162554 | SELF-ALIGNED THREE DIMENSIONAL CHIP STACK AND METHOD FOR MAKING THE SAME - Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip. | 2017-06-08 |
20170162555 | SOLDER COMPOSITION AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Solder compositions for semiconductor fabrication are provided that include silver (Ag) of 3.0 wt. % to 4.0 wt. %, copper (Cu) of 0.75 wt. % to 1.0 wt. %, nickel (Ni) of 0.08 wt. % to 1.0 wt. %, and tin (Sn) of 94 wt. % to 96.17 wt. %, or that include bismuth (Bi) of 0.3 wt. % to 2.0 wt. % in place of a portion of the tin (Sn) in the solder composition; and, semiconductor packages are also provided that use the solder compositions for bonding one or more components of the semiconductor packages to each other. | 2017-06-08 |
20170162556 | SEMICONDUCTOR ASSEMBLY HAVING ANTI-WARPING CONTROLLER AND VERTICAL CONNECTING ELEMENT IN STIFFENER - A semiconductor assembly includes an anti-warping controller, a semiconductor device, a balance layer and a first routing circuitry positioned within a through opening of a stiffener and a second routing circuitry positioned outside of the through opening of the stiffener and electrically connected to the first routing circuitry and a vertical connecting element of the stiffener. The mechanical robustness of the stiffener and the anti-warping controller can prevent the assembly from warping, whereas the vertical connecting element of the stiffener provides electrical connection between two opposite sides of the stiffener. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener. | 2017-06-08 |
20170162557 | TRENCH BASED CHARGE PUMP DEVICE - A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region. | 2017-06-08 |
20170162558 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers. | 2017-06-08 |
20170162559 | INTEGRATED VERTICAL SHARP TRANSISTOR AND FABRICATION METHOD THEREOF - The present invention relates to vertical integrated, quantized FET with sharp drain and BJT with sharp emitter implemented in one nano-BiCMOS process, using multiple identical single crystalline semiconductor pyramids, placed in-situ directly on the surface of diffusion regions. The devices' gate and base structures are formed at a level of 35-45 nm below the top of the pyramids. The bottom region of the pyramids contains the collector/source structures, while the top region of the pyramids contains the emitter/drain structures. The base structure for BJT is formed by selective epitaxial growth of Si—Si | 2017-06-08 |
20170162560 | SEMICONDUCTOR DEVICE - A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface side of a first conductivity-type substrate, a second conductivity-type base region formed on an upper surface side of the substrate, a second conductivity-type collector layer formed on a lower surface side of the substrate, and a diode region having a second conductivity-type anode layer formed on the upper surface side of the substrate and a first conductivity-type cathode layer formed on the lower surface side of the substrate, wherein the cathode layer is separated from the active region when planarly viewed, and on an upper surface side of the active region, a second conductivity type high-concentration region having an impurity concentration higher than that of the anode layer is formed. | 2017-06-08 |
20170162561 | Reverse Bipolar Junction Transistor Integrated Circuit - A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P− epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P− type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation. | 2017-06-08 |
20170162562 | SEMICONDUCTOR DEVICE - An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer. | 2017-06-08 |
20170162563 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers. | 2017-06-08 |
20170162564 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET. | 2017-06-08 |
20170162565 | STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES - A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends. | 2017-06-08 |
20170162566 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench. | 2017-06-08 |
20170162567 | SELF HEATING REDUCTION FOR ANALOG RADIO FREQUENCY (RF) DEVICE - A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer. | 2017-06-08 |
20170162568 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material. | 2017-06-08 |
20170162569 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 2017-06-08 |
20170162570 | Complementary Transistor Pair Comprising Field Effect Transistor Having Metal Oxide Channel Layer - A complementary transistor pair with an n-type enhancement-mode field effect transistor and a p-type field effect transistor is disclosed. The n-type enhancement-mode field effect transistor uses a metal oxide channel layer having a material selected from SnO | 2017-06-08 |
20170162572 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment. | 2017-06-08 |