23rd week of 2011 patent applcation highlights part 47 |
Patent application number | Title | Published |
20110136296 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device. The method includes: providing a first substrate where an active layer is formed on a buried insulation layer; forming a gate insulation layer on the active layer; forming a gate electrode on the gate insulation layer; forming a source/drain region on the active layer at both sides of the gate electrode; exposing the buried insulation layer around a thin film transistor (TFT) including the gate electrode and the source/drain region; forming an under cut at the bottom of the TFT by partially removing the buried insulation layer; and transferring the TFT on a second substrate. | 2011-06-09 |
20110136297 | INTEGRATED CIRCUIT CHIP THAT SUPPORTS THROUGH-CHIP ELECTROMAGNETIC COMMUNICATION - One embodiment of the present invention provides an integrated circuit chip, including an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The integrated circuit chip additionally comprises an electromagnetic via that facilitates communication between signal pads on the integrated circuit chip and signal pads on a second integrated circuit chip. The electromagnetic via couples a signal pad on the active face of the integrated circuit chip to the back face of the integrated circuit chip so that the integrated circuit chip can communicate with the second integrated circuit chip while the back face of the integrated circuit chip is adjacent to the active face of the second integrated circuit chip. Moreover, the electromagnetic via operates by facilitating non-conductive signaling through the integrated circuit chip. | 2011-06-09 |
20110136298 | METHOD OF MANUFACTURING A WIRING BOARD - A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires. | 2011-06-09 |
20110136299 | LEADFRAME FOR LEADLESS PACKAGE, STRUCTURE AND MANUFACTURING METHOD USING THE SAME - A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins. | 2011-06-09 |
20110136300 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE USING LASER ANNEALING FOR SELECTIVELY ACTIVATING IMPLANTED DOPANTS - A method for producing a semiconductor device such as a RC-IGBT or a BIGT having a patterned surface wherein partial regions doped with dopants of a first conductivity type and regions doped with dopants of a second conductivity type are on a same side of a semiconductor substrate is proposed. An exemplary method includes: (a) implanting dopants of the first conductivity type and implanting dopants of the second conductivity type into the surface to be patterned; (b) locally activating dopants of the first conductivity type by locally heating the partial region of the surface to be patterned to a first temperature (e.g., between 900 and 1000° C.) using a laser beam similar to those used in laser annealing; and (c) activating the dopants of the second conductivity type by heating the substrate to a second temperature lower than the first temperature (e.g., to a temperature below 600° C.). Boron is an exemplary dopant of the first conductivity type, and phosphorous is an exemplary dopant of the second conductivity type. Boron can be activated in the regions irradiated only with the laser beam, whereas phosphorus may be activated in a low temperature sintering step on the entire surface. | 2011-06-09 |
20110136301 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. | 2011-06-09 |
20110136302 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. | 2011-06-09 |
20110136303 | Method and Apparatus for Manufacturing Thin-Film Transistor - A method and apparatus of fabricating a thin film transistor is disclosed, which patterns an ohmic contact layer by a laser patterning process so that it is capable of preventing a semiconductor layer from being damaged, and reducing fabrication time, wherein the method comprises forming a gate electrode pattern on a substrate; forming a gate insulating layer on the gate electrode pattern; sequentially forming a semiconductor layer pattern and an ohmic contact layer pattern on the gate insulating layer; forming source and drain electrode patterns on the ohmic contact layer pattern, wherein the source and drain electrode patterns are provided at a fixed interval therebetween; and removing the ohmic contact layer pattern exposed between the source and drain electrode patterns through the use of laser. | 2011-06-09 |
20110136304 | Techniques to Enhance Selectivity of Electrical Breakdown of Carbon Nanotubes - Techniques are used to fabricate carbon nanotube devices. These techniques improve the selective removal of undesirable nanotubes such as metallic carbon nanotubes while leaving desirable nanotubes such as semiconducting carbon nanotubes. In a first technique, slot patterning is used to slice or break carbon nanotubes have a greater length than desired. By altering the width and spacing of the slotting, nanotubes have a certain length or greater can be removed. Once the lengths of nanotubes are confined to a certain or expected range, the electrical breakdown approach of removing nanotubes is more effective. In a second technique, a Schottky barrier is created at one electrode (e.g., drain or source). This Schottky barrier helps prevent the inadvertent removal the desirable nanotubes when using the electrical breakdown approach. The first and second techniques can be used individually or in combination with each other. | 2011-06-09 |
20110136305 | Group III Nitride Semiconductor Devices with Silicon Nitride Layers and Methods of Manufacturing Such Devices - Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer. | 2011-06-09 |
20110136306 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes oxidizing a surface of a semiconductor substrate to form a first insulating film covering a first area, a second area, and a third area of the semiconductor substrate; removing the portions of the first insulating film lying on the first area and the second area; oxidizing the surface of the semiconductor substrate to form a second insulating film covering the first area and the second area and further oxidizing the third area covered with the first insulating film; and removing the portion of the second insulating film lying on from the second area and the portion of the first insulating film lying on the third area. | 2011-06-09 |
20110136307 | SEMICONDUCTOR DEVICE HAVING BUFFER LAYER BETWEEN SIDEWALL INSULATING FILM AND SEMICONDUCTOR SUBSTRATE - A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate. | 2011-06-09 |
20110136308 | SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate. | 2011-06-09 |
20110136309 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - In one embodiment, a method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming disposable dielectric stack overlying a substrate. The method also includes forming the trench regions adjacent to the disposable dielectric stack. After the insulated gate electrodes are formed, the method includes removing the disposable dielectric stack, and then forming spacers adjacent the insulated gate electrodes. The method further includes using the spacers to form recessed regions in the insulated gate electrodes and the substrate, and then forming enhancement regions in the first and second recessed regions. | 2011-06-09 |
20110136310 | METHOD OF FORMING AN INSULATED GATE FIELD EFFECT TRANSISTOR DEVICE HAVING A SHIELD ELECTRODE STRUCTURE - A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and dielectric plugs are formed in the first recessed regions using the first layer as a stop layer. The first layer is then removed, and spacers are formed adjacent the dielectric plugs. Second recessed regions are formed in the substrate self-aligned to the spacers. | 2011-06-09 |
20110136311 | SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device having a locally buried insulation layer and a method of manufacturing a semiconductor device having the same are provided, in which a gate electrode is formed on a substrate, and oxygen ions are implanted into an active region to form a locally buried insulation layer. An impurity layer is formed on the locally buried insulation layer to form a source/drain. A silicide layer is formed on the source/drain and on the gate electrode. The locally buried insulation layer can prevent junction leakage, decrease junction capacitance and prevent a critical voltage of an MOS transistor from increasing due to body bias, thereby to improve characteristics of the device. | 2011-06-09 |
20110136312 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - The disclosure pertains to a semiconductor device and its manufacture method, the semiconductor device including non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. A semiconductor device and its manufacture method are to be provided, the semiconductor device having memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate ( | 2011-06-09 |
20110136313 | Methods of Forming CMOS Transistors with High Conductivity Gate Electrodes - Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region. | 2011-06-09 |
20110136314 | SYSTEMS AND METHODS FOR REDUCING CONTACT TO GATE SHORTS - A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the gate and the contact. The insulator may be formed by oxidizing the gate to form a dielectric between the contact and the gate after the contact is formed on the gate. | 2011-06-09 |
20110136315 | Multi-Level Phase Change Memory - A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments. | 2011-06-09 |
20110136316 | PHASE CHANGE MEMORY DEVICE IN WHICH A PHASE CHANGE LAYER IS STABLY FORMED AND PREVENTED FROM LIFTING AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions; a lower electrode formed in each of the phase change cell regions on the semiconductor substrate; an insulation layer formed on the semiconductor substrate to cover the lower electrode and defined with a contact hole which exposes the lower electrode; a heater formed in the contact hole; a conductive pattern formed on the insulation layer to be spaced apart from the heater; a phase change layer formed on the heater, the conductive pattern, and portions of the insulation layer between the heater and the conductive pattern; and an upper electrode formed on the phase change layer. This phase change memory device allows the phase change layer to be stably formed and prevents the phase change layer from lifting | 2011-06-09 |
20110136317 | Semiconductor device, method of fabricating the same, and semicondutor module, electronic circuit board, and electronic system including the device - Example embodiments relate to a semiconductor device including an oxide dielectric layer and a non-oxide dielectric layer, a method of fabricating the device, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device may include a lower electrode, an oxide dielectric layer disposed on the lower electrode, a non-oxide dielectric layer disposed on the oxide dielectric layer, and an upper electrode disposed on the non-oxide dielectric layer. | 2011-06-09 |
20110136318 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING OPTICAL DEVICES - Provided is a method of manufacturing a semiconductor device. According to the method, a first buried oxide layer is formed in the semiconductor substrate in a first region, such that a first semiconductor layer is defined on the first buried oxide layer. An active portion is defined by forming a trench in the semiconductor substrate in a second region. A capping semiconductor pattern is formed on a top surface and an upper portion of a sidewall of the active portion. An oxide layer is formed by oxidizing the capping semiconductor pattern and an exposed lower portion of the sidewall of the active portion, such that the oxide layer surrounds a non-oxidized portion of the active portion. The non-oxidized portion of the active portion is a core and one end of the core is connected to a first optical device formed at the first semiconductor. | 2011-06-09 |
20110136319 | Methods Of Forming Isolation Structures, And Methods Of Forming Nonvolatile Memory - Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another. | 2011-06-09 |
20110136320 | METHOD OF MANUFACTURING SOI SUBSTRATE - To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOL substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered. | 2011-06-09 |
20110136321 | METHOD FOR MANUFACTURING LAMINATION TYPE SEMICONDUCTOR INTEGRATED DEVICE - Provided is a method for manufacturing a lamination type semiconductor integrated device that can simultaneously attain grinding force resistance during back side grinding of a semiconductor wafer, heat resistance during anisotropic dry etching and the like, chemical resistance during plating and etching, smooth debonding of a support substrate for processing at the end, and low adherend staining; the method comprises at least a step of back side grinding of a first semiconductor wafer having a device formed on its surface and a step of laminating by electrical bonding the first semiconductor wafer with a second semiconductor wafer having a device formed on its surface, wherein, at the time of back side grinding of the first semiconductor wafer, back of the first semiconductor wafer is ground after surface of formed device on the first semiconductor wafer is bonded to a support substrate for processing by using a pressure-sensitive silicone adhesive. | 2011-06-09 |
20110136322 | Adhesive Sheet for a Stealth Dicing and a Production Method of a Semiconductor Wafer Device - An adhesive sheet is provided enabling to efficiently produce the very small size semiconductor chip by a stealth dicing method. An adhesive sheet for a stealth dicing includes a substrate and an adhesive layer formed on one side of the substrate, wherein a Young's modulus of the adhesive sheet at 23° C. is 200 to 600 MPa, and a storage elastic modulus of the adhesive layer at 23° C. is 0.10 to 50 MPa. | 2011-06-09 |
20110136323 | SEMICONDUCTOR DEVICE MANUFACTURING EQUIPMENT AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Semiconductor device manufacturing equipment in which in the process of dividing a substrate into individual semiconductor devices using a dicing blade, the possibility of an odd piece flying off a supporting member is prevented. A supporting member supports a substrate for semiconductor devices on one surface thereof. A dicing blade dices the substrate supported by the supporting member along dicing lines provided on the substrate to divide the substrate into a plurality of semiconductor devices. In a plan view, the edge of the supporting member's surface supporting the substrate overlaps a semiconductor device located at an outermost position of the substrate and lies inside a dicing line at an outermost position of the substrate. | 2011-06-09 |
20110136324 | SEMICONDUCTOR DICE TRANSFER-ENABLING APPARATUS AND METHOD FOR MANUFACTURING TRANSFER-ENABLING APPARATUS - A transfer-enabling apparatus, produced by a method of manufacturing, includes a substrate patterned with islands separated by trenches and an epitaxial layer, grown at least on the islands, providing semiconductor dice in such a configuration partially released from said substrate and suspended over the substrate, and interconnected, by anchors of epitaxial or other material that are attached to the substrate. The anchors are of width less than or equal to than the semiconductor dice and define fracture zones at connections of the anchors with the semiconductor dice. | 2011-06-09 |
20110136325 | Method for fabricating a monolithic integrated composite group III-V and group IV semiconductor device - According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT). | 2011-06-09 |
20110136326 | PILLAR DEVICES AND METHODS OF MAKING THEREOF - A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings. | 2011-06-09 |
20110136327 | HIGH MOBILITY MONOLITHIC P-I-N DIODES - Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers. | 2011-06-09 |
20110136328 | METHOD FOR DEPOSITING ULTRA FINE GRAIN POLYSILICON THIN FILM - According to the present invention, a method for depositing an ultra-fine crystal particle polysilicon thin film supplies a source gas in a chamber loaded with a substrate to deposit a polysilicon thin film on the substrate, wherein the source gas contains a silicon-based gas, an oxygen-based gas and a phosphorous-based gas. The mixture ratio of the oxygen-based gas to the silicon-based gas may be 0.15 or lower (but, excluding zero). Oxygen in the thin film may be 0.8 atomic percent or lower (but, excluding zero). | 2011-06-09 |
20110136329 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes preparing a semiconductor substrate which is a base substrate of the semiconductor device and which is formed with a concavity and convexity part on the surface of the semiconductor substrate. The method further comprises depositing on the surface of the semiconductor substrate an impurity thin film including an impurity atom which becomes a donor or an acceptor in the semiconductor substrate and performing an ion implantation from a diagonal upper direction to the impurity thin film deposited on the concavity and convexity part of the semiconductor substrate. The method still further comprises recoiling the impurity atom from the inside of the impurity thin film to the inside of the concavity and convexity part by performing the ion implantation. | 2011-06-09 |
20110136330 | Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof - A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines. | 2011-06-09 |
20110136331 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on a second region of the semiconductor substrate; and a second gate electrode on the second gate insulating film. The first gate insulating film includes a first insulating film composed of a first material containing a first metal, and the second gate insulating film includes a second insulating film composed of the first material and a second material containing a second metal. | 2011-06-09 |
20110136332 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES - A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer. | 2011-06-09 |
20110136333 | SEMICONDUCTOR MATERIALS AND METHODS OF PREPARATION AND USE THEREOF - Disclosed are new semiconductor materials prepared from dimeric perylene compounds. Such compounds can exhibit high n-type carrier mobility and/or good current modulation characteristics. In addition, the compounds of the present teachings can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions. | 2011-06-09 |
20110136334 | METHOD OF FORMING AT LEAST ONE BONDING STRUCTURE - A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad. | 2011-06-09 |
20110136335 | Semiconductor Device with Improved Contacts - A device with a solder joint made of a copper contact pad ( | 2011-06-09 |
20110136336 | METHODS OF FORMING CONDUCTIVE VIAS - Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer. | 2011-06-09 |
20110136337 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss. | 2011-06-09 |
20110136338 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent. | 2011-06-09 |
20110136339 | CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER - A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture. The manganese layer and the planarized copper containing conductor layer are then thermally oxidized to form a manganese oxide layer self aligned to a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. | 2011-06-09 |
20110136340 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask. | 2011-06-09 |
20110136341 | FIELD EFFECT TRANSISTOR HAVING MULTIPLE PINCH OFF VOLTAGES - A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths. | 2011-06-09 |
20110136342 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate. | 2011-06-09 |
20110136343 | COMPOSITION AND METHOD FOR LOW TEMPERATURE DEPOSITION OF SILICON-CONTAINING FILMS - This invention relates to silicon precursor compositions for forming silicon-containing films by low temperature (e.g., <300° C.) chemical vapor deposition processes for fabrication of ULSI devices and device structures. Such silicon precursor compositions comprise at least one disilane derivative compound that is fully substituted with alkylamino and/or dialkylamino functional groups. | 2011-06-09 |
20110136344 | COMPOSITION AND METHOD FOR POLISHING POLYSILICON - The invention provides a polishing composition comprising silica, an aminophosphonic acid, a polysaccharide, a tetraalkylammonium salt, a bicarbonate salt, an azole ring, and water, wherein the polishing composition has a pH of about 7 to about 11. The invention further provides a method of polishing a substrate with the polishing composition. | 2011-06-09 |
20110136345 | Process for the Manufacture of Etched Items - C4 compounds selected from the group of trifluorobutadienes and tetrafluorobutenes can be used as etching gases, especially for anisotropic etching in the production of etched items, for example, of semiconductors, e.g. semiconductor memories or semiconductor logic circuits, flat panels, or solar cells. Preferred compounds are 1,1,3-trifluoro-1,3-butadiene, (E)-1,1,1,3-tetrafluoro-2-butene, 2,4,4,4-tetrafluoro- | 2011-06-09 |
20110136346 | Substantially Non-Oxidizing Plasma Treatment Devices and Processes - Non-oxidizing plasma treatment devices for treating a semiconductor workpiece generally include a substantially non-oxidizing gas source; a plasma generating component in fluid communication with the non-oxidizing gas source; a process chamber in fluid communication with the plasma generating component, and an exhaust conduit centrally located in a bottom wall of the process chamber. In one embodiment, the process chamber is formed of an aluminum alloy containing less than 0.15% copper by weight; In other embodiments, the process chamber includes a coating of a non-copper containing material to prevent formation of copper hydride during processing with substantially non-oxidizing plasma. In still other embodiments, the process chamber walls are configured to be heated during plasma processing. Also disclosed are non-oxidizing plasma processes. | 2011-06-09 |
20110136347 | POINT-OF-USE SILYLAMINE GENERATION - The production and delivery of a reaction precursor containing one or more silylamines near a point of use is described. Silylamines may include trisilylamine (TSA) but also disilylamine (DSA) and monosilylamine (MSA). Mixtures involving two or more silylamines can change composition (e.g. proportion of DSA to TSA) over time. Producing silylamines near a point-of-use limits changing composition, reduces handling of unstable gases and reduces cost of silylamine-consuming processes. | 2011-06-09 |
20110136348 | PHONON-ENHANCED CRYSTAL GROWTH AND LATTICE HEALING - A system for modifying dislocation distributions in semiconductor materials is provided. The system includes one or more vibrational sources for producing at least one excitation of vibrational mode having phonon frequencies so as to enhance dislocation motion through a crystal lattice. | 2011-06-09 |
20110136349 | FLEXIBLE BATTERY CONNECTOR - A battery connector including an electrical connector including a plurality of terminals, each mechanically and electrically connectable with a battery, the terminals being in electrical communication with each other and mechanically connected to each other with a joint member that permits flexing the batteries with respect to one another. | 2011-06-09 |
20110136350 | Magnetic and Locking Cable Connectors - In embodiments of the present invention improved capabilities are described for a cable connector. The cable connector may have magnetic properties and/or a locking mechanism. The cable connector may be an HDMI connector and the cable may be an HDMI cable. Further, the connector may be plugged into the corresponding male/female connector port and be held in position by the magnetic properties associated with the connector and the port and/or by a lock lever mechanism. The magnetic array may be moved various distances in various directions. In addition, the connector and/or cable may include a processor, an integrated circuit, an indicator, an LED and/or a user interface. | 2011-06-09 |
20110136351 | MAGNETIC CONNECTOR FOR ELECTRONIC DEVICE - An electrical plug and receptacle relying on magnetic force from an electromagnet to maintain contact are disclosed. The plug and receptacle can be used as part of a power adapter for connecting an electronic device, such as a laptop computer, to a power supply. The plug includes electrical contacts, which are preferably biased toward corresponding contacts on the receptacle. The plug and receptacle each have a magnetic element. The magnetic element on one of the plug or receptacle can be a magnet or ferromagnetic material. The magnetic element on the other of the plug or receptacle is an electromagnet. When the plug and receptacle are brought into proximity, the magnetic attraction between the electromagnet magnet and its complement, whether another magnet or a ferromagnetic material, maintains the contacts in an electrically conductive relationship. | 2011-06-09 |
20110136352 | USB DEVICE - A USB device is provided. The USB device includes a housing, a circuit board, a chip, a USB connector and a metal connector. The circuit board is disposed in the housing. The chip is disposed on the circuit board. The USB connector is connected to the circuit board. The metal connector is connected to the USB connector, wherein the metal connector includes an extended portion, and the extended portion contacts the chip to dissipate heat from the chip. | 2011-06-09 |
20110136353 | APPARATUS AND METHOD FOR SCALABLE POWER DISTRIBUTION - In one aspect, the invention provides a system for power distribution. According to some embodiments, the system includes a rack mountable power distribution unit including a housing having a first end and a second end, the housing also including an outer wall defining a cavity within the housing, and fastening elements configured to allow the housing to be mounted within an electrical equipment rack. In accordance with these embodiments, the outer wall of the housing includes an opening extending linearly between the first end and the second end of the housing and a plurality of electrical conductors located within the cavity and oriented linearly between the first end and the second end. In accordance with further embodiments, the system includes a tap module including a plurality of contacts extending therefrom wherein each of the plurality of contacts is configured to be inserted into the opening before engaging one of the plurality of electrical conductors within the cavity, respectively. | 2011-06-09 |
20110136354 | ELECTRICAL PLUG HAVING ADJUSTABLE PRONGS - An electrical plug is provided. The plug includes a base, a cover, a live prong, a neutral prong, and a ground prong. The cover defines a first hole, a second hole, and a third hole through which the ground prong, the live prong, and the neutral prong, respectively extend. The ground prong includes a middle contact, a first contact including a first pin rotatably connected to the middle contact and a first blade fixed to the first pin, and a second contact including a second pin rotatably connected to the middle contact and a second blade fixed to the second pin. The first pin and the second pin are rotatably at opposite sides of the middle contact. The first blade and the second blade are on front and rear of the middle contact. | 2011-06-09 |
20110136355 | Port Attached To Flexible Mount - A system including a flexible mount that can be coupled to a computing device. A port can be attached to the flexible mount. The flexible mount can conform to the chassis of the computing device. | 2011-06-09 |
20110136356 | FLASH MEMORY DEVICE WITH SLIDABLE CONTACT MODULE - A flash memory device includes a circuit board and a contact module slidable with respect to the circuit board. The circuit board includes a plurality of first contacts each having a stiff first contact portion. The contact module includes a slider and a plurality of second contacts fixed to the slider. The slider is slidable with respect to the circuit board along a front-to-rear direction between a first position and a second position. The flash memory device is compatible to USB 2.0 and USB 3.0 receptacle connectors via the slidable contact module. | 2011-06-09 |
20110136357 | DATA STORAGE DEVICE AND PRINTING APPARATUS INCLUDING THE SAME - A data storage device is provided. At least a storage section configured to store information therein and a connection terminal configured to transmit information are mounted on a substrate. A casing accommodates the substrate, the casing is formed with an opening to expose a connection portion of the connection terminal to the outside. A shield plate configured to shield the opening of the casing. A shield plate actuation mechanism is configured to detect a connection state between the connection terminal and a receiving terminal to which the connection terminal is connected and actuate the shield plate. The shield plate actuation mechanism actuates the shield plate to shield the opening when the shield plate actuation mechanism detects that the connection terminal is separated from the receiving terminal. | 2011-06-09 |
20110136358 | SAFETY STRUCTURE FOR ELECTRIC RECEPTACLES AND POWER STRIPS - A symmetrically movable safety structure disposed inside of an upper lid of a power panel, includes a cover plate disposed with a jack corresponding to the upper lid, a first shielding part and a second shielding part, disposed within the cover plate, where a first bonding position and a second bonding position corresponding to the jack are formed at a contacting place of the above two shielding parts, and a first elastic part and a second elastic part, wherein the first elastic part is disposed between the cover plate and the first shielding part, the second elastic part is disposed between the cover plate and the second shielding part, and the first shielding part and the second shielding part contact with each other under elastic force application directions. | 2011-06-09 |
20110136359 | GUITAR END PIN JACK PLUG - A guitar end pin jack plug device is described which is mated with an end pin jack while the electrical plug is not mated with the end pin jack, for the purpose of preventing a support strap from coming off of the end pin jack. The present invention has a shaft which is inserted into and is retained by the end pin jack. The present invention also has a head which is of sufficient diameter to prevent the opening in the strap from coming completely off of the end pin jack. The present invention is much simpler than the prior art and is less subject to becoming ineffective over time as it is used and worn as compared to the prior art. While the present invention is described as being used on guitar end pin jacks, it is not limited to use with guitars. The present invention may be used on any article with similar jacks and support straps. | 2011-06-09 |
20110136360 | ELECTRICAL CARD CONNECTOR - An electrical card connector ( | 2011-06-09 |
20110136361 | Light String System - A lamp system used in a light string system comprises a light assembly and a socket assembly. The light assembly comprises a light source, a base in communication with the light source, and a bypass activating system. The socket assembly comprises a socket adapted to receive the light assembly and a bypass mechanism having a first position and a second position. The bypass mechanism is in the first position when the light assembly is not seated in the socket assembly. When the bypass mechanism in the first position, current flows across the bypass mechanism. When the light assembly is inserted into the socket assembly, the bypass activating system of the light assembly moves the bypass mechanism into the second position, and current flows through the light source instead of the bypass mechanism. | 2011-06-09 |
20110136362 | JOINT-PACK INTEGRATED SPACERS - A joint pack includes one or more phase members that utilize integrated standoff spacers that protrude and come into contact with opposing conductor plates to maintain a phase space between the phase members. The spacers are located along the insulating plates of the phase members away from the phase member's axial sleeves and protrude through apertures in the conductor plates disposed on the phase members, in which the standoff spacers also provide a barrier that prevents phase-conductors from being inserted too far within the phase space. The phase members include axial sleeves that fit within one another during assembly to form a nesting arrangement, thereby reducing the overall size of the joint pack while satisfying standards. The axial sleeves can be distinctively designed such that the phase members must be assembled in a predetermined order, with no components being omitted, to form the joint pack. | 2011-06-09 |
20110136363 | CONNECTOR DEVICE FOR CONNECTING A COLD CATHODE OF A NEON OR FLUORESCENT-TUBE LAMP TO A SUPPLY CABLE - The present application relates to a connector device for connecting a cold cathode of a neon or fluorescent tube lamp to a supply cable comprises a first body in form of a tubular housing, inside which a metal sheet is provided having elastically deflectable teeth for engaging one end of the fluorescent tube. A second body of the connector device is associated to one end of the supply cable. The first and second bodies are respectively provided with first and second coupling elements in form of two concentric cylindrical rings made of an electrically conductive material, which engage one inside the other in the coupled condition of the first and second bodies. In this engagement condition, the two concentric rings lock therebetween bent terminal portions of a first wire connected to the electrode of the fluorescent tube and a second wire forming part of the supply cable. | 2011-06-09 |
20110136364 | ELECTRICAL CONNECTORS - An electrical connector ( | 2011-06-09 |
20110136365 | ELECTRICAL CONNECTOR - An electrical connector including a housing provided with an opening through which a flat circuit device is inserted into the housing, a plurality of conductive contacts arranged on the housing, and reinforcing mount members provided respectively on end portions of the housing in its longitudinal direction to be used for mounting the housing on a solid circuit board, wherein a holding member is formed in the reinforcing mount member to extend into the housing for engaging with the flat circuit device inserted in the housing to hold the same, a releasing member is formed in the housing to be movable with a first end portion thereof operative to project out of the housing and a second end portion thereof operative to engage with the holding member, and the releasing member is moved so that the second end portion of the releasing member causes the holding member to be released from engagement with the flat circuit device inserted in the housing when the first end portion of the releasing member is pushed toward the inside of the housing under a condition wherein the holding member is put in the engagement with the flat circuit device to hold the same in the housing. | 2011-06-09 |
20110136366 | Locking mechanism for a computer signal line connector - A locking mechanism for a computer signal line connector includes at least a housing, a circuit board and a cable, and can be inserted with a signal connection line between a computer motherboard and a hard disk. Above the housing is provided with a locking mechanism which is composed of a lock piece, an operation stick, a V-shape pad, and an upper housing having a trench corresponding to the V-shape pad. Upon assembling for use, the operation stick is pushed forward or pulled backward, allowing a front end of the lock piece above the operation stick to be lifted up for unlocking, in order to achieve an effect of assembling and applying conveniently. | 2011-06-09 |
20110136367 | PRINTED BOARD CONNECTOR WITH LOCKING DEVICE - In order to simplify the assembly of a shielded connector, it is proposed that an electrically insulating base body provided as a carrier for electric contacts features a mounting surface with two openings, wherein a recess that respectively features an integral collar on its inner side is respectively arranged around these openings. | 2011-06-09 |
20110136368 | ELECTRICAL CONNECTOR ASSEMBLY WTH COMPACT CONFIGURATION - An electrical connector assembly ( | 2011-06-09 |
20110136369 | MINIATURE ELECTRICAL CONNECTOR - In accordance with one aspect, a connector includes contacts meeting MIL-C-39029/57 or MIL-C-39029/58 without requiring a retaining clip to hold such contacts in place and without embedding such contacts in a plastic housing. The contacts are attached to electrical power or data conductors and loaded into apertures in a rear and front insert. The rear and front insert are held together by a rear and front shell so the contacts remain secure in the apertures. In accordance with another aspect, a latching mechanism provides a robust, reliable mechanism for securing a socket portion of a connector to a plug portion of a connector. | 2011-06-09 |
20110136370 | CONNECTING STRUCTURE OF A LAMP HEAD BASE AND A LAMP TUBE BASE - The present invention relates to a connecting structure of a lamp head base ( | 2011-06-09 |
20110136371 | CONNECTOR AND OPERATING METHOD THEREOF - A connector is provided. The connector includes a connector body, a signal transmitting unit, a cover, a fastening plate, and an extension plate. The connector body has side walls to enclose an assembly hole. The signal transmitting unit is disposed in the assembly hole. The cover has a first end, a second end, and a first pivot and is disposed outside the assembly hole. The first end and the first pivot are disposed on two ends of a side case of the cover. The second end is opposite to the first end while the first pivot is axially connected to one side of the assembly hole. The fastening plate has a second pivot opposite and parallel to the first pivot. The second pivot axially connected to the side wall around the assembly hole. One end of the extension plate has a third pivot parallel to the first pivot and is rotatably connected to the fastening plate. The other end of the extension plate has a pressing portion to press the second end of the cover from outside to make the cover rotates toward the connector body and press the signal transmitting unit. | 2011-06-09 |
20110136372 | Communications Patching and Connector Systems Having Multi-Stage Near-End Alien Crosstalk Compensation Circuits - Communications patching devices include first and second connectors mounted immediately adjacent to each other. The first connector includes a first output terminal and a second output terminal that are connected to respective first and second conductive paths, and the second connector includes a third output terminal and a fourth output terminal that are connected to respective third and fourth conductive paths. The first and second conductive paths form a first differential pair of conductive paths and the first and second output terminals form a first differential pair of output terminals. The third and fourth conductive paths form a second differential pair of conductive paths, and the third and fourth output terminals form a second differential pair of output terminals. The output terminals are arranged such that a first signal coupling level from the first output terminal to the third output terminal in response to a communication signal that is transmitted through the first differential pair of output terminals exceeds a second signal coupling level from the first output terminal to the fourth output terminal in response to the communication signal. A first capacitor is provided between the first conductive path and the fourth conductive path and a second capacitor is provided between at least one of the first conductive path and the third conductive path or between the second conductive path and the fourth conductive path. | 2011-06-09 |
20110136373 | DATA CABLE - A data cable including an electrical line with a plurality of line leads, an electrical shield, a molded piece including first counterpart form-locking elements and a housing enclosing the molded piece, wherein the housing has a central opening. The data cable further including a plug connector disposed on an end of the data cable, wherein the plug connector is electrically connected to the shield, wherein the plug connector includes a bush that is enclosed by the molded piece. The bush includes a deep-drawn tube and a bead with second form-locking elements which with the counterpart form-locking elements form a first form-locking connection, wherein an outer contour of the molded piece and an inner contour of the central opening of the housing form a second form-locking connection. | 2011-06-09 |
20110136374 | SOCKET ASSEMBLY WITH A THERMAL MANAGEMENT STRUCTURE - A socket assembly includes a lighting package and a socket housing having a receptacle that removably receives the lighting package. A thermal management structure is coupled to the socket housing and is positioned at the receptacle in thermal engagement with the lighting package. The thermal management structure is configured to engage a heat sink to dissipate heat from the lighting package to the heat sink. Optionally, at least one of the socket housing and the thermal management structure may have mounting features configured to mount the socket assembly to a heat sink, where the lighting package is removable from the receptacle while the socket assembly remains mounted to the heat sink. The thermal management structure may be coupled to the socket housing such that the thermal management structure and the socket housing are coupled to a heat sink as a unit. | 2011-06-09 |
20110136375 | GUARDED COAXIAL CABLE ASSEMBLY - A guarded coaxial cable assembly including a micro-coaxial cable and at least one rail. | 2011-06-09 |
20110136376 | MODULAR LIMB SEGMENT CONNECTOR - A joint assembly for releasably securing a first and a second segment of an associated modular limb is provided. The joint assembly includes a male connector including a base and a load bearing blade secured to the base of the male connector protruding therefrom. The male connector is adapted to be secured to one of the first and second segments of the associated modular limb. A female connector is provided and includes a base and a load bearing socket secured to the base of the female connector. The socket is configured to selectively receive the blade of the male connector. The female connector is adapted to be secured to the other of the first and second segments of the associated modular limb. A locking member selectively retains the blade of the male connector in the socket of the female connector. The male connector, the female connector, and the locking member cooperate to form a resilient and selectively releasable modular limb joint. | 2011-06-09 |
20110136377 | ELECTRONIC CONNECTION BOX - An electric connection box includes: a case and a wired insulating plate with electric wires laid thereon and accommodated in the case. The electric wires are respectively connected to a plurality of press-contact terminals secured on the wired insulating plate, the plurality of press-contact terminals project to the outside through the case on the side of a front surface of the wired insulating plate. The case integrally includes connector peripheral wall portions configured to surround the plurality of press-contact terminals projecting to the outside. The electric connection box also includes joining and fixing portions positioned on both sides of an alignment of the plurality of press-contact terminals in the longitudinal direction that fix the wired insulating plate and the case with respect to each other. | 2011-06-09 |
20110136378 | METHOD OF INSTALLING ANTENNA AND COAXIAL CONNECTOR - A coaxial connector to be attached to a coaxial change-over switch includes an insulated connector housing; an outer connector conductor provided outside the insulated connector housing and capable of connecting to an outer conductor of a coaxial cable; and a contact provided in the insulated connector housing to be movable for connecting to a center conductor of the coaxial cable. The contact has a first portion including a distal end portion and a second portion connected to the first portion via a bent section. | 2011-06-09 |
20110136379 | ELECTRICAL CONNECTOR - An electrical connector includes a plurality of terminals, a housing and a shield plate. The terminals are arranged and held in the housing. The shield plate is formed by bending a metal plate and attached to the housing. The housing includes a sidewall and an edge wall at an end portion of the sidewall. The shield plate includes a shield portion covering an outer surface of the sidewall and a held. The held portion is supported on a holding portion disposed on the edge wall of the housing. The shield portion includes a regulating portion capable of abutting against the outer surface of the sidewall. The regulating portion regulates deformation of the shield portion when the shield plate is attached to the housing. | 2011-06-09 |
20110136380 | ELECTRIC CONNECTOR - To make it possible to improve the grounding property of a conductive shell with a simple configuration. | 2011-06-09 |
20110136381 | BIDIRECTIONAL PLUG HAVING SHORT CIRCUIT PREVENTION CIRCUIT - Disclosed herein is a bidirectional plug having a short circuit prevention circuit. The bidirectional plug includes a body part, a terminal part, connecting terminals, and a short circuit prevention circuit. The terminal part is connected to one end of the body part, and is inserted into an interface port of a communication device. The connecting terminals are respectively provided on two opposite surfaces of the terminal part, and make contact with a connecting pin provided in the interface port regardless of a direction from which the terminal part is inserted. The short circuit prevention circuit prevents a remaining connecting terminal, provided on a surface of the terminal part which is not in contact with a connecting pin, from making electrical contact with a tension ground pin provided in the interface port. | 2011-06-09 |
20110136382 | INSERT AND METHOD OF ASSEMBLING SUCH AN INSERT - The insert includes at least three contacts having essentially linear parts and at least one three-pole capacitance between three of the contacts. One of the contacts of each three-pole capacitance is connected to a central armature. A first dimension of the central armature, in the direction perpendicular to the substantially linear parts, is greater than a second dimension, in a direction parallel to the substantially linear parts, the second dimension defining the widths of the zones of the central armature. The mean width of the central armature, between the zones where it faces other armatures, connected to the other contacts of the three-pole capacitance, is greater than one third of the mean length of the central armature in these regions. Preferably, in at least one three-pole capacitance, the mean width of the central armature between the regions where it faces the lateral armatures is greater than one third of the distance between the lateral armatures. | 2011-06-09 |
20110136383 | TERMINATING CONNECTOR - Provided is a terminating connector that can connect probes to a terminal connected with desired cable cores without removing the terminating connector. One aspect provides a terminating connector comprises a plurality of terminals having a contact portion and a lead wire contact portion, a housing having a plurality of probe insertion portions and receiving the terminals, and a resistor element received in the housing and electrically connected to the terminals, wherein at least a part of the terminals is positioned in the probe insertion portions. | 2011-06-09 |
20110136384 | HDMI CONNECTOR STRUCTURE - An HDMI connector structure includes a base, a circuit board, a chassis and a metal casing. The base includes a containing space, a retaining wall formed at a front end of the containing space, and an opening formed on the retaining wall. The circuit board is installed in the containing space, and an end of the circuit board is passed through the opening and out of the retaining wall, and at least one surface of the circuit board has a plurality of conductive pins, and a transmission line segment is extended from an end of each conductive pin and electrically coupled to a conductive terminal The metal casing includes a hollow main body, and the base is installed in the empty main body, and a front end of the hollow main body is provided for exposing a port from an end of the circuit board. | 2011-06-09 |
20110136385 | Battery cable with provisions for integral circuit protection - A battery cable circuits protection device ( | 2011-06-09 |
20110136386 | BATTERY CONNECTOR - A connector has an insulating housing defining a plurality of terminal receiving cavities each extending vertically to pass therethrough, a plurality of conductive terminals received in the terminal receiving cavities and a shell mounted to the insulating housing. A rear surface of the insulating housing is protruded outward to from a projection defining an inserting groove passing therethrough. The shell has a base board, a holding board facing the base board and a pair of sideboards connecting the base board and the holding board. Top edges of the base board and the holding board are extended towards each other to form eave portions. An inserting portion is extended from a portion of the base board. The shell encircles the insulating housing with the eave portions covering tops of two opposed sides of the insulating housing and the inserting portion being inserted into the inserting groove and further connected to ground. | 2011-06-09 |
20110136387 | CARD EDGE CONNECTOR - A connector comprises a housing, a lever and a lock portion. The housing receives terminals. The lever is rotatably attached to the housing, and is configured to be rotatable between a first position, where an initial stage of fitting of the connector to a counterpart connector is established, and a second position, where the fitting thereof to the counterpart connector is completed. The lock portion is capable of locking the lever at the second position. The lock portion is slidably attached to a body portion of the lever, and is configured to be slid between a lock position where the lever is locked and a lock release position where the lever is released. The lever is provided with a positioning latch-portion that is configured to latch the lock portion at the lock position and the lock release position. The positioning latch-portion is provided with a concaved latch-portion and a convexed latch-portion that is configured to be elastically displaced to be engaged in or disengaged from the concaved latch-portion. | 2011-06-09 |
20110136388 | STRADDLE CARD EDGE CONNECTOR - A card edge connector includes an elongated housing and a number of contacts retained in the housing. Each contact has a retaining portion retained in the housing, a contact portion forwardly extending from a front end of the retaining portion and a connecting portion backwardly extending from a rear end of the retaining portion. The contacts are arranged in two rows and formed with a first receiving space between two rows of contact portions to receive a module and a second receiving space between two rows of connecting portions to receive a mother board. The first receiving space defines a first centre line along an insertion direction of the module. The second receiving space defines a second centre line which is parallel to the first centre line and offset to the first centre line along an up to down direction perpendicular to the insertion direction. | 2011-06-09 |
20110136389 | Combination Electric Plug Assembly - A combination electric plug assembly includes an electric plug, which has an electrically insulative housing defining a front receiving chamber and a set of power terminals and a set of signal terminals mounted in the front receiving chamber, and an adapter which has an electrically insulative housing defining a receiving chamber for receiving the electrically insulative housing of the electric plug, an electrically insulative core member suspending in the electrically insulative housing and insertable into the front receiving chamber of the electric plug, and a set of terminal power terminals and a set of signal terminals respectively mounted in the electrically insulative core member and respectively soldered to a circuit board of an electronic apparatus for the contact of the power terminals and signal terminals of the electric plug for transmitting power supply and signal at the same time. | 2011-06-09 |
20110136390 | LED SOCKET ASSEMBLY - A socket assembly includes sockets ganged together to form a pod with each of the sockets comprising a socket housing having a first end and a second end. The socket housing has a receptacle and a power track routed along the socket housing between the first and second ends. The power track has a positive rail and a negative rail. The sockets also comprises an anode on the socket housing at the receptacle being electrically connected to the positive rail and a cathode on the socket housing at the receptacle being electrically connected to the negative rail. The power tracks of adjacent sockets within the pod are electrically connected together to form a power circuit. Light emitting diode (LED) packages are received in corresponding receptacles of the sockets, and each LED package has a first contact and a second contact configured to be coupled to the anode and cathode, respectively, when the LED package is received in the corresponding receptacle. Each LED package has a base and an LED mounted to the base and being electrically connected to the first and second contacts. Optionally, the anode may be electrically connected to the positive rail via at least one of the other sockets. The cathode may be electrically connected to the negative rail via at least one of the other sockets. | 2011-06-09 |
20110136391 | CONNECTOR - A connector includes plurality of terminal fittings, a terminal holding member for holding the plurality of terminal fittings, and an electric wire holding member which is attached to the terminal holding member and holds plural electric wires. The electric wire holding member has a plurality of electric wire holding parts which hold ends of the plurality of electric wires at the same spacing as intervals between the plurality of terminal fittings and also are arranged in parallel with space in a longitudinal direction of the plurality of terminal fittings, and an exposure part for exposing exposed portions of core wires of the plurality of electric wires to the outside in order to connecting the exposed portions to the plurality of terminal fittings. | 2011-06-09 |
20110136392 | PLUG - A plug includes a plug housing and a metal terminal group. The metal terminal group includes a mating electrode group on the first end side thereof and a connection electrode group on the second end side, the mating electrode group including mating electrode sections that are disposed with an insulating resin interposed therebetween and are to be in contact with the contacts of a mating jack, the connection electrode group including connection electrode sections that are disposed with an insulating resin interposed therebetween and are connected to the electrodes of a connection member. The mating electrode sections are disposed coaxially with an axis P of the plug, and at least two of the connection electrode sections are disposed around the axis P so as to surround the axis P side by side. | 2011-06-09 |
20110136393 | DISPLAYPORT STRUCTURE - An improved DisplayPort structure includes a base, a circuit board, a chassis and a casing. The base has a containing space, a retaining wall formed at a front end of the containing space, an opening formed on the retaining wall. The circuit board is installed in the containing space, and an end of the circuit board is passed through the opening and out of the retaining wall, and at least one surface of the circuit board has a plurality of conductive pins, and a transmission line segment is extended from an end of each conductive pin and electrically coupled to a conductive terminal The casing is mounted onto the exterior of the base and the casing includes a hollow main body, and a port is formed at a front end of the main body and provided for exposing the circuit board. | 2011-06-09 |
20110136394 | LED SOCKET ASSEMBLY - A socket assembly includes a light emitting diode (LED) package having an LED printed circuit board (PCB) with an LED mounted thereto. The LED package has a power contact configured to receive power from a power source to power the LED. The socket assembly also includes a socket housing having a receptacle that removably receives the LED package. The socket housing has a securing feature engaging the LED PCB to secure the LED PCB within the receptacle, where the securing feature is configured to release the LED PCB to remove the LED PCB from the receptacle. Optionally, the socket housing may include mounting features configured to mount the socket housing to a base, where the LED package is removable from the socket housing while the socket housing remains mounted to the base. A second LED package may be provided, where the LED package is removable from the receptacle and is replaced by the second LED package. | 2011-06-09 |
20110136395 | Terminal Box for Solar Cell Module - A terminal box for a solar cell module includes a box body | 2011-06-09 |