23rd week of 2016 patent applcation highlights part 63 |
Patent application number | Title | Published |
20160163624 | PACKAGE STRUCTURE - A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface opposite to the active surface and bonding pads disposed on the active surface. The substrate includes a first solder mask, a first patterned circuit layer and a core layer having a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The first solder mask disposed on the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the second surface exposes the bonding pads. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate. A top surface of the molding compound is coplanar with a top surface of the first solder mask. | 2016-06-09 |
20160163625 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively. | 2016-06-09 |
20160163626 | INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME - The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated. | 2016-06-09 |
20160163627 | INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME - An interposer substrate includes a first insulating layer having opposite first and second surfaces; a first wiring layer formed in the first insulating layer, with a surface of the first wiring layer exposed from the first surface; first conductive pillars formed in the first insulating layer; a second wiring layer formed on the second surface; second conductive pillars formed on the second wiring layer; a second insulating layer formed on the second surface and covering the second conductive pillars and the second wiring layer, with end surfaces of the second conductive pillars exposed from the second insulating layer; and immersion tin layers formed on the first wiring layer and the end surfaces of second conductive pillars. The immersion tin layers are used as surface processing layers to be applied to products having ball pads that need to be exposed extensively. A method for fabricating the interposer substrate is also provided. | 2016-06-09 |
20160163628 | PACKAGE SUBSTRATE COMPRISING CAPACITOR, REDISTRIBUTION LAYER AND DISCRETE COAXIAL CONNECTION - A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects. | 2016-06-09 |
20160163629 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a package structure is provided, including forming a plurality of conductive pillars on a conductive layer, forming an insulating layer on the conductive layer and the conductive pillars, removing a portion of the conductive layer to allow the remaining portion of the conductive layer to serve as a wiring layer, disposing at least one electronic component on the wiring layer, and forming on the wiring layer and insulation layer an encapsulating layer to encapsulate the electronic component. Therefore, as there is already a wiring layer the wiring layer is capable of being integrated with the electronic component for allowing the conductive pillars to be bonded with solder balls to thereby shorten the signal transmission path. The present invention further provides a package structure thus fabricated. | 2016-06-09 |
20160163630 | INTERPOSER WITH EXTRUDED FEED-THROUGH VIAS - A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer. | 2016-06-09 |
20160163631 | CHIP CARRIER WITH DUAL-SIDED CHIP ACCESS AND A METHOD FOR TESTING A CHIP USING THE CHIP CARRIER - Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip). | 2016-06-09 |
20160163632 | PACKAGING STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of conducive vias that penetrate the dielectric layer, an electronic component disposed on the first surface of the dielectric layer and electrically connected to the wiring layer, an encapsulant encapsulating the electronic component, and a packaging substrate disposed on the second surface and electrically connected to the conductive vias. With the dielectric layer in replacement of a conventional silicon board and the wiring layer as a signal transmission medium between the electronic component and the packaging substrate, the package structure does not need through-silicon vias. Therefore, the package structure has a simple fabrication process and a low fabrication cost. The present invention further provides a method of fabricating the package structure. | 2016-06-09 |
20160163633 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a display unit with a first area and a second area, first gate lines on the first area and the second area that extend in a first direction in the first area and in a third direction in the second area, while sections extending in the first direction and in a second direction are repeated, and second gate lines on the second area that extend in the third direction while sections extending in the first direction and in the second direction are repeated. The second gate line includes a plurality of sub gate lines that extend in the second direction in the second area, and one end of each of the plurality of sub gate lines is connected to one end of each of the plurality of second gate lines. | 2016-06-09 |
20160163634 | POWER REDUCED COMPUTING - Systems for performing computing operations in a power-reduced environment include a processor in communication with two data storage media and a non-grid-based power source, such as a solar, wind, or mechanical source. The first data storage is adapted for communication with a network, rapid receipt and transfer of data, and low power use, such as a flash drive. The second data storage is adapted for actuation to record and retrieve data, and to store data in a stationary state requiring no power, such as an optical disc drive. The first data storage medium can communicate data to and from a network, receive input, and provide output, while the second data storage medium can be used to archive stored data based on the actuation state thereof. To conserve power and improve integrity, signals can be transmitted as a complementary pair of signals, along two non-linear paths having overlapping and misaligned portions. | 2016-06-09 |
20160163635 | SEMICONDUCTOR DEVICE - A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure. | 2016-06-09 |
20160163636 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor structure includes: providing a substrate with a dielectric layer and a passivation layer formed on the substrate; forming a via through the dielectric layer and exposing the substrate; forming a first conductive layer to fill the via with a top surface of the first conductive layer leveled with a top surface of the passivation layer; forming a patterned layer with an opening on the passivation layer. The opening is located above the first conductive layer with a dimension larger than the dimension of the via. The method also includes forming a trench in the dielectric layer; forming a second conductive layer to fill the trench and to electrically connect to the first conductive layer; then removing a portion of the second conductive layer, the patterned layer, and the passivation layer to make a top surface of the second conductive layer level with a top surface of the dielectric layer. | 2016-06-09 |
20160163637 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines. | 2016-06-09 |
20160163638 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes forming a first conductor pattern and a second conductor pattern running side by side with each other, including forming a first portion of the first conductor pattern and a second portion of the second conductor pattern by patterning using a first mask, and forming a second portion of the first conductor pattern and a first portion of the second conductor pattern by patterning using a second mask. A first inter-conductor capacity is formed by the first portion of the first conductor pattern and the first portion of the second conductor pattern. A second inter-conductor capacity is formed by the second portion of the first conductor pattern and the second portion of the second conductor pattern. | 2016-06-09 |
20160163639 | Substrate-less Stackable Package with Wire-Bond Interconnect - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 2016-06-09 |
20160163640 | INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS - A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line. | 2016-06-09 |
20160163641 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer. | 2016-06-09 |
20160163642 | WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION - The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged. | 2016-06-09 |
20160163643 | E-FUSE DEVICES AND METHOD FOR FABRICATING THE SAME - E-fuse devices, and a method of manufacturing the same, include a first metal pattern extending in a first direction to connect a first electrode and a second electrode to each other, a first barrier metal contacting lateral surfaces and a bottom surface of the first metal pattern, and a first capping insulation layer contacting a top surface of the first metal pattern, wherein the first metal pattern includes an exposed region, the first barrier metal or the first capping insulation layer not contacting a top surface or a bottom surface of the exposed region. | 2016-06-09 |
20160163644 | MERGED SOURCE/DRAIN AND GATE CONTACTS IN SRAM BITCELL - A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact. | 2016-06-09 |
20160163645 | SEMICONDUCTOR STRUCTURE WITH BOTTOM-FREE LINER FOR TOP CONTACT - A semiconductor structure includes a lined bottom contact filled with conductive material. The structure further includes a layer of dielectric material surrounding sides of the lined bottom contact, a top contact on the bottom contact, the top contact having a partial liner only along sides thereof with an absence of the liner at a bottom thereof and being filled with the conductive material, and a layer of the dielectric material surrounding sides of the partially lined top contact. Fabrication of the bottom-liner free top contact includes providing a starting structure, the structure including a lined bottom contact filled with conductive material, being surrounded by a layer of dielectric material and having a planarized top surface. The method further includes creating a top layer of dielectric material above the planarized top surface, creating a layer of liner material above the top dielectric layer, creating a top contact opening to the bottom contact, lining the top contact opening with a liner material, removing the liner at a bottom of the top contact opening, exposing the bottom contact, while preserving a portion of the liner on the top dielectric layer sufficient to allow adhesion of a subsequent conductive material, and filling the contact opening with the conductive material. | 2016-06-09 |
20160163646 | STRAPPED CONTACT IN A SEMICONDUCTOR DEVICE - An apparatus includes a first fin of a first transistor and a second fin of a second transistor. The apparatus also include a first contact coupled to the first fin and a second contact coupled to the second fin. The apparatus further includes a strapped contact coupled to the first contact and to the second contact. | 2016-06-09 |
20160163647 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device comprises a conductive layer, a first insulating film, a barrier metal, a contact electrode, and a surface electrode. The first insulating film is located on the conductive layer and comprises a contact hole reaching the conductive layer. At least a surface part of the first insulating film is a BPSG film. The barrier metal covers an inner surface of the contact hole. The contact electrode is located in the contact hole and on the barrier metal. The surface electrode is located on the BPSG film and the contact electrode. The barrier metal is not interposed between the BPSG film and the surface electrode so that the surface electrode is directly in contact with the BPSG film. At least a part of the surface electrode is a bonding pad. | 2016-06-09 |
20160163648 | Method for Forming an Electrical Contact - A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas. | 2016-06-09 |
20160163649 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer. | 2016-06-09 |
20160163650 | INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION AGAINST MECHANICAL THINNING AND FOR OTHER PURPOSES, AND METHODS OF FABRICATING SUCH ASSEMBLIES | 2016-06-09 |
20160163651 | OPTIMIZED WIRES FOR RESISTANCE OR ELECTROMIGRATION - Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings. | 2016-06-09 |
20160163652 | COATED FULLERENES, COMPOSITES AND DIELECTRICS MADE THEREFROM - The present invention relates to coated fullerenes comprising a layer of at least one inorganic material covering at least a portion of at least one surface of a fullerene and methods for making. The present invention further relates to composites comprising the coated fullerenes of the present invention and further comprising polymers, ceramics, and/or inorganic oxides. A coated fullerene interconnect device where at least two fullerenes are contacting each other to form a spontaneous interconnect is also disclosed as well as methods of making. In addition, dielectric films comprising the coated fullerenes of the present invention and methods of making are further disclosed. | 2016-06-09 |
20160163653 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device. Both the cathode and the first electrically conductive portion of the carrier are electrically isolated from a backside of the semiconductor substrate. | 2016-06-09 |
20160163654 | SEMICONDUCTOR DEVICE - In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N | 2016-06-09 |
20160163655 | INTEGRATED CIRCUIT COMPONENT SHIELDING - Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a plurality of vias disposed between the first and second conductive regions. The first and second conductive regions and the plurality of vias may surround an integrated circuit (IC) component and individual vias of the plurality of vias are spaced relative to one another to shield incoming or outgoing electromagnetic interference (EMI). Other embodiments may be described and/or claimed. | 2016-06-09 |
20160163656 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having an element; a front surface electrode connected to the element; a rear surface electrode connected to the element; a protective film disposed on the front surface of the semiconductor substrate in a separation region; and a temperature sensor disposed on a front surface side of the semiconductor substrate. The front surface electrode is divided into multiple pieces along at least two directions with the protective film. The separation region includes an opposing region located between opposing sides of divided pieces of the front surface electrode adjacent to each other, and an intersection region, at which the opposing region intersects. The temperature sensor is disposed in only the opposing region. | 2016-06-09 |
20160163657 | Packaging Devices and Methods for Semiconductor Devices - Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region. | 2016-06-09 |
20160163658 | ACTIVATING REACTIONS IN INTEGRATED CIRCUITS THROUGH ELECTRICAL DISCHARGE - Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit. | 2016-06-09 |
20160163659 | RADIO FREQUENCY DEVICE PROTECTED AGAINST OVERVOLTAGES - A device includes passive radio frequency components formed of portions of metal layers separated by insulating layers and crossed by vias. The insulating layers are positioned on an upper surface of an insulating substrate. Islands of a semiconductor material extend into the insulating substrate from the upper surface. Active integrated circuit components are formed in the islands. | 2016-06-09 |
20160163660 | SEMICONDUCTOR DEVICE HAVING HIGH FREQUENCY WIRING AND DUMMY METAL LAYER AT MULTILAYER WIRING STRUCTURE - A semiconductor device includes a semiconductor substrate, a plurality of wiring layers provided on the semiconductor substrate, a high frequency wiring provided at a first layer in the plurality of wiring layers, and a plurality of dummy metals provided in a second layer provided between the semiconductor substrate and the first layer having the high frequency wiring. The plurality of wiring layers at a top view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, the high frequency wiring vicinity region including a first region enclosed by an outer edge of the high frequency wiring and a second region surrounding the first region. The plurality of dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively. | 2016-06-09 |
20160163661 | RADIO FREQUENCY ISOLATION STRUCTURE WITH RACETRACK - Aspects of the present disclosure relate to a racetrack that forms part of an RF isolation structure of a packaged module and wireless devices that include such a packaged module. The racetrack can be disposed in a substrate and around an RF component that is on the substrate. The racetrack can include at least one break and/or at least one narrowed section without significantly degrading the EMI performance of the RF isolation structure. | 2016-06-09 |
20160163662 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding. | 2016-06-09 |
20160163663 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND SEMICONDUCTOR LIGHT-EMITTING APPARATUS HAVING THE SAME - An embodiment includes a semiconductor light-emitting device comprising: an electrode pad; a first under-barrier metal (UBM) layer stacked on the electrode pad; a second UBM layer stacked on the first UBM layer and having a multilayered structure including at least two layers; and a solder bump disposed on the second UBM layer, wherein adhesion between the second UBM layer and the first UBM layer is higher than adhesion between the first UBM layer and the solder bump. | 2016-06-09 |
20160163664 | SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor substrate includes a device-forming process of forming a plurality of device areas in a substrate section, a first wiring process of forming circuit wirings connected to the plurality of device areas, an electrode pad-forming process of forming a plurality of electrode pads, a second wiring process of forming a potential adjustment wiring electrically connecting at least a part of the electrode pads, an electrode-forming process of forming electrode bodies on the electrode pads by electroless plating after the second wiring process, and a potential adjustment-releasing process of releasing a connection by the potential adjustment wiring after the electrode-forming process. | 2016-06-09 |
20160163665 | CHIP STRUCTURE HAVING BONDING WIRE - A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy. | 2016-06-09 |
20160163666 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - To improve an integration degree of a semiconductor device. | 2016-06-09 |
20160163667 | SEMICONDUCTOR DEVICE - Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width. | 2016-06-09 |
20160163668 | MOUNTING STRUCTURE AND BGA BALL - A mounting structure includes a BGA including a BGA electrode, a circuit board including a circuit board electrode, and a solder joining portion which is arranged on the circuit board electrode and is connected to the BGA electrode. The solder joining portion is formed of Cu having a content ratio in a range from 0.6 mass % to 1.2 mass %, inclusive, Ag having a content ratio in a range from 3.0 mass % to 4.0 mass %, inclusive, Bi having a content ratio in a range from 0 mass % to 1.0 mass %, inclusive, In, and Sn. A range of the content ratio of In is different according to the content ratio of Cu. | 2016-06-09 |
20160163669 | ELONGATED PAD STRUCTURE - A 3DIC includes a die and a substrate. The die includes multiple bumps to provide electrical connection the substrate. The substrate includes multiple elongated contact pads. The elongated contact pads making electrical contact with the bumps and shaped to maintain alignment with the bumps over a temperature range. | 2016-06-09 |
20160163670 | Semiconductor Bonding Structure and Process - A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material. | 2016-06-09 |
20160163671 | INTEGRATED CIRCUIT PACKAGE WITH POWER PLATES - A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment. | 2016-06-09 |
20160163672 | DUAL-SIDE REINFORCEMENT FLUX FOR ENCAPSULATION - Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials with enhanced stability at room temperature. | 2016-06-09 |
20160163673 | WIRE BONDING APPARATUS AND BONDING METHOD - Provided is a wire bonding apparatus capable of performing high-speed wedge wire bonding, the apparatus including: a bonding tool having a through hole and a pressing surface for pressing a wire; a clamper for holding the wire; and a control unit. The control unit includes: wire tail extension unit that moves the bonding tool, after wedge bonding of the wire to a first lead, upward and along a second straight line connecting a second pad and a second lead, and causes the wire to extend from the through hole in a direction along the second straight line from the second pad to the second lead; and tail cut unit that, after causing the wire tail to extend, cuts the wire tail by moving the bonding tool in the direction along the second straight line connecting the second pad and the second lead while the clamper is closed. | 2016-06-09 |
20160163674 | Method of Packaging Integrated Circuits - Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed. | 2016-06-09 |
20160163675 | Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form - A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate. | 2016-06-09 |
20160163676 | SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP - In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board. | 2016-06-09 |
20160163677 | PACKAGE APPARATUS AND MANUFACTURING METHOD THEREOF - A package apparatus includes a first package module, a second package module and multiple conductive elements. The first package module includes a first molding compound layer, a first conductive pillar layer disposed in the first molding compound layer, a first internal component, and a first protection layer. The first internal component electrically connects to the first conductive pillar layer and disposed in the first molding compound layer. The first protection layer is disposed on the first molding compound layer and the first conductive pillar layer. The second package module includes a second molding compound layer, a second conductive pillar layer disposed in the second molding compound layer, and a second internal component. The second internal component electrically connects to the second conductive pillar layer and disposed in the second molding compound layer. The conductive elements are disposed between the first and the second conductive pillar layers. | 2016-06-09 |
20160163678 | SEMICONDUCTOR APPARATUS HAVING ELECTRICAL CONNECTIONS WITH THROUGH-VIA AND A METAL LAYER AND STACKING METHOD THEREOF - A semiconductor apparatus may include a first metal layer including a first unit pad. The semiconductor apparatus may include a second metal layer including first and second unit pads. The semiconductor apparatus may include a first through-via coupling the first unit pad of the first metal layer to a first bump; and a second through-via coupling the first unit pad of the second metal layer to a second bump. The second unit pad of the second metal layer may be disposed in a first direction from the first unit pad of the second metal layer, and may be electrically coupled to the first unit pad of the second metal layer. | 2016-06-09 |
20160163679 | MICROELECTRONIC ASSEMBLIES HAVING STACK TERMINALS COUPLED BY CONNECTORS EXTENDING THROUGH ENCAPSULATION - A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation. | 2016-06-09 |
20160163680 | Repairing Monolithic Stacked Integrated Circuits with a Redundant Layer and Lithography Process - Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect. | 2016-06-09 |
20160163681 | OPTICAL SENSOR PACKAGE AND OPTICAL SENSOR ASSEMBLY - There is provided an optical sensor package including a semiconductor base layer. A first surface of the semiconductor base layer is formed with a pixel array, a plurality of solder balls and an optical component such that when the optical sensor package is assembled with a substrate, the optical component is accommodated in an accommodation throughhole of the substrate so as to reduce the total thickness. | 2016-06-09 |
20160163682 | WORKPIECE WITH SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A WORKPIECE WITH SEMICONDUCTOR CHIPS - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. | 2016-06-09 |
20160163683 | POP Structures with Dams Encircling Air Gaps and Methods for Forming the Same - A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die. | 2016-06-09 |
20160163684 | Air Trench in Packages Incorporating Hybrid Bonding - A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench. | 2016-06-09 |
20160163685 | TUNABLE SCALING OF CURRENT GAIN IN BIPOLAR JUNCTION TRANSISTORS - Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout. | 2016-06-09 |
20160163686 | SEMICONDUCTOR DEVICES HAVING DUMMY PATTERNS AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other. | 2016-06-09 |
20160163687 | OXIDE DEFINITION (OD) GRADIENT REDUCED SEMICONDUCTOR DEVICE - An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region, and dummy cells in the high OD density region and the low OD density region to smooth a density gradient between the high OD density region and the low OD density region. | 2016-06-09 |
20160163689 | Semiconductor Devices with Transistor Cells and Thermoresistive Element - A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin. | 2016-06-09 |
20160163690 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated. | 2016-06-09 |
20160163691 | ESD PROTECTION DEVICE WITH IMPROVED BIPOLAR GAIN USING CUTOUT IN THE BODY WELL - An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor. | 2016-06-09 |
20160163692 | SINGLE-CHIP INTEGRATED CIRCUIT WITH CAPACITIVE ISOLATION AND METHOD FOR MAKING THE SAME - An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions. | 2016-06-09 |
20160163693 | STRUCTURE WITH INDUCTOR AND MIM CAPACITOR - A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core. | 2016-06-09 |
20160163694 | SEMICONDUCTOR DEVICE INCLUDING FIN CAPACITORS - A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins. | 2016-06-09 |
20160163695 | Integrated Circuit Comprising Group III-N Transistors Monolithically Integrated on a Silicon Substrate and a Method for Manufacturing Thereof - An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor. | 2016-06-09 |
20160163696 | POWER SEMICONDUCTOR DEVICE - Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region. Trenches formed in the first surface include a gate trench and a boundary trench disposed between the gate trench and the diode region. A fourth layer of the semiconductor substrate is provided on the first surface and has a portion included in the diode region. The fourth layer includes a trench-covering well region that covers the deepest part of the boundary trench, a plurality of isolated well regions, and a diffusion region that connects the trench-covering well region and the isolated well regions. The diffusion region has a lower impurity concentration than that of the isolated well regions. A first electrode is in contact with the isolated well regions and away from the diffusion region. | 2016-06-09 |
20160163697 | APPARATUS AND METHODS FOR HIGH VOLTAGE VARIABLE CAPACITOR ARRAYS WITH BODY-TO-GATE DIODES - Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells. | 2016-06-09 |
20160163698 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area. | 2016-06-09 |
20160163699 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed at a first side of the active fins. A second device isolation layer is disposed at a second side of the active fins. A top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side. A normal gate extends across the active fins in a second direction crossing the first direction. A first dummy gate extends across the active fins and the first device isolation layer in the second direction. A second dummy gate extends across the second device isolation layer in the second direction. | 2016-06-09 |
20160163700 | Fin Deformation Modulation - A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively. | 2016-06-09 |
20160163701 | FIN CUT ON SIT LEVEL - A method of forming semiconductor fins with variable pitches of arbitrary values in a sidewall image transfer (SIT) process is provided. After forming an array of first mandrel structures with a constant pitch and removing at least one first mandrel structure form the array, a set of second mandrel structures are formed overlapping the first mandrel structures. The combination of the first mandrel structures and the second mandrel structures defines pitches of sidewall spacer patterns to be subsequently formed. | 2016-06-09 |
20160163702 | FORMING SELF-ALIGNED NiSi PLACEMENT WITH IMPROVED PERFORMANCE AND YIELD - Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions | 2016-06-09 |
20160163703 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first MOS transistor and a second MOS transistor of a second conductivity type. The first MOS transistor includes a first main electrode connected to a first potential and a second main electrode connected to a second potential. The second MOS transistor includes a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential. The control electrodes of the first and second MOS transistors are connected in common. The first and second MOS transistors are formed on a common wide bandgap semiconductor substrate. In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide bandgap semiconductor substrate. In the second MOS transistor, a main current flows in a direction parallel to the main surface of the wide bandgap semiconductor substrate. | 2016-06-09 |
20160163704 | SEMICONDUCTOR DEVICE HAVING HETEROGENEOUS STRUCTURE AND METHOD FORMING THE SAME - A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first source are disposed on the first buffer layer and have heterogeneous structures. A first channel is disposed between the first drain and the first source. A first gate electrode is disposed on the first channel. A second drain and a second source are disposed on the first buffer layer. A second channel is disposed between the second drain and the second source. The second channel includes a different material from the first channel. A second gate electrode is disposed on the second channel. The first drain, the first source, the first channel and the first gate electrode are disposed in the NMOS region. The second drain, the second source, the second channel and the second gate electrode are disposed in the PMOS region. | 2016-06-09 |
20160163705 | FINFET WORK FUNCTION METAL FORMATION - An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities. | 2016-06-09 |
20160163706 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region. | 2016-06-09 |
20160163707 | EPITAXIALLY GROWN SILICON GERMANIUM CHANNEL FINFET WITH SILICON UNDERLAYER - Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region. | 2016-06-09 |
20160163708 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS - A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first MOSFET including a first gate insulating layer structure and a first gate electrode structure, and a second MOSFET including a group IV compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate. The group IV compound semiconductor layer is disposed on the second transistor region of the semiconductor substrate, and the second gate insulating layer and the second gate electrode structure are disposed on the group IV compound semiconductor layer. Each of the first and second gate insulating layer structures includes a high-k dielectric (insulating) layer. | 2016-06-09 |
20160163709 | Semiconductor Device - Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity. | 2016-06-09 |
20160163710 | SEMICONDUCTOR DEVICE - A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained. | 2016-06-09 |
20160163711 | WET BOTTLING PROCESS FOR SMALL DIAMETER DEEP TRENCH CAPACITORS - A method including forming a deep trench in a semiconductor-on-insulator substrate including an SOI layer directly on top of a buried oxide layer directly on top of a base substrate, masking only a top surface of the SOI layer and a sidewall of the SOI layer exposed within an upper portion of the deep trench with a dielectric material without masking any surface of the base substrate exposed within a lower portion of the deep trench, and forming a bottle shaped trench by etching the base substrate exposed in the lower portion of the deep trench selective to the dielectric material and the buried oxide layer. | 2016-06-09 |
20160163712 | VERTICAL FIN eDRAM - Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor. | 2016-06-09 |
20160163713 | STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINES ON SEPARATE METAL LAYERS FOR INCREASED PERFORMANCE, AND RELATED METHODS - Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer. | 2016-06-09 |
20160163714 | STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINE LANDING PADS SPLIT ACROSS BOUNDARY EDGES OF THE SRAM BIT CELLS - Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell. | 2016-06-09 |
20160163715 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure. | 2016-06-09 |
20160163716 | LAYOUTS AND FABRICATION METHODS FOR STATIC RANDOM ACCESS MEMORY - A layout of a random access memory is provided. The layer comprises a first sub-layout having a first pattern including a first number (N1) of first patterns and an adjacent second pattern having a second number (N2) of second patterns; a second sub-layout having a first gate pattern and a second gate pattern; and an interchangeable third sub-layout having covering patterns variable for forming different static random access memory when used with the first sub-layout and the second sub-layout. | 2016-06-09 |
20160163717 | Embedded SRAM and Methods of Forming the Same - A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes. | 2016-06-09 |
20160163718 | SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN - Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure. | 2016-06-09 |
20160163719 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers. | 2016-06-09 |
20160163720 | Semiconductor Device - A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor. | 2016-06-09 |
20160163721 | NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURE - A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device. | 2016-06-09 |
20160163722 | NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other. | 2016-06-09 |
20160163723 | FLASH MEMORY - A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance. | 2016-06-09 |
20160163724 | SCALABLE AND RELIABLE NON-VOLATILE MEMORY CELL - Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair. | 2016-06-09 |