23rd week of 2016 patent applcation highlights part 64 |
Patent application number | Title | Published |
20160163725 | SELECTIVE FLOATING GATE SEMICONDUCTOR MATERIAL DEPOSITION IN A THREE-DIMENSIONAL MEMORY STRUCTURE - A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses. | 2016-06-09 |
20160163726 | APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES - Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge. | 2016-06-09 |
20160163727 | METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE - Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described. | 2016-06-09 |
20160163728 | UNIFORM THICKNESS BLOCKING DIELECTRIC PORTIONS IN A THREE-DIMENSIONAL MEMORY STRUCTURE - A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions. | 2016-06-09 |
20160163729 | THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE - A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell. | 2016-06-09 |
20160163730 | SEMICONDUCTOR DEVICE - A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region. | 2016-06-09 |
20160163731 | VERTICAL THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME - The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one aspect, the vertical three-dimensional semiconductor device has a source layer formed over a substrate. A horizontal stack of alternating electrically isolating layers and electrically conductive gate layers are formed over the source layer, wherein one of the electrically isolating layers contacts the source layer. A vertical channel structure extends vertically through the horizontal stack of alternating layers. A drain is formed over the horizontal stack of alternating layers and over the vertical channel structure. The source layer is configured to inject charge carriers into the vertical channel structure, and the metal drain is configured to extract charge carriers from the vertical channel structure. A conductivity of the vertical channel structure is configured to change in response to an electrical bias applied to at least one of the electrically conductive gate layers. | 2016-06-09 |
20160163732 | SEMICONDUCTOR DEVICES - Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor. | 2016-06-09 |
20160163733 | Three-Dimensional Semiconductor Devices - A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively. | 2016-06-09 |
20160163734 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer. | 2016-06-09 |
20160163735 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure. | 2016-06-09 |
20160163736 | GATE ARRAY FOR HIGH-SPEED CMOS AND HIGH-SPEED CMOS TTL FAMILY - A system for implementing an integrated circuit(IC) is provided. The system includes one or more base layers. By using one or more single base layers integrated circuit can be made for a high-speed CMOS (HC) and high-speed CMOS TTL (transistor-transistor logic) compatible (HCT) families. A base layers may be fixed and just one or more metal patterns may be changed for respective integrated circuit (IC). A wafer bank includes large number of transistors to implement one or more circuits by changing the metal pattern required and can make the required circuit. | 2016-06-09 |
20160163737 | ARRAY SUBSTRATE, MANUFACTURING METHOD OF ARRAY SUBSTRATE AND DISPLAY DEVICE - Embodiments of the present invention disclose an array substrate, a manufacturing method of the array substrate and a display device, and the manufacturing method of the array substrate comprises: forming a gate line and a gate electrode on a base substrate; forming a gate insulating layer above the gate line and the gate electrode; successively depositing a semiconductor layer and a metal layer above the gate insulating layer, and forming an active layer, a source electrode and a drain electrode that are disposed above the gate electrode and a residual semiconductor layer disposed above the gate line and a signal line covering the residual semiconductor layer by using one patterning process; performing a patterning process for the signal line, the residual semiconductor layer disposed below the signal line and the gate insulating layer to form a via hole, so that a surface of the gate line, side sectional surfaces of the signal line, side sectional surfaces of the residual semiconductor layer and side sectional surfaces of the gate insulating layer are exposed through the via hole; and forming a lapping conductive layer at a position where the via hole is located, so that the signal line and the gate line are electrically connected. | 2016-06-09 |
20160163738 | DISPLAY PANEL MANUFACTURING METHOD AND DISPLAY PANEL - A display panel manufacturing method includes: forming connecting wires; forming a common wire which is connected to the connecting wires; forming a first pattern including a preparatory barrier and a channel, by forming a semiconductor film including an oxide semiconductor; forming a second pattern which contacts the channel and does not contact the preparatory barrier; forming a barrier by reducing resistance of the preparatory barrier; and separating the common wire and the barrier. | 2016-06-09 |
20160163739 | MULTI-GATE FIELD EFFECT TRANSISTOR (FET) INCLUDING ISOLATED FIN BODY - Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both. | 2016-06-09 |
20160163740 | SEMICONDUCTOR DEVICE, ELECTRO-OPTICAL DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - A first insulation layer includes a concave portion. A semiconductor layer includes a source area and a drain area, and a channel area disposed at the concave portion of the first insulation layer. A gate insulation layer covers the channel area. A gate electrode is disposed to be opposed to the channel area via the gate insulation layer. A first electrode is one of a source electrode and a drain electrode. A second electrode is the other of the source electrode and the drain electrode. | 2016-06-09 |
20160163741 | THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME - There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film. | 2016-06-09 |
20160163742 | SEMICONDUCTOR DEVICE - A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the oxide layer, a second drain electrode layer in contact with the oxide layer, a gate insulating film in contact with the oxide layer, a first gate electrode layer overlapping with the source electrode layer and the first drain electrode layer and overlapping with a top surface of the oxide layer with the gate insulating film interposed therebetween, a second gate electrode layer overlapping with the source electrode layer and the second drain electrode layer and overlapping with the top surface of the oxide layer with the gate insulating film interposed therebetween, and a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween. | 2016-06-09 |
20160163743 | LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A driver circuit includes a circuit | 2016-06-09 |
20160163744 | SEMICONDUCTOR DEVICE - A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed. | 2016-06-09 |
20160163745 | Organic Light-Emitting Diode Display With Double Gate Transistors - An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode and thin-film transistor circuitry that controls current flow through the organic light-emitting diode. The thin-film transistor circuitry may include silicon thin-film transistors and semiconducting-oxide thin-film transistors. Double gate transistor structures may be formed in the transistors of the thin-film transistor circuitry. A double gate transistor may have a semiconductor layer sandwiched between first and second dielectric layers. The first dielectric layer may be interposed between an upper gate and the semiconductor layer and the second dielectric layer may be interposed between a lower gate and the semiconductor layer. Capacitor structures may be formed from the layers of metal used in forming the upper and lower gates and other conductive structures. | 2016-06-09 |
20160163746 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a display device including forming one or more thin-film transistors (“TFTs”) each configured to include an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate. A storage capacitor including a first storage electrode and a second storage electrode overlapping the first storage electrode with the gate insulating layer interposed there between is also formed on the substrate. A top surface of the first storage electrode may include hillocks and the gate insulating layer is formed between the first storage electrode and the second storage electrode to conform to the shape of the top surface of the first storage electrode with the hillocks. | 2016-06-09 |
20160163747 | PHOTOELECTRIC CONVERSION DEVICE AND ELECTRONIC APPARATUS - An image sensor as a photoelectric conversion device includes a substrate, a photodiode, a transistor, and a planarizing layer, the photodiode, the transistor, and the planarizing layer are disposed above the substrate, the planarizing layer includes an opening section, a tilted section disposed so as to surround the opening section, and a flat section adapted to cover the transistor, the photodiode is formed in the opening section, and a reflecting film is formed above the tilted section and the flat section of the planarizing layer. | 2016-06-09 |
20160163748 | PIXEL CIRCUIT - A pixel circuit includes a floating diffusion layer of a first conductivity-type between a drain/source of a second conductivity-type and a source/drain of the second conductivity-type. The source/drain and the drain/source touch the floating diffusion layer. A cathode of a photoelectric converter is electrically connected to the floating diffusion layer. An anode of the photoelectric converter touches the cathode. The cathode is of the first conductivity-type and the anode is of the second conductivity-type. | 2016-06-09 |
20160163749 | DEEP TRENCH SPACING ISOLATION FOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSORS - An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided. | 2016-06-09 |
20160163750 | PACKAGE FOR AN OPTICAL SENSOR, OPTICAL SENSOR ARRANGEMENT AND METHOD OF PRODUCING A PACKAGE FOR AN OPTICAL SENSOR - A package for an optical sensor, comprises an optically opaque enclosure for forming a cavity when mounted onto a substrate and an optical element based on an optically translucent polymer. An aperture in the enclosure is designed to attach the optical element to the enclosure. | 2016-06-09 |
20160163751 | SUBSTRATE FOR EMBEDDING IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME, AND IMAGING APPARATUS - A substrate for embedding an imaging device includes: a core layer; a first multilayered wiring layer that is formed onto the core layer, the core layer and the first multilayered wiring layer having a cavity penetrating therethrough; a second multilayered wiring layer that is formed onto the core layer on a side opposite to the first multilayered wiring layer and that includes a conductive pattern formed at a position facing the cavity; a resin portion that is arranged inside the cavity and includes a bottom surface supported by the second multilayered wiring layer, a side face supported by the core layer, and a curved surface formed on a side opposite to the bottom surface; and an imaging device adhered along the curved surface inside the cavity. | 2016-06-09 |
20160163752 | IMAGE-ACQUISITION DEVICE - Provided is an image-acquisition device including a first image-acquisition surface including a photoelectric conversion film capable of subjecting incident light to photoelectric conversion while transmitting some of the incident light; a second image-acquisition surface including a photoelectric conversion layer that subjects the incident light transmitted by the first image-acquisition surface to photoelectric conversion; and a polarizing filter that is disposed between the two image-acquisition surfaces and that extracts polarization information from the incident light transmitted by the first image-acquisition surface. | 2016-06-09 |
20160163753 | NANOWIRE PHOTO-DETECTOR GROWN ON A BACK-SIDE ILLUMINATED IMAGE SENSOR - An embodiment relates to a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. | 2016-06-09 |
20160163754 | RADIATION DETECTOR, METHOD OF MANUFACTURING RADIATION DETECTOR, IMAGING UNIT, AND IMAGING AND DISPLAY SYSTEM - There is provided a radiation detector including: a plurality of photoelectric conversion devices, each photoelectric conversion device formed at least partially within an embedding layer and having a light receiving surface situated at least partially outside of the embedding layer, and a plurality of scintillator crystals, at least a first scintillator crystal of the plurality of scintillator crystals in contact with at least one light receiving surface at a proximal end, wherein a cross-section of the first scintillator crystal at the proximal end is smaller than a cross-section of the first scintillator crystal at a distal end. | 2016-06-09 |
20160163755 | IMAGE SENSOR CHIP SIDEWALL INTERCONNECTION - An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided. | 2016-06-09 |
20160163756 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam. | 2016-06-09 |
20160163757 | VERY SMALL PIXEL PITCH FOCAL PLANE ARRAY AND METHOD FOR MANUFACTURING THEREOF - An imaging device includes a first semiconductor layer having a first surface and a second surface and a first photodetector having a first implanted region formed in the first semiconductor layer and a pad formed over the first implanted region. The imaging device also includes a readout circuit disposed over the first surface of the first semiconductor layer. The readout circuit has a plurality of contact plugs facing the first surface of the first semiconductor layer. The imaging device further includes a second semiconductor layer disposed below the second surface of the first semiconductor, a second photodetector having a second implanted region formed in the second semiconductor layer, and a metalized via extending through the first semiconductor layer and the second semiconductor layer and electrically connecting the second implanted region to a second of the contact plugs of the readout circuit. | 2016-06-09 |
20160163758 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device with improved performance. In a method for manufacturing a semiconductor device, after forming a gate electrode of a transfer transistor over a p-type well, a photodiode is formed in one part of the p-type well positioned on one side with respect to the gate electrode. Then, a cap insulating film including silicon and nitrogen is formed over the photodiode before implanting impurity ions for formation of an n-type low-concentration semiconductor region of the transfer transistor, into the other part of the p-type well positioned on a side opposite to the one side with respect to the gate electrode. | 2016-06-09 |
20160163759 | PIXEL HAVING TWO SEMICONDUCTOR LAYERS, IMAGE SENSOR INCLUDING THE PIXEL, AND IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR - An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices. | 2016-06-09 |
20160163760 | CMOS IMAGE SENSOR STRUCTURE WITH IR/NIR INTEGRATION - A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device. | 2016-06-09 |
20160163761 | PHOTOELECTRIC CONVERSION DEVICE, METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND ELECTRONIC APPARATUS - An image sensor as a photoelectric conversion device includes: a lower electrode containing a high-melting-point metal; an upper electrode disposed in a layer higher than the lower electrode; a p-type semiconductor layer and an n-type semiconductor layer disposed between the lower electrode and the upper electrode; and a relay electrode containing the high-melting-point metal. The lower electrode and the relay electrode are formed in the same layer. An intermediate layer as a selenized film of the high-melting-point metal is formed on the lower electrode. | 2016-06-09 |
20160163762 | RADIATION IMAGE PICKUP UNIT AND RADIATION IMAGE PICKUP DISPLAY SYSTEM - There is provided a radiation image pickup unit including a plurality of pixels configured to generate signal charge based on radiation; and a field effect transistor for readout of the signal charge from the plurality of pixels, the transistor including a first silicon oxide film, a semiconductor layer including an active layer, and a second silicon oxide life stacked in order from substrate side, and a first gate electrode disposed to face the semiconductor layer with one of the first and the second silicon oxide films in between. The second silicon oxide film has a thickness equal to or larger than a thickness of the first silicon oxide film. | 2016-06-09 |
20160163763 | RADIATION IMAGE PICKUP UNIT AND RADIATION IMAGE PICKUP DISPLAY SYSTEM - There is provided a radiation image pickup unit including: a plurality of pixels each configured to generate a signal charge based on a radiation; a device substrate including a photoelectric conversion element for each pixel; a wavelength conversion layer provided on a light incident side of the device substrate, and configured to convert a wavelength of the radiation into other wavelength; and a partition wall separating the wavelength conversion layer for each pixel. The radiation image pickup unit is configured to allow a gap between the wavelength conversion layer and the device substrate to be equal to or larger than a threshold or equal to or smaller than the threshold, the threshold being preset based on a spatial frequency of an image pickup target. | 2016-06-09 |
20160163764 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed. Then, after an n-type well as an n-type semiconductor region forming the other part of the photodiode is formed, a microwave is applied to the semiconductor substrate to heat the semiconductor substrate. Thereafter, a drain region of the transfer transistor is formed. | 2016-06-09 |
20160163765 | WEARABLE DISPLAY - A conformable electronic device and methods for forming such devices are described. Embodiments of a conformable electronic device may include a silicon substrate having a thickness of 50 μm or less. An array of LEDs that are electrically coupled to a controller chip may be formed on a surface of the silicon substrate. In an embodiment, a top passivation layer is formed over the array of LEDs, the one or more controller chips, and the top surface of the silicon substrate. An embodiment also includes a bottom passivation layer formed on a bottom surface of the silicon substrate. | 2016-06-09 |
20160163766 | INTEGRATED CIRCUIT COMPRISING A GAS SENSOR - An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element. | 2016-06-09 |
20160163767 | NANOCOMPOSITE-BASED NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention provides a nanocomposite-based non-volatile memory device and a method for manufacturing the same, the nanocomposite-based non-volatile memory device comprising: a substrate; a lower electrode formed on the substrate; an active layer formed on the lower electrode and made of an insulating organic material, in which a polycrystalline four-element nanocomposite is dispersed; and an upper electrode formed on the active layer. | 2016-06-09 |
20160163768 | ORGANIC LIGHT EMITTING DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting display including a substrate, a first electrode and a second electrode on the substrate and facing each other, at least two organic light emitting layers between the first electrode and the second electrode, and at least two color filters on the second electrode, the organic light emitting layers emitting a first color light, and the color filters emitting a second color light and a third color light. | 2016-06-09 |
20160163769 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - In an organic light emitting display device and a method of manufacturing the same, the organic light emitting display device has a color filter on thin film transistor (COT) structure, in which data wirings are formed after formation of a pixel electrode, thereby integrating a protective layer and a barrier layer. Thus, a manufacturing process may be simplified to increase productivity. | 2016-06-09 |
20160163770 | TRANSPARENT ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a transparent organic light-emitting display (OLED) device having improved resolution by changing the layout of sub-pixel regions in a light-emitting area. The device comprises: a substrate having a plurality of pixels, each pixel including: a light emitting area including a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region; and a transmissive area through which external light passes, wherein the transmissive area is surrounded by edges of the first, second and third sub-pixel regions of the pixel; and an organic light-emitting element on thin film transistors in each of the sub-pixel regions, wherein the first sub-pixel region is arranged on a first line of the pixel extending in a first direction, the second sub-pixel region is arranged on a second line parallel to the first direction, and the third sub-pixel region is arranged on a third line extending in a second direction. | 2016-06-09 |
20160163771 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device is disclosed. The organic light emitting display device includes a first light emitting part between an anode and a cathode, the first light emitting part having a first light emitting layer, and a second light emitting part between the first light emitting part and the cathode, the second light emitting part having a second light emitting layer and a third light emitting layer, wherein the second light emitting layer includes a hole-type host and a first electron-type host, and the third light emitting layer includes a first electron-type host and a second electron-type host. | 2016-06-09 |
20160163772 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY PANEL AND DISPLAY DEVICE - An organic light-emitting diode (OLED) display panel and a display device are provided. A pixel unit of the OLED display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel and further includes an anode layer, a cathode layer and an organic function layer. The organic function layer includes: a first emission layer (EML1) configured to cover at least two adjacent sub-pixels comprising the first sub-pixel; a carrier blocking layer (CBL) configured to cover the second sub-pixel and the third sub-pixel; a second emission layer (EML2) arranged at an area provided with the first sub-pixel and the second sub-pixel and configured to at least cover the second sub-pixel; and a third emission layer (EML3) configured to cover at least two adjacent sub-pixels comprising the third sub-pixel. The OLED display panel can improve the pixel density. | 2016-06-09 |
20160163773 | OLED Display Modules For Large-Format OLED Displays - OLED display modules for large-format displays are disclosed. The OLED display module includes a matrix of OLEDs, with each OLED having an anode and a cathode, and an OLED drive circuit having electrical connections defined by rows and columns that electrically connect to the OLEDs in the OLED matrix. Groups of adjacent rows are arranged in parallel and groups of adjacent columns are arranged in parallel, thereby defining super pixels each having an array of four or more OLEDS, wherein the OLEDs in a given super pixel cannot be individually activated. The modules can be combined to form the large-format display. | 2016-06-09 |
20160163774 | FULL-COLOR ACTIVE MATRIX ORGANIC LIGHT EMITTING DISPLAY WITH HYBRID - A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band. | 2016-06-09 |
20160163775 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND THIN FILM DEPOSITION MASK FOR MANUFACTURING THE SAME - Provided is an organic light emitting display apparatus. The organic light emitting display apparatus includes a substrate having a light emitting area and a bezel area surrounding the light emitting area; and an organic light emitting element. The organic light emitting element includes an organic layer disposed in a plurality of columns in the light emitting area on the substrate. Each of the plurality of columns includes a different number of pixels disposed therein. The organic layer corresponds to the plurality of columns. | 2016-06-09 |
20160163776 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light-emitting diode (OLED) display having thin film transistors (TFTs) is disclosed. In one aspect, TFTs of the OLED display include a substrate and a first semiconductor layer formed over the substrate and including first channel, source, and drain regions and a lightly doped region between the first channel region and the first source and drain regions. The OLED display also includes a second semiconductor layer formed over the substrate and including second channel, source, and drain regions. The OLED display further includes first and second gate electrodes formed over the first semiconductor layer and a third gate electrode formed over the second semiconductor layer. The width of the second gate electrode is less than that of the first gate electrode and the lightly doped region overlaps a portion of the first gate electrode and does not overlap the second gate electrode. | 2016-06-09 |
20160163777 | DISPLAY UNIT, METHOD OF MANUFACTURING DISPLAY UNIT, AND ELECTRONIC APPARATUS - A display unit includes a display panel including a display region and a terminal region on a first substrate, the display region including a plurality of pixels, each of the plurality of pixels including a light emitting element, and the terminal region including a plurality of terminals at a part of a peripheral region of the display region. The light emitting element includes a first electrode, an organic layer, and a second electrode that is provided commonly to the plurality of pixels, in order from the first substrate side. The second electrode extends, continuously in a plan view, to an end of the first substrate in a region on the first substrate except for the terminal region, and is configured to be electrically disconnected from an exterior member of the display panel. | 2016-06-09 |
20160163778 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS - Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines. | 2016-06-09 |
20160163779 | DISPLAY APPARATUS COMPRISING FLEXIBLE DISPLAY PANEL - A display apparatus according to one aspect of the present disclosure includes at least one flexible display panel including a first picture element that emits a red light, a second picture element that emits a green light, a third picture element that emits a blue light, and a fourth picture element. Each of the first picture element, the second picture element, and the third picture element includes an organic electroluminescent element as a light source and is driven by an active matrix method. The fourth picture element includes an organic electroluminescent element as a light source and is driven by a passive method. | 2016-06-09 |
20160163780 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device is discussed. The organic light emitting display device includes a driving thin film transistor including an active layer and a gate electrode; a storage capacitor including a first electrode and a second electrode; a first pattern electrode including the gate electrode and the first electrode; an anode disposed on the driving thin film transistor and the storage capacitor; a second pattern electrode connected with an anode contact part which connects an output electrode connected with the active layer and the anode; and a patterned semiconductor layer including the active layer having a semiconductive characteristic and a shield unit having a conductive characteristic. | 2016-06-09 |
20160163781 | METAL-INSULATOR-METAL STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer. | 2016-06-09 |
20160163782 | HIGH PRECISION CAPACITOR DIELECTRIC - A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric. | 2016-06-09 |
20160163783 | Semiconductor Device And Semiconductor Memory Devices Having First, Second, And Third Insulating Layers - Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers. | 2016-06-09 |
20160163784 | COAXIAL CARBON NANOTUBE CAPACITOR FOR eDRAM - A deep trench (DT) opening is provided in a semiconductor substrate and then conducting carbon nanotubes are formed within the DT. Each conducting carbon nanotube is coated with a high k dielectric material and thereafter the remaining volume of the DT is filled with a conductive material. | 2016-06-09 |
20160163785 | High Breakdown Voltage Microelectronic Device Isolation Structure with Improved Reliability - A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node. | 2016-06-09 |
20160163786 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Hydrogen atoms and crystal defects are introduced into an n− semiconductor substrate by proton implantation. The crystal defects are generated in the n− semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current. | 2016-06-09 |
20160163787 | GATE PAD AND GATE FEED BREAKDOWN VOLTAGE ENHANCEMENT - A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. | 2016-06-09 |
20160163788 | SEMICONDUCTOR DEVICE HAVING BUFFER LAYER AND METHOD OF FORMING THE SAME - A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area. | 2016-06-09 |
20160163789 | SUPER-JUNCTION TRENCH MOSFETS WITH CLOSED CELL LAYOUT HAVING SHIELDED GATE - A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape. | 2016-06-09 |
20160163790 | SEMICONDUCTOR DEVICE - A semiconductor device that includes: a semiconductor layer of a first conductivity type, having a peripheral area and a cell area inside of the peripheral area; a region of a second conductivity type in the semiconductor layer in the cell area; and a plurality of guard rings of the second conductivity type in the semiconductor layer in the peripheral area, each having a substantially same depth as the region of the second conductivity type in the cell area. The plurality of guard rings include at least one first ring that has a diffusion region in the depth profile in the semiconductor layer that is wider at a top thereof. | 2016-06-09 |
20160163791 | Monolithic DMOS Transistor in Junction Isolated Process - A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon. | 2016-06-09 |
20160163792 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal. | 2016-06-09 |
20160163793 | SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either a body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If a body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit. | 2016-06-09 |
20160163794 | Radiation Hardened MOS Devices and Methods of Fabrication - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 2016-06-09 |
20160163795 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer. | 2016-06-09 |
20160163796 | SEMICONDUCTOR DEVICES WITH STRUCTURES FOR SUPPRESSION OF PARASITIC BIPOLAR EFFECT IN STACKED NANOSHEET FETS AND METHODS OF FABRICATING THE SAME - A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal. | 2016-06-09 |
20160163797 | Semiconductor Structure - The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region. | 2016-06-09 |
20160163798 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode. | 2016-06-09 |
20160163799 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type. | 2016-06-09 |
20160163800 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor layer having an upper surface and an end surface intersecting with the upper surface, an upper electrode (source electrode) formed on the upper surface and electrically connected to the semiconductor layer, and a protecting film extending from over at least a portion of the upper surface to over at least a portion of the end surface are provided. | 2016-06-09 |
20160163801 | GROUP III NITRIDE SUBSTRATES AND THEIR FABRICATION METHOD - Group III nitride substrate having a first side of nonpolar or semipolar plane and a second side has more than one stripe of metal buried, wherein the stripes are perpendicular to group III nitride's c-axis. More than 90% of stacking faults exist over metal stripes. Second side may expose a nonpolar or semipolar plane. Also disclosed is a group III nitride substrate having a first side of nonpolar or semipolar plane and a second side with exposed nonpolar or semipolar plane. The substrate contains bundles of stacking faults with spacing larger than 1 mm. The invention also provides methods of fabricating the group III nitride substrates above. | 2016-06-09 |
20160163802 | HIGH RESISTANCE LAYER FOR III-V CHANNEL DEPOSITED ON GROUP IV SUBSTRATES FOR MOS TRANSISTORS - Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems. | 2016-06-09 |
20160163803 | NITRIDE SEMICONDUCTOR ELEMENT AND NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Al | 2016-06-09 |
20160163804 | VERTICAL HIGH-VOLTAGE MOS TRANSISTOR AND METHOD OF FORMING THE MOS TRANSISTOR WITH IMPROVED ON-STATE RESISTANCE - A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region. | 2016-06-09 |
20160163805 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate. | 2016-06-09 |
20160163806 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film. | 2016-06-09 |
20160163807 | REDUCED PARASITIC CAPACITANCE WITH SLOTTED CONTACT - A FET device fabricated by providing a first conductor on a substrate, the first conductor having a first top surface with a first height above the substrate. A second conductor is provided adjacent the first conductor, the second conductor having a second top surface with a second height above the substrate. A portion of the second conductor is removed to provide a slot, wherein the slot is defined by opposing interior sidewalls and a bottom portion, such that the bottom portion of the slot is below the first height of the first conductor. An insulating material is deposited in the slot, the insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide space within the slot for a third conductor. The space within the slot is then filled with the third conductor. | 2016-06-09 |
20160163808 | SEMICONDUCTOR DEVICE WITH LOW-K GATE CAP AND SELF-ALIGNED CONTACT - A semiconductor device includes at least a gate formed upon a semiconductor substrate, a contact trench self aligned to the gate, and a multilayered gate caps comprising a first gate cap formed upon each gate and a low-k gate cap formed upon the first gate cap. The multilayered gate cap may electrically isolate the gate from a self aligned contact formed by filling the contact trench with electrically conductive material. The multilayered gate cap reduces parasitic capacitance formed between the source-drain region, gate, and multilayered gate cap that may adversely impact device performance and device power consumption. | 2016-06-09 |
20160163809 | LOW RESISTANCE REPLACEMENT METAL GATE STRUCTURE - A first sacrificial gate structure of a first width and a second sacrificial gate structure of a second width greater than the first width are provided on a semiconductor material portion. A dielectric spacer and a planarizing dielectric material are provided surrounding each sacrificial gate structure. Each sacrificial gate structure is then removed forming gate cavities. A high k dielectric material, a metal nitride hard mask and a physical vapor deposited (PVD) amorphous-silicon cap are provided. Vertical portions of the metal nitride hard mask and the high k dielectric material are removed from a portion of each gate cavity. Additional PVD amorphous silicon is then deposited and then all amorphous silicon and remaining metal nitride hard mask portions are removed. A work function portion having a stair-like surface, a diffusion barrier portion, a conductive metal structure and a dielectric cap are then formed into to each of the gate cavities. | 2016-06-09 |
20160163810 | GATE ALL AROUND DEVICE STRUCTURE AND FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE - A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack structure wrapping around the channel region. | 2016-06-09 |
20160163811 | VERTICAL FIELD EFFECT TRANSISTORS - Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin. | 2016-06-09 |
20160163812 | SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 μm. | 2016-06-09 |
20160163813 | METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS - Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor. | 2016-06-09 |
20160163814 | REPLACEMENT GATE PFET MATERIALS HAVING IMPROVED NBTI PERFORMANCE - A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer. | 2016-06-09 |
20160163815 | METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SUCH A SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions. | 2016-06-09 |
20160163816 | METHOD FOR FORMING AIR GAP STRUCTURE USING CARBON-CONTAINING SPACER - A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is formed above the carbon spacers and the line feature. The first dielectric layer is planarized to expose upper ends of the carbon-containing spacers. An ashing process is performed to remove the carbon-containing spacers and define air gaps adjacent the line feature. A cap layer is formed to seal the upper ends of the air gaps. | 2016-06-09 |
20160163817 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included. | 2016-06-09 |
20160163818 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench. | 2016-06-09 |
20160163819 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a sacrificial mandrel on the substrate, wherein the sacrificial mandrel comprises an indentation; and forming a spacer adjacent to the sacrificial mandrel. | 2016-06-09 |
20160163820 | FINFET AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers. | 2016-06-09 |
20160163821 | SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF - A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region. | 2016-06-09 |
20160163822 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING INCLUDING CAP LAYER AND NITRIDE SEMICONDUCTOR LAYER - To enhance the reliability of the semiconductor device using a nitride semiconductor. A channel layer is formed over a substrate, a barrier layer is formed over the channel layer, a cap layer is formed over the barrier layer, and a gate electrode is formed over the cap layer. In addition, a nitride semiconductor layer is formed in a region where the cap layer over the barrier layer is not formed, and a source electrode and a drain electrode are formed over the nitride semiconductor layer. The cap layer is a p-type semiconductor layer, and the nitride semiconductor layer includes the same type of material as the cap layer and is in an intrinsic state or an n-type state. | 2016-06-09 |
20160163823 | Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages - A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element | 2016-06-09 |
20160163824 | INTEGRATED CIRCUITS INCLUDING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure. | 2016-06-09 |