24th week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090146173 | SOLID STATE ILLUMINATION DEVICE - A solid state illumination device includes a solid state light emitting diode and a mounting base. The solid state light emitting diode includes encapsulation material, a wafer, and first and second electrodes. The first and second electrodes have first ends electrically connecting with the wafer, and opposite second ends exposed outside the encapsulation material. The wafer and the first ends are encapsulated in the encapsulation material. The mounting base includes a main body with a receptacle defined therein, first and second receiving holes receiving the first and second electrodes. The main body defines an indent communicating with the first receiving holes receiving a bulge extending from the first electrodes. | 2009-06-11 |
20090146174 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND CAMERA MODULE INCLUDING THE SAME - A semiconductor device includes: an insulating base; a semiconductor element provided on the insulating base; a protector provided on the semiconductor element; and a frame provided on a periphery of the insulating base and surrounding the semiconductor element. A region inside the frame is filled with a sealing resin, and at least one groove is provided in an upper corner portion of the frame on the semiconductor element side of the frame. | 2009-06-11 |
20090146175 | THERMAL STABLE TRANSPARENT SILICONE RESIN COMPOSITIONS AND METHODS FOR THEIR PREPARATION AND USE - A curable silicone composition includes (A) a polydiorganosiloxane having an average, per molecule, of at least two aliphatically unsaturated organic groups and at least one aromatic group; (B) a branched polyorganosiloxane having an average, per molecule, of at least one aliphatically unsaturated organic group and at least one aromatic group; (C) a polyorganohydrogensiloxane having an average per molecule of at least two silicon-bonded hydrogen atoms and at least one aromatic group, (D) a hydrosilylation catalyst, and (E) a silylated acetylenic inhibitor. The curable silicone composition cures to form a cured silicone resin having a refractive index >1.40. The curable silicone composition cures by heating to form a cured silicone resin with an optical transparency >95% at a thickness of 2.0 mm or less at 400 nm wavelength after thermal aging by heating at 200° C. for 14 days. | 2009-06-11 |
20090146176 | LIGHT EMITTING DIODE - The outer peripheral portion of a substrate is provided with a first peripheral edge and a second peripheral edge. The first peripheral edge is provided on the edge portion of a first upper surface of the substrate on which a light-emitting diode element is mounted. The second peripheral edge is formed either on an extension of an imaginary line connecting an edge of the light-emitting facet of the light-emitting diode element and the first peripheral edge or inwardly of the extension. The second peripheral edge is located at a position where the first peripheral edge blocks direct light from the light-emitting diode element. This configuration prevents the second upper surface of the substrate provided between the first peripheral edge and the second peripheral edge from becoming deteriorated due to the direct light. | 2009-06-11 |
20090146177 | VARIABLE THRESHOLD TRENCH IGBT WITH OFFSET EMITTER CONTACTS - A trench type IGBT as disclosed herein includes a plurality of channel regions having one threshold voltage for the normal operation of the device and a plurality of channel regions having a threshold voltage higher than the threshold voltage for the normal operation of the device. | 2009-06-11 |
20090146178 | PHOTODIODE - A photodiode in which increased sensitivity and speed are balanced. The photodiode includes: a semiconductor substrate; a plurality of active regions formed on the substrate by selective epitaxial growth; and a comb electrode provided for each of the plurality of active regions and in communication with each other to electrically connect the active regions together. | 2009-06-11 |
20090146179 | Planar arrays of photodiodes - An apparatus includes a light detector. The light detector includes a substrate with a planar surface and an array of photodiodes located along the planar surface. Each photodiode has a sequence of different semiconductor layers stacked vertically over the planar surface. The photodiodes are electrically connected in series. | 2009-06-11 |
20090146180 | LDMOS WITH CHANNEL STRESS - A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel. | 2009-06-11 |
20090146181 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS - An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer. | 2009-06-11 |
20090146182 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A nitride semiconductor device includes: first through third nitride semiconductor layers formed in sequence over a substrate. The second nitride semiconductor layer has a band gap energy larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer has an opening. A p-type fourth nitride semiconductor layer is formed so that the opening is filled therewith. A gate electrode is formed on the fourth nitride semiconductor layer. | 2009-06-11 |
20090146183 | Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device - Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method. | 2009-06-11 |
20090146184 | SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance. | 2009-06-11 |
20090146185 | INSULATED GATE E-MODE TRANSISTORS - Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region. | 2009-06-11 |
20090146186 | Gate after Diamond Transistor - A gate after diamond transistor and method of making comprising the steps of depositing a first dielectric layer on a semiconductor substrate, depositing a diamond particle nucleation layer on the first dielectric layer, growing a diamond thin film layer on the first dielectric layer, defining an opening for the gate in the diamond thin film layer, patterning of the diamond thin film layer for a gate metal to first dielectric layer surface, etching the first dielectric layer, depositing and defining a gate metal, and forming a contact window opening in the diamond thin film layer and the first dielectric layer to the ohmic contact. | 2009-06-11 |
20090146187 | Nitride semiconductor element and process for producing the same - An undoped GaN layer, a silicon film, an n type GaN layer, an MQW active layer and a p type GaN layer are stacked sequentially in this order on an AlN buffer layer formed on a sapphire substrate. In this manner, the silicon film is formed in the mid-section of the GaN layers. The AlN buffer layer is crystal-grown at a high temperature. The construction is formed such that a reflectivity of light from a crystal-growing surface is once decreased in a crystal-growing process of the n type GaN layer formed on the silicon film, and the reflectivity of light is increased from the crystal-growing surface in a crystal-growing process of a nitride semiconductor layer to be formed on the n type GaN layer. | 2009-06-11 |
20090146188 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device includes a plurality of integrated memory cells. Each cell includes a first inverter having a first driver transistor and a first load transistor which are formed on a semiconductor substrate in order to form a first storage node, a second inverter having a second driver transistor and a second load transistor which are formed on the semiconductor substrate in order to form a second storage node, a first transfer transistor connected between the first storage node and a bit line to serve as a transistor connecting the memory cell to the bit line, and a second transfer transistor connected between the second storage node and a complementary-bit line to serve as a transistor connecting the memory cell to the complementary-bit line. | 2009-06-11 |
20090146189 | Pads and pin-outs in three dimensional integrated circuits - A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a said circuit; and a memory array positioned above or below the substrate coupled to a said circuit to program the memory array. | 2009-06-11 |
20090146190 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising:
| 2009-06-11 |
20090146191 | LOW LEAKAGE SCHOTTKY CONTACT DEVICES AND METHOD - Method and apparatus are described for semiconductor devices. The method ( | 2009-06-11 |
20090146192 | MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation - A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiH | 2009-06-11 |
20090146193 | Conductive Interconnects - A method of making a conductive interconnect structure includes the steps of: electrodepositing a metal on a conductive surface ( | 2009-06-11 |
20090146194 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The local bending of a silicon nanowire induces tensile strain in the wire due to the stretching of the silicon lattice. This in turn enhances the mobility of the free carriers (electrons) in the direction of transport along the wire. Thus, for example, when Gate-All-Around MOSFETs are fabricated along the nanowire, the mobility enhancement will translate into an improvement in the performance (current drive, speed) of the silicon nanowire MOSFETs. In summary, a semiconductor device comprises a substrate and a nanowire in connection with the substrate at a drain and at a source region, and the nanowire is bent to achieve enhanced mobility of charge carriers. | 2009-06-11 |
20090146195 | Noise reduction in active pixel sensor arrays - A system for detecting high speed noise in active pixel sensors includes a photodiode for receiving low levels of light, a reset transistor, an amplifier transistor, a row select transistor, and a high-speed analog-to-digital converter. The reset transistor gate receives a reset signal, and the reset transistor drain receives a reset voltage. The amplifier transistor gate is connected to the photodiode and the reset transistor's source. The amplifier transistor receives a supply voltage at the drain terminal. The row select transistor gate terminal receives a row select signal. The row select drain terminal is connected to the amplifier transistor source terminal. The high-speed analog-to-digital converter includes an analog input port connected to the row select transistor source and a digital output port capable of resolving high-speed excitation events received by the photodiode. | 2009-06-11 |
20090146196 | IMAGE SENSOR - An image sensor, in particular a CMOS image sensor, for electronic cameras having a plurality of light-sensitive pixels which are arranged in rows and columns and whose signals are conducted via a plurality of column lines to column amplifiers, with a column amplifier being associated with each column line. At least one further column amplifier which is simultaneously also associated with at least one other column line is associated with the respective column line. A switching device switches the respective column line selectively to one of the associated column amplifiers. | 2009-06-11 |
20090146197 | PHOTO-DETECTOR ARRAY DEVICE WITH ROIC MONOLITHICALLY INTEGRATED FOR LASER-RADAR IMAGE SIGNAL AND MANUFACTURING METHOD THEREOF - A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved. | 2009-06-11 |
20090146198 | Photodiodes, image sensing devices and image sensors - Provided are photodiodes, image sensing devices and image sensors. An image sensing device includes a p-n junction photodiode having a metal pattern layer on an upper surface thereof. An image sensor includes the image sensing device and a micro-lens formed above the metal pattern layer. The metal pattern layer filters light having a first wavelength. | 2009-06-11 |
20090146199 | CMOS image sensor and method for fabricating the same - A CMOS image sensor and fabricating method can reduce leakage current of a photodiode reduced by configuring a triangular shape of a photodiode area to minimize an interface contacting the STI or performing deuterium annealing to remove dangling bonds from an interface contacting with oxide. The CMOS image sensor includes a semiconductor substrate, a device isolation layer on the semiconductor substrate, and a plurality of diodes, each having a shape minimizing an area of a boundary contacting with the device isolation layer. | 2009-06-11 |
20090146200 | MAGNESIUM-DOPED ZINC OXIDE STRUCTURES AND METHODS - Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties. | 2009-06-11 |
20090146201 | WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTIPLE CHARGE STORAGE ELEMENTS IN AN UNDERCUT REGION - A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided. | 2009-06-11 |
20090146202 | ORGANIC MEMORY DEVICE AND METHOD OF MANUFACTURE - An organic memory device is disclosed that has an active layer, at least one charge storage layer of a film of an organic dielectric material, and nanostractures and/or nano-particles of a charge-storing material on or in the film of dielectric material. Each of the nanostructures and/or nano-particles is separated from the others of the nanostractures and/or nano-particles by the organic dielectric material of the organic dielectric film. A method of manufacturing the organic memory device is also disclosed. | 2009-06-11 |
20090146203 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion, the first portions being formed on the respective tunnel insulating films, the second portions being formed on the respective first portions and having smaller width than the first portions in the first direction; an inter-gate insulating film formed on the floating gate electrodes; and first and second control gate electrodes respectively formed on sidewalls, in the first direction, of the second portion of each of the plurality of floating gate electrodes with the inter-gate insulating film interposed therebetween. | 2009-06-11 |
20090146204 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first poly layer over a semiconductor substrate, an IPD layer over the first poly layer, a second poly layer over the IPD layer, an oxide layer over a sidewall of the second poly layer, a first insulating layer over a sidewall of the oxide layer, and a second insulating layer over a sidewall of the first insulating layer. | 2009-06-11 |
20090146205 | Floating Gate of Flash Memory Device and Method of Forming the Same - Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface. | 2009-06-11 |
20090146206 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate and having a first hollow extending downward from its upper end; a first insulation layer formed in contact with the outer wall of the first columnar semiconductor layer; a second insulation layer formed on the inner wall of the first columnar semiconductor layer so as to leave the first hollow; and a plurality of first conductive layers formed to sandwich the first insulation layer with the first columnar semiconductor layer and functioning as control electrodes of the memory cells. | 2009-06-11 |
20090146207 | Nonvolatile Memory Devices Including Common Source - Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source. | 2009-06-11 |
20090146208 | Independently controlled, double gate nanowire memory cell with self-aligned contacts - A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used. | 2009-06-11 |
20090146209 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion. | 2009-06-11 |
20090146210 | Semiconductor on insulator (SOI) structure and method for fabrication - A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the buried oxide layer, thereby causing the source/drain junction to have a source/drain junction capacitance. The SOI structure also comprises at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thereby electrically isolating the at least one transistor. In one embodiment the at least one trench is formed after fabrication of the at least one transistor and is filled with only dielectric. In one embodiment, one or more wells may be formed in the device layer. In one embodiment the bulk semiconductor layer has a high resistivity of typically about 1000 ohms-centimeter or greater. | 2009-06-11 |
20090146211 | GROUNDING FRONT-END-OF-LINE STRUCTURES ON A SOI SUBSTRATE - Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate. | 2009-06-11 |
20090146212 | NEGATIVE DIFFERENTIAL RESISTANCE DIODE AND SRAM UTILIZING SUCH DEVICE - A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor. | 2009-06-11 |
20090146213 | Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit - Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain regions of the nMOSFET and the pMOSFET are connected to each other. A high potential is applied to a source region of the pMOSFET while an intermediate potential between the high and a low potential is applied to a source region of the nMOSFET. As a result, a NAND gate is provided. The intermediate potential between the high and the low potential is applied to the source region of the pMOSFET. The low potential is applied to the source region of the nMOSFET. As a result, a NOR gate is provided. | 2009-06-11 |
20090146214 | METHOD FOR MANUFACTURING AN EEPROM CELL - A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a second surface opposite to the first surface; and incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface. | 2009-06-11 |
20090146215 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on a second region of the semiconductor substrate; and a second gate electrode on the second gate insulating film. The first gate insulating film includes a first insulating film composed of a first material containing a first metal, and the second gate insulating film includes a second insulating film composed of the first material and a second material containing a second metal. | 2009-06-11 |
20090146216 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H | 2009-06-11 |
20090146217 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less. | 2009-06-11 |
20090146218 | PMOS DEPLETABLE DRAIN EXTENSION MADE FROM NMOS DUAL DEPLETABLE DRAIN EXTENSIONS - In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure. | 2009-06-11 |
20090146219 | Integrated circuit having memory cell array, and method of manufacturing same - An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the gate and gate dielectric are disposed on or above the first semiconductor layer that is disposed on or above an insulating layer or region, (ii) the body region of each transistor is electrically floating, (iii) the transistors of adjacent memory cells include a layout that provides a common first region, and (iv) the first regions of the transistors are comprised of a semiconductor material which is different from the material of the first semiconductor layer. Also disclosed are inventive methods of manufacturing, for example, such integrated circuit devices. | 2009-06-11 |
20090146220 | MULTI DEVICE AND METHOD OF MANUFACTURING THE SAME - Embodiments relate to a multi device that may include a first MOS transistor having a first gate oxide film, and a second MOS transistor having a second gate oxide film thicker than the first gate oxide film. According to embodiments, a LDD structure of the first MOS transistor may be a two-layered structure in which a first LDD region and a second LDD region are disposed vertically downward from the surface of a wafer, and the second LDD region is substantially the same as an LDD structure in the second MOS transistor in doping concentration. | 2009-06-11 |
20090146221 | METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF - Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer. | 2009-06-11 |
20090146222 | METHOD FOR FABRICATION OF SINGLE ELECTRON TRANSISTORS - A method for fabricating a Single Electron Transistor (SET). The method comprises forming a FinFET structure, forming an SET structure from the FinFET structure such that an active area of the SET structure is formed from a channel of the FinFET structure, whereby the active area is self-aligned with a source and a drain of the FinFET structure to form the SET structure. | 2009-06-11 |
20090146223 | PROCESS AND METHOD TO LOWER CONTACT RESISTANCE - A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface. | 2009-06-11 |
20090146224 | Composite Passivation Process for Nitride FET - A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage. | 2009-06-11 |
20090146225 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for manufacturing a semiconductor device includes a gate dielectric film formed over an active area of a semiconductor substrate, and a gate electrode formed over the gate dielectric film and formed of a silicidation film having a polysilicon area at the bottom of the gate electrode. Therefore, with embodiments, a work function can variously controlled and the gate pattern having different work function can be applied to the transistors by using a non-silicided polysilicon region due to the formation a partially silicided gate pattern, such that the resistance of the gate electrode and junction can be reduced, making it possible to maximize the device characteristics. | 2009-06-11 |
20090146226 | MECHANICAL MEMORY TARNSISTOR - A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element. | 2009-06-11 |
20090146227 | CAPACITIVE SENSOR AND MANUFACTURING METHOD THEREFOR - A capacitive sensor according to the present invention includes a semiconductor substrate, a fixed electrode serving as a first electrode formed on a surface of or in the semiconductor substrate, a structure formed on the semiconductor substrate to have a vibratable second electrode that is formed to be spaced from and opposed to the semiconductor substrate and from the fixed electrode serving as the first electrode, a sealing member serving as a first sealing member formed on the semiconductor substrate to be spaced from the structure, to cover the structure, and to have a through hole serving as a first through hole, and a movable electrode serving as a vibratable third electrode formed on the sealing member to block up the through hole, and to be spaced from and opposed to the movable electrode. | 2009-06-11 |
20090146228 | Microminiature moving device - A microminiature moving device has disposed on a single-crystal silicon substrate movable elements such as a movable rod and a movable comb electrode that are displaceable in parallel to the substrate surface and stationary parts that are fixedly secured to the single-crystal silicon substrate with an insulating layer sandwiched between. Depressions are formed in the surface regions of the single-crystal silicon substrate where no stationary parts are present and the movable parts are positioned above the depressions. The depressions form gaps large enough to prevent foreign bodies from causing shorts and malfunctioning of the movable parts. | 2009-06-11 |
20090146229 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments relate to a semiconductor device and a method for fabricating the same. According to embodiments, a semiconductor device may include a metal film spaced from a semiconductor substrate at a predetermined interval and in which a plurality of etching holes are formed. A bottom metal pattern disposed on and/or over a space between the semiconductor substrate and metal film and top metal pattern formed on and/or over the bottom metal pattern may be provided. A pillar may be formed on and/or over the semiconductor substrate and may support one side of a low surface of the bottom metal pattern. A pad may be formed on and/or over the semiconductor substrate, and an air layer corresponding to the bottom metal pattern may be inserted therein. According to embodiments, a pyro-electric switch transistor using a bi-metal with different coefficients of thermal expansion may be provided. | 2009-06-11 |
20090146230 | SEMICONDUCTOR PRESSURE SENSOR, METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A semiconductor pressure sensor includes: a first substrate; a buried insulating film laminated on the first substrate; a second substrate laminated on the buried insulating film; a plurality of electrodes including a lower electrode and at least two upper electrodes, the lower electrode being formed on the second substrate; and a piezoelectric film laminated on the lower electrode and having the upper electrodes formed thereon. In the sensor, there is removed at least a portion of a region of the first substrate corresponding to a region of the second substrate including the piezoelectric film and the electrodes. | 2009-06-11 |
20090146231 | Magnetic memory device having a C-shaped structure and method of manufacturing the same - A non-volatile magnetic memory device having one or more memory cells, each of the memory cells includes a magnetic switch including a C-shaped magnetic component and a write coil located proximate the magnetic component, the write coil coupled to receive a current sufficient to create a remnant magnetic polarity in the magnetic component, and a Hall sensor, positioned proximate the magnetic component, to detect the remnant magnetic polarity indicative of a stored data bit. | 2009-06-11 |
20090146232 | MAGNETORESISTIVE DEVICE - A magnetoresistive device comprises a ferromagnetic region, a non-ferromagnetic region, an insulating region and a conductive region. The insulating region is arranged between the ferromagnetic region and the conductive region so as to provide a tunnel barrier. The non-ferromagnetic region separates the insulating region and the ferromagnetic region. | 2009-06-11 |
20090146233 | NON-MAGNETIC SEMICONDUCTOR SPIN TRANSISTOR - A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. | 2009-06-11 |
20090146234 | MICROELECTRONIC IMAGING UNITS HAVING AN INFRARED-ABSORBING LAYER AND ASSOCIATED SYSTEMS AND METHODS - Infrared (IR) absorbing layers and microelectronic imaging units that employ such layers are disclosed herein. In one embodiment, a method of manufacturing a microelectronic imaging unit includes attaching an IR-absorbing lamina having a filler material to a backside die surface of an imager workpiece. An individual imaging die is singulated from the workpiece such that a section of the infrared-absorbing lamina remains attached to the individual imaging die. The individual imaging die is coupled to an interposer substrate with a portion of the IR-absorbing lamina positioned therebetween. In another embodiment, the IR-absorbing lamina is a die attach film and the filler material is carbon black. | 2009-06-11 |
20090146235 | Solid-state image capturing device, camera module and electronic information device - A solid-state image capturing device includes a plurality of electrode pads for inputting and outputting a signal or voltage from and to the outside, a plurality of photoelectric conversion elements, a planarization film for planarizing the difference in the level on the surface above the plurality of photoelectric conversion elements, a microlens for focusing incident light on each of the plurality of photoelectric conversion elements, and a protection film provided above the microlens and the planarization film, the planarization film and the protection film above the plurality of electrode pads being removed as an opening, where the protection film has a protection film removing area that at least includes an area removed across all or a corner portion of the opening and the image capturing area. | 2009-06-11 |
20090146236 | PHOTOSENSITIVE RESIN COMPOSITION FOR PAD PROTECTIVE LAYER, AND METHOD FOR MAKING IMAGE SENSOR USING THE SAME - The present invention provides a photosensitive resin composition for a pad protective layer that includes (A) an alkali soluble resin, (B) a reactive unsaturated compound, (C) a photoinitiator, and (D) a solvent. The (A) alkali soluble resin includes a copolymer including about 5 to about 50 wt % of a unit having the Chemical Formula 1, about 1 to about 25 wt % of a unit having the Chemical Formula 2, and about 45 to about 90 wt % of a unit having the Chemical Formula 3, and a method of making an image sensor using the photosensitive resin composition. | 2009-06-11 |
20090146237 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THEREOF - An image sensor and a method for manufacturing thereof include a semiconductor substrate having a plurality of unit pixels formed therein, a dielectric film formed over the semiconductor substrate, a seed lens array including a plurality of seed lenses formed spaced apart by a gap of a predetermined width over the dielectric film, a color micro lens array formed over the seed lens array, the color micro lens array including a color micro lens formed over and contacting a respective one of the seed lenses. In accordance with embodiments, each color micro lens has a thickness that is one-half the predetermined width to thereby fill the gap between the seed lenses. | 2009-06-11 |
20090146238 | CMOS-BASED PLANAR TYPE SILICON AVALANCHE PHOTO DIODE USING SILICON EPITAXIAL LAYER AND METHOD OF MANUFACTURING THE SAME - A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed. | 2009-06-11 |
20090146239 | PHOTODIODE - A photodiode balanced in increased sensitivity and speed. The photodiode includes a semiconductor substrate, an active region formed on the semiconductor substrate, and a comb electrode connected to the active region. The comb electrode includes a plurality of electrode fingers, and each of the electrode fingers includes a transparent electrode contacting the active region, and an opaque electrode formed on the transparent electrode. Here, the width of the opaque electrode is set smaller than the width of the transparent electrode. | 2009-06-11 |
20090146240 | SILICON-BASED VISIBLE AND NEAR-INFRARED OPTOELECTRIC DEVICES - In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns. | 2009-06-11 |
20090146241 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus. The semiconductor apparatus of the invention including a first conductive type semiconductor substrate, a first conductive type first semiconductor region with an impurity concentration lower than that of the semiconductor substrate and formed on a first principal surface of the semiconductor substrate, a second conductive type second semiconductor region formed in a surface region of the first semiconductor region and which forms a PN junction with the first semiconductor region, a contact region including a part of the first semiconductor region and a part of the second semiconductor region, an insulating layer having an opening part through which at least the contact region are exposed, a first electrode formed so as to be in contact with at least the contact region and a second electrode formed on a second principal surface of the semiconductor substrate, wherein the second semiconductor region, viewed from a direction perpendicular to the first principal surface includes a first region in which a plurality of islands of the second semiconductor are aligned with intervals and a second region which connects each end of the islands of the first region each other. | 2009-06-11 |
20090146242 | METAL ION TRANSISTOR AND RELATED METHODS - A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode. | 2009-06-11 |
20090146243 | Semiconductor Device Having Recessed Channel and Method for Manufacturing the Same - A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region. | 2009-06-11 |
20090146244 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed. | 2009-06-11 |
20090146245 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below the surface of the semiconductor material, filling the cavity with a sacrificial material, forming a dielectric material over the sacrificial material and over at least a portion of the surface of the semiconductor material, and removing a portion of the dielectric material to form an opening to expose a portion of the sacrificial material, wherein the opening has a width that is substantially less than a width of the cavity and the dielectric material is rigid or substantially rigid. The method further includes removing the sacrificial material. Other embodiments are described and claimed. | 2009-06-11 |
20090146246 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure. | 2009-06-11 |
20090146247 | SEMICONDUCTOR GROUND SHIELD - A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield. | 2009-06-11 |
20090146248 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed. | 2009-06-11 |
20090146249 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to form a semiconductor structure includes removing a portion of a semiconductor material to form one or more suspended structures and a cavity, the cavity having a boundary that is below a surface of the semiconductor material and wherein the one or more suspended structures extend from the surface into the cavity. The method further includes altering the one or more suspended structures to form one or more altered suspended structures and forming a material over the one or more altered suspended structures and in a region between the one or more altered suspended structures. Other embodiments are described and claimed. | 2009-06-11 |
20090146250 | Semiconductor device - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof. | 2009-06-11 |
20090146251 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times. | 2009-06-11 |
20090146252 | INTEGRATED INDUCTOR STRUCTURE - This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding structure is chequered with a plurality of N wells and a plurality of P wells. The N wells and P wells are arranged in a chessboard-like manner. A P+ pickup ring is provided in the substrate to encompass the well shielding structure. A guard ring is formed directly on the P+ pickup ring. | 2009-06-11 |
20090146253 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Manufacturing an inductor includes forming a spiral metal wire on a semiconductor substrate; forming a connection hole exposing a portion of the metal wire by selectively etching a first dielectric film formed to bury the metal wire, and forming a first metal film on the first dielectric film on which the connection hole is formed; forming a second dielectric film on the first metal film; and forming a first photoresist film for forming a second metal wire corresponding to the spiral metal wire on the second dielectric film, and forming the second metal wire by selectively etching the second dielectric film and the first metal film using the first photoresist pattern as an etching mask; wherein the second dielectric film prevents an etching of the top of the second metal wire resulting from the difference in etch rate between the first photoresist pattern and first metal film. | 2009-06-11 |
20090146254 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion. | 2009-06-11 |
20090146255 | Capacitor for Semiconductor Device and Method for Manufacturing the Same - Disclosed is a capacitor of a semiconductor device, capable of varying a capacitance according to a design of the semiconductor device. The capacitor can include a first electrode area and a second electrode area with a dielectric therebetween. The first electrode area can have a metal electrode spanning the entire first electrode area. The second electrode area can include a plurality of metal electrodes connected to each other through thin bridge patterns. Internal pads can be arranged around the electrode areas and are connected to certain ones of the plurality of metal electrodes of the second electrode area in order to provide a voltage capable of melting or breaking certain ones of the thin bridge patterns. The capacitance of the capacitor arranged according to embodiments can be adjusted to a desirable level using the internal pads. Therefore, a designer can easily design the capacitor or change the design of the capacitor. | 2009-06-11 |
20090146256 | METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING CAPACITOR - A method of forming a semiconductor device may include, but is not limited to, the following processes. A second insulating film may be formed over a first insulating film. At least one through-hole may be formed, which penetrates the first and second insulating films. At least one first electrode may be formed, which extends at least along the side wall of the at least one through-hole. The first inter-layer insulator may be removed, while using the second insulating film as a temporary supporter that supports the at least one first electrode. At least one permanent supporter may be formed, which supports the at least one first electrode. The second insulating film as the temporary supporter may be removed, while leaving the at least one permanent supporter to support the at least one first electrode. | 2009-06-11 |
20090146257 | Capacitor and semiconductor device including the same - A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode. | 2009-06-11 |
20090146258 | SELF-ALIGNED VERTICAL PNP TRANSISTOR FOR HIGH PERFORMANCE SiGe CBiCMOS PROCESS - A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction. | 2009-06-11 |
20090146259 | Sub-Resolution Assist Feature To Improve Symmetry for Contact Hole Lithography - A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature. | 2009-06-11 |
20090146260 | Semiconductor wafer including cracking stopper structure and method of forming the same - A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region. | 2009-06-11 |
20090146261 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device having a VIA hole without disconnection caused by step is achieved. | 2009-06-11 |
20090146262 | INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECHNOLOGY - An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate. | 2009-06-11 |
20090146263 | STRUCTURE AND METHOD TO INCREASE EFFECTIVE MOSFET WIDTH - An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI. | 2009-06-11 |
20090146264 | THIN FILM TRANSISTOR ON SODA LIME GLASS WITH BARRIER LAYER - The present invention generally comprises a low cost TFT and a method of manufacturing a TFT. For TFTs, soda lime glass would be an attractive alternative to non-alkali glass, but a soda lime glass substrate will permit sodium to diffuse into the active layer and degrade the performance of the TFT. Substrates comprising a polyimide, because they are flexible, would also be attractive to utilize instead of non-alkali glass substrates, but the plastic substrates permit carbon to diffuse into the active layer. By depositing a silicon rich barrier layer over the soda lime glass substrate or substrate comprising a polyimide, both sodium and carbon diffusion may be reduced. Thus, a lower cost TFT may be produced with a soda lime glass substrate or a substrate comprising a polyimide as compared to a non-alkali glass substrate. | 2009-06-11 |
20090146265 | ULTRA LOW k PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES USING A SINGLE BIFUNCTIONAL PRECURSOR CONTAINING BOTH A SiCOH MATRIX FUNCTIONALITY AND ORGANIC POROGEN FUNCTIONALITY - A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH | 2009-06-11 |
20090146266 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate. | 2009-06-11 |
20090146267 | SECURE CONNECTOR GRID ARRAY PACKAGE - Methods, systems, IC packages, and electrical devices for providing data security for ICs. A substrate-on-substrate connector grid array package with an electrical shield can protect sensitive information in a secure IC from being accessed by physical attacks. A current flow in the electrical shield can be monitored for disturbances which can indicate an attack on the IC package. | 2009-06-11 |
20090146268 | INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION - An integrated circuit package system comprising: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area. | 2009-06-11 |
20090146269 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD - An integrated circuit package system includes: forming a first lead and a second lead; connecting an integrated circuit die with the first lead; forming an encapsulation over the integrated circuit die, the first lead, and the second lead with a portion of a top side of the second lead exposed; and forming a shield over the encapsulation, the first lead, and the second lead with the shield not in contact with the first lead. | 2009-06-11 |
20090146270 | Embedded Package Security Tamper Mesh - Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die. | 2009-06-11 |
20090146271 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM - An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second integrated circuits stacked in a second offset configuration, below and to the die-attach paddle; connecting the second integrated circuits and a first edge lead adjacent to the first edge; and encapsulating the first integrated circuits, second integrated circuits, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed. | 2009-06-11 |
20090146272 | ELECTRONIC DEVICE - Embodiments provide an electronic device including a carrier defining a first major surface, a chip attached to the first major surface, an array of leads connected to the first major surface, and a thickness of encapsulation material disposed on the first major surface of the carrier. Each lead extends through the thickness of the encapsulation material. | 2009-06-11 |